coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/cannonlake: Check for supported UART index
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20999 ) Change subject: soc/intel/cannonlake: Check for supported UART index ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58525/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13925/ : SUCCESS -- To view, visit https://review.coreboot.org/20999 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Gerrit-Change-Number: 20999 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 14 Aug 2017 08:22:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Check for supported UART index
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20997 ) Change subject: soc/intel/skylake: Check for supported UART index ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58523/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13923/ : SUCCESS -- To view, visit https://review.coreboot.org/20997 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Gerrit-Change-Number: 20997 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 14 Aug 2017 08:16:43 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Add Kconfig option to select UART index
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20998 ) Change subject: soc/intel/cannonlake: Add Kconfig option to select UART index ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58522/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13922/ : SUCCESS -- To view, visit https://review.coreboot.org/20998 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Gerrit-Change-Number: 20998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 14 Aug 2017 08:05:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Fix gpio pad reset config discrepency
by Rizwan Qureshi (Code Review) 14 Aug '17

14 Aug '17

Rizwan Qureshi has posted comments on this change. ( https://review.coreboot.org/20993 ) Change subject: soc/intel/skylake: Fix gpio pad reset config discrepency ...................................................................... Patch Set 1: > Rizwan, i guess macros has some issue. The buildbot is reporting an issue for RVP7 which uses the RSMRST macro, there is a subsequent patch for RVP7 which is passing. I think it is better to put everything together. -- To view, visit https://review.coreboot.org/20993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c Gerrit-Change-Number: 20993 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 08:01:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Check for supported UART index
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20999 Change subject: soc/intel/cannonlake: Check for supported UART index ...................................................................... soc/intel/cannonlake: Check for supported UART index if UART index is 2 then Base address for LPSS UART2 is selected else assert because cannonlake chrome design don't support legacy UART selection. Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/uart.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/20999/1 diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c index 38f499d..ce1241f 100644 --- a/src/soc/intel/cannonlake/uart.c +++ b/src/soc/intel/cannonlake/uart.c @@ -14,6 +14,7 @@ */ #include <assert.h> +#include <console/console.h> #include <console/uart.h> #include <device/pci_def.h> #include <intelblocks/gpio.h> @@ -79,6 +80,11 @@ uintptr_t uart_platform_base(int idx) { + /* Same base address for all debug port usage. In reality UART2 + * is currently only supported. */ + if (idx != 2) + die("unsupported UART index"); + /* We can only have one serial console at a time */ return UART_DEBUG_BASE_ADDRESS; } -- To view, visit https://review.coreboot.org/20999 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586 Gerrit-Change-Number: 20999 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Add Kconfig option to select UART index
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20998 Change subject: soc/intel/cannonlake: Add Kconfig option to select UART index ...................................................................... soc/intel/cannonlake: Add Kconfig option to select UART index Cannonlake SOC has two possible ways to make serial console functional. 1. Using 0x3F8 as Legacy UART 2. PCI based LPSS UART2 PCI based LPSS UART2 is default enable for Chrome Design. Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/20998/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 471fe6c..655fb7e 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -48,6 +48,13 @@ select DRIVERS_UART select DRIVERS_UART_8250IO +config UART_FOR_CONSOLE + int + default 2 + help + Index for UART port to use for console: + 0 = Legacy UART, 2 = LPSS UART2 + config DCACHE_RAM_BASE default 0xfef00000 -- To view, visit https://review.coreboot.org/20998 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28 Gerrit-Change-Number: 20998 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Check for supported UART index
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20997 Change subject: soc/intel/skylake: Check for supported UART index ...................................................................... soc/intel/skylake: Check for supported UART index if UART index is 2 then Base address for LPSS UART2 is selected else assert because skylake chrome design don't support legacy UART selection. Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/uart_debug.c 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/20997/1 diff --git a/src/soc/intel/skylake/uart_debug.c b/src/soc/intel/skylake/uart_debug.c index f3d576b..20a2513 100644 --- a/src/soc/intel/skylake/uart_debug.c +++ b/src/soc/intel/skylake/uart_debug.c @@ -14,6 +14,7 @@ */ #include <stddef.h> +#include <console/console.h> #include <console/uart.h> #include <soc/iomap.h> #include <soc/serialio.h> @@ -22,5 +23,8 @@ { /* Same base address for all debug port usage. In reality UART2 * is currently only supported. */ + if (idx != 2) + die("unsupported UART index"); + return UART_DEBUG_BASE_ADDRESS; } -- To view, visit https://review.coreboot.org/20997 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I306d3d299f8d6a890ae519c74008f9d0d9dd1a76 Gerrit-Change-Number: 20997 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add Kconfig option to select UART index
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20996 Change subject: soc/intel/skylake: Add Kconfig option to select UART index ...................................................................... soc/intel/skylake: Add Kconfig option to select UART index Skylake/Kabylake SOC has two possible ways to make serial console functional. 1. Using 0x3F8 as Legacy UART 2. PCI based LPSS UART2 PCI based LPSS UART2 is default enable for Chrome Design. Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/20996/1 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index f0402a9..2fba1d4 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -200,6 +200,13 @@ select DRIVERS_UART_8250MEM_32 select NO_UART_ON_SUPERIO +config UART_FOR_CONSOLE + int + default 2 + help + Index for UART port to use for console: + 0 = Legacy UART, 2 = LPSS UART2 + config SKYLAKE_SOC_PCH_H bool default n -- To view, visit https://review.coreboot.org/20996 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae Gerrit-Change-Number: 20996 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/google/soraka: GPIO config should not reset during warm reset
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20994 ) Change subject: mb/google/soraka: GPIO config should not reset during warm reset ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58521/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13921/ : SUCCESS -- To view, visit https://review.coreboot.org/20994 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If32f839144b9201dc23e95c7572b595a70248286 Gerrit-Change-Number: 20994 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 06:22:44 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/intel/rvp7: use the correct pad reset config for GPP
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20995 ) Change subject: mb/intel/rvp7: use the correct pad reset config for GPP ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58520/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13920/ : SUCCESS -- To view, visit https://review.coreboot.org/20995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7720ddd3ef6749610411ecf33a56c0c24994fdfc Gerrit-Change-Number: 20995 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 06:21:52 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017