coreboot-gerrit August 2017

coreboot-gerrit@coreboot.org

1 participants
1999 discussions

Change in coreboot[master]: ec/lenovo/h8/ssdt: Add keyboard backlight interface
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21002 ) Change subject: ec/lenovo/h8/ssdt: Add keyboard backlight interface ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58536/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13935/ : SUCCESS -- To view, visit https://review.coreboot.org/21002 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c Gerrit-Change-Number: 21002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 17:13:47 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: drvs/ec/lenovo/h8: Add ssdt generator
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20985 ) Change subject: drvs/ec/lenovo/h8: Add ssdt generator ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58533/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13932/ : SUCCESS -- To view, visit https://review.coreboot.org/20985 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ida825196650966194a883945896a038b0790fe45 Gerrit-Change-Number: 20985 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 17:12:45 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: ec/lenovo/h8/ssdt: Add UWB ACPI interface
by Patrick Rudolph (Code Review) 14 Aug '17

14 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/21003 Change subject: ec/lenovo/h8/ssdt: Add UWB ACPI interface ...................................................................... ec/lenovo/h8/ssdt: Add UWB ACPI interface Add ACPI methods GUWB and SUWB for thinkpad_acpi. Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/acpi/ec.asl M src/ec/lenovo/h8/ssdt.c 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/21003/1 diff --git a/src/ec/lenovo/h8/acpi/ec.asl b/src/ec/lenovo/h8/acpi/ec.asl index 085c9e2..9643102 100644 --- a/src/ec/lenovo/h8/acpi/ec.asl +++ b/src/ec/lenovo/h8/acpi/ec.asl @@ -42,6 +42,9 @@ Offset (0x30), , 6, ALMT, 1, /* Audio Mute + LED */ + Offset (0x31), + , 2, + UWBE, 1, /* Ultra Wideband enable */ Offset (0x3a), AMUT, 1, /* Audio Mute (internal use) */ , 3, diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index 26c0d84..7ed134b 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -239,6 +239,69 @@ acpigen_pop_len(); /* Method */ } +/* Generate ACPI methods GUWB and SUWB */ +static void h8_dsdt_uwb(struct device *dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + if (!conf) + return; + + const bool has_uwb = conf->has_uwb; + + /* Method (GUWB, 0) */ + acpigen_write_method("GUWB", 0); + /* Store(Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + if (has_uwb) { + /* UWB present */ + /* Or(Local0, One, Local0) */ + acpigen_write_or(LOCAL0_OP, ONE_OP, LOCAL0_OP); + + /* If(LEqual(\_SB.PCI0.LPCB.EC.UWBE, One)) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring(h8_dsdt_scope(dev, "UWBE")); + acpigen_emit_byte(ONE_OP); + + /* Or(Local0, 2, Local0) */ + acpigen_emit_byte(OR_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer(2); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* If */ + } + /* Return(Local0) */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* Method */ + + /* Method (SUWB, 1) */ + acpigen_write_method("SUWB", 1); + if (has_uwb) { + /* And(Arg0, 2, Local0) */ + acpigen_emit_byte(AND_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(2); + acpigen_emit_byte(LOCAL0_OP); + /* If(Lequal(Local0, 2)) */ + acpigen_write_if_lequal_op_int(LOCAL0_OP, 2); + /* Store(One, \_SB.PCI0.LPCB.EC.UWBE) */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_namestring(h8_dsdt_scope(dev, "UWBE")); + acpigen_pop_len(); /* If */ + /* Else */ + acpigen_write_else(); + /* Store(Zero, \_SB.PCI0.LPCB.EC.UWBE) */ + acpigen_write_store(); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_namestring(h8_dsdt_scope(dev, "UWBE")); + acpigen_pop_len(); /* Else */ + } + acpigen_pop_len(); /* Method */ +} + + /* * Generates EC SSDT. */ @@ -256,6 +319,7 @@ h8_dsdt_bluetooth(dev); h8_dsdt_wwan(dev); h8_dsdt_keyboard_backlight(dev); + h8_dsdt_uwb(dev); acpigen_pop_len(); /* Scope HKEY */ } -- To view, visit https://review.coreboot.org/21003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I8f9a56e45c0d765b0e06b8d3600bd3575dd09491 Gerrit-Change-Number: 21003 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: ec/lenovo/h8/ssdt: Add keyboard backlight interface
by Patrick Rudolph (Code Review) 14 Aug '17

14 Aug '17

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/21002 Change subject: ec/lenovo/h8/ssdt: Add keyboard backlight interface ...................................................................... ec/lenovo/h8/ssdt: Add keyboard backlight interface Add methods MLCG and MLCS for thinkpad_acpi kernel module. Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/ec/lenovo/h8/ssdt.c 1 file changed, 72 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/21002/1 diff --git a/src/ec/lenovo/h8/ssdt.c b/src/ec/lenovo/h8/ssdt.c index 0c68b2b..26c0d84 100644 --- a/src/ec/lenovo/h8/ssdt.c +++ b/src/ec/lenovo/h8/ssdt.c @@ -168,6 +168,77 @@ acpigen_pop_len(); /* Method */ } +/* Generate ACPI methods MLCG and MLCS */ +static void h8_dsdt_keyboard_backlight(struct device *dev) +{ + struct ec_lenovo_h8_config *conf = dev->chip_info; + if (!conf) + return; + + const bool has_kbbl = conf->has_keyboard_backlight; + + /* Method (MLCG, 1) */ + acpigen_write_method("MLCG", 1); + /* Store(Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + if (has_kbbl) { + /* Keyboard backlight present */ + /* Or(Local0, (1 << 9), Local0) */ + acpigen_emit_byte(OR_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_integer((1 << 9)); + acpigen_emit_byte(LOCAL0_OP); + + /* If(LEqual(\_SB.PCI0.LPCB.EC.KBLT, One)) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_namestring(h8_dsdt_scope(dev, "KBLT")); + acpigen_emit_byte(ONE_OP); + + /* Or(Local0, 1, Local0) */ + acpigen_write_or(LOCAL0_OP, ONE_OP, LOCAL0_OP); + acpigen_pop_len(); /* If */ + } + /* Return(Local0) */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_pop_len(); /* Method */ + + /* Method (MLCS, 1) */ + acpigen_write_method("MLCS", 1); + if (has_kbbl) { + /* And(Arg0, 3, Local0) */ + acpigen_emit_byte(AND_OP); + acpigen_emit_byte(ARG0_OP); + acpigen_write_integer(3); + acpigen_emit_byte(LOCAL0_OP); + + /* If(LGREATER_OP(Local0, 0)) */ + acpigen_write_if(); + acpigen_emit_byte(LGREATER_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_emit_byte(ZERO_OP); + + /* FIXME: Support 2bit brightness control */ + /* Store(One, \_SB.PCI0.LPCB.EC.KBLT) */ + acpigen_write_store(); + acpigen_emit_byte(ONE_OP); + acpigen_emit_namestring(h8_dsdt_scope(dev, "KBLT")); + acpigen_pop_len(); /* If */ + /* Else */ + acpigen_write_else(); + /* Store(Zero, \_SB.PCI0.LPCB.EC.KBLT) */ + acpigen_write_store(); + acpigen_emit_byte(ZERO_OP); + acpigen_emit_namestring(h8_dsdt_scope(dev, "KBLT")); + acpigen_pop_len(); /* Else */ + } + /* Return(Zero) */ + acpigen_emit_byte(RETURN_OP); + acpigen_emit_byte(ZERO_OP); + acpigen_pop_len(); /* Method */ +} + /* * Generates EC SSDT. */ @@ -184,6 +255,7 @@ /* Used by thinkpad_acpi */ h8_dsdt_bluetooth(dev); h8_dsdt_wwan(dev); + h8_dsdt_keyboard_backlight(dev); acpigen_pop_len(); /* Scope HKEY */ } -- To view, visit https://review.coreboot.org/21002 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia65e770e772936c9c32be33c30839a2dee2a107c Gerrit-Change-Number: 21002 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: soc/intel/apollolake: Provide option to use Common MP Init
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20895 ) Change subject: soc/intel/apollolake: Provide option to use Common MP Init ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58532/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13931/ : SUCCESS -- To view, visit https://review.coreboot.org/20895 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6 Gerrit-Change-Number: 20895 Gerrit-PatchSet: 6 Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 11:47:30 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21001 ) Change subject: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58531/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13930/ : SUCCESS -- To view, visit https://review.coreboot.org/21001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab Gerrit-Change-Number: 21001 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 11:07:31 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/21001 Change subject: soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition ...................................................................... soc/intel/cannonlake: Rectify LPC Lock Enable (LE) bit definition LPC pci config register BIOS Control (BC) - offset 0xDC bit 1 is for Lock Down. Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/include/soc/lpc.h 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/21001/1 diff --git a/src/soc/intel/cannonlake/include/soc/lpc.h b/src/soc/intel/cannonlake/include/soc/lpc.h index 3488ee2..3ea9be9 100644 --- a/src/soc/intel/cannonlake/include/soc/lpc.h +++ b/src/soc/intel/cannonlake/include/soc/lpc.h @@ -48,7 +48,7 @@ #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_CNTL 0xdc #define LPC_BC_BILD (1 << 7) /* BILD */ -#define LPC_BC_LE (1 << 2) /* LE */ +#define LPC_BC_LE (1 << 1) /* LE */ #define LPC_BC_EISS (1 << 5) /* EISS */ #define PCCTL 0xE0 /* PCI Clock Control */ #define CLKRUN_EN (1 << 0) -- To view, visit https://review.coreboot.org/21001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I4780d2e41c833c0146640f715759dbb0a948c4ab Gerrit-Change-Number: 21001 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21000 ) Change subject: soc/intel/skylake: Move LPC lock down config after PCI enumeration ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58530/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13929/ : SUCCESS -- To view, visit https://review.coreboot.org/21000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Gerrit-Change-Number: 21000 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Mon, 14 Aug 2017 11:02:13 +0000 Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after PCI enumeration
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/21000 to look at the new patch set (#2). Change subject: soc/intel/skylake: Move LPC lock down config after PCI enumeration ...................................................................... soc/intel/skylake: Move LPC lock down config after PCI enumeration This patch to ensure that coreboot is meeting Intel Silicon recommendation to performing register lockdown. TEST=Ensure LPC register 0xDC bit 1 and 7 is set. Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/finalize.c A src/soc/intel/skylake/lockdown.c 3 files changed, 69 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/21000/2 -- To view, visit https://review.coreboot.org/21000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Gerrit-Change-Number: 21000 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: soc/intel/skylake: Move LPC lock down config after PCI enumeration
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21000 ) Change subject: soc/intel/skylake: Move LPC lock down config after PCI enumeration ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58529/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/13928/ : SUCCESS -- To view, visit https://review.coreboot.org/21000 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee Gerrit-Change-Number: 21000 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 10:55:18 +0000 Gerrit-HasComments: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2017