coreboot-gerrit August 2017

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Change in coreboot[master]: libpayload: add time()
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21011 ) Change subject: libpayload: add time() ...................................................................... Patch Set 2: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/58553/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/13949/ : SUCCESS -- To view, visit https://review.coreboot.org/21011 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e Gerrit-Change-Number: 21011 Gerrit-PatchSet: 2 Gerrit-Owner: Nicola Corna <nicola(a)corna.info> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 21:51:22 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/common/mp_init: Refactor MP Init code to get rid of microcode p...
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21010 ) Change subject: intel/common/mp_init: Refactor MP Init code to get rid of microcode param ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58550/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13947/ : SUCCESS -- To view, visit https://review.coreboot.org/21010 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b Gerrit-Change-Number: 21010 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 21:50:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/common/block/sgx: Refactor SGX common code.
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21006 ) Change subject: intel/common/block/sgx: Refactor SGX common code. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58546/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13943/ : SUCCESS -- To view, visit https://review.coreboot.org/21006 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad Gerrit-Change-Number: 21006 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 21:41:12 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: libpayload: add time()
by Nicola Corna (Code Review) 14 Aug '17

14 Aug '17

Nicola Corna has uploaded this change for review. ( https://review.coreboot.org/21011 Change subject: libpayload: add time() ...................................................................... libpayload: add time() Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e --- M payloads/libpayload/include/time.h M payloads/libpayload/libc/time.c 2 files changed, 21 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/21011/1 diff --git a/payloads/libpayload/include/time.h b/payloads/libpayload/include/time.h index 25f476c..8871824 100644 --- a/payloads/libpayload/include/time.h +++ b/payloads/libpayload/include/time.h @@ -44,6 +44,7 @@ suseconds_t tv_usec; /**< Microseconds */ }; +time_t time (time_t* tloc); int gettimeofday(struct timeval *tv, void *tz); /** @} */ diff --git a/payloads/libpayload/libc/time.c b/payloads/libpayload/libc/time.c index 4ed788f..cfad278 100644 --- a/payloads/libpayload/libc/time.c +++ b/payloads/libpayload/libc/time.c @@ -121,13 +121,12 @@ #endif /** - * Return the current time broken into a timeval structure. + * Return the current time. * - * @param tv A pointer to a timeval structure. - * @param tz Added for compatability - not used. - * @return 0 for success (this function cannot return non-zero currently). + * @param tloc When not NULL, set this variable to the current time. + * @return The current time. */ -int gettimeofday(struct timeval *tv, void *tz) +time_t time (time_t* tloc) { /* * Call the gtod init when we need it - this keeps the code from @@ -138,7 +137,22 @@ update_clock(); - tv->tv_sec = clock.secs; + if (tloc) + *tloc = clock.secs; + + return clock.secs; +} + +/** + * Return the current time broken into a timeval structure. + * + * @param tv A pointer to a timeval structure. + * @param tz Added for compatability - not used. + * @return 0 for success (this function cannot return non-zero currently). + */ +int gettimeofday(struct timeval *tv, void *tz) +{ + tv->tv_sec = time(NULL); tv->tv_usec = clock.usecs; return 0; -- To view, visit https://review.coreboot.org/21011 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I97e393537ccc71ea454bb0d6cdbbb7ed32485f1e Gerrit-Change-Number: 21011 Gerrit-PatchSet: 1 Gerrit-Owner: Nicola Corna <nicola(a)corna.info>

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Change in coreboot[master]: intel/common/mp_init: Refactor MP Init code to get rid of microcode p...
by Pratikkumar V Prajapati (Code Review) 14 Aug '17

14 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21010 Change subject: intel/common/mp_init: Refactor MP Init code to get rid of microcode param ...................................................................... intel/common/mp_init: Refactor MP Init code to get rid of microcode param Refactor MP Init which - removes global variable for microcode - remove passing microcode patch pointer as param - uses device_t data pointer for microcode pointer usage Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/include/intelblocks/mp_init.h M src/soc/intel/skylake/cpu.c 3 files changed, 16 insertions(+), 29 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/21010/1 diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 7e57b79..a5138eb 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -27,24 +27,21 @@ #include <intelblocks/msr.h> #include <soc/cpu.h> -static const void *microcode_patch; - /* SoC override function */ -__attribute__((weak)) void soc_core_init(device_t dev, const void *microcode) +__attribute__((weak)) void soc_core_init(device_t dev) { /* no-op */ } -__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus, - const void *microcode) +__attribute__((weak)) void soc_init_cpus(struct bus *cpu_bus) { /* no-op */ } -static void init_one_cpu(device_t dev) +static void init_one_cpu(device_t dev) { - soc_core_init(dev, microcode_patch); - intel_microcode_load_unlocked(microcode_patch); + soc_core_init(dev); + intel_microcode_load_unlocked(dev->data); } static struct device_operations cpu_dev_ops = { @@ -102,7 +99,10 @@ */ void get_microcode_info(const void **microcode, int *parallel) { - *microcode = microcode_patch; + device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + assert(dev != NULL); + + *microcode = dev->data; *parallel = 1; } @@ -111,23 +111,10 @@ device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); assert(dev != NULL); - microcode_patch = intel_microcode_find(); - intel_microcode_load_unlocked(microcode_patch); + dev->data = intel_microcode_find(); + intel_microcode_load_unlocked(dev->data); - dev->data = microcode_patch; - /* - * TODO: This parameter "microcode_patch" should be removed - * in this function call once the following two cases are resolved - - * - * 1) SGX enabling for the BSP issue gets solved, due to which - * configure_sgx() function is kept inside soc/cpu.c soc_init_cpus(). - * 2) uCode loading after SMM relocation is deleted inside - * per_cpu_smm_trigger() mp_ops callback function in soc/cpu.c, - * since as per current BWG, uCode loading can be done after - * all feature programmings are done. There is no specific - * recommendation to do it after SMM Relocation. - */ - soc_init_cpus(dev->link_list, microcode_patch); + soc_init_cpus(dev->link_list); } /* Ensure to re-program all MTRRs based on DRAM resource settings */ diff --git a/src/soc/intel/common/block/include/intelblocks/mp_init.h b/src/soc/intel/common/block/include/intelblocks/mp_init.h index 1e5531c..7118d70 100644 --- a/src/soc/intel/common/block/include/intelblocks/mp_init.h +++ b/src/soc/intel/common/block/include/intelblocks/mp_init.h @@ -62,7 +62,7 @@ * In this function SOC must perform CPU feature programming * during Ramstage phase. */ -void soc_core_init(device_t dev, const void *microcode); +void soc_core_init(device_t dev); /* * In this function SOC must fill required mp_ops params, also it @@ -72,6 +72,6 @@ * Also, if there is any other SOC specific functionalities to be * implemented before or after MP Init, it can be done here. */ -void soc_init_cpus(struct bus *cpu_bus, const void *microcode); +void soc_init_cpus(struct bus *cpu_bus); #endif /* SOC_INTEL_COMMON_BLOCK_MP_INIT_H */ diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e20e5a0..9ade614 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -407,7 +407,7 @@ } /* All CPUs including BSP will run the following function. */ -void soc_core_init(device_t cpu, const void *microcode) +void soc_core_init(device_t cpu) { /* Clear out pending MCEs */ configure_mca(); @@ -491,7 +491,7 @@ .post_mp_init = post_mp_init, }; -void soc_init_cpus(struct bus *cpu_bus, const void *microcode) +void soc_init_cpus(struct bus *cpu_bus) { if (mp_init_with_smm(cpu_bus, &mp_ops)) printk(BIOS_ERR, "MP initialization failure.\n"); -- To view, visit https://review.coreboot.org/21010 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b Gerrit-Change-Number: 21010 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/common/sgx: Use data pointer of device_t to get microcode
by Pratikkumar V Prajapati (Code Review) 14 Aug '17

14 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21009 Change subject: intel/common/sgx: Use data pointer of device_t to get microcode ...................................................................... intel/common/sgx: Use data pointer of device_t to get microcode Get microcode patch pointer from device_t struct of CPU. Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/sgx.c 2 files changed, 12 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/21009/1 diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index cc2dc7f..9929f0f 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -25,7 +25,7 @@ /* * Configure SGX. */ -void sgx_configure(const void *microcode_patch); +void sgx_configure(void); /* * Configure core PRMRR diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 53a68cf..55cb272 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <console/console.h> #include <chip.h> #include <cpu/x86/msr.h> @@ -156,13 +157,20 @@ return 0; } -void sgx_configure(const void *microcode_patch) +void sgx_configure(void) { - device_t dev = SA_DEV_ROOT; + device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + assert(dev != NULL); + config_t *conf = dev->chip_info; if (!conf->sgx_enable || !is_sgx_supported() || !is_prmrr_set()) { printk(BIOS_ERR, "SGX: pre-conditions not met\n"); + return; + } + + if (!dev->data) { + printk(BIOS_ERR, "SGX: microcode not set in device struct\n"); return; } @@ -177,7 +185,7 @@ cpu_lock_sgx_memory(); /* Reload the microcode patch */ - intel_microcode_load_unlocked(microcode_patch); + intel_microcode_load_unlocked(dev->data); /* Lock the SGX feature */ lock_sgx(); -- To view, visit https://review.coreboot.org/21009 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799 Gerrit-Change-Number: 21009 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: device_t struct: Introduce device specific data field
by Pratikkumar V Prajapati (Code Review) 14 Aug '17

14 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21008 Change subject: device_t struct: Introduce device specific data field ...................................................................... device_t struct: Introduce device specific data field Let device store anything it needs. For CPU, data pointer would store microcode patch address (MP init code sets it now). This would be efficient as, device_t can be located easily and its data can be accessed. e.g. to get microcode patch address for CPU device device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); and then dev->data can be used, rather than loading microcode each time from boot media. Change-Id: I7e377621dd9c00388c4e148c451f9e01cb7fe4fa Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/include/device/device.h M src/soc/intel/common/block/cpu/mp_init.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/21008/1 diff --git a/src/include/device/device.h b/src/include/device/device.h index 54d4ec3..04962dd 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -146,6 +146,7 @@ const char *name; #endif DEVTREE_CONST void *chip_info; + const void *data; /* device specific data. Store anything you want */ }; /** diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index fd8b5db..7e57b79 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -102,7 +102,7 @@ */ void get_microcode_info(const void **microcode, int *parallel) { - *microcode =microcode_patch; + *microcode = microcode_patch; *parallel = 1; } @@ -114,6 +114,7 @@ microcode_patch = intel_microcode_find(); intel_microcode_load_unlocked(microcode_patch); + dev->data = microcode_patch; /* * TODO: This parameter "microcode_patch" should be removed * in this function call once the following two cases are resolved - -- To view, visit https://review.coreboot.org/21008 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e377621dd9c00388c4e148c451f9e01cb7fe4fa Gerrit-Change-Number: 21008 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Fix SGX init sequence.
by Pratikkumar V Prajapati (Code Review) 14 Aug '17

14 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21007 Change subject: soc/intel/skylake: Fix SGX init sequence. ...................................................................... soc/intel/skylake: Fix SGX init sequence. Configure core PRMRR first on all the cores and then follow the SGX init sequence. Second microcode load would run the MCHECK. To pass MCHECK, PRMRR on all cores needs to be configured first. Hence, PRMRR configuration would be called from soc_core_init while MP init for each core and then from soc_init_cpus, BSP would call sgx_configure for each core (including for itself). This code flow satisfies the MCHECK passing pre-conditions; and apparently this patch fixes the behavior of calling configure_sgx() “again” for BSP. (So removed the TODO comment also). Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/skylake/cpu.c 1 file changed, 3 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/21007/1 diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 1a08191..e20e5a0 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -437,8 +437,8 @@ /* Enable Turbo */ enable_turbo(); - /* Configure SGX */ - sgx_configure(microcode); + /* Configure Core PRMRR for SGX. */ + prmrr_core_configure(); } static int adjust_apic_id(int index, int apic_id) @@ -499,13 +499,7 @@ /* Thermal throttle activation offset */ configure_thermal_target(); - /* - * TODO: somehow calling configure_sgx() in cpu_core_init() is not - * successful on the BSP (other threads are fine). Have to run it again - * here to get SGX enabled on BSP. This behavior needs to root-caused - * and we shall not have this redundant call. - */ - sgx_configure(microcode); + mp_run_on_all_cpus(sgx_configure, 2000); } int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) -- To view, visit https://review.coreboot.org/21007 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1 Gerrit-Change-Number: 21007 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: intel/common/block/sgx: Refactor SGX common code.
by Pratikkumar V Prajapati (Code Review) 14 Aug '17

14 Aug '17

Pratikkumar V Prajapati has uploaded this change for review. ( https://review.coreboot.org/21006 Change subject: intel/common/block/sgx: Refactor SGX common code. ...................................................................... intel/common/block/sgx: Refactor SGX common code. To correct the SGX init sequence; PRMRR on all cores first needs to be set, then follow the SGX init sequence. This patch would refactor the common SGX code (and add needed checks in the init sequence) so that SOC specific code can call SGX init in correct order. Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/sgx.h M src/soc/intel/common/block/sgx/sgx.c 2 files changed, 47 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/21006/1 diff --git a/src/soc/intel/common/block/include/intelblocks/sgx.h b/src/soc/intel/common/block/include/intelblocks/sgx.h index 03d4ab5..cc2dc7f 100644 --- a/src/soc/intel/common/block/include/intelblocks/sgx.h +++ b/src/soc/intel/common/block/include/intelblocks/sgx.h @@ -27,4 +27,9 @@ */ void sgx_configure(const void *microcode_patch); +/* + * Configure core PRMRR + */ +void prmrr_core_configure(void); + #endif /* SOC_INTEL_COMMON_BLOCK_SGX_H */ diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c index 5a0b61d..53a68cf 100644 --- a/src/soc/intel/common/block/sgx/sgx.c +++ b/src/soc/intel/common/block/sgx/sgx.c @@ -33,11 +33,16 @@ return ((cpuid_regs.ebx & SGX_SUPPORTED) && (msr.lo & PRMRR_SUPPORTED)); } -static int configure_core_prmrr(void) +void prmrr_core_configure(void) { msr_t prmrr_base; msr_t prmrr_mask; msr_t msr; + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + + if (!conf->sgx_enable || !is_sgx_supported()) + return; /* * PRMRR base and mask are read from the UNCORE PRMRR MSRs @@ -47,13 +52,13 @@ prmrr_mask = rdmsr(UNCORE_PRMRR_PHYS_MASK_MSR); if (!prmrr_base.lo) { printk(BIOS_ERR, "SGX Error: Uncore PRMRR is not set!\n"); - return -1; + return; } msr = rdmsr(PRMRR_PHYS_MASK_MSR); /* If it is locked don't attempt to write PRMRR MSRs. */ if (msr.lo & PRMRR_PHYS_MASK_LOCK) - return 0; + return; /* Program core PRMRR MSRs */ prmrr_base.lo |= MTRR_TYPE_WRBACK; /* cache writeback mem attrib */ @@ -61,7 +66,20 @@ prmrr_mask.lo &= ~PRMRR_PHYS_MASK_VALID; /* Do not set the valid bit */ prmrr_mask.lo |= PRMRR_PHYS_MASK_LOCK; /* Lock it */ wrmsr(PRMRR_PHYS_MASK_MSR, prmrr_mask); - return 0; +} + +static int is_prmrr_set(void) +{ + msr_t prmrr_base, prmrr_mask; + prmrr_base = rdmsr(PRMRR_PHYS_BASE_MSR); + prmrr_mask = rdmsr(PRMRR_PHYS_MASK_MSR); + + /* if PRMRR base is zero and PRMRR mask is locked + then PRMRR is not set */ + if (prmrr_base.hi && prmrr_base.lo + && (prmrr_mask.lo & PRMRR_PHYS_MASK_LOCK)) + return 0; + return 1; } static void enable_sgx(void) @@ -125,17 +143,28 @@ } } +static int is_prmrr_approved(void) +{ + msr_t msr; + msr = rdmsr(PRMRR_PHYS_MASK_MSR); + if (msr.lo & PRMRR_PHYS_MASK_VALID) { + printk(BIOS_INFO, "SGX: MCHECK aprroved SGX PRMRR\n"); + return 1; + } + + printk(BIOS_INFO, "SGX: MCHECK didnot aprrove SGX PRMRR\n"); + return 0; +} + void sgx_configure(const void *microcode_patch) { device_t dev = SA_DEV_ROOT; config_t *conf = dev->chip_info; - if (!conf->sgx_enable || !is_sgx_supported()) + if (!conf->sgx_enable || !is_sgx_supported() || !is_prmrr_set()) { + printk(BIOS_ERR, "SGX: pre-conditions not met\n"); return; - - /* Initialize PRMRR core MSRs */ - if (configure_core_prmrr() < 0) - return; + } /* Enable the SGX feature */ enable_sgx(); @@ -153,6 +182,8 @@ /* Lock the SGX feature */ lock_sgx(); - /* Activate the SGX feature */ - activate_sgx(); + /* Activate the SGX feature, if PRMRR configuration + was aprroved by MCHECK */ + if (is_prmrr_approved()) + activate_sgx(); } -- To view, visit https://review.coreboot.org/21006 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad Gerrit-Change-Number: 21006 Gerrit-PatchSet: 1 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com>

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Change in coreboot[master]: drivers/ics954309: conditionalize clockgen setup
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21005 ) Change subject: drivers/ics954309: conditionalize clockgen setup ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58545/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13942/ : SUCCESS -- To view, visit https://review.coreboot.org/21005 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib17a67a31658256040d63cd45b354c1dfced952a Gerrit-Change-Number: 21005 Gerrit-PatchSet: 1 Gerrit-Owner: Andrey Korolyov <andrey(a)xdel.ru> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 20:52:59 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017