coreboot-gerrit August 2017

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Change in coreboot[master]: soc/intel/skylake: Fix gpio pad reset config discrepency
by Subrata Banik (Code Review) 14 Aug '17

14 Aug '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/20993 ) Change subject: soc/intel/skylake: Fix gpio pad reset config discrepency ...................................................................... Patch Set 1: Rizwan, i guess macros has some issue. -- To view, visit https://review.coreboot.org/20993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c Gerrit-Change-Number: 20993 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 06:20:33 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20539 ) Change subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58518/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13918/ : SUCCESS -- To view, visit https://review.coreboot.org/20539 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Gerrit-Change-Number: 20539 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 06:19:07 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Fix gpio pad reset config discrepency
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20993 ) Change subject: soc/intel/skylake: Fix gpio pad reset config discrepency ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/58519/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/13919/ : SUCCESS -- To view, visit https://review.coreboot.org/20993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c Gerrit-Change-Number: 20993 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Youness Alaoui <snifikino(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 06:19:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/intel/rvp7: use the correct pad reset config for GPP
by Rizwan Qureshi (Code Review) 14 Aug '17

14 Aug '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/20995 Change subject: mb/intel/rvp7: use the correct pad reset config for GPP ...................................................................... mb/intel/rvp7: use the correct pad reset config for GPP GPIO pad reset configs for GPP and GPD pads are not same and SoC definitions have been updated use the appropriate one. Change-Id: I7720ddd3ef6749610411ecf33a56c0c24994fdfc Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/20995/1 diff --git a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h index 2233339..7aaed9a 100644 --- a/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h +++ b/src/mainboard/intel/kblrvp/variants/rvp7/include/variant/gpio.h @@ -64,7 +64,7 @@ /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* PCH_CLK_PCI_TPM */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* PCH_LPC_CLK */ PAD_CFG_GPI_APIC(GPP_A11, NONE, DEEP), -/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, RSMRST), +/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 1, GPP_RSMRST), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), @@ -144,7 +144,7 @@ /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, 20K_PD, DEEP), /* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), -/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, RSMRST), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, GPP_RSMRST), /* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* SATA_DEVSLP2 */ PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), -- To view, visit https://review.coreboot.org/20995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7720ddd3ef6749610411ecf33a56c0c24994fdfc Gerrit-Change-Number: 20995 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: mb/google/soraka: GPIO config should not reset during warm reset
by Rizwan Qureshi (Code Review) 14 Aug '17

14 Aug '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/20994 Change subject: mb/google/soraka: GPIO config should not reset during warm reset ...................................................................... mb/google/soraka: GPIO config should not reset during warm reset Setting GPIO pad reset config to DEEP will reset te gpio configuration across warm reset, set it to RSMRST to preserve the configuration. Also, GPIO pad reset configs for GPP and GPD pads are not same and SoC definitions have been updated use the appropriate one. BUG=b:64386481 Change-Id: If32f839144b9201dc23e95c7572b595a70248286 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/mainboard/google/poppy/variants/soraka/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/20994/1 diff --git a/src/mainboard/google/poppy/variants/soraka/gpio.c b/src/mainboard/google/poppy/variants/soraka/gpio.c index 6e0a54f..313378c 100644 --- a/src/mainboard/google/poppy/variants/soraka/gpio.c +++ b/src/mainboard/google/poppy/variants/soraka/gpio.c @@ -370,7 +370,7 @@ /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { /* B8 : SRCCLKREQ3# ==> WLAN_PE_RST */ - PAD_CFG_GPO(GPP_B8, 0, DEEP), + PAD_CFG_GPO(GPP_B8, 0, GPP_RSMRST), #if IS_ENABLED(CONFIG_POPPY_USE_SPI_TPM) /* B15 : GSPI0_CS# ==> PCH_SPI_H1_3V3_CS_L */ -- To view, visit https://review.coreboot.org/20994 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: If32f839144b9201dc23e95c7572b595a70248286 Gerrit-Change-Number: 20994 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Fix gpio pad reset config discrepency
by Rizwan Qureshi (Code Review) 14 Aug '17

14 Aug '17

Rizwan Qureshi has uploaded this change for review. ( https://review.coreboot.org/20993 Change subject: soc/intel/skylake: Fix gpio pad reset config discrepency ...................................................................... soc/intel/skylake: Fix gpio pad reset config discrepency The pad reset config field values for RSMRST differ between GPP (Primary well GPIOs) and GPD (Deep Sleep Well GPIOs) pads. Currently same value (11b) is being used for both. To eliminate the confusion add separate macros for each config. BUG=b:64386481 TEST=Check if the pad config is repserved across reset when RSMRST is selected Change-Id: Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/soc/intel/skylake/include/soc/gpio_defs.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/20993/1 diff --git a/src/soc/intel/skylake/include/soc/gpio_defs.h b/src/soc/intel/skylake/include/soc/gpio_defs.h index 34461f2..90c54c5 100644 --- a/src/soc/intel/skylake/include/soc/gpio_defs.h +++ b/src/soc/intel/skylake/include/soc/gpio_defs.h @@ -224,7 +224,8 @@ #define PADRSTCFG_DSW_PWROK 0 #define PADRSTCFG_DEEP 1 #define PADRSTCFG_PLTRST 2 -#define PADRSTCFG_RSMRST 3 +#define PADRSTCFG_GPP_RSMRST 0 +#define PADRSTCFG_GPD_RSMRST 3 /* RXPADSTSEL - raw signal or internal state */ #define RXPADSTSEL_SHIFT 29 #define RXPADSTSEL_MASK 0x1 -- To view, visit https://review.coreboot.org/20993 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib5c2b90a5af022ceb7312ff56fa8b4cc31ef8b8c Gerrit-Change-Number: 20993 Gerrit-PatchSet: 1 Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20539 ) Change subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58517/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13917/ : SUCCESS -- To view, visit https://review.coreboot.org/20539 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Gerrit-Change-Number: 20539 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 05:55:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
by V Sowmya (Code Review) 14 Aug '17

14 Aug '17

V Sowmya has uploaded a new patch set (#1). ( https://review.coreboot.org/20539 ) Change subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros ...................................................................... soc/intel/apollolake: Rename SRAM BAR2 base and size macros Rename BAR2 SRAM base and size macros to align with the spec. * PMC_SRAM_BASE_1 -> PMC_SRAM_BASE_2 * PMC_SRAM_SIZE_1 -> PMC_SRAM_BASE_2 Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/sram.c 2 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20539/1 -- To view, visit https://review.coreboot.org/20539 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Gerrit-Change-Number: 20539 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros
by V Sowmya (Code Review) 14 Aug '17

14 Aug '17

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/20539 Change subject: soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros ...................................................................... soc/intel/apollolake: Rename SRAM BAR0 and BAR2 macros Rename BAR0 and BAR2 SRAM base and size macros to align with the spec. * PMC_SRAM_BASE_0 -> SRAM_BASE_0 * PMC_SRAM_SIZE_0 -> SRAM_BASE_0 * PMC_SRAM_BASE_1 -> SRAM_BASE_2 * PMC_SRAM_SIZE_1 -> SRAM_BASE_2 Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/sram.c 3 files changed, 11 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/20539/2 diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl index 8aeaef6..5c53af4 100644 --- a/src/soc/intel/apollolake/acpi/pmc_ipc.asl +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -52,9 +52,9 @@ Store (MCH_BASE_ADDRESS + MAILBOX_INTF, MIBA) CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) - Store (PMC_SRAM_BASE_0, SBAS) + Store (SRAM_BASE_0, SBAS) Return (^RBUF) } } -} \ No newline at end of file +} diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index a8e4bc9..c3eb66b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -39,10 +39,10 @@ #define PMC_BAR1 0xfe044000 #define PMC_BAR0_SIZE (8 * KiB) -#define PMC_SRAM_BASE_0 0xfe900000 -#define PMC_SRAM_SIZE_0 (8 * KiB) -#define PMC_SRAM_BASE_1 0xfe902000 -#define PMC_SRAM_SIZE_1 (4 * KiB) +#define SRAM_BASE_0 0xfe900000 +#define SRAM_SIZE_0 (8 * KiB) +#define SRAM_BASE_2 0xfe902000 +#define SRAM_SIZE_2 (4 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c index 0225327..70e1330 100644 --- a/src/soc/intel/apollolake/sram.c +++ b/src/soc/intel/apollolake/sram.c @@ -26,13 +26,13 @@ pci_dev_read_resources(dev); res = new_resource(dev, PCI_BASE_ADDRESS_0); - res->base = PMC_SRAM_BASE_0; - res->size = PMC_SRAM_SIZE_0; + res->base = SRAM_BASE_0; + res->size = SRAM_SIZE_0; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; res = new_resource(dev, PCI_BASE_ADDRESS_2); - res->base = PMC_SRAM_BASE_1; - res->size = PMC_SRAM_SIZE_1; + res->base = SRAM_BASE_2; + res->size = SRAM_SIZE_2; res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } @@ -51,7 +51,7 @@ pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_MEMORY; res->flags |= IORESOURCE_STORED; - report_resource_stored(dev, res, " SRAM BAR 1"); + report_resource_stored(dev, res, " SRAM BAR 2"); } static const struct device_operations device_ops = { -- To view, visit https://review.coreboot.org/20539 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I48d65c30368c4500549b535341b14ca262d7fc48 Gerrit-Change-Number: 20539 Gerrit-PatchSet: 2 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com>

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Change in coreboot[master]: payloads/Makefile.inc: Add GRUB2 to list of payloads
by build bot (Jenkins) (Code Review) 14 Aug '17

14 Aug '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/20992 ) Change subject: payloads/Makefile.inc: Add GRUB2 to list of payloads ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/58516/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/13916/ : SUCCESS -- To view, visit https://review.coreboot.org/20992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iea4a609631ac2007b7b1845ff540abc912004be0 Gerrit-Change-Number: 20992 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 14 Aug 2017 00:27:10 +0000 Gerrit-HasComments: No

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coreboot-gerrit August 2017