coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Add Intel common RTC code support
by Subrata Banik (Code Review) 31 Mar '17

31 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18558 ) Change subject: soc/intel/common/block: Add Intel common RTC code support ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/18558/4/src/soc/intel/common/block/rtc/rtc.c File src/soc/intel/common/block/rtc/rtc.c: PS4, Line 27: don't keep a API name with "soc" -- To view, visit https://review.coreboot.org/18558 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id9dfcdbc300c25f43936d1efb5d6f9d81d3c8453 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions
by HAOUAS Elyes (Code Review) 31 Mar '17

31 Mar '17

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 28: (2 comments) Please, why don't you use SPD-Byte 12 for Refresh Rate? https://review.coreboot.org/#/c/18305/28/src/northbridge/intel/i945/raminit… File src/northbridge/intel/i945/raminit.c: PS28, Line 454: 2 sorry, why is there an offset of 1 ? PS28, Line 564: sysinfo->refresh = 0; : if (max_tRR == 15625 * 256 / 2) { : sysinfo->refresh = 1; why don't you use SPD Byte 12: Refresh Rate? (JEDEC_DDR2_SPD_Specification_Rev1.3.pdf) -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 28 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Use intel/common/uart driver
by Subrata Banik (Code Review) 31 Mar '17

31 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19003 ) Change subject: soc/intel/skylake: Use intel/common/uart driver ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/#/c/19003/4/src/soc/intel/skylake/include/soc/b… File src/soc/intel/skylake/include/soc/bootblock.h: PS4, Line 29: soc_consol pch_uart_init looks much better -- To view, visit https://review.coreboot.org/19003 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id132df15ae5a6aef75d6434df18fc71d8d28c3ca Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code
by Subrata Banik (Code Review) 31 Mar '17

31 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18952 ) Change subject: soc/intel/common/block: Add Intel common UART code ...................................................................... Patch Set 7: (4 comments) https://review.coreboot.org/#/c/18952/7/src/soc/intel/common/block/include/… File src/soc/intel/common/block/include/intelblocks/uart.h: PS7, Line 4: Copyright 2017 Intel Corporation. header issue PS7, Line 21: soc_uart_init common code shouldn't have anything like "soc" https://review.coreboot.org/#/c/18952/7/src/soc/intel/common/block/uart/uar… File src/soc/intel/common/block/uart/uart.c: PS7, Line 20: device_t dev can't we have dev as local PS7, Line 33: /* Take UART out of reset */ : write32(base + LPSS_RESET_CTL_REG, LPSS_CNT_RST_RELEASE); : : /* Set M and N divisor inputs and enable clock */ : clk_sel = LPSS_CLOCK_DIV_N(clk_n_val) | LPSS_CLOCK_DIV_M(clk_m_val); : write32(base + LPSS_CLOCK_CTL_REG, clk_sel | LPSS_CNT_CLK_UPDATE); : write32(base + LPSS_CLOCK_CTL_REG, clk_sel | LPSS_CNT_CLOCK_EN); > Aren't these generic to all lpss blocks? including i2c and spi as well? If lets create a LPSS.c with a common LPSS block. then from i2c an spi, just API call -- To view, visit https://review.coreboot.org/18952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 31 Mar '17

31 Mar '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 17: (4 comments) https://review.coreboot.org/#/c/18557/17/src/soc/intel/common/block/fast_sp… File src/soc/intel/common/block/fast_spi/fast_spi.c: Line 22: > can we have some /*TODO*/ so that next time, when we create flash_ctrl.c as okay PS17, Line 155: device_t dev > can't we use device_t as local here after we have common pci_dev name? yes sure, will fix it. https://review.coreboot.org/#/c/18557/17/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/fast_spi.h: PS17, Line 4: Copyright 2017 Intel Corporation. > please adhere comments from Summet, missing (C) ok https://review.coreboot.org/#/c/18557/17/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/fast_spi_def.h: PS17, Line 4: * Copyright 2017 Intel Corporation. > -same ok -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Subrata Banik (Code Review) 31 Mar '17

31 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 17: (4 comments) https://review.coreboot.org/#/c/18557/17/src/soc/intel/common/block/fast_sp… File src/soc/intel/common/block/fast_spi/fast_spi.c: Line 22: can we have some /*TODO*/ so that next time, when we create flash_ctrl.c as library, we know what all code we need to remove and make as static to ensure user shouldn't know abut such functionality PS17, Line 155: device_t dev can't we use device_t as local here after we have common pci_dev name? https://review.coreboot.org/#/c/18557/17/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/fast_spi.h: PS17, Line 4: Copyright 2017 Intel Corporation. please adhere comments from Summet, missing (C) https://review.coreboot.org/#/c/18557/17/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/fast_spi_def.h: PS17, Line 4: * Copyright 2017 Intel Corporation. -same -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by build bot (Jenkins) (Code Review) 31 Mar '17

31 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 18: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50992/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6960/ : SUCCESS -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 18 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 31 Mar '17

31 Mar '17

Hello build bot (Jenkins), Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18557 to look at the new patch set (#18). Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... soc/intel/common/block: [WIP]Add Intel common FAST_SPI code Create Intel Common FAST_SPI Controller code. This code currently only contains the code for SPI initialization required in Bootblock phase, which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h More code will get added up in the subsequent phases. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- A src/soc/intel/common/block/fast_spi/Kconfig A src/soc/intel/common/block/fast_spi/Makefile.inc A src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/include/intelblocks/fast_spi.h A src/soc/intel/common/block/include/intelblocks/fast_spi_def.h 5 files changed, 371 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/18557/18 -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 18 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by build bot (Jenkins) (Code Review) 31 Mar '17

31 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 17: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50991/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6959/ : SUCCESS -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 31 Mar '17

31 Mar '17

Hello build bot (Jenkins), Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18557 to look at the new patch set (#17). Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... soc/intel/common/block: [WIP]Add Intel common FAST_SPI code Create Intel Common FAST_SPI Controller code. This code currently only contains the code for SPI initialization required in Bootblock phase, which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h More code will get added up in the subsequent phases. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- A src/soc/intel/common/block/fast_spi/Kconfig A src/soc/intel/common/block/fast_spi/Makefile.inc A src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/include/intelblocks/fast_spi.h A src/soc/intel/common/block/include/intelblocks/fast_spi_def.h 5 files changed, 369 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/18557/17 -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 17 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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coreboot-gerrit March 2017