March 2017 - coreboot-gerrit - mail.coreboot.org

Patch set updated for coreboot: mainboard/pcengines/apu2: Add LPC TPM support
by Philipp Deppenwiese Feb. 28, 2017

Feb. 28, 2017

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18523 -gerrit commit 3a26a9ec7e61d4009b46c542437078eb054d770a Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 1 02:37:36 2017 +0100 mainboard/pcengines/apu2: Add LPC TPM support APU2 exposes a LPC header which can be used in conjunction with a LPC TPM module. Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/pcengines/apu2/Kconfig | 1 + src/mainboard/pcengines/apu2/devicetree.cb | 8 +++++++- src/mainboard/pcengines/apu2/romstage.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 4303b84..cc815df 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select HUDSON_DISABLE_IMC select USE_BLOBS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..369150d 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -73,7 +73,13 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.607 off end device pnp 2e.e off end end # SIO NCT5104D - end # LPC 0x439d + chip drivers/pc80/tpm + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end # LPC TPM + end # LPC 0x439d device pci 14.7 on end # SD device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..cd3f6de 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -33,6 +33,8 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> +#include <tpm.h> + #include "gpio_ftns.h" static void early_lpc_init(void); @@ -106,6 +108,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

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Patch set updated for coreboot: mainboard/pcengines/apu2: Add LPC TPM support
by Philipp Deppenwiese Feb. 28, 2017

Feb. 28, 2017

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18523 -gerrit commit 6fca42bcfb8170c16ea105d5834001724da22188 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 1 02:37:36 2017 +0100 mainboard/pcengines/apu2: Add LPC TPM support APU2 exposes a LPC header which can be used in conjunction with a LPC TPM module. Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/pcengines/apu2/Kconfig | 1 + src/mainboard/pcengines/apu2/devicetree.cb | 8 +++++++- src/mainboard/pcengines/apu2/romstage.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 4303b84..cc815df 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select HUDSON_DISABLE_IMC select USE_BLOBS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..248b401 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -73,7 +73,13 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.607 off end device pnp 2e.e off end end # SIO NCT5104D - end # LPC 0x439d + chip drivers/pc80/tpm + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + end # LPC 0x439d device pci 14.7 on end # SD device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..d89dca2 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -33,6 +33,8 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> +#include <tpm.h> + #include "gpio_ftns.h" static void early_lpc_init(void); @@ -106,6 +108,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

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New patch to review for coreboot: mainboard/pcengines/apu2: Add LPC TPM support
by Philipp Deppenwiese Feb. 28, 2017

Feb. 28, 2017

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18523 -gerrit commit a3e6fb52977658191b955ac137fe7e25512ac110 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 1 02:37:36 2017 +0100 mainboard/pcengines/apu2: Add LPC TPM support APU2 exposes a LPC header which can be used in cojunction with a LPC TPM module. Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/pcengines/apu2/Kconfig | 1 + src/mainboard/pcengines/apu2/devicetree.cb | 8 +++++++- src/mainboard/pcengines/apu2/romstage.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 4303b84..cc815df 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select HUDSON_DISABLE_IMC select USE_BLOBS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..248b401 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -73,7 +73,13 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.607 off end device pnp 2e.e off end end # SIO NCT5104D - end # LPC 0x439d + chip drivers/pc80/tpm + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end + end # LPC 0x439d device pci 14.7 on end # SD device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..d89dca2 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -33,6 +33,8 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> +#include <tpm.h> + #include "gpio_ftns.h" static void early_lpc_init(void); @@ -106,6 +108,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } +#if CONFIG_LPC_TPM + init_tpm(s3resume); +#endif + outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

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New patch to review for coreboot: amd/pi: Add AMD fam16h TPM acpi path support
by Philipp Deppenwiese Feb. 28, 2017

Feb. 28, 2017

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18522 -gerrit commit 4e7f706c57a6ce8a1c013c82f8c90e08fd6f093d Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 1 02:24:33 2017 +0100 amd/pi: Add AMD fam16h TPM acpi path support Change-Id: I5322d731a0dc655f2da14b87fa6cbc1e54b5abd5 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/northbridge/amd/pi/00730F01/northbridge.c | 9 +++++++++ src/southbridge/amd/pi/hudson/lpc.c | 16 ++++++++++++++++ src/southbridge/amd/pi/hudson/pci_devs.h | 1 + 3 files changed, 26 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index ed8e17a..3a2f730 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -864,6 +864,14 @@ static void domain_set_resources(device_t dev) } } +static const char *domain_acpi_name(struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = domain_read_resources, .set_resources = domain_set_resources, @@ -871,6 +879,7 @@ static struct device_operations pci_domain_ops = { .init = NULL, .scan_bus = pci_domain_scan_bus, .ops_pci_bus = pci_bus_default_ops, + .acpi_name = domain_acpi_name, }; static void sysconf_init(device_t dev) // first node diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 1dacfd0..061008d 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -29,6 +29,7 @@ #include <pc80/i8254.h> #include <pc80/i8259.h> #include "hudson.h" +#include "pci_devs.h" static void lpc_init(device_t dev) { @@ -324,6 +325,20 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } +static const char *lpc_acpi_name(struct device *dev) +{ + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + /* DSDT: acpi/lpc.asl */ + case LPC_DEVFN: + return "LIBR"; + } + + return NULL; +} + static struct pci_operations lops_pci = { .set_subsystem = pci_dev_set_subsystem, }; @@ -338,6 +353,7 @@ static struct device_operations lpc_ops = { .init = lpc_init, .scan_bus = scan_lpc_bus, .ops_pci = &lops_pci, + .acpi_name = lpc_acpi_name, }; static const unsigned short pci_device_ids[] = { diff --git a/src/southbridge/amd/pi/hudson/pci_devs.h b/src/southbridge/amd/pi/hudson/pci_devs.h index 2caa44c..1dd2f39 100644 --- a/src/southbridge/amd/pi/hudson/pci_devs.h +++ b/src/southbridge/amd/pi/hudson/pci_devs.h @@ -86,6 +86,7 @@ /* LPC BUS */ #define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV #define LPC_FUNC 3 #define LPC_DEVID 0x780E #define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC)

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New patch to review for coreboot: acpi: Update the ACPI ID for coreboot
by Duncan Laurie Feb. 28, 2017

Feb. 28, 2017

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18521 -gerrit commit 73a6ee1d7bf5fd5df76387657330d8604bef49bf Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Feb 28 16:58:06 2017 -0800 acpi: Update the ACPI ID for coreboot The newly assigned ACPI ID for coreboot is 'BOOT' http://www.uefi.org/acpi_id_list Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific ACPI objects instead of the placeholder range of "GOOGCBxx". Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/arch/x86/include/arch/acpi.h | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 9dfbe2f..a767a45 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -53,13 +53,16 @@ #define OEM_ID "CORE " /* Must be exactly 6 bytes long! */ #define ASLC "CORE" /* Must be exactly 4 bytes long! */ -/* Use GOOGCBxx range until coreboot ID is official */ -#define COREBOOT_ACPI_ID "GOOG" /* ACPI ID for coreboot HIDs */ +/* + * The assigned ACPI ID for the coreboot project is 'BOOT' + * http://www.uefi.org/acpi_id_list + */ +#define COREBOOT_ACPI_ID "BOOT" /* ACPI ID for coreboot HIDs */ /* List of ACPI HID that use the coreboot ACPI ID */ enum coreboot_acpi_ids { - COREBOOT_ACPI_ID_CBTABLE = 0xCB00, /* GOOGCB00 */ - COREBOOT_ACPI_ID_MAX = 0xCBFF, /* GOOGCBFF */ + COREBOOT_ACPI_ID_CBTABLE = 0x0000, /* BOOT0000 */ + COREBOOT_ACPI_ID_MAX = 0xFFFF, /* BOOTFFFF */ }; /* RSDP (Root System Description Pointer) */

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