coreboot-gerrit March 2017

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New patch to review for coreboot: [NOTFORMERGE] binaryPI: Redo CAR teardown with empty stack
by Kyösti Mälkki 01 Mar '17

01 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18525 -gerrit commit e307fe36db57bec69e33bfd86919a46caa449e21 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 11:33:05 2017 +0200 [NOTFORMERGE] binaryPI: Redo CAR teardown with empty stack This is squashed set of commits for amd/agesa/cache_as_ram.inc that have not yet landed. Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/cache_as_ram.inc | 92 +++++++++++++++++------------------------ 1 file changed, 37 insertions(+), 55 deletions(-) diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 24db600..f43e6a4 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -26,43 +26,24 @@ #include "gcccar.inc" #include <cpu/x86/cache.h> -/* - * XMM map: - * xmm0: BIST - * xmm1: backup ebx -- cpu_init_detected - */ - .code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup, cache_as_ram_setup_out cache_as_ram_setup: - post_code(0xa0) - - /* enable SSE2 128bit instructions */ - /* Turn on OSFXSR [BIT9] and OSXMMEXCPT [BIT10] onto CR4 register */ - - movl %cr4, %eax - orl $(3<<9), %eax - movl %eax, %cr4 - - /* Get the cpu_init_detected */ - mov $1, %eax - cpuid - shr $24, %ebx - - /* Save the BIST result */ - cvtsi2sd %ebp, %xmm0 - - /* for normal part %ebx already contain cpu_init_detected from fallback call */ + /* Preserve BIST. */ + movl %eax, %ebp - /* Save the cpu_init_detected */ - cvtsi2sd %ebx, %xmm1 + post_code(0xa0) post_code(0xa1) + /* NOTE: %ebx, %ebp are preserved in AMD_ENABLE_STACK. */ AMD_ENABLE_STACK + /* Align the stack to 128 bits. No harm on i386, required on x86_64? */ + and $0xFFFFFFF0, %esp + #ifdef __x86_64__ /* switch to 64 bit long mode */ mov %esi, %ecx @@ -105,42 +86,36 @@ cache_as_ram_setup: # use call far to switch to 64-bit code segment ljmp $0x18, $1f 1: - /* Pass the cpu_init_detected */ - cvtsd2si %xmm1, %esi - /* Pass the BIST result */ - cvtsd2si %xmm0, %edi + .code64 + + /* Calling conventions preserve BIST in %ebp. */ - /* align the stack */ - and $0xFFFFFFF0, %esp + call early_all_cores + + movl %ebp, %edi + call romstage_main + movl %eax, %ebx - .code64 - call cache_as_ram_main .code32 #else - /* Restore the BIST result */ - cvtsd2si %xmm0, %edx + /* Calling conventions preserve BIST in %ebp. */ - /* Restore the cpu_init_detected */ - cvtsd2si %xmm1, %ebx + call early_all_cores + + pushl %ebp + call romstage_main + movl %eax, %ebx - pushl %ebx /* init detected */ - pushl %edx /* bist */ - call cache_as_ram_main #endif - /* Should never see this postcode */ - post_code(0xaf) -stop: - jmp stop +/* Register %ebx is new stacktop for remaining of romstage. + * It is the only register preserved in AMD_DISABLE_STACK. + */ disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - /* Disable cache */ movl %cr0, %eax orl $CR0_CacheDisable, %eax @@ -152,13 +127,20 @@ disable_cache_as_ram: movl %cr0, %eax andl $0x9fffffff, %eax movl %eax, %cr0 - xorl %eax, %eax - /* Restore the return stack */ wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret + +#ifdef __x86_64__ +.code64 +#endif + + movl %ebx, %esp + call romstage_after_car + + /* Should never see this postcode */ + post_code(0xaf) +stop: + jmp stop cache_as_ram_setup_out: #ifdef __x86_64__

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Patch set updated for coreboot: binaryPI platforms: Drop any ACPI S3 support
by Kyösti Mälkki 01 Mar '17

01 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18501 -gerrit commit 3bf90dc9b63bc985a84c37800bdf1aded78fc775 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 10:18:45 2017 +0200 binaryPI platforms: Drop any ACPI S3 support No board with binaryPI currently supports HAVE_ACPI_RESUME. For platforms with PSP the approach is also very different from what we previously had here. Furthermore, s3_resume.[ch] files under cpu/amd/pi do not distinguish between NonVolatile and Volatile buffers of S3 storage. This means the Volatile buffer that is maintained and available in CBMEM is unnecessarily copied to SPI flash. This has been fixed on open-source AGESA directory, so development of S3 suspend support with binaryPI is better continued with that. Unfortunately there are further complications and indications that open-source AGESA may have always had a low-memory corruption issue. This has to be investigated separately before restoring or claiming S3 is supported on binaryPI. Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/pi/00630F01/model_15_init.c | 4 - src/cpu/amd/pi/00660F01/model_15_init.c | 4 - src/cpu/amd/pi/00670F00/model_15_init.c | 4 - src/cpu/amd/pi/00730F01/model_16_init.c | 4 - src/cpu/amd/pi/Makefile.inc | 17 -- src/cpu/amd/pi/s3_resume.c | 293 -------------------------------- src/cpu/amd/pi/s3_resume.h | 37 ---- src/northbridge/amd/pi/agesawrapper.c | 213 ----------------------- 8 files changed, 576 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/model_15_init.c b/src/cpu/amd/pi/00630F01/model_15_init.c index afbade4..925c60c 100644 --- a/src/cpu/amd/pi/00630F01/model_15_init.c +++ b/src/cpu/amd/pi/00630F01/model_15_init.c @@ -30,7 +30,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> static void model_15_init(device_t dev) { @@ -65,9 +64,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c index e252c3d..c31dec8 100644 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ b/src/cpu/amd/pi/00660F01/model_15_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> #include <amdlib.h> #include <PspBaseLib.h> @@ -80,9 +79,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index dd1c8e3..02e5b79 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam15.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> #include <amdlib.h> #include <PspBaseLib.h> @@ -80,9 +79,6 @@ static void model_15_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index a9751a2..294814f 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -29,7 +29,6 @@ #include <cpu/x86/mtrr.h> #include <cpu/amd/amdfam16.h> #include <arch/acpi.h> -#include <cpu/amd/pi/s3_resume.h> static void model_16_init(device_t dev) { @@ -63,9 +62,6 @@ static void model_16_init(device_t dev) msr.lo |= SYSCFG_MSR_MtrrFixDramEn; wrmsr(SYSCFG_MSR, msr); - if (acpi_is_wakeup()) - restore_mtrr(); - x86_mtrr_check(); x86_enable_cache(); diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 0e31d9f..3dcbbc3 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,8 +18,6 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 -romstage-y += s3_resume.c -ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc @@ -27,18 +25,3 @@ cpu_incs-y += $(src)/cpu/amd/pi/cache_as_ram.inc romstage-y += heapmanager.c ramstage-y += heapmanager.c ramstage-y += amd_late_init.c - -ifeq ($(CONFIG_HAVE_ACPI_RESUME), y) - -$(obj)/coreboot_s3nv.rom: $(obj)/config.h - echo " S3 NVRAM $(CONFIG_S3_DATA_POS) (S3 storage area)" - # force C locale, so cygwin awk doesn't try to interpret the 0xff below as UTF-8 (or worse) - printf %d $(CONFIG_S3_DATA_SIZE) | LC_ALL=C awk '{for (i=0; i<$$1; i++) {printf "%c", 255}}' > $@.tmp - mv $@.tmp $@ - -cbfs-files-y += s3nv -s3nv-file := $(obj)/coreboot_s3nv.rom -s3nv-position := $(CONFIG_S3_DATA_POS) -s3nv-type := raw - -endif # CONFIG_HAVE_ACPI_RESUME == y diff --git a/src/cpu/amd/pi/s3_resume.c b/src/cpu/amd/pi/s3_resume.c deleted file mode 100644 index 338f921..0000000 --- a/src/cpu/amd/pi/s3_resume.c +++ /dev/null @@ -1,293 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2012 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <AGESA.h> -#include <Lib/amdlib.h> -#include <console/console.h> -#include <cpu/x86/msr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/amd/car.h> -#include <cpu/amd/mtrr.h> -#include <cpu/x86/cache.h> -#include <cbmem.h> -#include <device/device.h> -#include <arch/io.h> -#include <arch/acpi.h> -#include <program_loading.h> -#include <string.h> -#include "Porting.h" -#include <northbridge/amd/pi/BiosCallOuts.h> -#include <halt.h> -#include "s3_resume.h" - -/* The size needs to be 4k aligned, which is the sector size of most flashes. */ -#define S3_DATA_VOLATILE_SIZE 0x6000 -#define S3_DATA_MTRR_SIZE 0x1000 -#define S3_DATA_NONVOLATILE_SIZE 0x1000 - -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) && \ - (S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE + S3_DATA_NONVOLATILE_SIZE) > CONFIG_S3_DATA_SIZE -#error "Please increase the value of S3_DATA_SIZE" -#endif - -static void get_s3nv_data(S3_DATA_TYPE S3DataType, u32 *pos, u32 *len) -{ - /* FIXME: Find file from CBFS. */ - u32 s3_data = CONFIG_S3_DATA_POS; - - switch (S3DataType) { - case S3DataTypeVolatile: - *pos = s3_data; - *len = S3_DATA_VOLATILE_SIZE; - break; - case S3DataTypeMTRR: - *pos = s3_data + S3_DATA_VOLATILE_SIZE; - *len = S3_DATA_MTRR_SIZE; - break; - case S3DataTypeNonVolatile: - *pos = s3_data + S3_DATA_VOLATILE_SIZE + S3_DATA_MTRR_SIZE; - *len = S3_DATA_NONVOLATILE_SIZE; - break; - default: - *pos = 0; - *len = 0; - break; - } -} - -void restore_mtrr(void) -{ - u32 msr; - volatile UINT32 *msrPtr; - msr_t msr_data; - - printk(BIOS_SPEW, "%s\n", __func__); - - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - msrPtr = (UINT32 *)(pos + sizeof(UINT32)); - - disable_cache(); - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Now restore the Fixed MTRRs */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x250, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x258, msr_data); - - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(0x259, msr_data); - - for (msr = 0x268; msr <= 0x26F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Restore the Variable MTRRs */ - for (msr = 0x200; msr <= 0x20F; msr++) { - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(msr, msr_data); - } - - /* Restore SYSCFG MTRR */ - msr_data.lo = *msrPtr; - msrPtr ++; - msr_data.hi = *msrPtr; - msrPtr ++; - wrmsr(SYS_CFG, msr_data); -} - -#ifdef __PRE_RAM__ -static void move_stack_high_mem(void) -{ - uintptr_t high_stack = romstage_ram_stack_base(HIGH_ROMSTAGE_STACK_SIZE, - ROMSTAGE_STACK_CBMEM); - if (!high_stack) - halt(); - - /* TODO: Make the switch with empty stack instead. */ - memcpy((void*)high_stack, (void *)BSP_STACK_BASE_ADDR, HIGH_ROMSTAGE_STACK_SIZE); - -#ifdef __x86_64__ - __asm__ - volatile ("add %0, %%rsp; add %0, %%rbp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#else - __asm__ - volatile ("add %0, %%esp; add %0, %%ebp; invd"::"g" - (high_stack - BSP_STACK_BASE_ADDR) - :); -#endif -} -#endif - -#ifndef __PRE_RAM__ -/* FIXME: Why store MTRR in SPI, just use CBMEM ? */ -static u8 mtrr_store[S3_DATA_MTRR_SIZE]; - -static void write_mtrr(u8 **p_nvram_pos, unsigned idx) -{ - msr_t msr_data; - msr_data = rdmsr(idx); - - memcpy(*p_nvram_pos, &msr_data, sizeof(msr_data)); - *p_nvram_pos += sizeof(msr_data); -} - -void OemAgesaSaveMtrr(void) -{ - msr_t msr_data; - u32 i; - - u8 *nvram_pos = (u8 *) mtrr_store; - - /* Enable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo |= SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Fixed MTRRs */ - write_mtrr(&nvram_pos, 0x250); - write_mtrr(&nvram_pos, 0x258); - write_mtrr(&nvram_pos, 0x259); - - for (i = 0x268; i < 0x270; i++) - write_mtrr(&nvram_pos, i); - - /* Disable access to AMD RdDram and WrDram extension bits */ - msr_data = rdmsr(SYS_CFG); - msr_data.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - wrmsr(SYS_CFG, msr_data); - - /* Variable MTRRs */ - for (i = 0x200; i < 0x210; i++) - write_mtrr(&nvram_pos, i); - - /* SYS_CFG */ - write_mtrr(&nvram_pos, 0xC0010010); - /* TOM */ - write_mtrr(&nvram_pos, 0xC001001A); - /* TOM2 */ - write_mtrr(&nvram_pos, 0xC001001D); - -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataTypeMTRR, &pos, &size); - spi_SaveS3info(pos, size, mtrr_store, nvram_pos - (u8 *) mtrr_store); -#endif -} - -u32 OemAgesaSaveS3Info(S3_DATA_TYPE S3DataType, u32 DataSize, void *Data) -{ -#if IS_ENABLED(CONFIG_SPI_FLASH) - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - spi_SaveS3info(pos, size, Data, DataSize); -#endif - return AGESA_SUCCESS; -} -#endif - -void OemAgesaGetS3Info(S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data) -{ - AMD_CONFIG_PARAMS StdHeader; - - u32 pos, size; - get_s3nv_data(S3DataType, &pos, &size); - - if (S3DataType == S3DataTypeNonVolatile) { - *DataSize = *(UINT32 *) pos; - *Data = (void *) (pos + sizeof(UINT32)); - } else if (S3DataType == S3DataTypeVolatile) { - u32 len = *(UINT32 *) pos; - void *src = (void *) (pos + sizeof(UINT32)); - void *dst = (void *) GetHeapBase(&StdHeader); - memcpy(dst, src, len); - *DataSize = len; - *Data = dst; - } -} - -#ifdef __PRE_RAM__ -static void set_resume_cache(void) -{ - msr_t msr; - - /* disable fixed mtrr for now, it will be enabled by mtrr restore */ - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~(SYSCFG_MSR_MtrrFixDramEn | SYSCFG_MSR_MtrrFixDramModEn); - wrmsr(SYSCFG_MSR, msr); - - /* Enable cached access to RAM in the range 0M to CACHE_TMP_RAMTOP */ - msr.lo = 0 | MTRR_TYPE_WRBACK; - msr.hi = 0; - wrmsr(MTRR_PHYS_BASE(0), msr); - msr.lo = ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID; - msr.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(0), msr); - - /* Set the default memory type and disable fixed and enable variable MTRRs */ - msr.hi = 0; - msr.lo = (1 << 11); - wrmsr(MTRR_DEF_TYPE_MSR, msr); - - enable_cache(); -} - -void prepare_for_resume(void) -{ - if (cbmem_recovery(1)) { - printk(BIOS_EMERG, "Unable to recover CBMEM\n"); - halt(); - } - - post_code(0x62); - printk(BIOS_DEBUG, "Move CAR stack.\n"); - move_stack_high_mem(); - - post_code(0x63); - disable_cache_as_ram(); - printk(BIOS_DEBUG, "CAR disabled.\n"); - set_resume_cache(); - -} -#endif diff --git a/src/cpu/amd/pi/s3_resume.h b/src/cpu/amd/pi/s3_resume.h deleted file mode 100644 index c23c662..0000000 --- a/src/cpu/amd/pi/s3_resume.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef S3_RESUME_H -#define S3_RESUME_H - -typedef enum { - S3DataTypeNonVolatile=0, ///< NonVolatile Data Type - S3DataTypeVolatile, ///< Volatile Data Type - S3DataTypeMTRR ///< MTRR storage -} S3_DATA_TYPE; - -void restore_mtrr(void); -void prepare_for_resume(void); - -u32 OemAgesaSaveS3Info (S3_DATA_TYPE S3DataType, u32 DataSize, void *Data); -void OemAgesaGetS3Info (S3_DATA_TYPE S3DataType, u32 *DataSize, void **Data); -void OemAgesaSaveMtrr (void); - -void spi_SaveS3info(u32 pos, u32 size, u8 *buf, u32 len); - -/* This covers node 0 only. */ -#define HIGH_ROMSTAGE_STACK_SIZE (0x48000 - BSP_STACK_BASE_ADDR) - -#endif diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 0fe8eab..864c8ad 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -15,7 +15,6 @@ #include <AGESA.h> #include <cbfs.h> -#include <cpu/amd/pi/s3_resume.h> #include <cpu/x86/mtrr.h> #include <cpuRegisters.h> #include <FchPlatform.h> @@ -23,9 +22,6 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/BiosCallOuts.h> -VOID FchInitS3LateRestore (IN FCH_DATA_BLOCK *FchDataPtr); -VOID FchInitS3EarlyRestore (IN FCH_DATA_BLOCK *FchDataPtr); - void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} #define FILECODE UNASSIGNED_FILE_FILECODE @@ -361,215 +357,6 @@ AGESA_STATUS agesawrapper_amdlaterunaptask ( return Status; } -#if CONFIG_HAVE_ACPI_RESUME - -AGESA_STATUS agesawrapper_amdinitresume(void) -{ - AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdParamStruct, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdParamStruct.StdHeader)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct (&AmdParamStruct); - - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr; - - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeNonVolatile; - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdResumeParamsPtr->S3DataBlock.NvStorageSize, - (void **) &AmdResumeParamsPtr->S3DataBlock.NvStorage); - - status = AmdInitResume ((AMD_RESUME_PARAMS *)AmdParamStruct.NewStructPtr); - - if (status != AGESA_SUCCESS) agesawrapper_amdreadeventlog(AmdParamStruct.StdHeader.HeapStatus); - AmdReleaseStruct (&AmdParamStruct); - - return status; -} - -#ifndef __PRE_RAM__ -AGESA_STATUS agesawrapper_fchs3earlyrestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - FCH_DATA_BLOCK FchParams; - AMD_CONFIG_PARAMS StdHeader; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - LibAmdMemFill (&FchParams, - 0, - sizeof(FchParams), - &StdHeader); - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - - FchInitS3EarlyRestore(&FchParams); - - return status; -} -#endif /* #ifndef __PRE_RAM__ */ - -AGESA_STATUS agesawrapper_amds3laterestore(void) -{ - AGESA_STATUS Status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - S3_DATA_TYPE S3DataType; - - agesawrapper_amdinitcpuio(); - LibAmdMemFill (&AmdS3LateParams, - 0, - sizeof(AMD_S3LATE_PARAMS), - &(AmdS3LateParams.StdHeader)); - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); - - AmdCreateStruct (&AmdInterfaceParams); - - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - S3DataType = S3DataTypeVolatile; - - OemAgesaGetS3Info (S3DataType, - (u32 *) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize, - (void **) &AmdS3LateParamsPtr->S3DataBlock.VolatileStorage); - - Status = AmdS3LateRestore (AmdS3LateParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - return Status; -} - -#ifndef __PRE_RAM__ - -AGESA_STATUS agesawrapper_fchs3laterestore(void) -{ - AGESA_STATUS status = AGESA_SUCCESS; - - AMD_CONFIG_PARAMS StdHeader; - FCH_DATA_BLOCK FchParams; - - StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - StdHeader.HeapBasePtr = GetHeapBase(&StdHeader) + 0x10; - StdHeader.AltImageBasePtr = 0; - StdHeader.CalloutPtr = &GetBiosCallout; - StdHeader.Func = 0; - StdHeader.ImageBasePtr = 0; - - LibAmdMemFill (&FchParams, - 0, - sizeof(FchParams), - &StdHeader); - - FchParams.StdHeader = &StdHeader; - s3_resume_init_data(&FchParams); - FchInitS3LateRestore(&FchParams); - - /* PIC IRQ routine */ - for (byte = 0x0; byte < sizeof(picr_data); byte ++) { - outb(byte, 0xC00); - outb(picr_data[byte], 0xC01); - } - - /* APIC IRQ routine */ - for (byte = 0x0; byte < sizeof(intr_data); byte ++) { - outb(byte | 0x80, 0xC00); - outb(intr_data[byte], 0xC01); - } - - return status; -} - -AGESA_STATUS agesawrapper_amdS3Save(void) -{ - AGESA_STATUS Status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - S3_DATA_TYPE S3DataType; - - LibAmdMemFill (&AmdInterfaceParams, - 0, - sizeof(AMD_INTERFACE_PARAMS), - &(AmdInterfaceParams.StdHeader)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - - AmdCreateStruct(&AmdInterfaceParams); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *)AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; - - Status = AmdS3Save(AmdS3SaveParamsPtr); - if (Status != AGESA_SUCCESS) { - agesawrapper_amdreadeventlog(AmdInterfaceParams.StdHeader.HeapStatus); - ASSERT(Status == AGESA_SUCCESS); - } - - S3DataType = S3DataTypeNonVolatile; - printk(BIOS_DEBUG, "NvStorageSize=%x, NvStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.NvStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.NvStorage); - - printk(BIOS_DEBUG, "VolatileStorageSize=%x, VolatileStorage=%x\n", - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - (unsigned int)AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - - if (AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize != 0) { - S3DataType = S3DataTypeVolatile; - - Status = OemAgesaSaveS3Info ( - S3DataType, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorageSize, - AmdS3SaveParamsPtr->S3DataBlock.VolatileStorage); - } - OemAgesaSaveMtrr(); - - AmdReleaseStruct (&AmdInterfaceParams); - - return Status; -} - -#endif /* #ifndef __PRE_RAM__ */ -#endif /* CONFIG_HAVE_ACPI_RESUME */ - AGESA_STATUS agesawrapper_amdreadeventlog (UINT8 HeapStatus) { AGESA_STATUS Status;

1 0

Patch set updated for coreboot: binaryPI boards: Drop any ACPI S3 support
by Kyösti Mälkki 01 Mar '17

01 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18500 -gerrit commit de336d1401dfd1a49358128c6f1a9a8d016f266b Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Feb 26 10:11:21 2017 +0200 binaryPI boards: Drop any ACPI S3 support None of the boards currently have HAVE_ACPI_RESUME and and ACPI S3 support calls should not appear under board directories anyways. Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/bettong/mainboard.c | 3 --- src/mainboard/amd/bettong/romstage.c | 30 ++++++------------------ src/mainboard/amd/db-ft3b-lc/mainboard.c | 4 ---- src/mainboard/amd/db-ft3b-lc/romstage.c | 34 ++++++++------------------- src/mainboard/amd/gardenia/mainboard.c | 3 --- src/mainboard/amd/gardenia/romstage.c | 30 ++++++------------------ src/mainboard/amd/lamar/mainboard.c | 7 ------ src/mainboard/amd/lamar/romstage.c | 31 +++++++------------------ src/mainboard/amd/olivehillplus/mainboard.c | 4 ---- src/mainboard/amd/olivehillplus/romstage.c | 36 +++++++++-------------------- src/mainboard/bap/ode_e21XX/mainboard.c | 4 ---- src/mainboard/bap/ode_e21XX/romstage.c | 36 +++++++++-------------------- src/mainboard/pcengines/apu2/mainboard.c | 4 ---- src/mainboard/pcengines/apu2/romstage.c | 36 +++++++++-------------------- 14 files changed, 65 insertions(+), 197 deletions(-) diff --git a/src/mainboard/amd/bettong/mainboard.c b/src/mainboard/amd/bettong/mainboard.c index c31f5b7..11d6084 100644 --- a/src/mainboard/amd/bettong/mainboard.c +++ b/src/mainboard/amd/bettong/mainboard.c @@ -84,9 +84,6 @@ static void bettong_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 6b12afc..29cd8a7 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,9 +27,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif /* Must come first to enable PCI MMCONF. */ amd_initmmio(); @@ -63,27 +59,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); - if (s3resume || acpi_is_wakeup_s4()) { + if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } diff --git a/src/mainboard/amd/db-ft3b-lc/mainboard.c b/src/mainboard/amd/db-ft3b-lc/mainboard.c index 6f8742c..419a57d 100644 --- a/src/mainboard/amd/db-ft3b-lc/mainboard.c +++ b/src/mainboard/amd/db-ft3b-lc/mainboard.c @@ -17,7 +17,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -125,9 +124,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 79cc0f9..0ba1c1d 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -77,28 +75,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 7ebe087..acc9b7c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index eca9d3b..0136a98 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -20,7 +20,6 @@ #include <cpu/x86/lapic.h> #include <cpu/x86/bist.h> #include <cpu/amd/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> @@ -28,9 +27,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val; -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif amd_initmmio(); hudson_lpc_port80(); @@ -62,27 +58,15 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + post_code(0x40); + AGESAWRAPPER(amdinitpost); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* TODO: Disable cache is not ok. */ + disable_cache_as_ram(); - if (s3resume || acpi_is_wakeup_s4()) { + if (acpi_is_wakeup_s4()) { outb(0xEE, PM_INDEX); outb(0x8, PM_DATA); } diff --git a/src/mainboard/amd/lamar/mainboard.c b/src/mainboard/amd/lamar/mainboard.c index 25e685b..4e010fc 100644 --- a/src/mainboard/amd/lamar/mainboard.c +++ b/src/mainboard/amd/lamar/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -147,12 +146,6 @@ static void pirq_setup(void) static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - /* - * The mainboard is the first place that we get control in ramstage. Check - * for S3 resume and call the approriate AGESA/CIMx resume functions. - */ - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); /* Initialize the PIRQ data structures for consumption */ pirq_setup(); diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bda8c0f..5530a25 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -32,7 +31,6 @@ #include <cpu/x86/lapic.h> #include <southbridge/amd/common/amd_defs.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" #include "superio/fintek/f81216h/f81216h.h" @@ -88,29 +86,16 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } - else if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x61); - prepare_for_resume(); - } + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); post_code(0x50); copy_and_run(); diff --git a/src/mainboard/amd/olivehillplus/mainboard.c b/src/mainboard/amd/olivehillplus/mainboard.c index 1e82768..8693737 100644 --- a/src/mainboard/amd/olivehillplus/mainboard.c +++ b/src/mainboard/amd/olivehillplus/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 534a8e5..c98ae25 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -87,29 +85,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/bap/ode_e21XX/mainboard.c b/src/mainboard/bap/ode_e21XX/mainboard.c index 1e82768..8693737 100644 --- a/src/mainboard/bap/ode_e21XX/mainboard.c +++ b/src/mainboard/bap/ode_e21XX/mainboard.c @@ -20,7 +20,6 @@ #include <device/pci_def.h> #include <arch/acpi.h> #include <northbridge/amd/pi/BiosCallOuts.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> @@ -31,9 +30,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 5deeaa8..d8342c9 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f81866d/f81866d.h> @@ -81,29 +79,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7); diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index d2ab638..043bc17 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -16,7 +16,6 @@ #include <arch/acpi.h> #include <arch/io.h> #include <console/console.h> -#include <cpu/amd/pi/s3_resume.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> @@ -183,9 +182,6 @@ static void mainboard_enable(device_t dev) // pm_write16 ( PM_S_STATE_CONTROL, pm_read16( PM_S_STATE_CONTROL ) | (1 << 14)); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..a0d925f 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -17,7 +17,6 @@ #include <string.h> #include <device/pci_def.h> #include <device/pci_ids.h> -#include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> @@ -31,7 +30,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> -#include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> #include "gpio_ftns.h" @@ -82,29 +80,17 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - //PspMboxBiosCmdDramInfo(); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* - If code hangs here, please check cahaltasm.S - */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - - AGESAWRAPPER(amds3laterestore); - - post_code(0x61); - prepare_for_resume(); - } + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + //PspMboxBiosCmdDramInfo(); + post_code(0x41); + AGESAWRAPPER(amdinitenv); + /* + If code hangs here, please check cahaltasm.S + */ + disable_cache_as_ram(); outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

1 0

Patch set updated for coreboot: cpu/amd/agesa: Unify init files
by Paul Menzel 01 Mar '17

01 Mar '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18507 -gerrit commit 56e0d32083ed69fc43ca25f511b2c362f2d36c7c Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 27 01:26:42 2017 +0100 cpu/amd/agesa: Unify init files The init files for the AMD families using the AGESA platform initialization code are quite similar. So reduce the differences, by using the same comments, variable names, console messages, and blank lines. Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/amd/agesa/family10/model_10_init.c | 1 - src/cpu/amd/agesa/family12/model_12_init.c | 1 - src/cpu/amd/agesa/family14/model_14_init.c | 12 ++++++------ src/cpu/amd/agesa/family15rl/model_15_init.c | 2 +- src/cpu/amd/agesa/family15tn/model_15_init.c | 4 ++-- src/cpu/amd/agesa/family16kb/model_16_init.c | 3 +-- 6 files changed, 10 insertions(+), 13 deletions(-) diff --git a/src/cpu/amd/agesa/family10/model_10_init.c b/src/cpu/amd/agesa/family10/model_10_init.c index ef70725..8caf0c9 100644 --- a/src/cpu/amd/agesa/family10/model_10_init.c +++ b/src/cpu/amd/agesa/family10/model_10_init.c @@ -83,7 +83,6 @@ static void model_10_init(device_t dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); diff --git a/src/cpu/amd/agesa/family12/model_12_init.c b/src/cpu/amd/agesa/family12/model_12_init.c index 2fc943c..e533017 100644 --- a/src/cpu/amd/agesa/family12/model_12_init.c +++ b/src/cpu/amd/agesa/family12/model_12_init.c @@ -88,7 +88,6 @@ static void model_12_init(device_t dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 5e8c9de..ecf1cfb 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -34,8 +34,9 @@ static void model_14_init(device_t dev) { - u32 i; + u8 i; msr_t msr; + int msrno; #if IS_ENABLED(CONFIG_LOGICAL_CPUS) u32 siblings; #endif @@ -58,11 +59,11 @@ static void model_14_init(device_t dev) /* Set shadow WB, RdMEM, WrMEM */ msr.lo = msr.hi = 0; wrmsr (0x259, msr); - msr.hi = msr.lo = 0x1e1e1e1e; + msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); - for (i = 0x268; i <= 0x26f; i++) - wrmsr(i, msr); + for (msrno = 0x268; msrno <= 0x26f; i++) + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -97,6 +98,7 @@ static void model_14_init(device_t dev) msr.hi |= 1 << (33 - 32); wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); } + printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif /* DisableCf8ExtCfg */ @@ -108,8 +110,6 @@ static void model_14_init(device_t dev) msr = rdmsr(HWCR_MSR); msr.lo |= (1 << 0); wrmsr(HWCR_MSR, msr); - - printk(BIOS_SPEW, "%s done.\n", __func__); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c index b28ad57..6d2bec2 100644 --- a/src/cpu/amd/agesa/family15rl/model_15_init.c +++ b/src/cpu/amd/agesa/family15rl/model_15_init.c @@ -130,7 +130,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */ + { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 */ { 0, 0 }, }; diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index 5153a8b..fa4a691 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -129,8 +129,8 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ - { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */ + { X86_VENDOR_AMD, 0x610f00 }, /* TN-A0 */ + { X86_VENDOR_AMD, 0x610f31 }, /* RL-A1 (Richland) */ { 0, 0 }, }; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index f62e698..a8d076c 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -78,7 +78,6 @@ static void model_16_init(device_t dev) wrmsr(MCI_STATUS + (i * 4), msr); } - /* Enable the local CPU APICs */ setup_lapic(); @@ -114,7 +113,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ + { X86_VENDOR_AMD, 0x700f00 }, /* KB-A0 */ { 0, 0 }, };

1 0

Patch set updated for coreboot: cpu/intel/model_6{e, f}x: Unify init files
by Paul Menzel 01 Mar '17

01 Mar '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18506 -gerrit commit 30e8b97c844d54445b3212d0abb08835569aabb6 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Mon Feb 27 01:01:55 2017 +0100 cpu/intel/model_6{e,f}x: Unify init files The init files for the Core Duo and Core 2 Duo are very similar. Reduce the differences, by using the same order for the include statements, the same blank lines, and the same comments. Change-Id: I0de060222a61a482377c760c6031d73c7e318edf Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/cpu/intel/model_6ex/model_6ex_init.c | 11 +++++++---- src/cpu/intel/model_6fx/model_6fx_init.c | 11 +++++------ 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index cc1260e..a93b113 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -21,8 +21,8 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> -#include <cpu/intel/microcode.h> #include <cpu/intel/hyperthreading.h> +#include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> @@ -34,10 +34,10 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset. + msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); //dynamic L2 + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -50,7 +50,7 @@ static void configure_c_states(void) msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr); - /* set C_LVL controls */ + /* Set C_LVL controls and IO Capture Address */ msr.hi = 0; msr.lo = (PMB0_BASE + 4) | ((HIGHEST_CLEVEL - 2) << 16); // -2 because LVL0+1 aren't counted wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr); @@ -128,6 +128,9 @@ static void model_6ex_init(struct device *cpu) x86_setup_mtrrs(); x86_mtrr_check(); + /* Setup Page Attribute Tables (PAT) */ + // TODO set up PAT + /* Enable the local CPU APICs */ setup_lapic(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index d29895b..3a6319a 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -21,9 +21,9 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> #include <cpu/x86/lapic.h> +#include <cpu/intel/hyperthreading.h> #include <cpu/intel/microcode.h> #include <cpu/intel/speedstep.h> -#include <cpu/intel/hyperthreading.h> #include <cpu/x86/cache.h> #include <cpu/x86/name.h> #include <cpu/intel/common/common.h> @@ -34,12 +34,11 @@ static void configure_c_states(void) msr_t msr; msr = rdmsr(MSR_PMG_CST_CONFIG_CONTROL); - msr.lo |= (1 << 15); // config lock until next reset msr.lo |= (1 << 14); // Deeper Sleep - msr.lo |= (1 << 10); // Enable IO MWAIT redirection - msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk - msr.lo |= (1 << 3); // Dynamic L2 + msr.lo |= (1 << 10); // Enable I/O MWAIT redirection for C-States + msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk + msr.lo |= (1 << 3); // dynamic L2 /* Number of supported C-States */ msr.lo &= ~7; @@ -47,7 +46,7 @@ static void configure_c_states(void) wrmsr(MSR_PMG_CST_CONFIG_CONTROL, msr); - /* Set Processor MWAIT IO BASE */ + /* Set Processor MWAIT IO BASE (P_BLK) */ msr.hi = 0; msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16); wrmsr(MSR_PMG_IO_BASE_ADDR, msr);

1 0

Patch set updated for coreboot: drivers/spi: Measure execution time of `spi_flash_probe()`
by Paul Menzel 01 Mar '17

01 Mar '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18503 -gerrit commit 660f4aca97fa3151acb943e912a70e9aacb7d67f Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Sun Feb 26 19:58:24 2017 +0100 drivers/spi: Measure execution time of `spi_flash_probe()` Measure the time of the execution of the method `spi_flash_probe()`. It’s useful to analyze the boot process, and to compare different flash ROM chips. TEST=Build and boot on ASRock E350M1, and observe the new messages. ``` Manufacturer: ef SF: Detected W25Q32 with sector size 0x1000, total 0x400000 spi_flash_probe: Probing the flash chip took 24 usecs SF: Successfully erased 4096 bytes @ 0xffff1000 Manufacturer: ef SF: Detected W25Q32 with sector size 0x1000, total 0x400000 spi_flash_probe: Probing the flash chip took 21 usecs SF: Successfully erased 4096 bytes @ 0xffff0000 ``` Change-Id: I448e12508b09a8796c5351b17495113afe9a50ef Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> --- src/drivers/spi/spi_flash.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 95362f2..b2e928b 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -331,6 +331,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) { struct spi_slave spi; struct spi_flash *flash; + struct stopwatch sw; + + stopwatch_init(&sw); if (spi_setup_slave(bus, cs, &spi)) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); @@ -365,6 +368,9 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) CONFIG_BOOT_DEVICE_SPI_FLASH_BUS == bus && !spi_flash_dev) spi_flash_dev = flash; + printk(BIOS_DEBUG, "%s: Probing the flash chip took %ld usecs\n", + __func__, stopwatch_duration_usecs(&sw)); + return flash; }

1 0

New patch to review for coreboot: lint: Remove signed-off-by check
by Zheng Bao 01 Mar '17

01 Mar '17

Zheng Bao (fishbaozi(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18524 -gerrit commit 8968751094ee61cbea707f0338f464e92d259cb4 Author: Zheng Bao <fishbaozi(a)gmail.com> Date: Wed Mar 1 13:56:25 2017 +0800 lint: Remove signed-off-by check The command "git log -n 1" only gets the last commit message, instead of this time. Pre-commit in git, "It takes no parameters, and is invoked before obtaining the proposed commit log message and making a commit." Only commit-msg can handle the message. Change-Id: I01208ae984915142521da541b81eecd288be7e19 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/lint/lint-stable-020-signed-off-by | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/util/lint/lint-stable-020-signed-off-by b/util/lint/lint-stable-020-signed-off-by deleted file mode 100755 index 40b6e9e..0000000 --- a/util/lint/lint-stable-020-signed-off-by +++ /dev/null @@ -1,23 +0,0 @@ -#!/bin/sh -# This file is part of the coreboot project. -# -# Copyright 2016 Google Inc. -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License, or (at your option) -# any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# DESCR: Check for a signed-off-by line on the latest git commit - -# This test is mainly for the jenkins server -if [ -n "$(command -v git)" ] && [ -d .git ]; then - if [ -z "$(git log -n 1 | grep '[[:space:]]\+Signed-off-by: ')" ]; then - echo "No Signed-off-by line in commit message" - fi -fi

1 0

Patch set updated for coreboot: mainboard/google/reef: Configure SDCARD card detect pin
by Venkateswarlu V Vinjamuri 01 Mar '17

01 Mar '17

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18497 -gerrit commit 88e66bf941a93b528b7a5971313057fd6c90bd97 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Fri Feb 24 15:54:39 2017 -0800 mainboard/google/reef: Configure SDCARD card detect pin This configures GPIO_177 as GPI for SDCARD card detect. BUG=chrome-os-partner:63070 TEST=None Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 3 +++ src/mainboard/google/reef/variants/baseboard/gpio.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index b0c82e2..443918e 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -17,6 +17,9 @@ chip soc/intel/apollolake # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF register "prt0_gpio" = "GPIO_122" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "GPIO_177" + # EMMC TX DATA Delay 1 # Refer to EDS-Vol2-22.3. # [14:8] steps of delay for HS400, each 125ps. diff --git a/src/mainboard/google/reef/variants/baseboard/gpio.c b/src/mainboard/google/reef/variants/baseboard/gpio.c index a9a6248..043d024 100644 --- a/src/mainboard/google/reef/variants/baseboard/gpio.c +++ b/src/mainboard/google/reef/variants/baseboard/gpio.c @@ -59,7 +59,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPIO_175, UP_20K, DEEP, NF1), /* SDCARD_D2 */ PAD_CFG_NF(GPIO_176, UP_20K, DEEP, NF1), /* SDCARD_D3 */ /* Card detect is active LOW with external pull up. */ - PAD_CFG_NF(GPIO_177, NONE, DEEP, NF1), /* SDCARD_CD_N */ + PAD_CFG_GPI_GPIO_DRIVER(GPIO_177, NONE, DEEP), /* SDCARD_CD_N */ PAD_CFG_NF(GPIO_178, UP_20K, DEEP, NF1), /* SDCARD_CMD */ /* CLK feedback, internal signal, needs 20K pull down */ PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), /* SDCARD_CLK_FB */

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add PM methods to power gate SD card
by Venkateswarlu V Vinjamuri 01 Mar '17

01 Mar '17

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18496 -gerrit commit 033295823261e7cf5b445d4f1a693bce8ce35147 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Fri Feb 24 15:37:30 2017 -0800 soc/intel/apollolake: Add PM methods to power gate SD card This implements GNVS variable to store the address of GPIO_177. _PS0/_PS3 methods to power gate the sd card controller. BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 1 + src/soc/intel/apollolake/acpi/scs.asl | 51 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 3 ++ src/soc/intel/apollolake/include/soc/nvs.h | 3 +- 5 files changed, 61 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 3c1faa5..6aa985d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -183,6 +183,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Assign address of PERST_0 if GPIO is defined in devicetree */ if (cfg->prt0_gpio != GPIO_PRT0_UDEF) gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); + + /* Assign Gpio address of SDCARD Card detect */ + gnvs->sdcd = (uintptr_t)gpio_dwx_address(cfg->sdcard_cd_gpio); + } /* Save wake source information for calculating ACPI _SWS values */ diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 657c834..947120d 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -39,6 +39,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x19 - 0x20 - NHLT Address NHLL, 32, // 0x21 - 0x24 - NHLT Length PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SDCD, 32, // 0x29 - 0x2D - SD_CD Address /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index 4108017..cc157e2 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -22,6 +22,9 @@ Scope (\_SB.PCI0) { Field (SBMM, DWordAcc, NoLock, Preserve) { GENR, 32, + Offset (0x08), + , 5, /* 5th bit represents Force Card Detect SD Card */ + GRR3, 1, /* GPPRVRW3 used for SD Card detect Bypass. */ } /* SCC power gate control method, this method must be serialized as @@ -64,4 +67,52 @@ Scope (\_SB.PCI0) { ^^SCPG(1,0x00000041) } } /* Device (SDHA) */ + + /* SD CARD */ + Device (SDC) + { + Name (_ADR, 0x001B0000) + + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 0, + "\\_SB.GPO3", 0, ResourceConsumer, , ) {26} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + OperationRegion (PCCS, PCI_Config, 0x84, 0x04) + Field (PCCS, WordAcc, NoLock, Preserve) { + PMSR, 32 /* 4h: Power Gating Control */ + } + + Method (_PS0, 0, NotSerialized) + { + /* Store DW0 into local1 */ + Store (\_SB.GPC0 (\SDCD), Local1) + /* Extract rxstate [bit 1] of sdcard card detect pin */ + And (Local1, 0x2, Local1) + /* If the sdcard is present, rxstate is low (GPIO_177). + * If sdcard is not present, rxstate is High. + * Write the inverted value of rxstate to GRR3. + */ + Not (Local1, \_SB.PCI0.GRR3) + + /* Disable power gate by clearing bit 1 and 0 */ + And (^PMSR, 0xFFFFFFFC, ^PMSR) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate by restore bit 1 and 0 */ + Store (0, \_SB.PCI0.GRR3) + Or (^PMSR, 0x3, ^PMSR) + } + + } /* Device (SDC) */ } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index d60ffbf..22d3b4e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -117,6 +117,9 @@ struct soc_intel_apollolake_config { /* GPIO pin for PERST_0 */ uint16_t prt0_gpio; + /* GPIO pin for SDCARD Card Detect */ + uint16_t sdcard_cd_gpio; + /* USB2 eye diagram settings per port */ struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 21894ca..1e774b8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -39,7 +39,8 @@ typedef struct global_nvs_t { uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t unused[215]; + uint32_t sdcd; /* 0x29 - 0x2D - SD_CD Address */ + uint8_t unused[211]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: mainboard/pcengines/apu2: Add LPC TPM support
by Philipp Deppenwiese 01 Mar '17

01 Mar '17

Philipp Deppenwiese (zaolin.daisuki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18523 -gerrit commit 0002281c04efb33178214e88d88e5ef6c3ac902d Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Wed Mar 1 02:37:36 2017 +0100 mainboard/pcengines/apu2: Add LPC TPM support APU2 exposes a LPC header which can be used in conjunction with a LPC TPM module. Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819 Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- src/mainboard/pcengines/apu2/Kconfig | 1 + src/mainboard/pcengines/apu2/devicetree.cb | 8 +++++++- src/mainboard/pcengines/apu2/romstage.c | 6 ++++++ 3 files changed, 14 insertions(+), 1 deletion(-) diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 4303b84..cc815df 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select HUDSON_DISABLE_IMC select USE_BLOBS + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb index 3c5ec81..369150d 100644 --- a/src/mainboard/pcengines/apu2/devicetree.cb +++ b/src/mainboard/pcengines/apu2/devicetree.cb @@ -73,7 +73,13 @@ chip northbridge/amd/pi/00730F01/root_complex device pnp 2e.607 off end device pnp 2e.e off end end # SIO NCT5104D - end # LPC 0x439d + chip drivers/pc80/tpm + register "irq_polarity" = "2" + device pnp 0c31.0 on + irq 0x70 = 10 + end + end # LPC TPM + end # LPC 0x439d device pci 14.7 on end # SD device pci 16.0 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..2c4e652 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -33,6 +33,8 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include <Fch/Fch.h> +#include <tpm.h> + #include "gpio_ftns.h" static void early_lpc_init(void); @@ -106,6 +108,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) prepare_for_resume(); } +#if CONFIG_LPC_TPM + init_tpm(false); +#endif + outb(0xEA, 0xCD6); outb(0x1, 0xcd7);

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coreboot-gerrit March 2017