coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: device/dram/ddr2: Add function to select common CAS en freq
by Arthur Heymans 01 Mar '17

01 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit a3da4fe6bd9c9bb94acd34667cf645e4236342a0 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Mar 1 20:10:55 2017 +0100 device/dram/ddr2: Add function to select common CAS en freq This function finds highest common CAS and select tCLK based on the dimm with highest minumum tCLK at that selected CAS. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 57 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 3 ++- 2 files changed, 59 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 1ee22bb..b0412bf 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -628,3 +629,59 @@ void dram_print_spd_ddr2(const struct dimm_attr_st *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +u32 get_common_freq_cas(u8 cas_mask, const struct dimm_attr_st *dimm, + int num_dimms, u8 *selected_cas) +{ + int i, high_common_cas; + u32 tCLK = 0; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i].cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 0; + } + + high_common_cas = spd_get_msbs(cas_mask); + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + if (dimm[i].cycle_time[high_common_cas] == 0) + printk(BIOS_DEBUG, "No minimum tCLK defined for dimm %d at CAS %d\n", + i, high_common_cas); + if (tCLK < dimm[i].cycle_time[high_common_cas]) + tCLK = dimm[i].cycle_time[high_common_cas]; + } + + if (tCLK == 0) { + printk(BIOS_DEBUG, "No valid minimum tCLK found\n"); + return 0; + } + + if (tCLK <= TCK_800MHZ) { + tCLK = TCK_800MHZ; + } else if (tCLK <= TCK_666MHZ) { + tCLK = TCK_666MHZ; + } else if (tCLK <= TCK_533MHZ) { + tCLK = TCK_533MHZ; + } else if (tCLK <= TCK_400MHZ) { + tCLK = TCK_400MHZ; + } else if (tCLK <= TCK_333MHZ) { + tCLK = TCK_333MHZ; + } else if (tCLK <= TCK_266MHZ) { + tCLK = TCK_266MHZ; + } else if (tCLK <= TCK_200MHZ) { + tCLK = TCK_200MHZ; + } else { + printk(BIOS_DEBUG, "Too slow common tCLK found\n"); + return 0; + } + + *selected_cas = high_common_cas; + return tCLK; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 7f59a7a..e7515ba 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -213,6 +213,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); void dram_print_spd_ddr2(const struct dimm_attr_st *dimm); - +u32 get_common_freq_cas(u8 cas_mask, const struct dimm_attr_st *dimm, int num_dimms, + u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

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Patch set updated for coreboot: soc/intel/skylake: indicate voltage margining enabled/disabled
by Rizwan Qureshi 01 Mar '17

01 Mar '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469 -gerrit commit d99533d509dbd53a963500c17456f9e2a6efeda1 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 23 14:43:39 2017 +0530 soc/intel/skylake: indicate voltage margining enabled/disabled Support for voltage margining is dependent on the platform. Enbaling voltage margining puts additional constraints for the SLP_S0# to be asserted and hence moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction, voltage marigining can be enabled. Use the UPD provided by FSP to enable/disable voltage margining. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/chip.h | 8 ++++++++ src/soc/intel/skylake/chip_fsp20.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2e4adb2..8e6fa69 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -333,6 +333,14 @@ struct soc_intel_skylake_config { * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s */ u8 PmConfigPwrBtnOverridePeriod; + + /* + * PCH Pm Slp S0 Voltage Margining Enable + * Indicates platform has support for VCCPrim_Core Voltage Margining + * in SLP_S0# asserted state. + */ + u8 PchPmSlpS0VmEnable; + /* * Reset Power Cycle Duration could be customized in the unit of second. * PCH HW default is 4 seconds, and range is 1~4 seconds. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8b8c37c..3d2f2cb 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -220,6 +220,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + + /* Disable Voltage margining if S0ix is enabled */ + if (config->s0ix_enable) + params->PchPmSlpS0VmEnable = 0x0; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode;

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Patch set updated for coreboot: intel/broadwell: Use the correct SATA port config for setting IOBP register
by Youness Alaoui 01 Mar '17

01 Mar '17

Youness Alaoui (snifikino(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18514 -gerrit commit 1998e2f5d7142ccd90a79cbb9ff20309371bd09a Author: Youness Alaoui <kakaroto(a)kakaroto.homelinux.net> Date: Mon Feb 27 12:03:39 2017 -0500 intel/broadwell: Use the correct SATA port config for setting IOBP register Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata: Add support for setting IOBP registers for Ports 2 and 3.) [1]. Setting one of the SATA port 3 IOBP setting was using the value from the port 2 register. On the purism/librem13 (on which SATA port 3 is tested), this change doesn't seem to affect anything, as that typo wasn't exhibiting any visible problems anyways. [1] https://review.coreboot.org/18408 Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48 Signed-off-by: Youness Alaoui <youness.alaoui(a)puri.sm> --- src/soc/intel/broadwell/sata.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 1f2e690..7b9bd0c 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -161,7 +161,7 @@ static void sata_init(struct device *dev) pch_iobp_update(SATA_IOBP_SP3_SECRT88, ~(SATA_SECRT88_VADJ_MASK << SATA_SECRT88_VADJ_SHIFT), - (config->sata_port2_gen3_tx & + (config->sata_port3_gen3_tx & SATA_SECRT88_VADJ_MASK) << SATA_SECRT88_VADJ_SHIFT);

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Patch set updated for coreboot: soc/intel/skylake: Add option to indicate voltage margining enabled/disabled
by Rizwan Qureshi 01 Mar '17

01 Mar '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18469 -gerrit commit 0d8b304e1657e7f27852334f9684fd84531b868f Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 23 14:43:39 2017 +0530 soc/intel/skylake: Add option to indicate voltage margining enabled/disabled Support for voltage margining is dependent on the platform. Enbaling voltage margining puts additional constraints for the SLP_S0# to be asserted and hence moving to S0ix state. If the platform PMIC/VR supports PCH voltage reduction, voltage marigining can be enabled. Use the UPD provided by FSP to enable/disable voltage margining. Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/chip.h | 8 ++++++++ src/soc/intel/skylake/chip_fsp20.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 2e4adb2..8e6fa69 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -333,6 +333,14 @@ struct soc_intel_skylake_config { * Values: 0x0 - 4s, 0x1 - 6s, 0x2 - 8s, 0x3 - 10s, 0x4 - 12s, 0x5 - 14s */ u8 PmConfigPwrBtnOverridePeriod; + + /* + * PCH Pm Slp S0 Voltage Margining Enable + * Indicates platform has support for VCCPrim_Core Voltage Margining + * in SLP_S0# asserted state. + */ + u8 PchPmSlpS0VmEnable; + /* * Reset Power Cycle Duration could be customized in the unit of second. * PCH HW default is 4 seconds, and range is 1~4 seconds. diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 8b8c37c..3d2f2cb 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -220,6 +220,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->PchPmPwrBtnOverridePeriod = config->PmConfigPwrBtnOverridePeriod; params->PchPmPwrCycDur = config->PmConfigPwrCycDur; + + /* Disable Voltage margining if S0ix is enabled */ + if (config->s0ix_enable) + params->PchPmSlpS0VmEnable = 0x0; + params->PchSirqEnable = config->SerialIrqConfigSirqEnable; params->PchSirqMode = config->SerialIrqConfigSirqMode;

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Patch set updated for coreboot: libpayload-x86: Enable SSE and FPU when present
by Patrick Rudolph 01 Mar '17

01 Mar '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18345 -gerrit commit 14cc7b3c49ebcd1cf31bf2e1d2e0e8ff3f0bf30f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 15 10:49:48 2017 +0100 libpayload-x86: Enable SSE and FPU when present Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- payloads/libpayload/arch/x86/head.S | 43 +++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S index 94a4d41..5250470 100644 --- a/payloads/libpayload/arch/x86/head.S +++ b/payloads/libpayload/arch/x86/head.S @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -89,6 +90,48 @@ _init: movl $_stack, %esp pushl %eax + /* Enable special x86 functions if present. */ + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + + movl $0, %eax + cpuid + /* Test if CPUID(eax=1) is available. */ + test %eax, %eax + je cpuid_done + + /* Get CPU features. */ + movl $1, %eax + cpuid + +cpuid_fpu: + /* Test if x87 FPU is present */ + test $1, %edx + je cpuid_sse + + fninit + movl %cr0, %eax + andl $0xFFFFFFFB, %eax /* clear EM */ + orl $0x00000022, %eax /* set MP, NE */ + movl %eax, %cr0 + +cpuid_sse: + /* Test if SSE is available */ + test $0x02000000, %edx + je cpuid_done + + movl %cr4, %eax + orl $0x00000600, %eax /* set OSFXSR, OSXMMEXCPT */ + movl %eax, %cr4 + +cpuid_done: + popl %edx + popl %ecx + popl %ebx + popl %eax + /* Let's rock. */ call start_main

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Patch set updated for coreboot: device/dram/ddr2: Add common ddr2 spd decoder
by Patrick Rudolph 01 Mar '17

01 Mar '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18273 -gerrit commit 50365181babf88187dc97797cc0494907b76781a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 31 19:43:17 2017 +0100 device/dram/ddr2: Add common ddr2 spd decoder Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid compilation errors. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/dram/Makefile.inc | 2 +- src/device/dram/ddr2.c | 630 +++++++++++++++++++++++++++++++ src/device/dram/ddr3.c | 2 +- src/include/device/dram/ddr2.h | 218 +++++++++++ src/include/device/dram/ddr3.h | 2 +- src/northbridge/via/vx900/raminit_ddr3.c | 2 +- 6 files changed, 852 insertions(+), 4 deletions(-) diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index b1a6755..c982ef4 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-y += ddr3.c +romstage-y += ddr3.c ddr2.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c new file mode 100644 index 0000000..1ee22bb --- /dev/null +++ b/src/device/dram/ddr2.c @@ -0,0 +1,630 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file ddr2.c + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr2.h> +#include <string.h> + +/*============================================================================== + * = DDR2 SPD decoding helpers + *----------------------------------------------------------------------------*/ + +/** + * \brief Checks if the DIMM is Registered based on byte[20] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[20] of the SPD. + */ +int spd_dimm_is_registered_ddr2(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Calculate the checksum of a DDR2 SPD unique identifier + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the checksum of SPD data bytes 63, or 0 when spd data is truncated. + */ +u8 spd_ddr2_calc_checksum(u8 *spd, int len) +{ + int i; + u8 c = 0; + + if (len < 63) + /* Not enough bytes available to get the checksum */ + return 0; + + for (i = 0; i < 63; i++) + c += spd[i]; + + return c; +} + +/** + * \brief Return size of SPD. + * + * Returns size of SPD. Usually 128 Byte. + */ +u32 spd_decode_spd_size_ddr2(u8 byte0) +{ + return MAX(byte0, SPD_SIZE_MAX_DDR2); +} + +/** + * \brief Return size of eeprom. + * + * Returns size of eeprom. Usually 256 Byte. + */ +u32 spd_decode_eeprom_size_ddr2(u8 byte1) +{ + if (!byte1) + return 0; + + if (byte1 > 0x0e) + return 0x3fff; + + return 1 << byte1; +} + +/** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_msbs(u8 c) +{ + int i; + for (i = 7; i >= 0; i--) + if (c & (1 << i)) + return i; + + return 0; +} + +/** + * \brief Decode SPD tck cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_tck_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + + switch (c & 0xf) { + case 0xa: + low = 25; + break; + case 0xb: + low = 33; + break; + case 0xc: + low = 66; + break; + case 0xd: + low = 75; + break; + default: + low = (c & 0xf) * 10; + } + + return ((high * 100 + low) << 8) / 100; +} + +/** + * \brief Decode SPD bcd style timings + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_bcd_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + low = c & 0xf; + + return ((high * 10 + low) << 8) / 100; +} + +/** + * \brief Decode SPD tRP, tRRP cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_quarter_time(u8 c) +{ + u8 high, low; + + high = c >> 2; + low = 25 * (c & 0x3); + + return ((high * 100 + low) << 8) / 100; +} + +/** + * \brief Decode SPD tRR time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static u32 spd_decode_tRR_time(u8 c) +{ + switch (c) { + default: + case 0: + return 15625 << 8; + case 1: + return 15625 << 6; + case 2: + return 15625 << 7; + case 3: + return 15625 << 9; + case 4: + return 15625 << 10; + case 5: + return 15625 << 11; + } +} + +/** + * \brief Decode SPD tRC,tRFC time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static void spd_decode_tRCtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC) +{ + u8 b40, b41, b42; + + b40 = spd_40_41_42[0]; + b41 = spd_40_41_42[1]; + b42 = spd_40_41_42[2]; + + *tRC = b41 * 100; + *tRFC = b42 * 100; + + if (b40 & 0x01) + *tRFC += 256 * 100; + + switch ((b40 >> 1) & 0x07) { + case 1: + *tRFC += 25; + break; + case 2: + *tRFC += 33; + break; + case 3: + *tRFC += 50; + break; + case 4: + *tRFC += 66; + break; + case 5: + *tRFC += 75; + break; + default: + break; + } + + switch ((b40 >> 4) & 0x07) { + case 1: + *tRC += 25; + break; + case 2: + *tRC += 33; + break; + case 3: + *tRC += 50; + break; + case 4: + *tRC += 66; + break; + case 5: + *tRC += 75; + break; + default: + break; + } + + /* Convert to 1/256th us */ + *tRC = (*tRC << 8) / 100; + *tRFC = (*tRFC << 8) / 100; +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR2 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]) +{ + u8 spd_size, cl, reg8; + u16 eeprom_size; + int ret = SPD_STATUS_OK; + + memset(dimm, 0, sizeof(*dimm)); + + spd_size = spd_decode_spd_size_ddr2(spd[0]); + eeprom_size = spd_decode_eeprom_size_ddr2(spd[1]); + + printram("EEPROM with 0x%04x bytes\n", eeprom_size); + printram("SPD contains 0x%02x bytes\n", spd_size); + + if (spd_size < 64 || eeprom_size < 64) { + printram("ERROR: SPD to small\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { + printram("ERROR: SPD checksum error\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_CRC_ERROR; + } + + reg8 = spd[62]; + if ((reg8 & 0xf0) != 0x10) { + printram("ERROR: Unsupported SPD revision %01x.%01x\n", + reg8 >> 4, reg8 & 0xf); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + dimm->rev = reg8; + printram(" Revision : %01x.%01x\n", dimm->rev >> 4, dimm->rev & 0xf); + + reg8 = spd[2]; + printram(" Type : 0x%02x\n", reg8); + if (reg8 != 0x08) { + printram("ERROR: Unsupported SPD type %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR2; + + dimm->row_bits = spd[3]; + printram(" Rows : %u\n", dimm->row_bits); + if ((dimm->row_bits > 31) || + ((dimm->row_bits > 15) && (dimm->rev < 0x13))) { + printram(" Invalid number of memory rows\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->col_bits = spd[4]; + printram(" Columns : %u\n", dimm->col_bits); + if (dimm->col_bits > 15) { + printram(" Invalid number of memory columns\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->ranks = (spd[5] & 0x7) + 1; + printram(" Ranks : %u\n", dimm->ranks); + + dimm->mod_width = spd[6]; + printram(" Module data width : x%u\n", dimm->mod_width); + if (!dimm->mod_width) { + printram(" Invalid module data width\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->width = spd[13]; + printram(" SDRAM width : x%u\n", dimm->width); + if (!dimm->width) { + printram(" Invalid SDRAM width\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->banks = spd[17]; + printram(" Banks : %u\n", dimm->banks); + if (!dimm->banks) { + printram(" Invalid module banks count\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + switch (spd[8]) { + case 0: + dimm->flags.operable_5_00V = 1; + printram(" Voltage : 5.0V\n"); + break; + case 1: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 2: + dimm->flags.operable_1_50V = 1; + printram(" Voltage : 1.5V\n"); + break; + case 3: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 4: + dimm->flags.operable_2_50V = 1; + printram(" Voltage : 2.5V\n"); + break; + case 5: + dimm->flags.operable_1_80V = 1; + printram(" Voltage : 1.8V\n"); + break; + default: + printram(" Unknown voltage level.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->cas_supported = spd[18]; + if ((dimm->cas_supported & 0x3) || !dimm->cas_supported) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported); + + if ((dimm->rev < 0x13) && (dimm->cas_supported & 0x80)) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + if ((dimm->rev < 0x12) && (dimm->cas_supported & 0x40)) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + /* CL=X */ + cl = spd_get_msbs(dimm->cas_supported); + + /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */ + dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); + /* SDRAM Access from Clock */ + dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); + + if (dimm->cas_supported & (1 << (cl - 1))) { + /* Minimum Clock Cycle at CLX-1 */ + dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]); + /* Maximum Data Access Time (tAC) from Clock at CLX-1 */ + dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]); + } + if (dimm->cas_supported & (1 << (cl - 2))) { + /* Minimum Clock Cycle at CLX-2 */ + dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]); + /* Maximum Data Access Time (tAC) from Clock at CLX-2 */ + dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]); + } + + reg8 = (spd[31] >> 5) | (spd[31] << 3); + if (!reg8) { + printram(" Invalid rank density.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + /* Rank density */ + dimm->ranksize_mb = 128 * reg8; + /* Module density */ + dimm->size_mb = dimm->ranksize_mb * dimm->ranks; + if (dimm->size_mb < 1024) + printram(" Capacity : %u MB\n", dimm->size_mb); + else + printram(" Capacity : %u GB\n", dimm->size_mb >> 10); + + /* SDRAM Maximum Cycle Time (tCKmax) */ + dimm->tCK = spd_decode_tck_time(spd[43]); + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd_decode_quarter_time(spd[36]); + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd_decode_quarter_time(spd[29]); + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd_decode_quarter_time(spd[28]); + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd_decode_quarter_time(spd[27]); + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = spd[30] << 8; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + spd_decode_tRCtRFC_time(&spd[40], &dimm->tRC, &dimm->tRFC); + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd_decode_quarter_time(spd[37]); + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd_decode_quarter_time(spd[38]); + /* Data Input Setup Time Before Strobe */ + dimm->tDS = spd_decode_bcd_time(spd[34]); + /* Data Input Hold Time After Strobe */ + dimm->tDH = spd_decode_bcd_time(spd[35]); + /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */ + dimm->tDQSQ = (spd[44] << 8) / 100; + /* SDRAM Device Maximum Read Data Hold Skew Factor */ + dimm->tQHS = (spd[45] << 8) / 100; + /* PLL Relock Time in us */ + dimm->tPLL = spd[46] << 8; + /* Refresh rate in us */ + dimm->tRR = spd_decode_tRR_time(spd[12]); + + /* Number of PLLs on DIMM */ + if (dimm->rev >= 0x11) + dimm->plls = (spd[21] >> 2) & 0x3; + + /* SDRAM Thermal and Refresh Options */ + printram(" General features :"); + if ((dimm->rev >= 0x12) && (spd[22] & 0x04)) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if ((dimm->rev >= 0x12) && (spd[22] & 0x02)) { + dimm->flags.terminate_50ohms = 1; + printram(" 50Ohm"); + } + if (spd[22] & 0x01) { + dimm->flags.weak_driver = 1; + printram(" WEAK_DRIVER"); + } + printram("\n"); + + /* SDRAM Supported Burst length */ + printram(" Burst length :"); + if (spd[16] & 0x06) { + dimm->flags.bl8 = 1; + printram(" BL8"); + } + if (spd[22] & 0x04) { + dimm->flags.bl4 = 1; + printram(" BL4"); + } + printram("\n"); + + dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; + printram(" Dimm type : %x\n", dimm->dimm_type); + + dimm->flags.is_ecc = !!(spd[11] & 0x3); + printram(" ECC support : %x\n", dimm->flags.is_ecc); + + dimm->flags.stacked = !!(spd[5] & 0x10); + printram(" Package : %s\n", + dimm->flags.stacked ? "stack" : "planar"); + + if (spd_size > 71) { + memcpy(&dimm->manufacturer_id, &spd[64], 4); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); + } + + if (spd_size > 90) { + dimm->part_number[16] = 0; + memcpy(dimm->part_number, &spd[73], 16); + printram(" Part number : %s\n", dimm->part_number); + } + + if (spd_size > 94) { + dimm->year = spd[93] + 2000; + dimm->weeks = spd[94]; + printram(" Date : %d week %d\n", dimm->year, dimm->weeks); + } + + if (spd_size > 98) { + memcpy(&dimm->serial, &spd[95], 4); + printram(" Serial number : 0x%08x\n", dimm->serial); + } + return ret; +} + +/* + * The information printed below has a more informational character, and is not + * necessarily tied in to RAM init debugging. Hence, we stop using printram(), + * and use the standard printk()'s below. + */ + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); +} + +static void print_us(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); +} + +/** +* \brief Print the info in DIMM +* +* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected, or for a purely informative output. +* +* @param dimm pointer to already decoded @ref dimm_attr structure +*/ +void dram_print_spd_ddr2(const struct dimm_attr_st *dimm) +{ + char buf[32]; + int i; + + printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); + printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Width : x%u\n", dimm->width); + printk(BIOS_INFO, " Banks : %u\n", dimm->banks); + + /* CAS Latencies Supported */ + printk(BIOS_INFO, " CAS latencies :"); + for (i = 2; i < 8; i++) { + if (dimm->cas_supported & (1 << i)) + printk(BIOS_INFO, " %u", i); + } + printk(BIOS_INFO, "\n"); + + for (i = 2; i < 8; i++) { + if (!(dimm->cas_supported & (1 << i))) + continue; + + strcpy(buf, " tCK at CLx : "); + /* Simple snprintf replacement */ + buf[11] = '0' + i; + print_ns(buf, dimm->cycle_time[i]); + + strcpy(buf, " tAC at CLx : "); + /* Simple snprintf replacement */ + buf[11] = '0' + i; + print_ns(buf, dimm->access_time[i]); + } + print_ns(" tCKmax : ", dimm->tCK); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tDS : ", dimm->tDS); + print_ns(" tDH : ", dimm->tDH); + print_ns(" tDQSQmax : ", dimm->tDQSQ); + print_ns(" tQHSmax : ", dimm->tQHS); + print_us(" tPLL : ", dimm->tPLL); + print_us(" tRR : ", dimm->tRR); +} diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index db661a9..87aa3c5 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -36,7 +36,7 @@ * * @param type DIMM type. This is byte[3] of the SPD. */ -int dimm_is_registered(enum spd_dimm_type type) +int spd_dimm_is_registered_ddr3(enum spd_dimm_type type) { if ((type == SPD_DIMM_TYPE_RDIMM) | (type == SPD_DIMM_TYPE_MINI_RDIMM) diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h new file mode 100644 index 0000000..7f59a7a --- /dev/null +++ b/src/include/device/dram/ddr2.h @@ -0,0 +1,218 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) + */ + +#ifndef DEVICE_DRAM_DDR2L_H +#define DEVICE_DRAM_DDR2L_H + +/** + * @file ddr2.h + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR2 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_800MHZ 320 +#define TCK_700MHZ 365 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/* + * Module type (byte 20, bits 5:0) of SPD + * This definition is specific to DDR2. DDR3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DIMM_TYPE_RDIMM = 0x01, + SPD_DIMM_TYPE_UDIMM = 0x02, + SPD_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, + SPD_DIMM_TYPE_MICRO_DIMM = 0x08, + SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_UDIMM = 0x20, + /* Masks to bits 5:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0x3f, +}; + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Module can work at 5.00V */ + unsigned operable_5_00V:1; + /* Module can work at 3.33V */ + unsigned operable_3_33V:1; + /* Module can work at 2.50V */ + unsigned operable_2_50V:1; + /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ + unsigned operable_1_80V:1; + /* Module can work at 1.50V */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_25V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* Supports weak driver */ + unsigned weak_driver:1; + /* Supports terminating at 50 Ohm */ + unsigned terminate_50ohms:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* Supports burst length 8 */ + unsigned bl8:1; + /* Supports burst length 4 */ + unsigned bl4:1; + /* DIMM Package is stack */ + unsigned stacked:1; + }; + unsigned int raw; +}; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + /* BCD SPD revision */ + u8 rev; + /* Supported CAS mask, bit 0 == CL0 .. bit7 == CL7 */ + u8 cas_supported; + /* Maximum cloclk to data cycle times for various CAS. + * Fields 0 and 1 are unused. */ + u32 cycle_time[8]; + /* Maximum data access times for various CAS. + * Fields 0 and 1 are unused. */ + u32 access_time[8]; + /* Flags extracted from SPD */ + union dimm_flags_st flags; + /* Number of banks */ + u8 banks; + /* SDRAM width */ + u8 width; + /* Module width */ + u8 mod_width; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Number of PLLs on module */ + u8 plls; + /* Size of module in MiB */ + u16 size_mb; + /* Size of one rank in MiB */ + u16 ranksize_mb; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tIS; + u32 tIH; + u32 tDS; + u32 tDH; + + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tDQSQ; + u32 tQHS; + + /* Latencies are in units of 1/256 us */ + u32 tPLL; + u32 tRR; + + /* Manufacturer ID */ + u32 manufacturer_id; + /* ASCII part number - NULL terminated */ + u8 part_number[17]; + /* Year manufactured */ + u16 year; + /* Week manufactured */ + u8 weeks; + /* Unique serial number */ + u32 serial; +}; + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +/** Maximum SPD size supported */ +#define SPD_SIZE_MAX_DDR2 128 + +int spd_dimm_is_registered_ddr2(enum spd_dimm_type type); +u8 spd_ddr2_calc_checksum(u8 *spd, int len); +u32 spd_decode_spd_size_ddr2(u8 byte0); +u32 spd_decode_eeprom_size_ddr2(u8 byte1); +int spd_decode_ddr2(struct dimm_attr_st *dimm, u8 spd[SPD_SIZE_MAX_DDR2]); +void dram_print_spd_ddr2(const struct dimm_attr_st *dimm); + + +#endif /* DEVICE_DRAM_DDR2L_H */ diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 905aa84..67d4458 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -201,7 +201,7 @@ typedef u8 spd_raw_data[256]; u16 spd_ddr3_calc_crc(u8 *spd, int len); u16 spd_ddr3_calc_unique_crc(u8 *spd, int len); int spd_decode_ddr3(dimm_attr * dimm, spd_raw_data spd_data); -int dimm_is_registered(enum spd_dimm_type type); +int spd_dimm_is_registered_ddr3(enum spd_dimm_type type); void dram_print_spd_ddr3(const dimm_attr * dimm); int spd_xmp_decode_ddr3(dimm_attr * dimm, spd_raw_data spd, diff --git a/src/northbridge/via/vx900/raminit_ddr3.c b/src/northbridge/via/vx900/raminit_ddr3.c index 4878571..2de7734 100644 --- a/src/northbridge/via/vx900/raminit_ddr3.c +++ b/src/northbridge/via/vx900/raminit_ddr3.c @@ -703,7 +703,7 @@ static void vx900_dram_freq(ramctr_timing * ctrl) pci_mod_config8(MCU, 0x6b, 0x80, 0x00); /* Step 8 - If we have registered DIMMs, we need to set bit[0] */ - if (dimm_is_registered(ctrl->dimm_type)) { + if (spd_dimm_is_registered_ddr3(ctrl->dimm_type)) { printram("Enabling RDIMM support in memory controller\n"); pci_mod_config8(MCU, 0x6c, 0x00, 0x01); }

1 0

Patch set updated for coreboot: libpayload: Enable SSE and FPU when present
by Patrick Rudolph 01 Mar '17

01 Mar '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18345 -gerrit commit fc2b8d15528cf5e281770fe6289d30e79422d220 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Jan 15 10:49:48 2017 +0100 libpayload: Enable SSE and FPU when present Allows to use SSE and floating point in payloads without digging to much into x86 assembly code. Tested on Lenovo T500 (Intel Core2Duo). Both floating point operation and SSE is properly working. Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- payloads/libpayload/arch/x86/head.S | 43 +++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/payloads/libpayload/arch/x86/head.S b/payloads/libpayload/arch/x86/head.S index 94a4d41..5250470 100644 --- a/payloads/libpayload/arch/x86/head.S +++ b/payloads/libpayload/arch/x86/head.S @@ -2,6 +2,7 @@ * This file is part of the libpayload project. * * Copyright (C) 2008 Advanced Micro Devices, Inc. + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -89,6 +90,48 @@ _init: movl $_stack, %esp pushl %eax + /* Enable special x86 functions if present. */ + pushl %eax + pushl %ebx + pushl %ecx + pushl %edx + + movl $0, %eax + cpuid + /* Test if CPUID(eax=1) is available. */ + test %eax, %eax + je cpuid_done + + /* Get CPU features. */ + movl $1, %eax + cpuid + +cpuid_fpu: + /* Test if x87 FPU is present */ + test $1, %edx + je cpuid_sse + + fninit + movl %cr0, %eax + andl $0xFFFFFFFB, %eax /* clear EM */ + orl $0x00000022, %eax /* set MP, NE */ + movl %eax, %cr0 + +cpuid_sse: + /* Test if SSE is available */ + test $0x02000000, %edx + je cpuid_done + + movl %cr4, %eax + orl $0x00000600, %eax /* set OSFXSR, OSXMMEXCPT */ + movl %eax, %cr4 + +cpuid_done: + popl %edx + popl %ecx + popl %ebx + popl %eax + /* Let's rock. */ call start_main

1 0

Patch set updated for coreboot: mb/google/poppy:[TESTONLY] report IMGU and CIO2 devices do not support Cache Coherent DMA
by Rizwan Qureshi 01 Mar '17

01 Mar '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18512 -gerrit commit 7dac809b0581dd65568009cf057635a6a673861e Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Feb 27 21:12:41 2017 +0530 mb/google/poppy:[TESTONLY] report IMGU and CIO2 devices do not support Cache Coherent DMA report IMGU and CIO2 devices do not support Cache Coherent DMA via _CCA ACPI object. Change-Id: I177cca42174fcb0bcc095088df30768b637f42df Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/dsdt.asl | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index 2007691..4f8e645 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -36,6 +36,23 @@ DefinitionBlock( Scope (\_SB) { + + /* Imaging Unit - Device 05, Function 0 */ + + Device (IMGU) + { + Name (_ADR, 0x00050000) + Name (_DDN, "Imaging Unit") + Name (_CCA, ZERO) + } + + Device (CIO2) + { + Name (_ADR, 0x0014003) + Name (_DDN, "Camera and Imaging Subsystem") + Name (_CCA, ZERO) + } + Device (PWRB) { Name (_HID, EisaId ("PNP0C0C"))

1 0

Patch set updated for coreboot: mb/google/poppy: Add camera support
by Rizwan Qureshi 01 Mar '17

01 Mar '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18081 -gerrit commit 93365c9ed4cc9cb64dd2801c3bd310a64d1fca0a Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jan 10 08:42:07 2017 +0530 mb/google/poppy: Add camera support Enable OV camera and TPS68470 PMIC support. Also enable the SA Imaging Unit and CIO2 devices. BUG=None BRANCH=None TEST=CIO2 and IMGU devices listed by lspci, SSDT table has the required ACPI entries. Change-Id: I5d8a1eb775029e949aeb3de26d8bae10a9d531b8 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 2 + src/mainboard/google/poppy/devicetree.cb | 128 ++++++++++++++++++++++++++++++- 2 files changed, 127 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 224f9b2..c95dc77 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -6,6 +6,8 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_16384 select DRIVERS_I2C_GENERIC select DRIVERS_I2C_HID + select DRIVERS_I2C_TPS68470 + select DRIVERS_I2C_OV_CAMERA select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index e2af00f..30b598c 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -36,7 +36,8 @@ chip soc/intel/skylake register "XdciEnable" = "0" register "SsicPortEnable" = "0" register "SmbusEnable" = "1" - register "Cio2Enable" = "0" + register "Cio2Enable" = "1" + register "SaImguEnable" = "1" register "ScsEmmcEnabled" = "1" register "ScsEmmcHs400Enabled" = "1" register "ScsSdCardEnabled" = "2" @@ -211,7 +212,75 @@ chip soc/intel/skylake end end # I2C #0 device pci 15.1 on end # I2C #1 - device pci 15.2 on end # I2C #2 + device pci 15.2 on + chip drivers/i2c/tps68470 + # PMIC CLDB Buffer + register "cldb_buf" = "{ \ + 0x00, 0x02, 0x00, 0x50,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00,\ + 0x00, 0x00, 0x00, 0x00\ + }" + device i2c 4d on end + end + chip drivers/i2c/ov_camera + register "acpi_hid" = ""OVTID850"" + register "acpi_name" = ""CAM0"" + register "acpi_uid" = "0" + register "vcm_addr" = "0xc" + register "eeprom0_addr" = "0x50" + + # Camera SSDB Buffer + register "buf.ssdb.version" = "0x00" + register "buf.ssdb.sensor_card_sku" = "0x50" + + register "buf.ssdb.csi2_data_stream_interface" = "{ \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + }" + + register "buf.ssdb.bdf_value" = "0x00" + register "buf.ssdb.dphy_link_en_fuses" = "0x00" + register "buf.ssdb.lanes_clock_division" = "0x00" + register "buf.ssdb.link_used" = "0x00" + register "buf.ssdb.lanes_used" = "0x04" + register "buf.ssdb.csi_rx_dly_cnt_termen_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane3" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane3" = "0x00" + register "buf.ssdb.max_lane_speed" = "0x00" + register "buf.ssdb.sensor_calibration_file_index" = "0x00" + register "buf.ssdb.sensor_calibration_file_index_mbz" = "{0x00, 0x00, 0x00}" + register "buf.ssdb.rom_type" = "0x08" + register "buf.ssdb.vcm_type" = "0x03" + register "buf.ssdb.platform" = "0x09" + register "buf.ssdb.platform_sub" = "0x00" + register "buf.ssdb.flash_support" = "0x02" + register "buf.ssdb.privacy_led" = "0x01" + register "buf.ssdb.degree" = "0x00" + register "buf.ssdb.mipi_define" = "0x01" + register "buf.ssdb.mclk" = "0x016E3600" + register "buf.ssdb.control_logic_id" = "0x00" + register "buf.ssdb.mipi_data_format" = "0x00" + register "buf.ssdb.silicon_version" = "0x00" + register "buf.ssdb.customer_id" = "0x00" + + device i2c 10 on end + end + + end # I2C #2 device pci 15.3 on chip drivers/i2c/hid register "generic.hid" = ""WCOM50C1"" @@ -252,7 +321,60 @@ chip soc/intel/skylake device i2c 13 on end end end # I2C #5 - device pci 19.2 on end # I2C #4 + device pci 19.2 on + chip drivers/i2c/ov_camera + register "acpi_hid" = ""INT3479"" + register "acpi_name" = ""CAM1"" + register "acpi_uid" = "0" + register "vcm_addr" = "0xc" + register "eeprom0_addr" = "0x50" + + # Camera SSDB Buffer + register "buf.ssdb.version" = "0x00" + register "buf.ssdb.sensor_card_sku" = "0x50" + + register "buf.ssdb.csi2_data_stream_interface" = "{ \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + 0x00, 0x00, 0x00, 0x00, \ + }" + + register "buf.ssdb.bdf_value" = "0x00" + register "buf.ssdb.dphy_link_en_fuses" = "0x00" + register "buf.ssdb.lanes_clock_division" = "0x00" + register "buf.ssdb.link_used" = "0x01" + register "buf.ssdb.lanes_used" = "0x02" + register "buf.ssdb.csi_rx_dly_cnt_termen_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_clane" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane0" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane1" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane2" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_termen_dlane3" = "0x00" + register "buf.ssdb.csi_rx_dly_cnt_settle_dlane3" = "0x00" + register "buf.ssdb.max_lane_speed" = "0x00" + register "buf.ssdb.sensor_calibration_file_index" = "0x00" + register "buf.ssdb.sensor_calibration_file_index_mbz" = "{0x00, 0x00, 0x00}" + register "buf.ssdb.rom_type" = "0x08" + register "buf.ssdb.vcm_type" = "0x03" + register "buf.ssdb.platform" = "0x09" + register "buf.ssdb.platform_sub" = "0x00" + register "buf.ssdb.flash_support" = "0x02" + register "buf.ssdb.privacy_led" = "0x01" + register "buf.ssdb.degree" = "0x00" + register "buf.ssdb.mipi_define" = "0x01" + register "buf.ssdb.mclk" = "0x016E3600" + register "buf.ssdb.control_logic_id" = "0x00" + register "buf.ssdb.mipi_data_format" = "0x00" + register "buf.ssdb.silicon_version" = "0x00" + register "buf.ssdb.customer_id" = "0x00" + + device i2c 10 on end + end + end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_PCI_EXP"

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Patch set updated for coreboot: drivers/i2c/tps68470: Add TPS68470 PMIC SSDT generator
by Rizwan Qureshi 01 Mar '17

01 Mar '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18063 -gerrit commit f79ffd16ae604db3bdcfa06bb21ff1630f98a0d6 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Mon Jan 9 19:00:06 2017 +0530 drivers/i2c/tps68470: Add TPS68470 PMIC SSDT generator Add TPS68470 PMIC SSDT generator. Change-Id: Iaa1dba094a7f791d5b624e545b03b510a4306337 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/drivers/i2c/tps68470/Kconfig | 2 + src/drivers/i2c/tps68470/Makefile.inc | 1 + src/drivers/i2c/tps68470/chip.h | 26 ++++++++++ src/drivers/i2c/tps68470/tps68470.c | 94 +++++++++++++++++++++++++++++++++++ 4 files changed, 123 insertions(+) diff --git a/src/drivers/i2c/tps68470/Kconfig b/src/drivers/i2c/tps68470/Kconfig new file mode 100644 index 0000000..75d81dc --- /dev/null +++ b/src/drivers/i2c/tps68470/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_TPS68470 + bool diff --git a/src/drivers/i2c/tps68470/Makefile.inc b/src/drivers/i2c/tps68470/Makefile.inc new file mode 100644 index 0000000..3fa4412 --- /dev/null +++ b/src/drivers/i2c/tps68470/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_TPS68470) += tps68470.c diff --git a/src/drivers/i2c/tps68470/chip.h b/src/drivers/i2c/tps68470/chip.h new file mode 100644 index 0000000..d82d9bd --- /dev/null +++ b/src/drivers/i2c/tps68470/chip.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> + +#define TPS68470_MAX_CLDB_BUF 32 + +struct drivers_i2c_tps68470_config { + + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned bus_speed; + + uint8_t cldb_buf[TPS68470_MAX_CLDB_BUF]; +}; diff --git a/src/drivers/i2c/tps68470/tps68470.c b/src/drivers/i2c/tps68470/tps68470.c new file mode 100644 index 0000000..f7c2ce1 --- /dev/null +++ b/src/drivers/i2c/tps68470/tps68470.c @@ -0,0 +1,94 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define TPS68470_ACPI_NAME "PMIC" + +static void tps68470_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_tps68470_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", "INT3472"); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + acpigen_write_method_serialized("CLDB",0); + acpigen_write_return_byte_buffer(config->cldb_buf, + TPS68470_MAX_CLDB_BUF); + + acpigen_pop_len(); /* Method */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + +} + +static const char *tps68470_acpi_name(struct device *dev) +{ + return TPS68470_ACPI_NAME; +} +#endif + +static struct device_operations tps68470_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &tps68470_acpi_name, + .acpi_fill_ssdt_generator = &tps68470_fill_ssdt, +#endif +}; + +static void tps68470_enable(struct device *dev) +{ + dev->ops = &tps68470_ops; +} + +struct chip_operations drivers_i2c_tps68470_ops = { + CHIP_NAME("TPS 68470 PMIC") + .enable_dev = &tps68470_enable +};

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coreboot-gerrit March 2017