the following patch was just integrated into master:
commit a154a910cb8a611aeb85757f3ca447eeaf75f93e
Author: Mono <mono-for-coreboot(a)donderklumpen.de>
Date: Sun Feb 26 13:35:17 2017 +0100
mb/apple/macbook21: Remove PCI reset code from romstage
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from
romstage). The PCI reset was copied from code specific for Roda
RK886EX and Kontron 986LCD-M. It is not needed on the MacBook.
Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e
Signed-off-by: Axel Holewa <mono-for-coreboot(a)donderklumpen.de>
Reviewed-on: https://review.coreboot.org/18502
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/18502 for details.
-gerrit
the following patch was just integrated into master:
commit 308aefffc6818bb46ef0f7b9b1f8dda8aaf5e08e
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Fri Feb 24 12:53:07 2017 +0100
nb/intel/i945: Fix sdram_enhanced_addressing_mode for channel1
Change-Id: I304467353bb9989f0d7e0ad7d1b632081f66b1af
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/18482
Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/18482 for details.
-gerrit
the following patch was just integrated into master:
commit c16d3893631de304493ffa3ec14d0171dc5321e8
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Thu Feb 23 16:56:54 2017 +0530
src/include: Include stdint.h since struct dimm_info uses it
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.
BUG=none
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
Reviewed-on: https://review.coreboot.org/18471
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <f4bug(a)amsat.org>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18471 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18471
-gerrit
commit 64f50ed767aafad9ba38a90054e803f523d61bac
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Thu Feb 23 16:56:54 2017 +0530
src/include: Include stdint.h since struct dimm_info uses it
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.
BUG=none
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
---
src/include/memory_info.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 4613628..02904af 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -16,6 +16,8 @@
#ifndef _MEMORY_INFO_H_
#define _MEMORY_INFO_H_
+#include <stdint.h>
+
/*
* If this table is filled and put in CBMEM,
* then these info in CBMEM will be used to generate smbios type 17 table
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18471
-gerrit
commit 2450e7be5d772035bdc83f7a79800dde306369a3
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Thu Feb 23 16:56:54 2017 +0530
src/include: Include stdint.h since struct dimm_info uses it
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.
BUG=none
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
---
src/include/memory_info.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/include/memory_info.h b/src/include/memory_info.h
index 4613628..02904af 100644
--- a/src/include/memory_info.h
+++ b/src/include/memory_info.h
@@ -16,6 +16,8 @@
#ifndef _MEMORY_INFO_H_
#define _MEMORY_INFO_H_
+#include <stdint.h>
+
/*
* If this table is filled and put in CBMEM,
* then these info in CBMEM will be used to generate smbios type 17 table
the following patch was just integrated into master:
commit e13b77564f71dd125f2e4691407ac39efe552b6e
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Tue Feb 21 16:24:49 2017 +0530
soc/intel/common: Save Memory DIMM Information in SMBIOS table
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
Reviewed-on: https://review.coreboot.org/18418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18418 for details.
-gerrit
the following patch was just integrated into master:
commit 9e54978f6ef7c12d6da07f64ad665c0e47deba50
Author: Barnali Sarkar <barnali.sarkar(a)intel.com>
Date: Fri Feb 10 21:46:05 2017 +0530
src/vendorcode: Add Memory Info Data HOB Header
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com>
Reviewed-on: https://review.coreboot.org/18326
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18326 for details.
-gerrit
Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18526
-gerrit
commit 06a7c50b471ad534340379a1e64827dd1512788d
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Wed Mar 1 13:31:40 2017 +0200
[NOTFORMERGE] binaryPI CAR: Revert invd to wbinvd change
Requires binaryPI romstages to get fixed first.
The change was originally applied as a workaround to allow
disable_cache_as_ram() to be called with a stack frame, in
the middle of cache_as_ram_main().
Comments next to AMD_DISABLE_STACK tell to destroy the stack.
AGESA documentation and comparison to another CAR implementation
under NDA (cpcar.inc) tell to use invalidate without writeback here.
Also, using writeback here is suspected to cause low-memory
corruption on S3 resume path for platforms without PSP.
There is no documentation telling one must use writeback here
for any affected APU platforms touched here.
Now that disable_cache_as_ram() equivalent executes with no
stack, we can avoid pointless differentiation of CAR setup code
between different AMD APUs, and also in comparison against
perhaps the more authoritive CAR setup in cpcar.inc used with
UEFI implementations.
Change-Id: I693c104c3aab3be537c00695cbd764a48bd603b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
---
src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc | 2 +-
src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc | 2 +-
src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc | 2 +-
src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc | 3 +--
4 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
index 2707cab..15f3247 100644
--- a/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
@@ -903,7 +903,7 @@ fam15_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- wbinvd # Clear the cache tag RAMs
+ invd # Clear the cache tag RAMs
#.if (bh == 01h) || (bh == 03h) ; Is this TN or KV?
cmp $01, %bh
jz 4f
diff --git a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
index d6782a3..19102fc 100644
--- a/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
@@ -638,7 +638,7 @@ fam15_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- wbinvd #bao # Clear the cache tag RAMs
+ invd # Clear the cache tag RAMs
# #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
# cmp $01, %bh
# jz 4f
diff --git a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
index d6782a3..19102fc 100644
--- a/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
@@ -638,7 +638,7 @@ fam15_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- wbinvd #bao # Clear the cache tag RAMs
+ invd # Clear the cache tag RAMs
# #.if (bh == 01h) || (bh == 03h) ; Is this TN or KM?
# cmp $01, %bh
# jz 4f
diff --git a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
index 2c51eb1..a0a7965 100644
--- a/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
+++ b/src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
@@ -602,8 +602,7 @@ fam16_disable_stack_remote_read_exit:
_RDMSR
btr $INVD_WBINVD, %eax # Disable INVD -> WBINVD conversion
_WRMSR
- wbinvd # Clear the cache tag RAMs
- #invd
+ invd # Clear the cache tag RAMs
#Do Standard Family 16 work
mov $HWCR, %ecx # MSR:C001_0015h