coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

1 participants
2925 discussions

New patch to review for coreboot: console: Enable printk for ENV_LIBAGESA
by Kyösti Mälkki 02 Mar '17

02 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18545 -gerrit commit b9e39488091d6691496d77653bfe989e1e0e1632 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 2 12:29:59 2017 +0200 console: Enable printk for ENV_LIBAGESA Messages from AGESA proper are additionally controlled by various IDS parameters in buildsOpts.c file of mainboard. Change-Id: I83e975d37ad2bdecb09c483ecae71c0ed6877731 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/console/console.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/console/console.h b/src/include/console/console.h index 013ef20..7edce52 100644 --- a/src/include/console/console.h +++ b/src/include/console/console.h @@ -42,7 +42,7 @@ void __attribute__ ((noreturn)) die(const char *msg); #define __CONSOLE_ENABLE__ \ ((ENV_BOOTBLOCK && IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) || \ (ENV_POSTCAR && IS_ENABLED(CONFIG_POSTCAR_CONSOLE)) || \ - ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || \ + ENV_VERSTAGE || ENV_ROMSTAGE || ENV_RAMSTAGE || ENV_LIBAGESA || \ (ENV_SMM && CONFIG_DEBUG_SMI)) #if __CONSOLE_ENABLE__

1 0

New patch to review for coreboot: Stage rules.h: Add ENV_LIBAGESA
by Kyösti Mälkki 02 Mar '17

02 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18544 -gerrit commit 17d90245949d4935a2e61043d4f033d1a3614fcf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 2 13:01:58 2017 +0200 Stage rules.h: Add ENV_LIBAGESA Definition is required to enable use of printk() from AGESA proper. Change-Id: I6666a003c91794490f670802d496321ffb965cd3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/include/rules.h | 19 +++++++++++++++++++ src/vendorcode/amd/agesa/Makefile.inc | 1 + 2 files changed, 20 insertions(+) diff --git a/src/include/rules.h b/src/include/rules.h index a632804..45622ea 100644 --- a/src/include/rules.h +++ b/src/include/rules.h @@ -27,6 +27,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "bootblock" #elif defined(__ROMSTAGE__) @@ -37,6 +38,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "romstage" #elif defined(__SMM__) @@ -47,6 +49,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "smm" #elif defined(__VERSTAGE__) @@ -57,6 +60,7 @@ #define ENV_VERSTAGE 1 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "verstage" #elif defined(__RAMSTAGE__) @@ -67,6 +71,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "ramstage" #elif defined(__RMODULE__) @@ -77,6 +82,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 1 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "rmodule" #elif defined(__POSTCAR__) @@ -87,8 +93,20 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 1 +#define ENV_LIBAGESA 0 #define ENV_STRING "postcar" +#elif defined(__LIBAGESA__) +#define ENV_BOOTBLOCK 0 +#define ENV_ROMSTAGE 0 +#define ENV_RAMSTAGE 0 +#define ENV_SMM 0 +#define ENV_VERSTAGE 0 +#define ENV_RMODULE 0 +#define ENV_POSTCAR 0 +#define ENV_LIBAGESA 1 +#define ENV_STRING "libagesa" + #else /* * Default case of nothing set for random blob generation using @@ -103,6 +121,7 @@ #define ENV_VERSTAGE 0 #define ENV_RMODULE 0 #define ENV_POSTCAR 0 +#define ENV_LIBAGESA 0 #define ENV_STRING "UNKNOWN" #endif diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index fab6f63..f2423d0 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -12,6 +12,7 @@ subdirs-y += common classes-y += libagesa libagesa-y = +libagesa-generic-ccopts += -D__LIBAGESA__ ifeq ($(CONFIG_ARCH_ROMSTAGE_X86_32),y) $(eval $(call create_class_compiler,libagesa,x86_32))

1 0

New patch to review for coreboot: AGESA: Make eventlog more tolerant to failures
by Kyösti Mälkki 02 Mar '17

02 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18543 -gerrit commit 38cd64645b8364b20ce64c71a3ba5caff5675955 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 2 13:52:54 2017 +0200 AGESA: Make eventlog more tolerant to failures We have been forced to build AGESA with ASSERT() as non-fatal for some board, as hitting those errors is not uncommon. For the cases touched here, abort eventlog operations early with null pointers and errors. Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c | 9 +++++++++ src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c | 9 +++++++++ src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c | 9 +++++++++ src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c | 9 +++++++++ src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c | 9 +++++++++ src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c | 9 +++++++++ 6 files changed, 54 insertions(+) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c index 6a0033f..b703e9d 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c @@ -117,6 +117,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -205,6 +207,9 @@ PutEventLog ( AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return; + Index = AgesaEventAlloc->WriteRecordPtr; // Add the new event log data into a circular buffer @@ -267,6 +272,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return AGESA_BOUNDS_CHK; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { @@ -324,6 +331,8 @@ PeekEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return FALSE; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c index fcd23fb..3f8c63b 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c @@ -121,6 +121,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -219,6 +221,9 @@ PutEventLog ( AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return; + Index = AgesaEventAlloc->WriteRecordPtr; // Add the new event log data into a circular buffer @@ -281,6 +286,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return AGESA_BOUNDS_CHK; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { @@ -338,6 +345,8 @@ PeekEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return FALSE; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c index b7c507f..f6c2c9c 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c @@ -124,6 +124,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -222,6 +224,9 @@ PutEventLog ( AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return; + Index = AgesaEventAlloc->WriteRecordPtr; // Add the new event log data into a circular buffer @@ -284,6 +289,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return AGESA_BOUNDS_CHK; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { @@ -341,6 +348,8 @@ PeekEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return FALSE; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c index a9a2821..0e00fe6 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c @@ -122,6 +122,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -220,6 +222,9 @@ PutEventLog ( AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return; + Index = AgesaEventAlloc->WriteRecordPtr; // Add the new event log data into a circular buffer @@ -282,6 +287,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return AGESA_BOUNDS_CHK; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { @@ -339,6 +346,8 @@ PeekEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return FALSE; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c index c6f20bd..7d0306f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c @@ -121,6 +121,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -219,6 +221,9 @@ PutEventLog ( AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return; + Index = AgesaEventAlloc->WriteRecordPtr; // Add the new event log data into a circular buffer @@ -281,6 +286,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return AGESA_BOUNDS_CHK; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { @@ -338,6 +345,8 @@ PeekEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return FALSE; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c index 5df76fb..ae87458 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c @@ -121,6 +121,8 @@ AmdReadEventLog ( ASSERT (Event != NULL); Event->StdHeader.HeapBasePtr = HeapGetBaseAddress (&Event->StdHeader); Status = GetEventLog (&LogEvent, &Event->StdHeader); + if (Status != AGESA_SUCCESS) + return Status; Event->EventClass = LogEvent.EventClass; Event->EventInfo = LogEvent.EventInfo; @@ -219,6 +221,9 @@ PutEventLog ( AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return; + Index = AgesaEventAlloc->WriteRecordPtr; // Add the new event log data into a circular buffer @@ -281,6 +286,8 @@ GetEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return AGESA_BOUNDS_CHK; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) { @@ -338,6 +345,8 @@ PeekEventLog ( GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); + if (AgesaEventAlloc == NULL) + return FALSE; if ((AgesaEventAlloc->ReadRecordPtr == AgesaEventAlloc->WriteRecordPtr) && (AgesaEventAlloc->ReadWriteFlag == 1)) {

1 0

New patch to review for coreboot: AGESA: Apply a threshold on event logging
by Kyösti Mälkki 02 Mar '17

02 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18542 -gerrit commit 80e33e007d735293257bc9944c3b6f2ae037c382 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Mar 2 13:53:21 2017 +0200 AGESA: Apply a threshold on event logging Implement as defined in AMD.h, do not add entries below STATUS_LOG_LEVEL == AGESA_ALERT in the eventlog. Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c | 3 +++ src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c | 3 +++ src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c | 3 +++ src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c | 3 +++ src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c | 3 +++ src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c | 3 +++ 6 files changed, 18 insertions(+) diff --git a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c index 3c41f5d..6a0033f 100644 --- a/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f10/Proc/CPU/cpuEventLog.c @@ -199,6 +199,9 @@ PutEventLog ( UINT16 Index; AGESA_STRUCT_BUFFER *AgesaEventAlloc; + if (EventClass < AGESA_STATUS_LOG_LEVEL) + return; + AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); diff --git a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c index f802542..fcd23fb 100644 --- a/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f12/Proc/CPU/cpuEventLog.c @@ -213,6 +213,9 @@ PutEventLog ( (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); + if (EventClass < AGESA_STATUS_LOG_LEVEL) + return; + AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); diff --git a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c index e0ad3c6..b7c507f 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f14/Proc/CPU/cpuEventLog.c @@ -216,6 +216,9 @@ PutEventLog ( (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); + if (EventClass < AGESA_STATUS_LOG_LEVEL) + return; + AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); diff --git a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c index 98d818c..a9a2821 100644 --- a/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f15/Proc/CPU/cpuEventLog.c @@ -214,6 +214,9 @@ PutEventLog ( (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); + if (EventClass < AGESA_STATUS_LOG_LEVEL) + return; + AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c index f73f50b..c6f20bd 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuEventLog.c @@ -213,6 +213,9 @@ PutEventLog ( (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); + if (EventClass < AGESA_STATUS_LOG_LEVEL) + return; + AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL); diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c index 4b6a9f9..5df76fb 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/CPU/cpuEventLog.c @@ -213,6 +213,9 @@ PutEventLog ( (EventClass == AGESA_UNSUPPORTED) ? "UNSUPPORTED" : "SUCCESS", EventInfo, DataParam1, DataParam2, DataParam3, DataParam4); + if (EventClass < AGESA_STATUS_LOG_LEVEL) + return; + AgesaEventAlloc = NULL; GetEventLogHeapPointer (&AgesaEventAlloc, StdHeader); ASSERT (AgesaEventAlloc != NULL);

1 0

Patch set updated for coreboot: AGESA: Use printk for IDS output
by Kyösti Mälkki 02 Mar '17

02 Mar '17

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15320 -gerrit commit cb7cc6c13dce5cd5caa33e7c4aa3809994c468c3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed Jun 22 22:50:10 2016 +0300 AGESA: Use printk for IDS output In all simplicity, with OptionsIds.c under mainboard directory set to: IDSOPT_IDS_ENABLED TRUE IDSOPT_TRACING_ENABLED TRUE And in src/Kconfig config WARNINGS_ARE_ERRORS default n With these settings AGESA outputs complete debugging log where-ever you have your coreboot console configured. Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/vendorcode/amd/agesa/f14/Include/Ids.h | 16 ++++----------- src/vendorcode/amd/agesa/f15/Include/Ids.h | 29 +++++----------------------- src/vendorcode/amd/agesa/f15tn/Include/Ids.h | 12 ++++-------- src/vendorcode/amd/agesa/f16kb/Include/Ids.h | 16 ++++----------- 4 files changed, 17 insertions(+), 56 deletions(-) diff --git a/src/vendorcode/amd/agesa/f14/Include/Ids.h b/src/vendorcode/amd/agesa/f14/Include/Ids.h index 451c4d6..7637aa7 100644 --- a/src/vendorcode/amd/agesa/f14/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f14/Include/Ids.h @@ -561,19 +561,11 @@ typedef enum { //vv- for debug reference only #define IDS_HDT_CONSOLE_S3_EXIT(x) #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE - #ifdef __GNUC__ - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) - #endif + #ifndef __GNUC__ + #pragma warning(disable: 4127) + #define IDS_HDT_CONSOLE(f, s, ...) #else - #ifndef __GNUC__ - #pragma warning(disable: 4127) - #define IDS_HDT_CONSOLE(f, s, ...) - #else - #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); - #endif + #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); #endif #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) diff --git a/src/vendorcode/amd/agesa/f15/Include/Ids.h b/src/vendorcode/amd/agesa/f15/Include/Ids.h index 07ceeaf..380cb55 100644 --- a/src/vendorcode/amd/agesa/f15/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f15/Include/Ids.h @@ -530,30 +530,11 @@ typedef enum { //vv- for debug reference only #define IDS_HDT_CONSOLE_S3_EXIT(x) #define IDS_HDT_CONSOLE_S3_AP_EXIT(x) - #ifdef __GNUC__ - #if CONFIG_REDIRECT_IDS_HDT_CONSOLE_TO_SERIAL - /* print all*/ - //#define IDS_HDT_CONSOLE(f, s, args...) do {do_printk(BIOS_DEBUG, s, ##args);} while (0) - #define IDS_HDT_CONSOLE(f, s, args...) do {\ - if (f == MAIN_FLOW) {\ - do_printk(BIOS_DEBUG, s, ##args);\ - } else if (f == MEM_FLOW) {\ - do_printk(BIOS_DEBUG, s, ##args);\ - } else if (f == CPU_TRACE) {\ - do_printk(BIOS_DEBUG, s, ##args);\ - } else if (f == HT_TRACE) {\ - do_printk(BIOS_DEBUG, s, ##args);\ - } else if (f == GNB_TRACE) {\ - do_printk(BIOS_DEBUG, s, ##args);\ - } else if (f == FCH_TRACE) {\ - do_printk(BIOS_DEBUG, s, ##args);\ - }\ - } while(0) - #else - #define IDS_HDT_CONSOLE(s, args...) do {} while(0) - #endif - #else - #define IDS_HDT_CONSOLE(s, args...) + #ifndef __GNUC__ + #pragma warning(disable: 4127) + #define IDS_HDT_CONSOLE(f, s, ...) + #else + #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); #endif #define IDS_HDT_CONSOLE_FLUSH_BUFFER(x) diff --git a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h index b2cf9f3..52b1824 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/Ids.h @@ -730,15 +730,11 @@ typedef enum { //vv- for debug reference only #endif #else #ifdef VA_ARGS_SUPPORTED - #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE - #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__) - #else + #ifndef __GNUC__ #pragma warning(disable: 4127) - #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \ - else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \ - else if (f == HT_TRACE) AmdIdsDebugPrintHt (s, __VA_ARGS__); \ - else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \ - else AmdIdsDebugPrint (f, s, __VA_ARGS__) + #define IDS_HDT_CONSOLE(f, s, ...) + #else + #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); #endif #else #define IDS_HDT_CONSOLE AmdIdsDebugPrint diff --git a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h index 53477cb..aa0ec05 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/Ids.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/Ids.h @@ -737,19 +737,11 @@ typedef enum { //vv- for debug reference only /// AGESA tracing service #if IDSOPT_TRACING_ENABLED == TRUE - #ifdef VA_ARGS_SUPPORTED - #if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE - #define IDS_HDT_CONSOLE(f, s, ...) AmdIdsDebugPrint (f, s, __VA_ARGS__) - #else - #pragma warning(disable: 4127) - #define IDS_HDT_CONSOLE(f, s, ...) if (f == MEM_FLOW) AmdIdsDebugPrintMem (s, __VA_ARGS__); \ - else if (f == CPU_TRACE) AmdIdsDebugPrintCpu (s, __VA_ARGS__); \ - else if (f == HT_TRACE) AmdIdsDebugPrintHt (s, __VA_ARGS__); \ - else if (f == GNB_TRACE) AmdIdsDebugPrintGnb (s, __VA_ARGS__); \ - else AmdIdsDebugPrint (f, s, __VA_ARGS__) - #endif + #ifndef __GNUC__ + #pragma warning(disable: 4127) + #define IDS_HDT_CONSOLE(f, s, ...) #else - #define IDS_HDT_CONSOLE AmdIdsDebugPrint + #define IDS_HDT_CONSOLE(f, s, ...) printk (BIOS_DEBUG, s, ##__VA_ARGS__); #endif #define CONSOLE AmdIdsDebugPrintAll #define IDS_HDT_CONSOLE_DEBUG_CODE(Code) Code

1 0

Patch set updated for coreboot: intelblocks/msr: Move x86 MSR definition into common location
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18509 -gerrit commit dc84c8e4bbca2b6e126066db979f25cb1d46cf0e Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:42:09 2017 +0530 intelblocks/msr: Move x86 MSR definition into common location Move all common MSRs as per IA SDM into a common location to avoid duplication. Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/include/cpu/x86/msr.h | 1 - .../intel/common/block/include/intelblocks/msr.h | 102 +++++++++++++++++++++ 2 files changed, 102 insertions(+), 1 deletion(-) diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index f830f3b..f01162b 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -16,7 +16,6 @@ static void wrmsr(unsigned long index, msr_t msr) } #else - typedef struct msr_struct { unsigned lo; diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h new file mode 100644 index 0000000..27607f5 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_MSR_H +#define SOC_INTEL_COMMON_MSR_H + +#define MSR_CORE_THREAD_COUNT 0x35 +#define IA32_FEATURE_CONTROL 0x3a +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_IA32_PERF_CTL 0x199 +#define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc +#define MSR_EVICT_CTL 0x2e0 +#define IA32_MC0_STATUS 0x401 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_PKG_POWER_LIMIT 0x610 +/* + * For Mobile, RAPL default PL1 time window value set to 28 seconds. + * RAPL time window calculation defined as follows: + * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], + * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. + */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_COUNTER_24_MHZ 0x637 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +#define MSR_IA32_PQR_ASSOC 0x0c8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#define MSR_IA32_L3_MASK_1 0x0c91 +#define MSR_IA32_L3_MASK_2 0x0c92 +#define MSR_L2_QOS_MASK(reg) (0xd10 + reg) + +#endif /* SOC_INTEL_COMMON_MSR_H */ +

1 0

New patch to review for coreboot: mb/getac/p470: Do not select EARLY_CBMEM_INIT
by Arthur Heymans 02 Mar '17

02 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18541 -gerrit commit 5b055200c3bd7f1dbcbc4a27781920e256045f65 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Mar 2 14:57:05 2017 +0100 mb/getac/p470: Do not select EARLY_CBMEM_INIT This is selected by default and not overwritten anywhere else for this board. Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/getac/p470/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index ea68bed..cdcd9cc 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -33,7 +33,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select CHANNEL_XOR_RANDOMIZATION - select EARLY_CBMEM_INIT select VGA select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG

1 0

New patch to review for coreboot: console/init: Consider NVRAM log level in romstage
by Paul Menzel 02 Mar '17

02 Mar '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18540 -gerrit commit 150f189bcef4d05402dced64eda6ac99c6601aff Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Thu Mar 2 14:43:10 2017 +0100 console/init: Consider NVRAM log level in romstage Change-Id: Ibfc9f942a3100c2be184d150f1acd2fbc7a627ad Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/console/init.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/console/init.c b/src/console/init.c index 189079b..81668a1 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -32,10 +32,8 @@ int console_log_level(int msg_level) asmlinkage void console_init(void) { -#if !defined(__PRE_RAM__) console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL; get_option(&console_loglevel, "debug_level"); -#endif #if CONFIG_EARLY_PCI_BRIDGE && !defined(__SMM__) pci_early_bridge_init();

1 0

Patch set updated for coreboot: soc/intel/glk: Include cache_as_ram_fsp.S inside glk/bootblock
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18453 -gerrit commit 095f9428a3943bd9b452ece6faed92558ad78305 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 16:22:58 2017 +0530 soc/intel/glk: Include cache_as_ram_fsp.S inside glk/bootblock Add option to use FSP APIs to initialize & Tear Down the Cache-As-Ram. Change-Id: I4964fa27967323062c6243e023d2caa82b7f0440 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Makefile.inc | 2 + src/soc/intel/glk/bootblock/cache_as_ram_fsp.S | 111 +++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index b2a430a..8ca6162 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -10,6 +10,8 @@ subdirs-y += ../../../cpu/x86/cache subdirs-y += ../common/basecode subdirs-y += ../common/block/* +bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S + CPPFLAGS_common += -I$(src)/soc/intel/glk/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk diff --git a/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S b/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S new file mode 100644 index 0000000..f55582a --- /dev/null +++ b/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +#define FSP_HDR_OFFSET 0x94 + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add FSP_HDR_OFFSET, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ + add 0x1c(%ebx), %eax /* add the FSP ImageBase */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +/* + * If the TempRamInit API is successful, then when returning, the ECX and + * EDX registers will point to the temporary but writeable memory range + * available to the bootloader where ECX is the start and EDX is the end of + * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more + * information. + * + * Return Values: + * EAX | Return Status + * ECX | Temporary Memory Start + * EDX | Temporary Memory End + * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call + */ + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00"

1 0

Patch set updated for coreboot: soc/intel/glk: Use intel/common/xhci driver
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18450 -gerrit commit a8a4591b86b9855023f750f273ae2f3414ae0fa5 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 15:39:23 2017 +0530 soc/intel/glk: Use intel/common/xhci driver Change-Id: I08fbe7c7ac83d12af1cc77450001103a7069d7d8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index c882e58..1ce077f 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_COMMON_XHCI select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit March 2017