coreboot-gerrit March 2017

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Patch set updated for coreboot: soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP]
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18449 -gerrit commit 28482bf2f5cbe4aaf0ceecc3e9347fbf28b8f4e6 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 15:01:26 2017 +0530 soc/intel/glk: Add Kconfig and Makefile.inc for GLK SoC[WIP] Copied from APL latest git. Change-Id: Icf1bb95cd2503e12f8ce26d77d2cd940a2ea1b69 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 232 +++++++++++++++++++++++++++++++++++++++++ src/soc/intel/glk/Makefile.inc | 40 +++++++ 2 files changed, 272 insertions(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig new file mode 100644 index 0000000..a0f9664 --- /dev/null +++ b/src/soc/intel/glk/Kconfig @@ -0,0 +1,232 @@ +config SOC_INTEL_GLK + bool + help + Intel GLK support + +if SOC_INTEL_GLK + +config CPU_SPECIFIC_OPTIONS + def_bool y + select ACPI_INTEL_HARDWARE_SLEEP_VALUES + select ARCH_BOOTBLOCK_X86_32 + select ARCH_RAMSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_CONSOLE + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if BOOT_DEVICE_SPI_FLASH + select BOOT_DEVICE_SUPPORTS_WRITES + # CPU specific options + select CPU_INTEL_FIRMWARE_INTERFACE_TABLE + select IOAPIC + select SMP + select SSE2 + select SUPPORT_CPU_UCODE_IN_CBFS + # Audio options + select ACPI_NHLT + select SOC_INTEL_COMMON_NHLT + # Misc options + select C_ENVIRONMENT_BOOTBLOCK + select CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM if RELOCATABLE_RAMSTAGE + select COLLECT_TIMESTAMPS + select COMMON_FADT + select GENERIC_GPIO_LIB + select HAVE_INTEL_FIRMWARE + select HAVE_SMI_HANDLER + select MRC_SETTINGS_PROTECT + select NO_FIXED_XIP_ROM_SIZE + select NO_XIP_EARLY_STAGES + select PARALLEL_MP + select PARALLEL_MP_AP_WORK + select PCIEXP_ASPM + select PCIEXP_COMMON_CLOCK + select PCIEXP_CLK_PM + select PCIEXP_L1_SUB_STATE + select POSTCAR_CONSOLE + select POSTCAR_STAGE + select REG_SCRIPT + select RELOCATABLE_RAMSTAGE # Build fails if this is not selected + select RTC + select SMM_TSEG + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_ACPI + select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_LPSS_I2C + select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select UDELAY_TSC + select TSC_CONSTANT_RATE + select TSC_MONOTONIC_TIMER + select HAVE_MONOTONIC_TIMER + select PLATFORM_USES_FSP2_0 + select HAVE_HARD_RESET + select SOC_INTEL_COMMON + select SOC_INTEL_COMMON_GFX_OPREGION + select ADD_VBT_DATA_FILE + +config CHROMEOS + select CHROMEOS_RAMOOPS_DYNAMIC + select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC + select SEPARATE_VERSTAGE + select VBOOT_OPROM_MATTERS + select VBOOT_SAVE_RECOVERY_REASON_ON_REBOOT + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + select VIRTUAL_DEV_SWITCH + +config TPM_ON_FAST_SPI + bool + default n + select LPC_TPM + help + TPM part is conntected on Fast SPI interface, but the LPC MMIO + TPM transactions are decoded and serialized over the SPI interface. + +config SOC_INTEL_COMMON_RESET + bool + default y + +config MMCONF_BASE_ADDRESS + hex "PCI MMIO Base Address" + default 0xe0000000 + +config IOSF_BASE_ADDRESS + hex "MMIO Base Address of sideband bus" + default 0xd0000000 + +config DCACHE_RAM_BASE + hex "Base address of cache-as-RAM" + default 0xfef00000 + +config DCACHE_RAM_SIZE + hex "Length in bytes of cache-as-RAM" + default 0xc0000 + help + The size of the cache-as-ram region required during bootblock + and/or romstage. + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + +config CPU_ADDR_BITS + int + default 36 + +config SOC_INTEL_COMMON_LPSS_I2C_CLOCK_MHZ + depends on SOC_INTEL_COMMON_LPSS_I2C + int + default 133 + +config CONSOLE_UART_BASE_ADDRESS + depends on CONSOLE_SERIAL + hex "MMIO base address for UART" + default 0xde000000 + +config SOC_UART_DEBUG + bool "Enable SoC UART debug port selected by UART_FOR_CONSOLE." + default n + select CONSOLE_SERIAL + select DRIVERS_UART + select DRIVERS_UART_8250MEM_32 + select NO_UART_ON_SUPERIO + +# 32KiB bootblock is all that is mapped in by the CSE at top of 4GiB. +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + +# This SoC does not map SPI flash like many previous SoC. Therefore we provide +# a custom media driver that facilitates mapping +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n + +config ROMSTAGE_ADDR + hex + default 0xfef20000 + help + The base address (in CAR) where romstage should be linked + +config VERSTAGE_ADDR + hex + default 0xfef40000 + help + The base address (in CAR) where verstage should be linked + +config CACHE_MRC_SETTINGS + bool + default y + +config MRC_SETTINGS_VARIABLE_DATA + bool + default y + +config FSP_M_ADDR + hex + default 0xfef40000 + help + The address FSP-M will be relocated to during build time + +config NEED_LBP2 + bool "Write contents for logical boot partition 2." + default n + help + Write the contents from a file into the logical boot partition 2 + region defined by LBP2_FMAP_NAME. + +config LBP2_FMAP_NAME + string "Name of FMAP region to put logical boot partition 2" + depends on NEED_LBP2 + default "SIGN_CSE" + help + Name of FMAP region to write logical boot partition 2 data. + +config LBP2_FILE_NAME + string "Path of file to write to logical boot partition 2 region" + depends on NEED_LBP2 + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/lbp2.bin" + help + Name of file to store in the logical boot partition 2 region. + +config NEED_IFWI + bool "Write content into IFWI region" + default n + help + Write the content from a file into IFWI region defined by + IFWI_FMAP_NAME. + +config IFWI_FMAP_NAME + string "Name of FMAP region to pull IFWI into" + depends on NEED_IFWI + default "IFWI" + help + Name of FMAP region to write IFWI. + +config IFWI_FILE_NAME + string "Path of file to write to IFWI region" + depends on NEED_IFWI + default "3rdparty/blobs/mainboard/$(CONFIG_MAINBOARD_DIR)/ifwi.bin" + help + Name of file to store in the IFWI region. + +config HEAP_SIZE + hex + default 0x8000 + +config SPI_FLASH_INCLUDE_ALL_DRIVERS + bool + default n + +config SMM_RESERVED_SIZE + hex + default 0x100000 + +config IFD_CHIPSET + string + default "aplk" + +endif diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc new file mode 100644 index 0000000..92c3bc2 --- /dev/null +++ b/src/soc/intel/glk/Makefile.inc @@ -0,0 +1,40 @@ +ifeq ($(CONFIG_SOC_INTEL_GLK),y) + +subdirs-y += ../../../cpu/intel/microcode +subdirs-y += ../../../cpu/intel/turbo +subdirs-y += ../../../cpu/x86/lapic +subdirs-y += ../../../cpu/x86/mtrr +subdirs-y += ../../../cpu/x86/smm +subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../../../cpu/x86/cache + +CPPFLAGS_common += -I$(src)/soc/intel/glk/include +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk + +# Since FSP-M runs in CAR we need to relocate it to a specific address +$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_M_ADDR) + +ifeq ($(CONFIG_NEED_LBP2),y) +files_added:: + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward +endif + +# Bootblock on GLK platform lies in the IFWI region. In order to place +# the bootblock at the right location in IFWI image - +# a. Using ifwitool: +# 1. Create IFWI image (ifwi.bin.tmp) from input image +# (CONFIG_IFWI_FILE_NAME). +# 2. Delete OBBP sub-partition, if present. +# 3. Replace IBBL directory entry in IBBP sub-partition with currently +# generated bootblock.bin. +# b. Using cbfstool: +# 1. Write ifwi.bin.tmp to coreboot.rom using CONFIG_IFWI_FMAP_NAME. +ifeq ($(CONFIG_NEED_IFWI),y) +files_added:: $(IFWITOOL) + $(IFWITOOL) $(CONFIG_IFWI_FILE_NAME) create -f $(objcbfs)/ifwi.bin.tmp + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp delete -n OBBP + $(IFWITOOL) $(objcbfs)/ifwi.bin.tmp replace -n IBBP -f $(objcbfs)/bootblock.bin -d -e IBBL + $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_IFWI_FMAP_NAME) -f $(objcbfs)/ifwi.bin.tmp --fill-upward +endif + +endif

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Patch set updated for coreboot: soc/intel/common: Include common block directory [WIP]
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18378 -gerrit commit 2fff13e5dafe9bdca310134c35a9ab50d95b9086 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Feb 16 16:15:14 2017 +0530 soc/intel/common: Include common block directory [WIP] Change-Id: Id6561033fc77c64c61ab0341337523e14f55dd80 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/common/Makefile.inc | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index d6e1e75..58e4383 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -1,5 +1,8 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON),y) +subdirs-y += basecode/ +subdirs-y += block/* + bootblock-y += util.c verstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c @@ -33,6 +36,9 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_NHLT) += nhlt.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c +CPPFLAGS_common += -I$(src)/soc/intel/common/basecode/include/ +CPPFLAGS_common += -I$(src)/soc/intel/common/block/include/ + # Create and add the MRC cache to the cbfs image ifneq ($(CONFIG_CHROMEOS),y) $(obj)/mrc.cache: $(obj)/config.h

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Patch set updated for coreboot: nb/intel/i945: Fix sdram_on_die_termination
by HAOUAS Elyes 02 Mar '17

02 Mar '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18548 -gerrit commit 98313d8f615421f02c0a63129a7442733c27b328 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Mar 2 19:55:44 2017 +0100 nb/intel/i945: Fix sdram_on_die_termination Fix one DIMM per channel detection. "if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {" is true when both of dimm[0] and dimm[1] are not populated. Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 43 +++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7ccefb..32e4337 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2793,22 +2793,45 @@ static void sdram_on_die_termination(struct sys_info *sysinfo) u32 reg32; int cas; + int chan0has1dimms, chan1has1dimms; + + chan0has1dimm = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) || + (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); + + chan1has1dimm = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) || + (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); reg32 = MCHBAR32(ODTC); reg32 &= ~(3 << 16); reg32 |= (1 << 14) | (1 << 6) | (2 << 16); MCHBAR32(ODTC) = reg32; - if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) { - printk(BIOS_DEBUG, "one dimm per channel config..\n"); - - reg32 = MCHBAR32(C0ODT); - reg32 &= ~(7 << 28); - MCHBAR32(C0ODT) = reg32; - reg32 = MCHBAR32(C1ODT); - reg32 &= ~(7 << 28); - MCHBAR32(C1ODT) = reg32; + if (sysinfo->dual_channel) { + if (chan0has1dimm && chan1has1dimm) { + printk(BIOS_DEBUG, "one dimm per channel config..\n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } + } else { + if (chan0has1dimm) { + printk(BIOS_DEBUG, "one dimm per channel config..\n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } } cas = sysinfo->cas;

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Patch merged into coreboot/master: Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit 610d1c67b2298a9840681c2b4492b6d3fdf44a46 Author: Daniel Kulesz <daniel.ina1(a)googlemail.com> Date: Wed Feb 15 14:35:43 2017 +0100 Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h" This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6. The commit introduced a regression which is causing MC4 failures when 8 RDIMMs are populated in a configuration with a single CPU package. Using just 4 RDIMMs, the failure does not occur. After reverting the commit, I tested configurations with 1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an Opteron 6276. The MC4 failures did not occur anymore. Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65 Signed-off-by: Daniel Kulesz <daniel.ina1(a)googlemail.com> Reviewed-on: https://review.coreboot.org/18369 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson(a)raptorengineering.com> See https://review.coreboot.org/18369 for details. -gerrit

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Patch set updated for coreboot: drivers/intel/txe: Add HECI driver
by Andrey Petrov 02 Mar '17

02 Mar '17

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18547 -gerrit commit 5d8a81066ea435f165562d185054e83dd5e1f807 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 1 15:51:57 2017 -0800 drivers/intel/txe: Add HECI driver Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/txe/Kconfig | 5 + src/drivers/intel/txe/Makefile.inc | 2 + src/drivers/intel/txe/txe.c | 399 +++++++++++++++++++++++++++++++++++++ src/drivers/intel/txe/txe.h | 58 ++++++ 4 files changed, 464 insertions(+) diff --git a/src/drivers/intel/txe/Kconfig b/src/drivers/intel/txe/Kconfig new file mode 100644 index 0000000..be5ceb1 --- /dev/null +++ b/src/drivers/intel/txe/Kconfig @@ -0,0 +1,5 @@ +config TXE_COMMON + bool + default n + help + Unified TXE driver diff --git a/src/drivers/intel/txe/Makefile.inc b/src/drivers/intel/txe/Makefile.inc new file mode 100644 index 0000000..4d7bf43 --- /dev/null +++ b/src/drivers/intel/txe/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_TXE_COMMON) += txe.c +ramstage-$(CONFIG_TXE_COMMON) += txe.c diff --git a/src/drivers/intel/txe/txe.c b/src/drivers/intel/txe/txe.c new file mode 100644 index 0000000..9a58fe3 --- /dev/null +++ b/src/drivers/intel/txe/txe.c @@ -0,0 +1,399 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <timer.h> +#include "txe.h" + +/* default for early boot */ +#define HECI1_BASE_ADDRESS 0xfed1a000 + +#define HECI_DELAY_READY (15 * 1000) +#define HECI_DELAY 100 +#define HECI_SEND_TIMEOUT (5 * 1000) +#define HECI_READ_TIMEOUT (5 * 1000) + +#define SLOT_SIZE 4 + +struct txe_device { + uintptr_t sec_bar; +} g_txe CAR_GLOBAL; + +void heci_init(uintptr_t bar) { + + struct txe_device *txe = car_get_var_ptr(&g_txe); + device_t dev = HECI1_DEV; + u8 pcireg; + + if (!bar) + bar = HECI1_BASE_ADDRESS; + + /* assume initialized, nothing to do */ + if (txe->sec_bar) + return; + + /* Assign Resources to HECI1 */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI1 */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Open my own bar, with blackjack and hookers */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + + txe->sec_bar = bar; +} + +static uint32_t read_bar(uint32_t offset) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return read32((void *)(txe->sec_bar + offset)); +} + +static void write_bar(uint32_t offset, uint32_t val) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return write32((void *)(txe->sec_bar + offset), val); +} + +static uint32_t read_me_csr(void) +{ + return read_bar(MMIO_ME_CSR); +} + +static uint32_t read_host_csr(void) +{ + return read_bar(MMIO_HOST_CSR); +} + +static void write_host_csr(uint32_t data) +{ + write_bar(MMIO_HOST_CSR, data); +} + +static uint8_t get_cb_msg_count(uint32_t data) +{ + int8_t read_offset = (data >> 8); + int8_t write_offset = (data >> 16); + return write_offset - read_offset; +} + +static uint32_t me_filled_slots(void) +{ + return get_cb_msg_count(read_me_csr()); +} + +static uint8_t host_filled_slots(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + + return csr.fields.me_cir_buff - get_cb_msg_count(csr.data); +} + +static void clear_int(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_sts = 1; + write_host_csr(csr.data); +} + +static uint32_t read_slot(void) +{ + return read_bar(MMIO_ME_CB_RW); +} + +static void write_slot(uint32_t val) +{ + write_bar(MMIO_ME_CB_WW, val); +} + +static int wait_write_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (host_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); + return 0; + } + } + return 1; +} + +static int wait_read_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (me_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timed out reading answer!\n"); + return 0; + } + } + return 1; +} + +/* get number of full 4-byte slots */ +static uint32_t bytes_to_slots(uint32_t bytes) +{ + return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; +} + +static int me_ready(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + return !!csr.fields.host_ready; +} + +static int wait_heci_ready(void) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!me_ready()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + +static void host_gen_interrupt(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_gen = 1; + write_host_csr(csr.data); +} + +static int +send_one_message(union mei_header *hdr, void *buff) +{ + uint32_t pend_len, pend_slots, i, remainder, tmp; + uint32_t *p = (uint32_t*)buff; + + /* get space for the header */ + wait_write_slots(1); + + /* first, write header */ + write_slot(hdr->data); + + pend_len = hdr->fields.length; + pend_slots = bytes_to_slots(pend_len); + + wait_write_slots(pend_slots); + + /* write the body in whole slots */ + while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { + write_slot(*p++); + i += SLOT_SIZE; + } + + remainder = pend_len % SLOT_SIZE; + /* pad to 4 bytes not touching caller's buffer */ + if (remainder) { + memcpy(&tmp, p, remainder); + write_slot(tmp); + } + + host_gen_interrupt(); + + if (!me_ready()) + return 0; + + return hdr->fields.length; +} + +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client) +{ + union me_csr csr; + union mei_header hdr; + uint32_t sent = 0, remaining, slots, cb_size; + uint8_t *p = (uint8_t*) msg; + + if (!msg || !len) + return 0; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + csr.data = read_me_csr(); + /* reserve one slot for header */ + cb_size = (csr.fields.me_cir_buff - 1) * SLOT_SIZE - 1; + + remaining = len; + slots = len / SLOT_SIZE; + + /* + * Fragment the message into smaller messages not exceeding useful + * circullar buffer length. Mark last message complete. + */ + do { + hdr.fields.length = MIN(cb_size, remaining); + hdr.fields.client_address = client; + hdr.fields.host_address = host; + hdr.fields.is_complete = (remaining <= cb_size); + sent = send_one_message(&hdr, p); + p += sent; + remaining -= sent; + } while (remaining > 0 && sent != 0); + + return remaining==0; +} + +static uint32_t +recv_one_message(union mei_header *hdr, void *buff, uint32_t maxlen) +{ + uint32_t *p = (uint32_t *)buff; + uint32_t recv_slots, recv_len, reminder, reg, i; + + /* first get the header */ + if (!wait_read_slots(1)) + return 0; + + hdr->data = read_slot(); + recv_len = hdr->fields.length; + + if (!recv_len) + printk(BIOS_WARNING, "HECI: message is zero-sized\n"); + + recv_slots = bytes_to_slots(recv_len); + + if (recv_len > maxlen) { + printk(BIOS_ERR, "HECI: response is too big\n"); + return 0; + } + + /* wait for the rest of messages to arrive */ + wait_read_slots(recv_slots); + + /* fetch whole slots first */ + while (i < ALIGN_DOWN(recv_len, 4)) { + *p++ = read_slot(); + i += SLOT_SIZE; + } + + reminder = recv_len % SLOT_SIZE; + + if (reminder) { + reg = read_slot(); + memcpy(p, &reg, reminder); + } + + return recv_len; +} + +int heci_receive(void *buff, uint32_t *maxlen) +{ + union mei_header hdr; + uint32_t left, received; + uint8_t *p = (uint8_t *)buff; + + if (!buff || !maxlen || !*maxlen) + return 0; + + left = *maxlen; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + /* + * Receive multiple packets until we meet one marked complete or we run + * or we run out of space. + */ + do { + received = recv_one_message(&hdr, p, left); + left -= received; + p += received; + /* if read out all, ping to send more */ + if (!hdr.fields.is_complete && !me_filled_slots()) + host_gen_interrupt(); + } while (received && !hdr.fields.is_complete && left > 0); + + *maxlen = p - (uint8_t*) buff; + + /* if ME is not ready, something went wrong and we received junk */ + if (!me_ready()) + return 0; + + return hdr.fields.is_complete; +} + +#if ENV_RAMSTAGE + +static void update_sec_bar(struct device *dev) +{ + g_txe.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; +} + +static void txe_set_resources(struct device *dev) +{ + if (dev->path.pci.devfn == HECI1_DEVFN) + update_sec_bar(dev); + + pci_dev_set_resources(dev); +} + +static struct device_operations txe_ops = { + .set_resources = txe_set_resources, + .read_resources = pci_dev_read_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .enable_resources = pci_dev_enable_resources +}; + +static const struct pci_driver txe_driver __pci_driver = { + .ops = &txe_ops, + .vendor = PCI_VENDOR_ID_INTEL, + /* expectation is that soc/chipset code provides this */ + .device = PCI_DEVICE_ID_HECI1 +}; + +#endif diff --git a/src/drivers/intel/txe/txe.h b/src/drivers/intel/txe/txe.h new file mode 100644 index 0000000..b837dbf --- /dev/null +++ b/src/drivers/intel/txe/txe.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_INTEL_TXE_H_ +#define _DRIVERS_INTEL_TXE_H_ + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0c + +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +union mei_header { + u32 data; + struct { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; + } __attribute__ ((packed)) fields; +}; + +union me_csr { + u32 data; + struct { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_offset: 8; + u32 me_write_offset: 8; + u32 me_cir_buff: 8; + } __attribute__ ((packed)) fields; +}; + +/* set up device for use in early boot enviroument with temp bar */ +void heci_init(uintptr_t bar); +/* receive not less than maxlen into buff, returns 0 on failure */ +int heci_receive(void *buff, uint32_t *maxlen); +/* send message of size len, returns 0 on failure */ +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client); +#endif // _DRIVERS_INTEL_TXE_H_

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New patch to review for coreboot: nb/intel/i945: Fix sdram_on_die_termination
by HAOUAS Elyes 02 Mar '17

02 Mar '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18548 -gerrit commit 202ab12554d8b9d889059b9b9cbe24a3251901d1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Mar 2 19:55:44 2017 +0100 nb/intel/i945: Fix sdram_on_die_termination Fix one DIMM per channel detection. "if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {" is true when both of dimm[0] and dimm[1] are not populated. Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 42 +++++++++++++++++++++++++++--------- 1 file changed, 32 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7ccefb..8161562 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2799,16 +2799,38 @@ static void sdram_on_die_termination(struct sys_info *sysinfo) reg32 |= (1 << 14) | (1 << 6) | (2 << 16); MCHBAR32(ODTC) = reg32; - if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) { - printk(BIOS_DEBUG, "one dimm per channel config..\n"); - - reg32 = MCHBAR32(C0ODT); - reg32 &= ~(7 << 28); - MCHBAR32(C0ODT) = reg32; - reg32 = MCHBAR32(C1ODT); - reg32 &= ~(7 << 28); - MCHBAR32(C1ODT) = reg32; + if (sysinfo->dual_channel) { + if ((!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && + (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && + ((!(sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) && + (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED)) { + printk(BIOS_DEBUG, "one dimm per channel config..\n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } + } else { + if ((!(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) && + (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED || + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED)) { + printk(BIOS_DEBUG, "one dimm per channel config..\n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } } cas = sysinfo->cas;

1 0

New patch to review for coreboot: drivers/intel/txe: Add HECI driver
by Andrey Petrov 02 Mar '17

02 Mar '17

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18547 -gerrit commit a9ef1836692c8c15e237d0b4bdb8ad1b8d5eef2c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 1 15:51:57 2017 -0800 drivers/intel/txe: Add HECI driver Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/txe/Kconfig | 5 + src/drivers/intel/txe/Makefile.inc | 2 + src/drivers/intel/txe/txe.c | 399 +++++++++++++++++++++++++++++++++++++ src/drivers/intel/txe/txe.h | 58 ++++++ 4 files changed, 464 insertions(+) diff --git a/src/drivers/intel/txe/Kconfig b/src/drivers/intel/txe/Kconfig new file mode 100644 index 0000000..be5ceb1 --- /dev/null +++ b/src/drivers/intel/txe/Kconfig @@ -0,0 +1,5 @@ +config TXE_COMMON + bool + default n + help + Unified TXE driver diff --git a/src/drivers/intel/txe/Makefile.inc b/src/drivers/intel/txe/Makefile.inc new file mode 100644 index 0000000..4d7bf43 --- /dev/null +++ b/src/drivers/intel/txe/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_TXE_COMMON) += txe.c +ramstage-$(CONFIG_TXE_COMMON) += txe.c diff --git a/src/drivers/intel/txe/txe.c b/src/drivers/intel/txe/txe.c new file mode 100644 index 0000000..a6ab7f8 --- /dev/null +++ b/src/drivers/intel/txe/txe.c @@ -0,0 +1,399 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <timer.h> +#include "txe.h" + +/* default for early boot */ +#define HECI1_BASE_ADDRESS 0xfed1a000 + +#define HECI_DELAY_READY (15 * 1000) +#define HECI_DELAY 100 +#define HECI_SEND_TIMEOUT (5 * 1000) +#define HECI_READ_TIMEOUT (5 * 1000) + +#define SLOT_SIZE 4 + +struct txe_device { + uintptr_t sec_bar; +} g_txe CAR_GLOBAL; + +void heci_init(uintptr_t bar) { + + struct txe_device *txe = car_get_var_ptr(&g_txe); + device_t dev = HECI1_DEV; + u8 pcireg; + + if (!bar) + bar = HECI1_BASE_ADDRESS; + + /* assume initialized, nothing to do */ + if (txe->sec_bar) + return; + + /* Assign Resources to HECI1 */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI1 */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Open my own bar, with blackjack and hookers */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + + txe->sec_bar = bar; +} + +static uint32_t read_bar(uint32_t offset) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return read32((void *)(txe->sec_bar + offset)); +} + +static void write_bar(uint32_t offset, uint32_t val) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return write32((void *)(txe->sec_bar + offset), val); +} + +static uint32_t read_me_csr(void) +{ + return read_bar(MMIO_ME_CSR); +} + +static uint32_t read_host_csr(void) +{ + return read_bar(MMIO_HOST_CSR); +} + +static void write_host_csr(uint32_t data) +{ + write_bar(MMIO_HOST_CSR, data); +} + +static uint8_t get_cb_msg_count(uint32_t data) +{ + int8_t read_offset = (data >> 8); + int8_t write_offset = (data >> 16); + return write_offset - read_offset; +} + +static uint32_t me_filled_slots(void) +{ + return get_cb_msg_count(read_me_csr()); +} + +static uint8_t host_filled_slots(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + + return csr.fields.me_cir_buff - get_cb_msg_count(csr.data); +} + +static void clear_int(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_sts = 1; + write_host_csr(csr.data); +} + +static uint32_t read_slot(void) +{ + return read_bar(MMIO_ME_CB_RW); +} + +static void write_slot(uint32_t val) +{ + write_bar(MMIO_ME_CB_WW, val); +} + +static int wait_write_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (host_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); + return 0; + } + } + return 1; +} + +static int wait_read_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (me_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timed out reading answer!\n"); + return 0; + } + } + return 1; +} + +/* get number of full 4-byte slots */ +static uint32_t bytes_to_slots(uint32_t bytes) +{ + return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; +} + +static int me_ready(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + return !!csr.fields.host_ready; +} + +static int wait_heci_ready(void) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!me_ready()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + +static void host_gen_interrupt(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_gen = 1; + write_host_csr(csr.data); +} + +static int +send_one_message(union mei_header *hdr, void *buff) +{ + uint32_t pend_len, pend_slots, i, remainder, tmp; + uint32_t *p = (uint32_t*)buff; + + /* get space for the header */ + wait_write_slots(1); + + /* first, write header */ + write_slot(hdr->data); + + pend_len = hdr->fields.length; + pend_slots = bytes_to_slots(pend_len); + + wait_write_slots(pend_slots); + + /* write the body in whole slots */ + while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { + write_slot(*p++); + i += SLOT_SIZE; + } + + remainder = pend_len % SLOT_SIZE; + /* pad to 4 bytes not touching caller's buffer */ + if (remainder) { + memcpy(&tmp, p, remainder); + write_slot(tmp); + } + + host_gen_interrupt(); + + if (!me_ready()) + return 0; + + return hdr->fields.length; +} + +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client) +{ + union me_csr csr; + union mei_header hdr; + uint32_t sent = 0, remaining, slots, cb_size; + uint8_t *p = (uint8_t*) msg; + + if (!msg || !len) + return 0; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + csr.data = read_me_csr(); + /* reserve one slot for header */ + cb_size = (csr.fields.me_cir_buff - 1) * SLOT_SIZE - 1; + + remaining = len; + slots = len / SLOT_SIZE; + + /* + * Fragment the message into smaller messages not exceeding useful + * circullar buffer length. Mark last message complete. + */ + do { + hdr.fields.length = MIN(cb_size, remaining); + hdr.fields.client_address = client; + hdr.fields.host_address = host; + hdr.fields.is_complete = (remaining <= cb_size); + sent = send_one_message(&hdr, p); + p += sent; + remaining -= sent; + } while (remaining > 0 && sent != 0); + + return remaining==0; +} + +static uint32_t +recv_one_message(union mei_header *hdr, void *buff, uint32_t maxlen) +{ + uint32_t *p = (uint32_t *)buff; + uint32_t recv_slots, recv_len, reminder, reg, i; + + /* first get the header */ + if (!wait_read_slots(1)) + return 0; + + hdr->data = read_slot(); + recv_len = hdr->fields.length; + + if (!recv_len) + printk(BIOS_WARNING, "HECI: message is zero-sized\n"); + + recv_slots = bytes_to_slots(recv_len); + + if (recv_len > maxlen) { + printk(BIOS_ERR, "HECI: response is too big\n"); + return 0; + } + + /* wait for the rest of messages to arrive */ + wait_read_slots(recv_slots); + + /* fetch whole slots first */ + while (i < ALIGN_DOWN(recv_len, 4)) { + *p++ = read_slot(); + i += SLOT_SIZE; + } + + reminder = recv_len % SLOT_SIZE; + + if (reminder) { + reg = read_slot(); + memcpy(p, &reg, reminder); + } + + return recv_len; +} + +int heci_receive(void *buff, uint32_t *maxlen) +{ + union mei_header hdr; + uint32_t left, received; + uint8_t *p = (uint8_t *)buff; + + if (!buff || !maxlen || !*maxlen) + return 0; + + left = *maxlen; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + /* + * Receive multiple packets until we meet one marked complete or we run + * or we run out of space. + */ + do { + received = recv_one_message(&hdr, p, left); + left -= received; + p += received; + /* if read out all, ping to send more */ + if (!hdr.fields.is_complete && !me_filled_slots()) + host_gen_interrupt(); + } while (received && !hdr.fields.is_complete && left > 0); + + *maxlen = p - (uint8_t*) buff; + + /* if ME is not ready, something went wrong and we received junk */ + if (!me_ready()) + return 0; + + return hdr.fields.is_complete; +} + +#if ENV_RAMSTAGE + +static void update_sec_bar(struct device *dev) +{ + g_txe.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; +} + +static void txe_set_resources(struct device *dev) +{ + if (dev->path.pci.devfn == HECI1_DEVFN) + update_sec_bar(dev); + + pci_dev_set_resources(dev); +} + +static struct device_operations uart_ops = { + .set_resources = txe_set_resources, + .read_resources = pci_dev_read_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .enable_resources = pci_dev_enable_resources +}; + +static const struct pci_driver uart_driver __pci_driver = { + .ops = &uart_ops, + .vendor = PCI_VENDOR_ID_INTEL, + /* expectation is that soc/chipset code provides this */ + .device = PCI_DEVICE_ID_HECI1 +}; + +#endif diff --git a/src/drivers/intel/txe/txe.h b/src/drivers/intel/txe/txe.h new file mode 100644 index 0000000..b837dbf --- /dev/null +++ b/src/drivers/intel/txe/txe.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_INTEL_TXE_H_ +#define _DRIVERS_INTEL_TXE_H_ + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0c + +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +union mei_header { + u32 data; + struct { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; + } __attribute__ ((packed)) fields; +}; + +union me_csr { + u32 data; + struct { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_offset: 8; + u32 me_write_offset: 8; + u32 me_cir_buff: 8; + } __attribute__ ((packed)) fields; +}; + +/* set up device for use in early boot enviroument with temp bar */ +void heci_init(uintptr_t bar); +/* receive not less than maxlen into buff, returns 0 on failure */ +int heci_receive(void *buff, uint32_t *maxlen); +/* send message of size len, returns 0 on failure */ +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client); +#endif // _DRIVERS_INTEL_TXE_H_

1 0

New patch to review for coreboot: soc/intel/apollolake: Prepare to use common HECI driver
by Andrey Petrov 02 Mar '17

02 Mar '17

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18546 -gerrit commit afc436fb33ed6944e2036915714755bca7fb62a0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Mar 2 08:50:57 2017 -0800 soc/intel/apollolake: Prepare to use common HECI driver Change-Id: Ib284493d886b223e8c85607de5fdb56b698fe5fa Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/cse.c | 2 +- src/soc/intel/apollolake/heci.c | 2 +- src/soc/intel/apollolake/include/soc/pci_devs.h | 4 ++-- src/soc/intel/apollolake/include/soc/pci_ids.h | 2 ++ 4 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/apollolake/cse.c b/src/soc/intel/apollolake/cse.c index b8ab1f0..ba3898da 100644 --- a/src/soc/intel/apollolake/cse.c +++ b/src/soc/intel/apollolake/cse.c @@ -28,7 +28,7 @@ static uint32_t dump_status(int index, int reg_addr) { - uint32_t reg = pci_read_config32(CSE_DEV, reg_addr); + uint32_t reg = pci_read_config32(HECI1_DEV, reg_addr); printk(BIOS_DEBUG, "CSE FWSTS%d: 0x%08x\n", index, reg); diff --git a/src/soc/intel/apollolake/heci.c b/src/soc/intel/apollolake/heci.c index 4685895..55da98c 100644 --- a/src/soc/intel/apollolake/heci.c +++ b/src/soc/intel/apollolake/heci.c @@ -22,7 +22,7 @@ uint32_t heci_fw_sts(void) { - return pci_read_config32(CSE_DEV, REG_SEC_FW_STS0); + return pci_read_config32(HECI1_DEV, REG_SEC_FW_STS0); } bool heci_cse_normal(void) diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index d058f8b..572fd38 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -52,8 +52,8 @@ #define HDA_DEV _PCI_DEV(0xe, 0) #define HDA_DEVFN _PCI_DEVFN(0xe, 0) -#define CSE_DEV _PCI_DEV(0xf, 0) -#define CSE_DEVFN _PCI_DEVFN(0xf, 0) +#define HECI1_DEV _PCI_DEV(0xf, 0) +#define HECI1_DEVFN _PCI_DEVFN(0xf, 0) #define ISH_DEV _PCI_DEV(0x11, 0) #define ISH_DEVFN _PCI_DEVFN(0x11, 0) diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 130263b..2dce2ef 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -26,6 +26,8 @@ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_CSE0 0x5a9a /* 00:0f.0 */ +#define PCI_DEVICE_ID_HECI1 PCI_DEVICE_ID_APOLLOLAKE_CSE0 #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */

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Patch merged into coreboot/master: acpi: Update the ACPI ID for coreboot
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit 59eddac6ad1f948af69ee25f3dc26adb56a376d0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Feb 28 16:58:06 2017 -0800 acpi: Update the ACPI ID for coreboot The newly assigned ACPI ID for coreboot is 'BOOT' http://www.uefi.org/acpi_id_list Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific ACPI objects instead of the placeholder range of "GOOGCBxx". Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/18521 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/18521 for details. -gerrit

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Patch set updated for coreboot: nb/i945/gma.c: Refactor panel setup
by Arthur Heymans 02 Mar '17

02 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18141 -gerrit commit 76ff881c5ac03f52fd345ad989aecd0a68ebb3dc Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Jan 14 22:31:54 2017 +0100 nb/i945/gma.c: Refactor panel setup This reuses some of gm45 code to set up the panel. Panel start and stop delays and pwm frequency can now be set in devicetree. Linux does not make the difference between 945gm and gm45 for panel delays, so it is safe to assume the semantics of those registers are the same. The core display clock is computed according to "Mobile Intel® 945 Express Chipset Family" Datasheet. This selects Legacy backlight mode since most targets have some smm code that rely on this. This sets the same backlight frequency as vendor bios on Thinkpad X60 and T60. A default of 180Hz is selected for the PWM frequency if it is not defined in the devicetree, this might be annoying for displays that are LED backlit, but is a safe value for CCFL backlit displays. Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/drivers/intel/gma/i915_reg.h | 2 +- src/mainboard/apple/macbook21/devicetree.cb | 7 ++- src/mainboard/lenovo/t60/devicetree.cb | 7 ++- src/mainboard/lenovo/x60/devicetree.cb | 7 ++- src/northbridge/intel/i945/chip.h | 11 ++++- src/northbridge/intel/i945/gma.c | 69 ++++++++++++++++++++++++++--- 6 files changed, 93 insertions(+), 10 deletions(-) diff --git a/src/drivers/intel/gma/i915_reg.h b/src/drivers/intel/gma/i915_reg.h index 2ee5748..dee6865 100644 --- a/src/drivers/intel/gma/i915_reg.h +++ b/src/drivers/intel/gma/i915_reg.h @@ -62,7 +62,7 @@ #define GCFGC 0xf0 /* 915+ only */ #define GC_LOW_FREQUENCY_ENABLE (1 << 7) #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) -#define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) +#define GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4) #define GC_DISPLAY_CLOCK_MASK (7 << 4) #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index f37e768..b6e61eb 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index f66455b..6ad054c 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1280128" + register "pwm_freq" = "275" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index 0ac9273..28b63d3 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -22,7 +22,12 @@ chip northbridge/intel/i945 register "gpu_hotplug" = "0x00000220" register "gpu_lvds_use_spread_spectrum_clock" = "1" - register "gpu_backlight" = "0x1290128" + register "pwm_freq" = "180" + register "gpu_panel_power_up_delay" = "250" + register "gpu_panel_power_backlight_on_delay" = "2380" + register "gpu_panel_power_down_delay" = "250" + register "gpu_panel_power_backlight_off_delay" = "2380" + register "gpu_panel_power_cycle_delay" = "2" device cpu_cluster 0 on chip cpu/intel/socket_mFCPGA478 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 8eaa5b4..3925a73 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -4,8 +4,17 @@ #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { + /* In units of 100us timer */ + /* Timings as defined in VESA Notebook Panel Standard */ + u16 gpu_panel_power_up_delay; /* T1+T2 time sequence */ + u16 gpu_panel_power_down_delay; /* T3 time sequence */ + u16 gpu_panel_power_backlight_on_delay; /* T5 time sequence */ + u16 gpu_panel_power_backlight_off_delay; /* Tx time sequence */ + /* In units of 0.1s */ + u8 gpu_panel_power_cycle_delay; + u32 gpu_hotplug; - u32 gpu_backlight; + u32 pwm_freq; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; int pci_mmio_size; diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index eac8717..950feaf 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -47,6 +47,8 @@ #define BASE_FREQUENCY 100000 +#define DEFAULT_BLC_PWM 180 + static int gtt_setup(u8 *mmiobase) { unsigned long PGETBL_save; @@ -134,8 +136,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(mmiobase + RENDER_RING_BASE + i, 0); for (i = 0; i < 0x20; i += 4) write32(mmiobase + FENCE_REG_965_0 + i, 0); - write32(mmiobase + PP_ON_DELAYS, 0); - write32(mmiobase + PP_OFF_DELAYS, 0); /* Disable VGA. */ write32(mmiobase + VGACNTRL, VGA_DISP_DISABLE); @@ -292,9 +292,6 @@ static int intel_gma_init_lvds(struct northbridge_intel_i945_config *conf, write32(mmiobase + DSPSIZE(0), (hactive - 1) | ((vactive - 1) << 16)); write32(mmiobase + DSPPOS(0), 0); - /* Backlight init. */ - write32(mmiobase + BLC_PWM_CTL, conf->gpu_backlight); - edid.bytes_per_line = (edid.bytes_per_line + 63) & ~63; write32(mmiobase + DSPADDR(0), 0); write32(mmiobase + DSPSURF(0), 0); @@ -571,6 +568,63 @@ static int probe_edid(u8 *mmiobase, u8 slave) return 1; } +static u32 get_cdclk(struct device *const dev) +{ + u16 gcfgc = pci_read_config16(dev, GCFGC); + + if (gcfgc & GC_LOW_FREQUENCY_ENABLE) { + return 133333333; + } else { + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { + case GC_DISPLAY_CLOCK_333_320_MHZ: + return 320000000; + default: + case GC_DISPLAY_CLOCK_190_200_MHZ: + return 200000000; + } + } +} + +static u32 freq_to_blc_pwm_ctl(struct device *const dev, + u16 pwm_freq) +{ + u32 blc_mod; + + /* Set duty cycle to 100% due to use of legacy backlight control */ + blc_mod = get_cdclk(dev) / (32 * pwm_freq); + return BLM_LEGACY_MODE | ((blc_mod / 2) << 17) | ((blc_mod / 2) << 1); +} + + +static void panel_setup(u8 *mmiobase, struct device *const dev) +{ + const struct northbridge_intel_i945_config *const conf = dev->chip_info; + + u32 reg32; + + /* Set up Panel Power On Delays */ + reg32 = (conf->gpu_panel_power_up_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_on_delay & 0x1fff); + write32(mmiobase + PP_ON_DELAYS, reg32); + + /* Set up Panel Power Off Delays */ + reg32 = (conf->gpu_panel_power_down_delay & 0x1fff) << 16; + reg32 |= (conf->gpu_panel_power_backlight_off_delay & 0x1fff); + write32(mmiobase + PP_OFF_DELAYS, reg32); + + /* Set up Panel Power Cycle Delay */ + reg32 = (get_cdclk(dev) / 20000 - 1) << PP_REFERENCE_DIVIDER_SHIFT; + reg32 |= conf->gpu_panel_power_cycle_delay & 0x1f; + write32(mmiobase + PP_DIVISOR, reg32); + + /* Backlight init. */ + if (conf->pwm_freq) + write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + conf->pwm_freq)); + else + write32(mmiobase + BLC_PWM_CTL, freq_to_blc_pwm_ctl(dev, + DEFAULT_BLC_PWM)); +} static void gma_func0_init(struct device *dev) { @@ -605,6 +659,10 @@ static void gma_func0_init(struct device *dev) ); int err; + + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + panel_setup(mmiobase, dev); + /* probe if VGA is connected and always run */ /* VGA init if no LVDS is connected */ if (!probe_edid(mmiobase, 3) || probe_edid(mmiobase, 2)) @@ -615,6 +673,7 @@ static void gma_func0_init(struct device *dev) err = intel_gma_init_lvds(conf, pci_read_config32(dev, 0x5c) & ~0xf, iobase, mmiobase, graphics_base); + if (err == 0) gfx_set_init_done(1); /* Linux relies on VBT for panel info. */

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coreboot-gerrit March 2017