coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: autoport: add "-d" option to ectool to dump registers
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit bc5112029b633fffef2a0abca4a438bd6264f467 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri Feb 24 15:19:25 2017 +0800 autoport: add "-d" option to ectool to dump registers Change-Id: I7de37a026a0899c2d07ea17c9377c8d2283450ab Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/18481 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> See https://review.coreboot.org/18481 for details. -gerrit

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Patch set updated for coreboot: nb/intel/i945: Fix sdram_on_die_termination
by HAOUAS Elyes 02 Mar '17

02 Mar '17

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18548 -gerrit commit a1a1467cceef4cf74d9a95f2003fa2f28f8d7f8f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Mar 2 19:55:44 2017 +0100 nb/intel/i945: Fix sdram_on_die_termination Fix one DIMM per channel detection. "if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) {" is true when both of dimm[0] and dimm[1] are not populated. Change-Id: I7aec35f45250da554ddc5a68f5add157c313399c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.c | 43 +++++++++++++++++++++++++++--------- 1 file changed, 33 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index a7ccefb..bff3558 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2793,22 +2793,45 @@ static void sdram_on_die_termination(struct sys_info *sysinfo) u32 reg32; int cas; + int chan0has1dimm, chan1has1dimm; + + chan0has1dimm = (sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] == SYSINFO_DIMM_NOT_POPULATED) || + (sysinfo->dimm[0] == SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED); + + chan1has1dimm = (sysinfo->dimm[2] != SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[3] == SYSINFO_DIMM_NOT_POPULATED) || + (sysinfo->dimm[2] == SYSINFO_DIMM_NOT_POPULATED && + sysinfo->dimm[3] != SYSINFO_DIMM_NOT_POPULATED); reg32 = MCHBAR32(ODTC); reg32 &= ~(3 << 16); reg32 |= (1 << 14) | (1 << 6) | (2 << 16); MCHBAR32(ODTC) = reg32; - if ( !(sysinfo->dimm[0] != SYSINFO_DIMM_NOT_POPULATED && - sysinfo->dimm[1] != SYSINFO_DIMM_NOT_POPULATED) ) { - printk(BIOS_DEBUG, "one dimm per channel config..\n"); - - reg32 = MCHBAR32(C0ODT); - reg32 &= ~(7 << 28); - MCHBAR32(C0ODT) = reg32; - reg32 = MCHBAR32(C1ODT); - reg32 &= ~(7 << 28); - MCHBAR32(C1ODT) = reg32; + if (sysinfo->dual_channel) { + if (chan0has1dimm && chan1has1dimm) { + printk(BIOS_DEBUG, "one dimm per channel config..\n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } + } else { + if (chan0has1dimm) { + printk(BIOS_DEBUG, "one dimm per channel config..\n"); + + reg32 = MCHBAR32(C0ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C0ODT) = reg32; + reg32 = MCHBAR32(C1ODT); + reg32 &= ~(7 << 28); + MCHBAR32(C1ODT) = reg32; + } } cas = sysinfo->cas;

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Patch set updated for coreboot: soc/intel/common/block: Add cache as ram common code
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18381 -gerrit commit 220bad14c4a738ae23d58b51cb2c771127b136f0 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 16:39:53 2017 +0530 soc/intel/common/block: Add cache as ram common code Create sample model for common cache as ram programming. TEST=Booted till post code 0x2a and ensure to have CAR done by reading MSR. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/common/block/cpu/Kconfig | 47 +++ src/soc/intel/common/block/cpu/Makefile.inc | 2 + src/soc/intel/common/block/cpu/car/cache_as_ram.S | 177 ++++++++++++ src/soc/intel/common/block/cpu/car/car_big_core.S | 161 +++++++++++ .../intel/common/block/cpu/car/car_small_core.S | 103 +++++++ src/soc/intel/glk/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/cache_as_ram.S | 320 --------------------- 9 files changed, 492 insertions(+), 321 deletions(-) diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig new file mode 100644 index 0000000..a3987d2 --- /dev/null +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -0,0 +1,47 @@ +config SOC_INTEL_COMMON_CAR + bool + depends on !FSP_CAR + default CAR_CQOS if (!SOC_INTEL_CAR_BIG_CORE) + default CAR_NEM_ENHANCED if (!SOC_INTEL_CAR_SMALL_CORE) + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool + default y + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + +config CAR_CQOS + bool + default y + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainder for actual caching. + +config CAR_NEM_ENHANCED + bool + default y + help + Current limitation NEM mode is that code and data size is derived + from the need not to spill out any modified line: as in NEM mode + there is no memory behind, the modified data will be lost and NEM + results will be inconsistent, hence NEM ENHANCED mode ensure to + have, some “magic” way to guarantee that modified data is always + kept in cache while clean data is replaced. + +config SOC_INTEL_CAR_SMALL_CORE + bool + default n + help + Intel Processor CAR support on small core + +config SOC_INTEL_CAR_BIG_CORE + bool + default n + help + Intel Processor CAR support on big core + diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc new file mode 100644 index 0000000..1997641 --- /dev/null +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_CAR) += car/cache_as_ram.S + diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S new file mode 100644 index 0000000..6b5a089 --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> +#include <rules.h> +#include <intelblocks/msr.h> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + + post_code(0x20) + + /* + * Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. + */ +check_for_clean_reset: + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jz no_reset + /* perform soft reset */ + movw $0xcf9, %dx + movb $0x06, %al + outb %al, %dx + +no_reset: + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Configure default memory type to uncacheable (UC) */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + /* Clear enable bits and set default type to UC. */ + and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ + MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + * + * Examples: + * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov $MTRR_PHYS_MASK(0), %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + or $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + +#if IS_ENABLED(CONFIG_SOC_INTEL_CAR_SMALL_CORE) + #include "car_small_core.S" +#elif IS_ENABLED(CONFIG_SOC_INTEL_CAR_BIG_CORE) + #include "car_big_core.S" +#endif + +car_init_done: + + post_code(0x29) + + /* Setup bootblock stack */ + mov $_car_stack_end, %esp + + /*push TSC value to stack*/ + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ + +before_carstage: + post_code(0x2A) + + call bootblock_c_entry + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/common/block/cpu/car/car_big_core.S b/src/soc/intel/common/block/cpu/car/car_big_core.S new file mode 100644 index 0000000..5dabbb9 --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car_big_core.S @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr + post_code(0x26) + + /* Create n-way set associativity of cache */ + xorl %edi, %edi +find_llc_subleaf: + movl %edi, %ecx + movl $0x04, %eax + cpuid + inc %edi + and $0xe0, %al /* EAX[7:5] = Cache Level */ + cmp $0x60, %al /* Check to see if it is LLC */ + jnz find_llc_subleaf + + /* + * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * for 4/8/16 way of LLC + */ + shr $22, %ebx + inc %ebx + /* Calculate n-way associativity of LLC */ + mov %bl, %cl + + /* + * Maximizing RO cacheability while locking in the CAR to a + * single way since that particular way won't be victim candidate + * for evictions. + * This has been done after programing LLC_WAY_MASK_1 MSR + * with desired LLC way as mentioned below. + * + * Hence create Code and Data Size as per request + * Code Size (RO) : Up to 16M + * Data Size (RW) : Up to 256K + */ + movl $0x01, %eax + /* + * LLC Ways -> LLC_WAY_MASK_1: + * 4: 0x000E + * 8: 0x00FE + * 12: 0x0FFE + * 16: 0xFFFE + * + * These MSRs contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + shl %cl, %eax + subl $0x02, %eax + movl $MSR_IA32_L3_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 + * + * For SKL SOC, data size remains 256K consistently. + * Hence, creating 1-way associative cache for Data + */ + mov $MSR_IA32_L3_MASK_2, %ecx + mov $0x01, %eax + xorl %edx, %edx + wrmsr + /* + * Set MSR_IA32_PQR_ASSOC = 0x02 + * + * Possible values: + * 0: Default value, no way mask should be applied + * 1: Apply way mask 1 to LLC + * 2: Apply way mask 2 to LLC + * 3: Shouldn't be use in NEM Mode + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x02, %eax + xorl %edx, %edx + wrmsr + + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + /* + * Set MSR_IA32_PQR_ASSOC = 0x01 + * At this stage we apply LLC_WAY_MASK_1 to the cache. + * i.e. way 0 is protected from eviction. + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x01, %eax + xorl %edx, %edx + wrmsr + + /* + * Enable No-Eviction Mode Run State by setting + * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + */ + + movl $MSR_EVICT_CTL, %ecx + rdmsr + orl $0x02, %eax + wrmsr + + post_code(0x27) + /* + * Configure the BIOS code region as write-protected (WP) cacheable + * memory type using a single variable range MTRR. + * + * Ensure region to cache meets MTRR requirements for + * size and alignment. + */ + movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */ + movl $CONFIG_ROM_SIZE, %eax /* Code region size */ + cmpl $0, %edi + jz .halt_forever + cmpl $0, %eax + jz .halt_forever + + post_code(0x28) + /* + * Program base register + */ + xorl %edx, %edx /* clear upper dword */ + movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */ + movl %edi, %eax + orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */ + wrmsr + + movl $CONFIG_ROM_SIZE, %eax + + /* + * Compute MTRR mask value: Mask = NOT (Size - 1) + */ + dec %eax /* eax - size to cache less one byte */ + not %eax /* eax contains low 32 bits of mask */ + or $MTRR_PHYS_MASK_VALID, %eax + /* + * Program mask register + */ + movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */ + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + diff --git a/src/soc/intel/common/block/cpu/car/car_small_core.S b/src/soc/intel/common/block/cpu/car/car_small_core.S new file mode 100644 index 0000000..2b26f8f --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car_small_core.S @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#if IS_ENABLED(CONFIG_CAR_NEM) + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr +#else + /* + * Disable both L1 and L2 prefetcher. For yet-to-understood reason, + * prefetchers slow down filling cache with rep stos in CQOS mode. + */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) +#if (CONFIG_DCACHE_RAM_SIZE == L2_CACHE_SIZE) +/* + * If CAR size is set to full L2 size, mask is calculated as all-zeros. + * This is not supported by the CPU/uCode. + */ +#error "CQOS CAR may not use whole L2 cache area" +#endif + /* Calculate how many bits to be used for CAR */ + xor %edx, %edx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ + mov $CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ + div %ecx /* result is in eax */ + mov %eax, %ecx /* save to ecx */ + mov $1, %ebx + shl %cl, %ebx + sub $1, %ebx /* resulting mask is is in ebx */ + + /* Set this mask for initial cache fill */ + mov $MSR_L2_QOS_MASK(0), %ecx + rdmsr + mov %bl, %al + wrmsr + + /* Set CLOS selector to 0 */ + mov $IA32_PQR_ASSOC, %ecx + rdmsr + and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ + wrmsr + + /* We will need to block CAR region from evicts */ + mov $MSR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov %bl, %al + xor $~0, %al /* invert 8 bits */ + wrmsr +#endif + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + mov $CONFIG_DCACHE_RAM_BASE, %edi + mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xor %eax, %eax + rep stos %eax, %es:(%edi) + + post_code(0x27) + +#if IS_ENABLED(CONFIG_CAR_NEM) + /* Disable cache eviction (run stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x2, %eax + wrmsr +#else + /* Cache is populated. Use mask 1 that will block evicts */ + mov $IA32_PQR_ASSOC, %ecx + rdmsr + and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ + or $1, %edx /* select mask 1 */ + wrmsr + + /* Enable prefetchers */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr +#endif + + post_code(0x28) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index c08d705..4ce5ddd 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select RTC select SMM_TSEG + select SOC_INTEL_CAR_SMALL_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 67d2213..132fa6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC + select SOC_INTEL_CAR_BIG_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 2a6b152..181e17b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/cpu.c bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S deleted file mode 100644 index 3f8f0f0..0000000 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <cpu/x86/cache.h> -#include <cpu/x86/cr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/post_code.h> -#include <rules.h> - -#define IA32_PQR_ASSOC 0x0c8f -#define IA32_L3_MASK_1 0x0c91 -#define IA32_L3_MASK_2 0x0c92 -#define CACHE_INIT_VALUE 0 -#define MSR_EVICT_CTL 0x2e0 - -.global bootblock_pre_c_entry -bootblock_pre_c_entry: - - post_code(0x20) - - /* - * Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. - */ -check_for_clean_reset: - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - cmp $0, %eax - jz no_reset - /* perform soft reset */ - movw $0xcf9, %dx - movb $0x06, %al - outb %al, %dx - -no_reset: - post_code(0x21) - - /* Clear/disable fixed MTRRs */ - mov $fixed_mtrr_list_size, %ebx - xor %eax, %eax - xor %edx, %edx -clear_fixed_mtrr: - add $-2, %ebx - movzwl fixed_mtrr_list(%ebx), %ecx - wrmsr - jnz clear_fixed_mtrr - - post_code(0x22) - - /* Figure put how many MTRRs we have, and clear them out */ - mov $MTRR_CAP_MSR, %ecx - rdmsr - movzb %al, %ebx /* Number of variable MTRRs */ - mov $MTRR_PHYS_BASE(0), %ecx - xor %eax, %eax - xor %edx, %edx - -clear_var_mtrr: - wrmsr - inc %ecx - wrmsr - inc %ecx - dec %ebx - jnz clear_var_mtrr - - post_code(0x23) - - /* Configure default memory type to uncacheable (UC) */ - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - /* Clear enable bits and set default type to UC. */ - and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ - MTRR_DEF_TYPE_FIX_EN), %eax - wrmsr - - /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB - * based on the physical address size supported for this processor - * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] - * - * Examples: - * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing - * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing - */ - - movl $0x80000008, %eax /* Address sizes leaf */ - cpuid - sub $32, %al - movzx %al, %eax - xorl %esi, %esi - bts %eax, %esi - dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - - post_code(0x24) - - /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx - mov $CONFIG_DCACHE_RAM_BASE, %eax - or $MTRR_TYPE_WRBACK, %eax - xor %edx,%edx - wrmsr - - /* Configure the MTRR mask for the size region */ - mov $MTRR_PHYS_MASK(0), %ecx - mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ - dec %eax - not %eax - or $MTRR_PHYS_MASK_VALID, %eax - wrmsr - - post_code(0x25) - - /* Enable variable MTRRs */ - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - or $MTRR_DEF_TYPE_EN, %eax - wrmsr - - /* Enable caching */ - mov %cr0, %eax - and $~(CR0_CD | CR0_NW), %eax - invd - mov %eax, %cr0 - - /* Disable cache eviction (setup stage) */ - mov $MSR_EVICT_CTL, %ecx - rdmsr - or $0x1, %eax - wrmsr - post_code(0x26) - - /* Create n-way set associativity of cache */ - xorl %edi, %edi -find_llc_subleaf: - movl %edi, %ecx - movl $0x04, %eax - cpuid - inc %edi - and $0xe0, %al /* EAX[7:5] = Cache Level */ - cmp $0x60, %al /* Check to see if it is LLC */ - jnz find_llc_subleaf - - /* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE - * for 4/8/16 way of LLC - */ - shr $22, %ebx - inc %ebx - /* Calculate n-way associativity of LLC */ - mov %bl, %cl - - /* - * Maximizing RO cacheability while locking in the CAR to a - * single way since that particular way won't be victim candidate - * for evictions. - * This has been done after programing LLC_WAY_MASK_1 MSR - * with desired LLC way as mentioned below. - * - * Hence create Code and Data Size as per request - * Code Size (RO) : Up to 16M - * Data Size (RW) : Up to 256K - */ - movl $0x01, %eax - /* - * LLC Ways -> LLC_WAY_MASK_1: - * 4: 0x000E - * 8: 0x00FE - * 12: 0x0FFE - * 16: 0xFFFE - * - * These MSRs contain one bit per each way of LLC - * - If this bit is '0' - the way is protected from eviction - * - If this bit is '1' - the way is not protected from eviction - */ - shl %cl, %eax - subl $0x02, %eax - movl $IA32_L3_MASK_1, %ecx - xorl %edx, %edx - wrmsr - /* - * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 - * - * For SKL SOC, data size remains 256K consistently. - * Hence, creating 1-way associative cache for Data - */ - mov $IA32_L3_MASK_2, %ecx - mov $0x01, %eax - xorl %edx, %edx - wrmsr - /* - * Set IA32_PQR_ASSOC = 0x02 - * - * Possible values: - * 0: Default value, no way mask should be applied - * 1: Apply way mask 1 to LLC - * 2: Apply way mask 2 to LLC - * 3: Shouldn't be use in NEM Mode - */ - movl $IA32_PQR_ASSOC, %ecx - movl $0x02, %eax - xorl %edx, %edx - wrmsr - - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - movl $CACHE_INIT_VALUE, %eax - cld - rep stosl - /* - * Set IA32_PQR_ASSOC = 0x01 - * At this stage we apply LLC_WAY_MASK_1 to the cache. - * i.e. way 0 is protected from eviction. - */ - movl $IA32_PQR_ASSOC, %ecx - movl $0x01, %eax - xorl %edx, %edx - wrmsr - - /* - * Enable No-Eviction Mode Run State by setting - * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. - */ - - movl $MSR_EVICT_CTL, %ecx - rdmsr - orl $0x02, %eax - wrmsr - - post_code(0x27) - /* - * Configure the BIOS code region as write-protected (WP) cacheable - * memory type using a single variable range MTRR. - * - * Ensure region to cache meets MTRR requirements for - * size and alignment. - */ - movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */ - movl $CONFIG_ROM_SIZE, %eax /* Code region size */ - cmpl $0, %edi - jz .halt_forever - cmpl $0, %eax - jz .halt_forever - - post_code(0x28) - /* - * Program base register - */ - xorl %edx, %edx /* clear upper dword */ - movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */ - movl %edi, %eax - orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */ - wrmsr - - movl $CONFIG_ROM_SIZE, %eax - - /* - * Compute MTRR mask value: Mask = NOT (Size - 1) - */ - dec %eax /* eax - size to cache less one byte */ - not %eax /* eax contains low 32 bits of mask */ - or $MTRR_PHYS_MASK_VALID, %eax - /* - * Program mask register - */ - movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */ - movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ - wrmsr - -car_init_done: - - post_code(0x29) - - /* Setup bootblock stack */ - mov $_car_stack_end, %esp - - /*push TSC value to stack*/ - movd %mm2, %eax - pushl %eax /* tsc[63:32] */ - movd %mm1, %eax - pushl %eax /* tsc[31:0] */ - -before_carstage: - post_code(0x2A) - - call bootblock_c_entry - /* Never reached */ - -.halt_forever: - post_code(POST_DEAD_CODE) - hlt - jmp .halt_forever - -fixed_mtrr_list: - .word MTRR_FIX_64K_00000 - .word MTRR_FIX_16K_80000 - .word MTRR_FIX_16K_A0000 - .word MTRR_FIX_4K_C0000 - .word MTRR_FIX_4K_C8000 - .word MTRR_FIX_4K_D0000 - .word MTRR_FIX_4K_D8000 - .word MTRR_FIX_4K_E0000 - .word MTRR_FIX_4K_E8000 - .word MTRR_FIX_4K_F0000 - .word MTRR_FIX_4K_F8000 -fixed_mtrr_list_size = . - fixed_mtrr_list

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Patch set updated for coreboot: intelblocks/msr: Move intel x86 MSR definition into common location
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18509 -gerrit commit 43e2f8f9158b437b85c4da6ec0cf2d9348e59b71 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 15:42:09 2017 +0530 intelblocks/msr: Move intel x86 MSR definition into common location Move all common MSRs as per IA SDM into a common location to avoid duplication. Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- .../intel/common/block/include/intelblocks/msr.h | 102 +++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h new file mode 100644 index 0000000..27607f5 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/msr.h @@ -0,0 +1,102 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_MSR_H +#define SOC_INTEL_COMMON_MSR_H + +#define MSR_CORE_THREAD_COUNT 0x35 +#define IA32_FEATURE_CONTROL 0x3a +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define MSR_PLATFORM_INFO 0xce +#define MSR_PMG_CST_CONFIG_CONTROL 0xe2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */ +#define PKG_C_STATE_LIMIT_C2_MASK 0x2 +/* Set MSR_PMG_CST_CONFIG_CONTROL[7:4] for Core C-State limit*/ +#define CORE_C_STATE_LIMIT_C10_MASK 0x70 +/* Set MSR_PMG_CST_CONFIG_CONTROL[10] to IO redirect to MWAIT */ +#define IO_MWAIT_REDIRECT_MASK 0x400 +/* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ +#define CST_CFG_LOCK_MASK 0x8000 +#define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_FEATURE_CONFIG 0x13c +#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL +#define FEATURE_CONFIG_LOCK (1 << 0) +#define SMM_MCA_CAP_MSR 0x17d +#define SMM_CPU_SVRSTR_BIT 57 +#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32)) +#define MSR_IA32_PERF_CTL 0x199 +#define IA32_MISC_ENABLE 0x1a0 +#define MSR_TEMPERATURE_TARGET 0x1a2 +#define MSR_PREFETCH_CTL 0x1a4 +#define PREFETCH_L1_DISABLE (1 << 0) +#define PREFETCH_L2_DISABLE (1 << 2) +#define MSR_MISC_PWR_MGMT 0x1aa +#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_POWER_CTL 0x1fc +#define MSR_EVICT_CTL 0x2e0 +#define IA32_MC0_STATUS 0x401 +#define SMM_FEATURE_CONTROL_MSR 0x4e0 +#define SMM_CPU_SAVE_EN (1 << 1) +#define MSR_PKG_POWER_SKU_UNIT 0x606 +#define MSR_C_STATE_LATENCY_CONTROL_0 0x60a +#define MSR_C_STATE_LATENCY_CONTROL_1 0x60b +#define MSR_C_STATE_LATENCY_CONTROL_2 0x60c +#define MSR_PKG_POWER_LIMIT 0x610 +/* + * For Mobile, RAPL default PL1 time window value set to 28 seconds. + * RAPL time window calculation defined as follows: + * Time Window = (float)((1+X/4)*(2*^Y), X Corresponds to [23:22], + * Y to [21:17] in MSR 0x610. 28 sec is equal to 0x6e. + */ +#define MB_POWER_LIMIT1_TIME_DEFAULT 0x6e +#define MSR_PKG_POWER_SKU 0x614 +#define MSR_DDR_RAPL_LIMIT 0x618 +#define MSR_C_STATE_LATENCY_CONTROL_3 0x633 +#define MSR_C_STATE_LATENCY_CONTROL_4 0x634 +#define MSR_C_STATE_LATENCY_CONTROL_5 0x635 +#define IRTL_VALID (1 << 15) +#define IRTL_1_NS (0 << 10) +#define IRTL_32_NS (1 << 10) +#define IRTL_1024_NS (2 << 10) +#define IRTL_32768_NS (3 << 10) +#define IRTL_1048576_NS (4 << 10) +#define IRTL_33554432_NS (5 << 10) +#define IRTL_RESPONSE_MASK (0x3ff) +#define MSR_COUNTER_24_MHZ 0x637 +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_CONFIG_TDP_LEVEL1 0x649 +#define MSR_CONFIG_TDP_LEVEL2 0x64a +#define MSR_CONFIG_TDP_CONTROL 0x64b +#define MSR_TURBO_ACTIVATION_RATIO 0x64c +#define PKG_POWER_LIMIT_MASK (0x7fff) +#define PKG_POWER_LIMIT_EN (1 << 15) +#define PKG_POWER_LIMIT_CLAMP (1 << 16) +#define PKG_POWER_LIMIT_TIME_SHIFT 17 +#define PKG_POWER_LIMIT_TIME_MASK (0x7f) +#define MSR_IA32_PQR_ASSOC 0x0c8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#define MSR_IA32_L3_MASK_1 0x0c91 +#define MSR_IA32_L3_MASK_2 0x0c92 +#define MSR_L2_QOS_MASK(reg) (0xd10 + reg) + +#endif /* SOC_INTEL_COMMON_MSR_H */ +

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Patch set updated for coreboot: soc/intel/glk: Include cache_as_ram_fsp.S inside glk/bootblock
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18453 -gerrit commit 2a7f16401aed2966dae5d907965105b06f5812de Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 16:22:58 2017 +0530 soc/intel/glk: Include cache_as_ram_fsp.S inside glk/bootblock Add option to use FSP APIs to initialize & Tear Down the Cache-As-Ram. Change-Id: I4964fa27967323062c6243e023d2caa82b7f0440 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Makefile.inc | 2 + src/soc/intel/glk/bootblock/cache_as_ram_fsp.S | 111 +++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/src/soc/intel/glk/Makefile.inc b/src/soc/intel/glk/Makefile.inc index 92c3bc2..3fd1263 100644 --- a/src/soc/intel/glk/Makefile.inc +++ b/src/soc/intel/glk/Makefile.inc @@ -8,6 +8,8 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache +bootblock-$(CONFIG_FSP_CAR) += bootblock/cache_as_ram_fsp.S + CPPFLAGS_common += -I$(src)/soc/intel/glk/include CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/glk diff --git a/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S b/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S new file mode 100644 index 0000000..f55582a --- /dev/null +++ b/src/soc/intel/glk/bootblock/cache_as_ram_fsp.S @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +#define FSP_HDR_OFFSET 0x94 + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add FSP_HDR_OFFSET, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ + add 0x1c(%ebx), %eax /* add the FSP ImageBase */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +/* + * If the TempRamInit API is successful, then when returning, the ECX and + * EDX registers will point to the temporary but writeable memory range + * available to the bootloader where ECX is the start and EDX is the end of + * the range i.e. [ECX,EDX). See Apollo Lake FSP Integration Guide for more + * information. + * + * Return Values: + * EAX | Return Status + * ECX | Temporary Memory Start + * EDX | Temporary Memory End + * EBX, EDI, ESI, EBP, MM0, MM1 | Preserved Through API Call + */ + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00"

1 0

Patch set updated for coreboot: soc/intel/glk: Use intel/common/xhci driver
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18450 -gerrit commit 2f2531d3556f9f19d059b37a11fa4ca8a0fec1f0 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 15:39:23 2017 +0530 soc/intel/glk: Use intel/common/xhci driver Change-Id: I08fbe7c7ac83d12af1cc77450001103a7069d7d8 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/glk/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index a0f9664..c08d705 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_COMMON_XHCI select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER

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Patch set updated for coreboot: soc/intel/skylake: Use intel/common/xhci driver
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18223 -gerrit commit 3eaacb4d439c637a728f80099b3feb70136b27b5 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Feb 16 16:16:37 2017 +0530 soc/intel/skylake: Use intel/common/xhci driver Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/xhci.c | 43 -------------------------------------- 3 files changed, 1 insertion(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 725a25d..67d2213 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -52,6 +52,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_COMMON_XHCI select SMM_TSEG select SMP select SSE2 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 4b6fcfc..2a6b152 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -90,7 +90,6 @@ ramstage-y += tsc_freq.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += vr_config.c -ramstage-y += xhci.c smm-y += cpu_info.c smm-y += gpio.c diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c deleted file mode 100644 index 0912f10..0000000 --- a/src/soc/intel/skylake/xhci.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <soc/ramstage.h> -#include <soc/cpu.h> - -static struct device_operations usb_xhci_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d2f, /* SunRisePoint LP */ - 0xa12f, /* KBL-H*/ - 0 -}; - -static const struct pci_driver pch_usb_xhci __pci_driver = { - .ops = &usb_xhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -};

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Patch set updated for coreboot: soc/intel/common/block: Add Intel XHCI driver support
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18221 -gerrit commit 5adef38291c3ed1304ead8e2ad3d7e642cda1288 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Thu Feb 16 16:08:49 2017 +0530 soc/intel/common/block: Add Intel XHCI driver support Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- .../intel/common/block/include/intelblocks/xhci.h | 22 +++++++++++ src/soc/intel/common/block/xhci/Kconfig | 4 ++ src/soc/intel/common/block/xhci/Makefile.inc | 1 + src/soc/intel/common/block/xhci/xhci.c | 44 ++++++++++++++++++++++ 4 files changed, 71 insertions(+) diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h new file mode 100644 index 0000000..2e893ca --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/xhci.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SOC_INTEL_COMMON_XHCI_H +#define SOC_INTEL_COMMON_XHCI_H + +void soc_xhci_init(struct device *dev); + +#endif /* SOC_INTEL_COMMON_XHCI_H */ + diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig new file mode 100644 index 0000000..23313d7 --- /dev/null +++ b/src/soc/intel/common/block/xhci/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_COMMON_XHCI + bool + help + Intel Processor common XHCI support diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc new file mode 100644 index 0000000..a501581 --- /dev/null +++ b/src/soc/intel/common/block/xhci/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_XHCI) += xhci.c diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c new file mode 100644 index 0000000..32fad93 --- /dev/null +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <intelblocks/xhci.h> + +__attribute__((weak)) void soc_xhci_init(struct device *dev) { /* no-op */ } + +static struct device_operations usb_xhci_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = soc_xhci_init, +}; + +static const unsigned short pci_device_ids[] = { + 0x5aa8, /* ApolloLake */ + 0x31a8, /* GLK */ + 0x9d2f, /* SunRisePoint LP */ + 0xa12f, /* KBL-H*/ + 0 +}; + +static const struct pci_driver pch_usb_xhci __pci_driver = { + .ops = &usb_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: soc/intel/skylake: Clean up XHCI code
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18508 -gerrit commit e1defc0863a78e003248d5e00b20fbda93e8258b Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 27 12:21:49 2017 +0530 soc/intel/skylake: Clean up XHCI code Don't need "skylake/include/soc/xhci.h", hence removed. Change-Id: I35df2003f311b557b622ce1d7a1c2e832693c2fc Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/include/soc/xhci.h | 60 -------------------------------- src/soc/intel/skylake/xhci.c | 1 - 2 files changed, 61 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/xhci.h b/src/soc/intel/skylake/include/soc/xhci.h deleted file mode 100644 index c520223..0000000 --- a/src/soc/intel/skylake/include/soc/xhci.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_XHCI_H_ -#define _SOC_XHCI_H_ - -#include <rules.h> - -/* XHCI PCI Registers */ -#define XHCI_PWR_CTL_STS 0x74 -#define XHCI_PWR_CTL_SET_MASK 0x3 -#define XHCI_PWR_CTL_SET_D0 0x0 -#define XHCI_PWR_CTL_SET_D3 0x3 -#define XHCI_PWR_CTL_ENABLE_PME (1 << 8) -#define XHCI_PWR_CTL_STATUS_PME (1 << 15) -#define XHCI_USB2PR 0xd0 -#define XHCI_USB2PRM 0xd4 -#define XHCI_USB2PR_HCSEL 0x7fff -#define XHCI_USB3PR 0xd8 -#define XHCI_USB3PR_SSEN 0x3f -#define XHCI_USB3PRM 0xdc -#define XHCI_USB3FUS 0xe0 -#define XHCI_USB3FUS_SS_MASK 3 -#define XHCI_USB3FUS_SS_SHIFT 3 -#define XHCI_USB3PDO 0xe8 - -/* XHCI Memory Registers */ -#define XHCI_USB3_PORTSC(port) (0x510 + (port * 0x10)) -#define XHCI_USB3_PORTSC_CHST (0x7f << 17) -#define XHCI_USB3_PORTSC_WCE (1 << 25) /* Wake on Connect */ -#define XHCI_USB3_PORTSC_WDE (1 << 26) /* Wake on Disconnect */ -#define XHCI_USB3_PORTSC_WOE (1 << 27) /* Wake on Overcurrent */ -#define XHCI_USB3_PORTSC_WRC (1 << 19) /* Warm Reset Complete */ -#define XHCI_USB3_PORTSC_LWS (1 << 16) /* Link Write Strobe */ -#define XHCI_USB3_PORTSC_PED (1 << 1) /* Port Enabled/Disabled */ -#define XHCI_USB3_PORTSC_WPR (1 << 31) /* Warm Port Reset */ -#define XHCI_USB3_PORTSC_PLS (0xf << 5) /* Port Link State */ -#define XHCI_PLSR_DISABLED (4 << 5) /* Port is disabled */ -#define XHCI_PLSR_RXDETECT (5 << 5) /* Port is disconnected */ -#define XHCI_PLSR_POLLING (7 << 5) /* Port is polling */ -#define XHCI_PLSW_ENABLE (5 << 5) /* Transition from disabled */ - -#if ENV_SMM -void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ); -#endif - -#endif diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c index 5ee34df..0912f10 100644 --- a/src/soc/intel/skylake/xhci.c +++ b/src/soc/intel/skylake/xhci.c @@ -21,7 +21,6 @@ #include <device/pci_ids.h> #include <arch/io.h> #include <soc/ramstage.h> -#include <soc/xhci.h> #include <soc/cpu.h> static struct device_operations usb_xhci_ops = {

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Patch set updated for coreboot: soc/intel/apollolake: Move XDCI in its own file
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18226 -gerrit commit 23be7a495e53a926fef0be6c20216fec0b1e5c64 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jan 24 21:56:36 2017 -0800 soc/intel/apollolake: Move XDCI in its own file Split out dual-port switching functionality into dedicated xdci.c. Change-Id: Ia58fc3fb6d017dd0c19cc450d1caba307fc89a7b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/xdci.c | 105 +++++++++++++++++++++++++ src/soc/intel/apollolake/xhci.c | 72 ----------------- 4 files changed, 107 insertions(+), 72 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index df93f0b..5e1cf73 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -83,6 +83,7 @@ ramstage-y += reset.c ramstage-y += smi.c ramstage-y += sram.c ramstage-y += spi.c +ramstage-y += xdci.c ramstage-y += xhci.c postcar-y += flash_ctrlr.c diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 130263b..4c2956f 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -28,6 +28,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_XDCI 0x5aaa /* 00:15.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */ diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c new file mode 100644 index 0000000..2812957 --- /dev/null +++ b/src/soc/intel/apollolake/xdci.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <timer.h> + +#define DUAL_ROLE_CFG0 0x80d8 +# define DRD_CONFIG_MASK (0x3 << 0) +# define DRD_CONFIG_DYNAMIC (0x0 << 0) +# define DRD_CONFIG_HOST (0x1 << 0) +# define DRD_CONFIG_DEVICE (0x2 << 0) +# define SW_VBUS_VALID_MASK (1 << 24) +# define SW_VBUS_DEASSERT_VALID (0 << 24) +# define SW_VBUS_ASSERT_VALID (1 << 24) +# define SW_IDPIN_EN_MASK (1 << 21) +# define SW_IDPIN_DIS (0 << 21) +# define SW_IDPIN_EN (1 << 21) +# define SW_IDPIN_MASK (1 << 20) +# define SW_IDPIN_HOST (0 << 20) +# define SW_IDPIN_DEVICE (1 << 20) +#define DUAL_ROLE_CFG1 0x80dc +# define DRD_MODE_MASK (1 << 29) +# define DRD_MODE_DEVICE (0 << 29) +# define DRD_MODE_HOST (1 << 29) + +static void configure_host_mode_port0(struct device *dev) +{ + uint32_t *cfg0; + uint32_t *cfg1; + const struct resource *res; + uint32_t reg; + struct stopwatch sw; + struct device *xhci_dev = XHCI_DEV; + + /* + * Only default to host mode if the xdci device is present and + * enabled. If it's disabled assume the switch was already done + * in FSP. + */ + if (!dev->enabled || !xhci_dev->enabled) + return; + + printk(BIOS_INFO, "Putting port 0 into host mode.\n"); + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + + cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); + cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); + + reg = read32(cfg0); + reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); + reg &= ~(SW_VBUS_VALID_MASK); + reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; + reg |= SW_VBUS_DEASSERT_VALID; + write32(cfg0, reg); + + stopwatch_init_msecs_expire(&sw, 10); + + /* Wait for the host mode status bit. */ + while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Timed out waiting for host mode.\n"); + break; + } + } + + printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +static void xdci_init(struct device *dev) +{ + configure_host_mode_port0(dev); +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xdci_init, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_XDCI, +}; diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c index 7b3cb46..3dd4f7d 100644 --- a/src/soc/intel/apollolake/xhci.c +++ b/src/soc/intel/apollolake/xhci.c @@ -14,88 +14,16 @@ */ #include <arch/io.h> -#include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <soc/pci_devs.h> #include <soc/pci_ids.h> -#include <timer.h> - -#define DUAL_ROLE_CFG0 0x80d8 -# define DRD_CONFIG_MASK (0x3 << 0) -# define DRD_CONFIG_DYNAMIC (0x0 << 0) -# define DRD_CONFIG_HOST (0x1 << 0) -# define DRD_CONFIG_DEVICE (0x2 << 0) -# define SW_VBUS_VALID_MASK (1 << 24) -# define SW_VBUS_DEASSERT_VALID (0 << 24) -# define SW_VBUS_ASSERT_VALID (1 << 24) -# define SW_IDPIN_EN_MASK (1 << 21) -# define SW_IDPIN_DIS (0 << 21) -# define SW_IDPIN_EN (1 << 21) -# define SW_IDPIN_MASK (1 << 20) -# define SW_IDPIN_HOST (0 << 20) -# define SW_IDPIN_DEVICE (1 << 20) -#define DUAL_ROLE_CFG1 0x80dc -# define DRD_MODE_MASK (1 << 29) -# define DRD_MODE_DEVICE (0 << 29) -# define DRD_MODE_HOST (1 << 29) - -static void configure_host_mode_port0(struct device *dev) -{ - uint32_t *cfg0; - uint32_t *cfg1; - const struct resource *res; - uint32_t reg; - struct device *xdci_dev = XDCI_DEV; - struct stopwatch sw; - - /* - * Only default to host mode if the xdci device is present and - * enabled. If it's disabled assume the switch was already done - * in FSP. - */ - if (xdci_dev == NULL || !xdci_dev->enabled) - return; - - printk(BIOS_INFO, "Putting port 0 into host mode.\n"); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - - cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); - cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); - - reg = read32(cfg0); - reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); - reg &= ~(SW_VBUS_VALID_MASK); - reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; - reg |= SW_VBUS_DEASSERT_VALID; - write32(cfg0, reg); - - stopwatch_init_msecs_expire(&sw, 10); - - /* Wait for the host mode status bit. */ - while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { - if (stopwatch_expired(&sw)) { - printk(BIOS_INFO, "Timed out waiting for host mode.\n"); - break; - } - } - - printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -static void xhci_init(struct device *dev) -{ - configure_host_mode_port0(dev); -} static const struct device_operations device_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, - .init = xhci_init, }; static const struct pci_driver pmc __pci_driver = {

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coreboot-gerrit March 2017