coreboot-gerrit March 2017

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Patch set updated for coreboot: drivers/intel/txe: Add HECI driver
by Andrey Petrov 02 Mar '17

02 Mar '17

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18547 -gerrit commit 705f0b7d734322b9eed33beea9f08db2094e1927 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 1 15:51:57 2017 -0800 drivers/intel/txe: Add HECI driver Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/txe/Kconfig | 5 + src/drivers/intel/txe/Makefile.inc | 2 + src/drivers/intel/txe/txe.c | 396 +++++++++++++++++++++++++++++++++++++ src/drivers/intel/txe/txe.h | 58 ++++++ 4 files changed, 461 insertions(+) diff --git a/src/drivers/intel/txe/Kconfig b/src/drivers/intel/txe/Kconfig new file mode 100644 index 0000000..be5ceb1 --- /dev/null +++ b/src/drivers/intel/txe/Kconfig @@ -0,0 +1,5 @@ +config TXE_COMMON + bool + default n + help + Unified TXE driver diff --git a/src/drivers/intel/txe/Makefile.inc b/src/drivers/intel/txe/Makefile.inc new file mode 100644 index 0000000..4d7bf43 --- /dev/null +++ b/src/drivers/intel/txe/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_TXE_COMMON) += txe.c +ramstage-$(CONFIG_TXE_COMMON) += txe.c diff --git a/src/drivers/intel/txe/txe.c b/src/drivers/intel/txe/txe.c new file mode 100644 index 0000000..419d8be --- /dev/null +++ b/src/drivers/intel/txe/txe.c @@ -0,0 +1,396 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <timer.h> +#include "txe.h" + +/* default for early boot */ +#define HECI1_BASE_ADDRESS 0xfed1a000 + +#define HECI_DELAY_READY (15 * 1000) +#define HECI_DELAY 100 +#define HECI_SEND_TIMEOUT (5 * 1000) +#define HECI_READ_TIMEOUT (5 * 1000) + +#define SLOT_SIZE 4 + +struct txe_device { + uintptr_t sec_bar; +} g_txe CAR_GLOBAL; + +void heci_init(uintptr_t tempbar) { + + struct txe_device *txe = car_get_var_ptr(&g_txe); + device_t dev = HECI1_DEV; + u8 pcireg; + + /* assume initialized, nothing to do */ + if (txe->sec_bar) + return; + + if (!bar) + bar = HECI1_BASE_ADDRESS; + + /* Assign Resources to HECI1 */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI1 */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, tempbar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); + + txe->sec_bar = tempbar; +} + +static uint32_t read_bar(uint32_t offset) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return read32((void *)(txe->sec_bar + offset)); +} + +static void write_bar(uint32_t offset, uint32_t val) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return write32((void *)(txe->sec_bar + offset), val); +} + +static uint32_t read_me_csr(void) +{ + return read_bar(MMIO_ME_CSR); +} + +static uint32_t read_host_csr(void) +{ + return read_bar(MMIO_HOST_CSR); +} + +static void write_host_csr(uint32_t data) +{ + write_bar(MMIO_HOST_CSR, data); +} + +static uint8_t get_cb_msg_count(uint32_t data) +{ + int8_t read_offset = (data >> 8); + int8_t write_offset = (data >> 16); + return write_offset - read_offset; +} + +static uint32_t me_filled_slots(void) +{ + return get_cb_msg_count(read_me_csr()); +} + +static uint8_t host_filled_slots(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + + return csr.fields.me_cir_buff - get_cb_msg_count(csr.data); +} + +static void clear_int(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_sts = 1; + write_host_csr(csr.data); +} + +static uint32_t read_slot(void) +{ + return read_bar(MMIO_ME_CB_RW); +} + +static void write_slot(uint32_t val) +{ + write_bar(MMIO_ME_CB_WW, val); +} + +static int wait_write_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (host_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); + return 0; + } + } + return 1; +} + +static int wait_read_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (me_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timed out reading answer!\n"); + return 0; + } + } + return 1; +} + +/* get number of full 4-byte slots */ +static uint32_t bytes_to_slots(uint32_t bytes) +{ + return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; +} + +static int me_ready(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + return !!csr.fields.host_ready; +} + +static int wait_heci_ready(void) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!me_ready()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + +static void host_gen_interrupt(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_gen = 1; + write_host_csr(csr.data); +} + +static int +send_one_message(union mei_header *hdr, void *buff) +{ + uint32_t pend_len, pend_slots, i, remainder, tmp; + uint32_t *p = (uint32_t*)buff; + + /* get space for the header */ + wait_write_slots(1); + + /* first, write header */ + write_slot(hdr->data); + + pend_len = hdr->fields.length; + pend_slots = bytes_to_slots(pend_len); + + wait_write_slots(pend_slots); + + /* write the body in whole slots */ + while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { + write_slot(*p++); + i += SLOT_SIZE; + } + + remainder = pend_len % SLOT_SIZE; + /* pad to 4 bytes not touching caller's buffer */ + if (remainder) { + memcpy(&tmp, p, remainder); + write_slot(tmp); + } + + host_gen_interrupt(); + + if (!me_ready()) + return 0; + + return hdr->fields.length; +} + +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client) +{ + union me_csr csr; + union mei_header hdr; + uint32_t sent = 0, remaining, slots, cb_size; + uint8_t *p = (uint8_t*) msg; + + if (!msg || !len) + return 0; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + csr.data = read_me_csr(); + /* reserve one slot for header */ + cb_size = (csr.fields.me_cir_buff - 1) * SLOT_SIZE - 1; + + remaining = len; + slots = len / SLOT_SIZE; + + /* + * Fragment the message into smaller messages not exceeding useful + * circullar buffer length. Mark last message complete. + */ + do { + hdr.fields.length = MIN(cb_size, remaining); + hdr.fields.client_address = client; + hdr.fields.host_address = host; + hdr.fields.is_complete = (remaining <= cb_size); + sent = send_one_message(&hdr, p); + p += sent; + remaining -= sent; + } while (remaining > 0 && sent != 0); + + return remaining==0; +} + +static uint32_t +recv_one_message(union mei_header *hdr, void *buff, uint32_t maxlen) +{ + uint32_t *p = (uint32_t *)buff; + uint32_t recv_slots, recv_len, reminder, reg, i; + + /* first get the header */ + if (!wait_read_slots(1)) + return 0; + + hdr->data = read_slot(); + recv_len = hdr->fields.length; + + if (!recv_len) + printk(BIOS_WARNING, "HECI: message is zero-sized\n"); + + recv_slots = bytes_to_slots(recv_len); + + if (recv_len > maxlen) { + printk(BIOS_ERR, "HECI: response is too big\n"); + return 0; + } + + /* wait for the rest of messages to arrive */ + wait_read_slots(recv_slots); + + /* fetch whole slots first */ + while (i < ALIGN_DOWN(recv_len, 4)) { + *p++ = read_slot(); + i += SLOT_SIZE; + } + + reminder = recv_len % SLOT_SIZE; + + if (reminder) { + reg = read_slot(); + memcpy(p, &reg, reminder); + } + + return recv_len; +} + +int heci_receive(void *buff, uint32_t *maxlen) +{ + union mei_header hdr; + uint32_t left, received; + uint8_t *p = (uint8_t *)buff; + + if (!buff || !maxlen || !*maxlen) + return 0; + + left = *maxlen; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + /* + * Receive multiple packets until we meet one marked complete or we run + * or we run out of space. + */ + do { + received = recv_one_message(&hdr, p, left); + left -= received; + p += received; + /* if read out all, ping to send more */ + if (!hdr.fields.is_complete && !me_filled_slots()) + host_gen_interrupt(); + } while (received && !hdr.fields.is_complete && left > 0); + + *maxlen = p - (uint8_t*) buff; + + /* if ME is not ready, something went wrong and we received junk */ + if (!me_ready()) + return 0; + + return hdr.fields.is_complete; +} + +#if ENV_RAMSTAGE + +static void update_sec_bar(struct device *dev) +{ + g_txe.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; +} + +static void txe_set_resources(struct device *dev) +{ + if (dev->path.pci.devfn == HECI1_DEVFN) + update_sec_bar(dev); + + pci_dev_set_resources(dev); +} + +static struct device_operations txe_ops = { + .set_resources = txe_set_resources, + .read_resources = pci_dev_read_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .enable_resources = pci_dev_enable_resources +}; + +static const struct pci_driver txe_driver __pci_driver = { + .ops = &txe_ops, + .vendor = PCI_VENDOR_ID_INTEL, + /* expectation is that soc/chipset code provides this */ + .device = PCI_DEVICE_ID_HECI1 +}; + +#endif diff --git a/src/drivers/intel/txe/txe.h b/src/drivers/intel/txe/txe.h new file mode 100644 index 0000000..b837dbf --- /dev/null +++ b/src/drivers/intel/txe/txe.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_INTEL_TXE_H_ +#define _DRIVERS_INTEL_TXE_H_ + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0c + +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +union mei_header { + u32 data; + struct { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; + } __attribute__ ((packed)) fields; +}; + +union me_csr { + u32 data; + struct { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_offset: 8; + u32 me_write_offset: 8; + u32 me_cir_buff: 8; + } __attribute__ ((packed)) fields; +}; + +/* set up device for use in early boot enviroument with temp bar */ +void heci_init(uintptr_t bar); +/* receive not less than maxlen into buff, returns 0 on failure */ +int heci_receive(void *buff, uint32_t *maxlen); +/* send message of size len, returns 0 on failure */ +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client); +#endif // _DRIVERS_INTEL_TXE_H_

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Patch set updated for coreboot: drivers/intel/txe: Add HECI driver
by Andrey Petrov 02 Mar '17

02 Mar '17

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18547 -gerrit commit 5aad623189ee886f07853ebcd25156399169bc18 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Wed Mar 1 15:51:57 2017 -0800 drivers/intel/txe: Add HECI driver Add common driver that can send/receive HECI messages. This driver is inspired by Linux kernel mei driver and somewhat based on Skylake's. Currently it has been only tested on Apollolake. BUG=b:35586975 BRANCH=reef TEST=tested on Apollolake to send single messages and receive both fragmented and non-fragmented versions. Change-Id: Ie3772700270f4f333292b80d59f79555851780f7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/txe/Kconfig | 5 + src/drivers/intel/txe/Makefile.inc | 2 + src/drivers/intel/txe/txe.c | 396 +++++++++++++++++++++++++++++++++++++ src/drivers/intel/txe/txe.h | 58 ++++++ 4 files changed, 461 insertions(+) diff --git a/src/drivers/intel/txe/Kconfig b/src/drivers/intel/txe/Kconfig new file mode 100644 index 0000000..be5ceb1 --- /dev/null +++ b/src/drivers/intel/txe/Kconfig @@ -0,0 +1,5 @@ +config TXE_COMMON + bool + default n + help + Unified TXE driver diff --git a/src/drivers/intel/txe/Makefile.inc b/src/drivers/intel/txe/Makefile.inc new file mode 100644 index 0000000..4d7bf43 --- /dev/null +++ b/src/drivers/intel/txe/Makefile.inc @@ -0,0 +1,2 @@ +romstage-$(CONFIG_TXE_COMMON) += txe.c +ramstage-$(CONFIG_TXE_COMMON) += txe.c diff --git a/src/drivers/intel/txe/txe.c b/src/drivers/intel/txe/txe.c new file mode 100644 index 0000000..5d20646 --- /dev/null +++ b/src/drivers/intel/txe/txe.c @@ -0,0 +1,396 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <lib.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <timer.h> +#include "txe.h" + +/* default for early boot */ +#define HECI1_BASE_ADDRESS 0xfed1a000 + +#define HECI_DELAY_READY (15 * 1000) +#define HECI_DELAY 100 +#define HECI_SEND_TIMEOUT (5 * 1000) +#define HECI_READ_TIMEOUT (5 * 1000) + +#define SLOT_SIZE 4 + +struct txe_device { + uintptr_t sec_bar; +} g_txe CAR_GLOBAL; + +void heci_init(uintptr_t bar) { + + struct txe_device *txe = car_get_var_ptr(&g_txe); + device_t dev = HECI1_DEV; + u8 pcireg; + + if (!bar) + bar = HECI1_BASE_ADDRESS; + + /* assume initialized, nothing to do */ + if (txe->sec_bar) + return; + + /* Assign Resources to HECI1 */ + /* Clear BIT 1-2 of Command Register */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config8(dev, PCI_COMMAND, pcireg); + + /* Program Temporary BAR for HECI1 */ + pci_write_config32(dev, PCI_BASE_ADDRESS_0, bar); + pci_write_config32(dev, PCI_BASE_ADDRESS_1, 0x0); + + /* Enable Bus Master and MMIO Space */ + pcireg = pci_read_config8(dev, PCI_COMMAND); + pcireg |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; + pci_write_config8(dev, PCI_COMMAND, pcireg); + + txe->sec_bar = bar; +} + +static uint32_t read_bar(uint32_t offset) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return read32((void *)(txe->sec_bar + offset)); +} + +static void write_bar(uint32_t offset, uint32_t val) +{ + struct txe_device *txe = car_get_var_ptr(&g_txe); + return write32((void *)(txe->sec_bar + offset), val); +} + +static uint32_t read_me_csr(void) +{ + return read_bar(MMIO_ME_CSR); +} + +static uint32_t read_host_csr(void) +{ + return read_bar(MMIO_HOST_CSR); +} + +static void write_host_csr(uint32_t data) +{ + write_bar(MMIO_HOST_CSR, data); +} + +static uint8_t get_cb_msg_count(uint32_t data) +{ + int8_t read_offset = (data >> 8); + int8_t write_offset = (data >> 16); + return write_offset - read_offset; +} + +static uint32_t me_filled_slots(void) +{ + return get_cb_msg_count(read_me_csr()); +} + +static uint8_t host_filled_slots(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + + return csr.fields.me_cir_buff - get_cb_msg_count(csr.data); +} + +static void clear_int(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_sts = 1; + write_host_csr(csr.data); +} + +static uint32_t read_slot(void) +{ + return read_bar(MMIO_ME_CB_RW); +} + +static void write_slot(uint32_t val) +{ + write_bar(MMIO_ME_CB_WW, val); +} + +static int wait_write_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (host_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timeout, buffer not drained\n"); + return 0; + } + } + return 1; +} + +static int wait_read_slots(uint32_t cnt) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_READ_TIMEOUT); + while (me_filled_slots() < cnt) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "HECI: timed out reading answer!\n"); + return 0; + } + } + return 1; +} + +/* get number of full 4-byte slots */ +static uint32_t bytes_to_slots(uint32_t bytes) +{ + return ALIGN_UP(bytes, SLOT_SIZE) / SLOT_SIZE; +} + +static int me_ready(void) +{ + union me_csr csr; + csr.data = read_me_csr(); + return !!csr.fields.host_ready; +} + +static int wait_heci_ready(void) +{ + struct stopwatch sw; + + stopwatch_init_msecs_expire(&sw, HECI_DELAY_READY); + while (!me_ready()) { + udelay(HECI_DELAY); + if (stopwatch_expired(&sw)) + return 0; + } + + return 1; +} + +static void host_gen_interrupt(void) +{ + union me_csr csr; + csr.data = read_host_csr(); + csr.fields.int_gen = 1; + write_host_csr(csr.data); +} + +static int +send_one_message(union mei_header *hdr, void *buff) +{ + uint32_t pend_len, pend_slots, i, remainder, tmp; + uint32_t *p = (uint32_t*)buff; + + /* get space for the header */ + wait_write_slots(1); + + /* first, write header */ + write_slot(hdr->data); + + pend_len = hdr->fields.length; + pend_slots = bytes_to_slots(pend_len); + + wait_write_slots(pend_slots); + + /* write the body in whole slots */ + while (i < ALIGN_DOWN(pend_len, SLOT_SIZE)) { + write_slot(*p++); + i += SLOT_SIZE; + } + + remainder = pend_len % SLOT_SIZE; + /* pad to 4 bytes not touching caller's buffer */ + if (remainder) { + memcpy(&tmp, p, remainder); + write_slot(tmp); + } + + host_gen_interrupt(); + + if (!me_ready()) + return 0; + + return hdr->fields.length; +} + +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client) +{ + union me_csr csr; + union mei_header hdr; + uint32_t sent = 0, remaining, slots, cb_size; + uint8_t *p = (uint8_t*) msg; + + if (!msg || !len) + return 0; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + csr.data = read_me_csr(); + /* reserve one slot for header */ + cb_size = (csr.fields.me_cir_buff - 1) * SLOT_SIZE - 1; + + remaining = len; + slots = len / SLOT_SIZE; + + /* + * Fragment the message into smaller messages not exceeding useful + * circullar buffer length. Mark last message complete. + */ + do { + hdr.fields.length = MIN(cb_size, remaining); + hdr.fields.client_address = client; + hdr.fields.host_address = host; + hdr.fields.is_complete = (remaining <= cb_size); + sent = send_one_message(&hdr, p); + p += sent; + remaining -= sent; + } while (remaining > 0 && sent != 0); + + return remaining==0; +} + +static uint32_t +recv_one_message(union mei_header *hdr, void *buff, uint32_t maxlen) +{ + uint32_t *p = (uint32_t *)buff; + uint32_t recv_slots, recv_len, reminder, reg, i; + + /* first get the header */ + if (!wait_read_slots(1)) + return 0; + + hdr->data = read_slot(); + recv_len = hdr->fields.length; + + if (!recv_len) + printk(BIOS_WARNING, "HECI: message is zero-sized\n"); + + recv_slots = bytes_to_slots(recv_len); + + if (recv_len > maxlen) { + printk(BIOS_ERR, "HECI: response is too big\n"); + return 0; + } + + /* wait for the rest of messages to arrive */ + wait_read_slots(recv_slots); + + /* fetch whole slots first */ + while (i < ALIGN_DOWN(recv_len, 4)) { + *p++ = read_slot(); + i += SLOT_SIZE; + } + + reminder = recv_len % SLOT_SIZE; + + if (reminder) { + reg = read_slot(); + memcpy(p, &reg, reminder); + } + + return recv_len; +} + +int heci_receive(void *buff, uint32_t *maxlen) +{ + union mei_header hdr; + uint32_t left, received; + uint8_t *p = (uint8_t *)buff; + + if (!buff || !maxlen || !*maxlen) + return 0; + + left = *maxlen; + + clear_int(); + + if (!wait_heci_ready()) { + printk(BIOS_ERR, "HECI: not ready\n"); + return 0; + } + + /* + * Receive multiple packets until we meet one marked complete or we run + * or we run out of space. + */ + do { + received = recv_one_message(&hdr, p, left); + left -= received; + p += received; + /* if read out all, ping to send more */ + if (!hdr.fields.is_complete && !me_filled_slots()) + host_gen_interrupt(); + } while (received && !hdr.fields.is_complete && left > 0); + + *maxlen = p - (uint8_t*) buff; + + /* if ME is not ready, something went wrong and we received junk */ + if (!me_ready()) + return 0; + + return hdr.fields.is_complete; +} + +#if ENV_RAMSTAGE + +static void update_sec_bar(struct device *dev) +{ + g_txe.sec_bar = find_resource(dev, PCI_BASE_ADDRESS_0)->base; +} + +static void txe_set_resources(struct device *dev) +{ + if (dev->path.pci.devfn == HECI1_DEVFN) + update_sec_bar(dev); + + pci_dev_set_resources(dev); +} + +static struct device_operations txe_ops = { + .set_resources = txe_set_resources, + .read_resources = pci_dev_read_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .enable_resources = pci_dev_enable_resources +}; + +static const struct pci_driver txe_driver __pci_driver = { + .ops = &txe_ops, + .vendor = PCI_VENDOR_ID_INTEL, + /* expectation is that soc/chipset code provides this */ + .device = PCI_DEVICE_ID_HECI1 +}; + +#endif diff --git a/src/drivers/intel/txe/txe.h b/src/drivers/intel/txe/txe.h new file mode 100644 index 0000000..b837dbf --- /dev/null +++ b/src/drivers/intel/txe/txe.h @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_INTEL_TXE_H_ +#define _DRIVERS_INTEL_TXE_H_ + +#define MMIO_ME_CB_RW 0x08 +#define MMIO_ME_CSR 0x0c + +#define MMIO_ME_CB_WW 0x00 +#define MMIO_HOST_CSR 0x04 + +union mei_header { + u32 data; + struct { + u32 client_address: 8; + u32 host_address: 8; + u32 length: 9; + u32 reserved: 6; + u32 is_complete: 1; + } __attribute__ ((packed)) fields; +}; + +union me_csr { + u32 data; + struct { + u32 int_en: 1; + u32 int_sts: 1; + u32 int_gen: 1; + u32 host_ready: 1; + u32 host_reset: 1; + u32 rsv: 3; + u32 me_read_offset: 8; + u32 me_write_offset: 8; + u32 me_cir_buff: 8; + } __attribute__ ((packed)) fields; +}; + +/* set up device for use in early boot enviroument with temp bar */ +void heci_init(uintptr_t bar); +/* receive not less than maxlen into buff, returns 0 on failure */ +int heci_receive(void *buff, uint32_t *maxlen); +/* send message of size len, returns 0 on failure */ +int heci_send(void *msg, uint32_t len, uint8_t host, uint8_t client); +#endif // _DRIVERS_INTEL_TXE_H_

1 0

Patch set updated for coreboot: src/vboot: add valid license headers to all files
by Martin Roth 02 Mar '17

02 Mar '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18407 -gerrit commit 00b7de41b0034638040e7a9d9f986937e64b6741 Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 18:06:16 2017 -0800 src/vboot: add valid license headers to all files Change-Id: I77d7d6048fee9b378aa04c1a62b830e08f95ec22 Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/vboot/secdata_mock.c | 16 ++++++++++++++-- src/vboot/secdata_tpm.c | 16 ++++++++++++++-- 2 files changed, 28 insertions(+), 4 deletions(-) diff --git a/src/vboot/secdata_mock.c b/src/vboot/secdata_mock.c index 31fa598..70454db 100644 --- a/src/vboot/secdata_mock.c +++ b/src/vboot/secdata_mock.c @@ -1,7 +1,19 @@ /* Copyright (c) 2015 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.. + */ + +/* * Functions for querying, manipulating and locking rollback indices * stored in the TPM NVRAM. */ diff --git a/src/vboot/secdata_tpm.c b/src/vboot/secdata_tpm.c index 4c1e128..0fdee85 100644 --- a/src/vboot/secdata_tpm.c +++ b/src/vboot/secdata_tpm.c @@ -1,7 +1,19 @@ /* Copyright (c) 2013 The Chromium OS Authors. All rights reserved. - * Use of this source code is governed by a BSD-style license that can be - * found in the LICENSE file. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.. + */ + +/* * Functions for querying, manipulating and locking rollback indices * stored in the TPM NVRAM. */

1 0

Patch set updated for coreboot: soc/intel/common/block: Add cache as ram common code
by Subrata Banik 02 Mar '17

02 Mar '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18381 -gerrit commit 609fa5c019efc3e4ff8effce76c851301293d552 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Wed Feb 22 16:39:53 2017 +0530 soc/intel/common/block: Add cache as ram common code Create sample model for common cache as ram programming. TEST=Booted till post code 0x2a and ensure to have CAR done by reading MSR. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 21 -- src/soc/intel/common/block/cpu/Kconfig | 47 +++ src/soc/intel/common/block/cpu/Makefile.inc | 2 + src/soc/intel/common/block/cpu/car/cache_as_ram.S | 177 ++++++++++++ src/soc/intel/common/block/cpu/car/car_big_core.S | 161 +++++++++++ .../intel/common/block/cpu/car/car_small_core.S | 103 +++++++ src/soc/intel/glk/Kconfig | 1 + src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 1 - src/soc/intel/skylake/bootblock/cache_as_ram.S | 320 --------------------- 10 files changed, 492 insertions(+), 342 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b37cde6..c8d7e7a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -251,27 +251,6 @@ config NHLT_DA7219 default n help Include DSP firmware settings for headset codec. -choice - prompt "Cache-as-ram implementation" - default CAR_CQOS - help - This option allows you to select how cache-as-ram (CAR) is set up. - -config CAR_NEM - bool "Non-evict mode" - help - Traditionally, CAR is set up by using Non-Evict mode. This method - does not allow CAR and cache to co-exist, because cache fills are - block in NEM mode. - -config CAR_CQOS - bool "Cache Quality of Service" - help - Cache Quality of Service allows more fine-grained control of cache - usage. As result, it is possible to set up portion of L2 cache for - CAR and use remainder for actual caching. - -endchoice config SPI_FLASH_INCLUDE_ALL_DRIVERS bool diff --git a/src/soc/intel/common/block/cpu/Kconfig b/src/soc/intel/common/block/cpu/Kconfig new file mode 100644 index 0000000..8e9cd66 --- /dev/null +++ b/src/soc/intel/common/block/cpu/Kconfig @@ -0,0 +1,47 @@ +config SOC_INTEL_COMMON_CAR + bool + depends on !FSP_CAR + default CAR_CQOS if (!SOC_INTEL_CAR_BIG_CORE) + default CAR_NEM_ENHANCED if (!SOC_INTEL_CAR_SMALL_CORE) + help + This option allows you to select how cache-as-ram (CAR) is set up. + +config CAR_NEM + bool + default y + help + Traditionally, CAR is set up by using Non-Evict mode. This method + does not allow CAR and cache to co-exist, because cache fills are + block in NEM mode. + +config CAR_CQOS + bool + default y + help + Cache Quality of Service allows more fine-grained control of cache + usage. As result, it is possible to set up portion of L2 cache for + CAR and use remainder for actual caching. + +config CAR_NEM_ENHANCED + bool + default y + help + Current limitation NEM mode is that code and data size is derive + from the need not to spill out any modified line: as in NEM mode + there is no memory behind, the modified data will be lost and NEM + results will be inconsistent, hence NEM ENHANCED mode ensure to + have, some “magic” way to guarantee that modified data is always + kept in cache while clean data is replaced. + +config SOC_INTEL_CAR_SMALL_CORE + bool + default n + help + Intel Processor CAR support on small core + +config SOC_INTEL_CAR_BIG_CORE + bool + default n + help + Intel Processor CAR support on big core + diff --git a/src/soc/intel/common/block/cpu/Makefile.inc b/src/soc/intel/common/block/cpu/Makefile.inc new file mode 100644 index 0000000..1997641 --- /dev/null +++ b/src/soc/intel/common/block/cpu/Makefile.inc @@ -0,0 +1,2 @@ +bootblock-$(CONFIG_SOC_INTEL_COMMON_CAR) += car/cache_as_ram.S + diff --git a/src/soc/intel/common/block/cpu/car/cache_as_ram.S b/src/soc/intel/common/block/cpu/car/cache_as_ram.S new file mode 100644 index 0000000..6b5a089 --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/cache_as_ram.S @@ -0,0 +1,177 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/post_code.h> +#include <rules.h> +#include <intelblocks/msr.h> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + + post_code(0x20) + + /* + * Use the MTRR default type MSR as a proxy for detecting INIT#. + * Reset the system if any known bits are set in that MSR. That is + * an indication of the CPU not being properly reset. + */ +check_for_clean_reset: + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax + cmp $0, %eax + jz no_reset + /* perform soft reset */ + movw $0xcf9, %dx + movb $0x06, %al + outb %al, %dx + +no_reset: + post_code(0x21) + + /* Clear/disable fixed MTRRs */ + mov $fixed_mtrr_list_size, %ebx + xor %eax, %eax + xor %edx, %edx + +clear_fixed_mtrr: + add $-2, %ebx + movzwl fixed_mtrr_list(%ebx), %ecx + wrmsr + jnz clear_fixed_mtrr + + post_code(0x22) + + /* Figure put how many MTRRs we have, and clear them out */ + mov $MTRR_CAP_MSR, %ecx + rdmsr + movzb %al, %ebx /* Number of variable MTRRs */ + mov $MTRR_PHYS_BASE(0), %ecx + xor %eax, %eax + xor %edx, %edx + +clear_var_mtrr: + wrmsr + inc %ecx + wrmsr + inc %ecx + dec %ebx + jnz clear_var_mtrr + + post_code(0x23) + + /* Configure default memory type to uncacheable (UC) */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + /* Clear enable bits and set default type to UC. */ + and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ + MTRR_DEF_TYPE_FIX_EN), %eax + wrmsr + + /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB + * based on the physical address size supported for this processor + * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] + * + * Examples: + * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing + * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing + */ + + movl $0x80000008, %eax /* Address sizes leaf */ + cpuid + sub $32, %al + movzx %al, %eax + xorl %esi, %esi + bts %eax, %esi + dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ + + post_code(0x24) + + /* Configure CAR region as write-back (WB) */ + mov $MTRR_PHYS_BASE(0), %ecx + mov $CONFIG_DCACHE_RAM_BASE, %eax + or $MTRR_TYPE_WRBACK, %eax + xor %edx,%edx + wrmsr + + /* Configure the MTRR mask for the size region */ + mov $MTRR_PHYS_MASK(0), %ecx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ + dec %eax + not %eax + or $MTRR_PHYS_MASK_VALID, %eax + wrmsr + + post_code(0x25) + + /* Enable variable MTRRs */ + mov $MTRR_DEF_TYPE_MSR, %ecx + rdmsr + or $MTRR_DEF_TYPE_EN, %eax + wrmsr + + /* Enable caching */ + mov %cr0, %eax + and $~(CR0_CD | CR0_NW), %eax + invd + mov %eax, %cr0 + +#if IS_ENABLED(CONFIG_SOC_INTEL_CAR_SMALL_CORE) + #include "car_small_core.S" +#elif IS_ENABLED(CONFIG_SOC_INTEL_CAR_BIG_CORE) + #include "car_big_core.S" +#endif + +car_init_done: + + post_code(0x29) + + /* Setup bootblock stack */ + mov $_car_stack_end, %esp + + /*push TSC value to stack*/ + movd %mm2, %eax + pushl %eax /* tsc[63:32] */ + movd %mm1, %eax + pushl %eax /* tsc[31:0] */ + +before_carstage: + post_code(0x2A) + + call bootblock_c_entry + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +fixed_mtrr_list: + .word MTRR_FIX_64K_00000 + .word MTRR_FIX_16K_80000 + .word MTRR_FIX_16K_A0000 + .word MTRR_FIX_4K_C0000 + .word MTRR_FIX_4K_C8000 + .word MTRR_FIX_4K_D0000 + .word MTRR_FIX_4K_D8000 + .word MTRR_FIX_4K_E0000 + .word MTRR_FIX_4K_E8000 + .word MTRR_FIX_4K_F0000 + .word MTRR_FIX_4K_F8000 +fixed_mtrr_list_size = . - fixed_mtrr_list diff --git a/src/soc/intel/common/block/cpu/car/car_big_core.S b/src/soc/intel/common/block/cpu/car/car_big_core.S new file mode 100644 index 0000000..5dabbb9 --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car_big_core.S @@ -0,0 +1,161 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr + post_code(0x26) + + /* Create n-way set associativity of cache */ + xorl %edi, %edi +find_llc_subleaf: + movl %edi, %ecx + movl $0x04, %eax + cpuid + inc %edi + and $0xe0, %al /* EAX[7:5] = Cache Level */ + cmp $0x60, %al /* Check to see if it is LLC */ + jnz find_llc_subleaf + + /* + * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE + * for 4/8/16 way of LLC + */ + shr $22, %ebx + inc %ebx + /* Calculate n-way associativity of LLC */ + mov %bl, %cl + + /* + * Maximizing RO cacheability while locking in the CAR to a + * single way since that particular way won't be victim candidate + * for evictions. + * This has been done after programing LLC_WAY_MASK_1 MSR + * with desired LLC way as mentioned below. + * + * Hence create Code and Data Size as per request + * Code Size (RO) : Up to 16M + * Data Size (RW) : Up to 256K + */ + movl $0x01, %eax + /* + * LLC Ways -> LLC_WAY_MASK_1: + * 4: 0x000E + * 8: 0x00FE + * 12: 0x0FFE + * 16: 0xFFFE + * + * These MSRs contain one bit per each way of LLC + * - If this bit is '0' - the way is protected from eviction + * - If this bit is '1' - the way is not protected from eviction + */ + shl %cl, %eax + subl $0x02, %eax + movl $MSR_IA32_L3_MASK_1, %ecx + xorl %edx, %edx + wrmsr + /* + * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 + * + * For SKL SOC, data size remains 256K consistently. + * Hence, creating 1-way associative cache for Data + */ + mov $MSR_IA32_L3_MASK_2, %ecx + mov $0x01, %eax + xorl %edx, %edx + wrmsr + /* + * Set MSR_IA32_PQR_ASSOC = 0x02 + * + * Possible values: + * 0: Default value, no way mask should be applied + * 1: Apply way mask 1 to LLC + * 2: Apply way mask 2 to LLC + * 3: Shouldn't be use in NEM Mode + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x02, %eax + xorl %edx, %edx + wrmsr + + movl $CONFIG_DCACHE_RAM_BASE, %edi + movl $CONFIG_DCACHE_RAM_SIZE, %ecx + shr $0x02, %ecx + xor %eax, %eax + cld + rep stosl + /* + * Set MSR_IA32_PQR_ASSOC = 0x01 + * At this stage we apply LLC_WAY_MASK_1 to the cache. + * i.e. way 0 is protected from eviction. + */ + movl $MSR_IA32_PQR_ASSOC, %ecx + movl $0x01, %eax + xorl %edx, %edx + wrmsr + + /* + * Enable No-Eviction Mode Run State by setting + * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. + */ + + movl $MSR_EVICT_CTL, %ecx + rdmsr + orl $0x02, %eax + wrmsr + + post_code(0x27) + /* + * Configure the BIOS code region as write-protected (WP) cacheable + * memory type using a single variable range MTRR. + * + * Ensure region to cache meets MTRR requirements for + * size and alignment. + */ + movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */ + movl $CONFIG_ROM_SIZE, %eax /* Code region size */ + cmpl $0, %edi + jz .halt_forever + cmpl $0, %eax + jz .halt_forever + + post_code(0x28) + /* + * Program base register + */ + xorl %edx, %edx /* clear upper dword */ + movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */ + movl %edi, %eax + orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */ + wrmsr + + movl $CONFIG_ROM_SIZE, %eax + + /* + * Compute MTRR mask value: Mask = NOT (Size - 1) + */ + dec %eax /* eax - size to cache less one byte */ + not %eax /* eax contains low 32 bits of mask */ + or $MTRR_PHYS_MASK_VALID, %eax + /* + * Program mask register + */ + movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */ + movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ + wrmsr + diff --git a/src/soc/intel/common/block/cpu/car/car_small_core.S b/src/soc/intel/common/block/cpu/car/car_small_core.S new file mode 100644 index 0000000..2b26f8f --- /dev/null +++ b/src/soc/intel/common/block/cpu/car/car_small_core.S @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#if IS_ENABLED(CONFIG_CAR_NEM) + /* Disable cache eviction (setup stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x1, %eax + wrmsr +#else + /* + * Disable both L1 and L2 prefetcher. For yet-to-understood reason, + * prefetchers slow down filling cache with rep stos in CQOS mode. + */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + or $(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr +#endif + +#if IS_ENABLED(CONFIG_CAR_CQOS) +#if (CONFIG_DCACHE_RAM_SIZE == L2_CACHE_SIZE) +/* + * If CAR size is set to full L2 size, mask is calculated as all-zeros. + * This is not supported by the CPU/uCode. + */ +#error "CQOS CAR may not use whole L2 cache area" +#endif + /* Calculate how many bits to be used for CAR */ + xor %edx, %edx + mov $CONFIG_DCACHE_RAM_SIZE, %eax /* dividend */ + mov $CACHE_QOS_SIZE_PER_BIT, %ecx /* divisor */ + div %ecx /* result is in eax */ + mov %eax, %ecx /* save to ecx */ + mov $1, %ebx + shl %cl, %ebx + sub $1, %ebx /* resulting mask is is in ebx */ + + /* Set this mask for initial cache fill */ + mov $MSR_L2_QOS_MASK(0), %ecx + rdmsr + mov %bl, %al + wrmsr + + /* Set CLOS selector to 0 */ + mov $IA32_PQR_ASSOC, %ecx + rdmsr + and $~IA32_PQR_ASSOC_MASK, %edx /* select mask 0 */ + wrmsr + + /* We will need to block CAR region from evicts */ + mov $MSR_L2_QOS_MASK(1), %ecx + rdmsr + /* Invert bits that are to be used for cache */ + mov %bl, %al + xor $~0, %al /* invert 8 bits */ + wrmsr +#endif + post_code(0x26) + + /* Clear the cache memory region. This will also fill up the cache */ + mov $CONFIG_DCACHE_RAM_BASE, %edi + mov $(CONFIG_DCACHE_RAM_SIZE >> 2), %ecx + xor %eax, %eax + rep stos %eax, %es:(%edi) + + post_code(0x27) + +#if IS_ENABLED(CONFIG_CAR_NEM) + /* Disable cache eviction (run stage) */ + mov $MSR_EVICT_CTL, %ecx + rdmsr + or $0x2, %eax + wrmsr +#else + /* Cache is populated. Use mask 1 that will block evicts */ + mov $IA32_PQR_ASSOC, %ecx + rdmsr + and $~IA32_PQR_ASSOC_MASK, %edx /* clear index bits first */ + or $1, %edx /* select mask 1 */ + wrmsr + + /* Enable prefetchers */ + mov $MSR_PREFETCH_CTL, %ecx + rdmsr + and $~(PREFETCH_L1_DISABLE | PREFETCH_L2_DISABLE), %eax + wrmsr +#endif + + post_code(0x28) diff --git a/src/soc/intel/glk/Kconfig b/src/soc/intel/glk/Kconfig index c08d705..4ce5ddd 100644 --- a/src/soc/intel/glk/Kconfig +++ b/src/soc/intel/glk/Kconfig @@ -47,6 +47,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_RAMSTAGE # Build fails if this is not selected select RTC select SMM_TSEG + select SOC_INTEL_CAR_SMALL_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 67d2213..132fa6d 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -46,6 +46,7 @@ config CPU_SPECIFIC_OPTIONS select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select RTC + select SOC_INTEL_CAR_BIG_CORE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_LPSS_I2C diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 2a6b152..181e17b 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -10,7 +10,6 @@ subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/cpu.c bootblock-y += bootblock/i2c.c bootblock-y += bootblock/pch.c diff --git a/src/soc/intel/skylake/bootblock/cache_as_ram.S b/src/soc/intel/skylake/bootblock/cache_as_ram.S deleted file mode 100644 index 3f8f0f0..0000000 --- a/src/soc/intel/skylake/bootblock/cache_as_ram.S +++ /dev/null @@ -1,320 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015-2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <cpu/x86/cache.h> -#include <cpu/x86/cr.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/post_code.h> -#include <rules.h> - -#define IA32_PQR_ASSOC 0x0c8f -#define IA32_L3_MASK_1 0x0c91 -#define IA32_L3_MASK_2 0x0c92 -#define CACHE_INIT_VALUE 0 -#define MSR_EVICT_CTL 0x2e0 - -.global bootblock_pre_c_entry -bootblock_pre_c_entry: - - post_code(0x20) - - /* - * Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. - */ -check_for_clean_reset: - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - and $(MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN), %eax - cmp $0, %eax - jz no_reset - /* perform soft reset */ - movw $0xcf9, %dx - movb $0x06, %al - outb %al, %dx - -no_reset: - post_code(0x21) - - /* Clear/disable fixed MTRRs */ - mov $fixed_mtrr_list_size, %ebx - xor %eax, %eax - xor %edx, %edx -clear_fixed_mtrr: - add $-2, %ebx - movzwl fixed_mtrr_list(%ebx), %ecx - wrmsr - jnz clear_fixed_mtrr - - post_code(0x22) - - /* Figure put how many MTRRs we have, and clear them out */ - mov $MTRR_CAP_MSR, %ecx - rdmsr - movzb %al, %ebx /* Number of variable MTRRs */ - mov $MTRR_PHYS_BASE(0), %ecx - xor %eax, %eax - xor %edx, %edx - -clear_var_mtrr: - wrmsr - inc %ecx - wrmsr - inc %ecx - dec %ebx - jnz clear_var_mtrr - - post_code(0x23) - - /* Configure default memory type to uncacheable (UC) */ - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - /* Clear enable bits and set default type to UC. */ - and $~(MTRR_DEF_TYPE_MASK | MTRR_DEF_TYPE_EN | \ - MTRR_DEF_TYPE_FIX_EN), %eax - wrmsr - - /* Configure MTRR_PHYS_MASK_HIGH for proper addressing above 4GB - * based on the physical address size supported for this processor - * This is based on read from CPUID EAX = 080000008h, EAX bits [7:0] - * - * Examples: - * MTRR_PHYS_MASK_HIGH = 00000000Fh For 36 bit addressing - * MTRR_PHYS_MASK_HIGH = 0000000FFh For 40 bit addressing - */ - - movl $0x80000008, %eax /* Address sizes leaf */ - cpuid - sub $32, %al - movzx %al, %eax - xorl %esi, %esi - bts %eax, %esi - dec %esi /* esi <- MTRR_PHYS_MASK_HIGH */ - - post_code(0x24) - - /* Configure CAR region as write-back (WB) */ - mov $MTRR_PHYS_BASE(0), %ecx - mov $CONFIG_DCACHE_RAM_BASE, %eax - or $MTRR_TYPE_WRBACK, %eax - xor %edx,%edx - wrmsr - - /* Configure the MTRR mask for the size region */ - mov $MTRR_PHYS_MASK(0), %ecx - mov $CONFIG_DCACHE_RAM_SIZE, %eax /* size mask */ - dec %eax - not %eax - or $MTRR_PHYS_MASK_VALID, %eax - wrmsr - - post_code(0x25) - - /* Enable variable MTRRs */ - mov $MTRR_DEF_TYPE_MSR, %ecx - rdmsr - or $MTRR_DEF_TYPE_EN, %eax - wrmsr - - /* Enable caching */ - mov %cr0, %eax - and $~(CR0_CD | CR0_NW), %eax - invd - mov %eax, %cr0 - - /* Disable cache eviction (setup stage) */ - mov $MSR_EVICT_CTL, %ecx - rdmsr - or $0x1, %eax - wrmsr - post_code(0x26) - - /* Create n-way set associativity of cache */ - xorl %edi, %edi -find_llc_subleaf: - movl %edi, %ecx - movl $0x04, %eax - cpuid - inc %edi - and $0xe0, %al /* EAX[7:5] = Cache Level */ - cmp $0x60, %al /* Check to see if it is LLC */ - jnz find_llc_subleaf - - /* - * Set MSR 0xC91 IA32_L3_MASK_! = 0xE/0xFE/0xFFE/0xFFFE - * for 4/8/16 way of LLC - */ - shr $22, %ebx - inc %ebx - /* Calculate n-way associativity of LLC */ - mov %bl, %cl - - /* - * Maximizing RO cacheability while locking in the CAR to a - * single way since that particular way won't be victim candidate - * for evictions. - * This has been done after programing LLC_WAY_MASK_1 MSR - * with desired LLC way as mentioned below. - * - * Hence create Code and Data Size as per request - * Code Size (RO) : Up to 16M - * Data Size (RW) : Up to 256K - */ - movl $0x01, %eax - /* - * LLC Ways -> LLC_WAY_MASK_1: - * 4: 0x000E - * 8: 0x00FE - * 12: 0x0FFE - * 16: 0xFFFE - * - * These MSRs contain one bit per each way of LLC - * - If this bit is '0' - the way is protected from eviction - * - If this bit is '1' - the way is not protected from eviction - */ - shl %cl, %eax - subl $0x02, %eax - movl $IA32_L3_MASK_1, %ecx - xorl %edx, %edx - wrmsr - /* - * Set MSR 0xC92 IA32_L3_MASK_2 = 0x1 - * - * For SKL SOC, data size remains 256K consistently. - * Hence, creating 1-way associative cache for Data - */ - mov $IA32_L3_MASK_2, %ecx - mov $0x01, %eax - xorl %edx, %edx - wrmsr - /* - * Set IA32_PQR_ASSOC = 0x02 - * - * Possible values: - * 0: Default value, no way mask should be applied - * 1: Apply way mask 1 to LLC - * 2: Apply way mask 2 to LLC - * 3: Shouldn't be use in NEM Mode - */ - movl $IA32_PQR_ASSOC, %ecx - movl $0x02, %eax - xorl %edx, %edx - wrmsr - - movl $CONFIG_DCACHE_RAM_BASE, %edi - movl $CONFIG_DCACHE_RAM_SIZE, %ecx - shr $0x02, %ecx - movl $CACHE_INIT_VALUE, %eax - cld - rep stosl - /* - * Set IA32_PQR_ASSOC = 0x01 - * At this stage we apply LLC_WAY_MASK_1 to the cache. - * i.e. way 0 is protected from eviction. - */ - movl $IA32_PQR_ASSOC, %ecx - movl $0x01, %eax - xorl %edx, %edx - wrmsr - - /* - * Enable No-Eviction Mode Run State by setting - * NO_EVICT_MODE MSR 2E0h bit [1] = '1'. - */ - - movl $MSR_EVICT_CTL, %ecx - rdmsr - orl $0x02, %eax - wrmsr - - post_code(0x27) - /* - * Configure the BIOS code region as write-protected (WP) cacheable - * memory type using a single variable range MTRR. - * - * Ensure region to cache meets MTRR requirements for - * size and alignment. - */ - movl $(0xFFFFFFFF - CONFIG_ROM_SIZE + 1), %edi /* Code region base */ - movl $CONFIG_ROM_SIZE, %eax /* Code region size */ - cmpl $0, %edi - jz .halt_forever - cmpl $0, %eax - jz .halt_forever - - post_code(0x28) - /* - * Program base register - */ - xorl %edx, %edx /* clear upper dword */ - movl $MTRR_PHYS_BASE(1), %ecx /* setup variable mtrr */ - movl %edi, %eax - orl $MTRR_TYPE_WRPROT, %eax /* set type to write protect */ - wrmsr - - movl $CONFIG_ROM_SIZE, %eax - - /* - * Compute MTRR mask value: Mask = NOT (Size - 1) - */ - dec %eax /* eax - size to cache less one byte */ - not %eax /* eax contains low 32 bits of mask */ - or $MTRR_PHYS_MASK_VALID, %eax - /* - * Program mask register - */ - movl $MTRR_PHYS_MASK(1) , %ecx /* setup variable mtrr */ - movl %esi, %edx /* edx <- MTRR_PHYS_MASK_HIGH */ - wrmsr - -car_init_done: - - post_code(0x29) - - /* Setup bootblock stack */ - mov $_car_stack_end, %esp - - /*push TSC value to stack*/ - movd %mm2, %eax - pushl %eax /* tsc[63:32] */ - movd %mm1, %eax - pushl %eax /* tsc[31:0] */ - -before_carstage: - post_code(0x2A) - - call bootblock_c_entry - /* Never reached */ - -.halt_forever: - post_code(POST_DEAD_CODE) - hlt - jmp .halt_forever - -fixed_mtrr_list: - .word MTRR_FIX_64K_00000 - .word MTRR_FIX_16K_80000 - .word MTRR_FIX_16K_A0000 - .word MTRR_FIX_4K_C0000 - .word MTRR_FIX_4K_C8000 - .word MTRR_FIX_4K_D0000 - .word MTRR_FIX_4K_D8000 - .word MTRR_FIX_4K_E0000 - .word MTRR_FIX_4K_E8000 - .word MTRR_FIX_4K_F0000 - .word MTRR_FIX_4K_F8000 -fixed_mtrr_list_size = . - fixed_mtrr_list

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Patch merged into coreboot/master: mainboard/google/poppy: Disable deep S3 on poppy
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit 2eb0837b907de38f7529ebf7f129254c4fd4f437 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Wed Feb 22 16:42:04 2017 -0800 mainboard/google/poppy: Disable deep S3 on poppy BUG=chrome-os-partner:62963 BRANCH=None TEST=Compiles successfully Change-Id: Icb929262fd67362b8e5c5cf31dce04ab1f496695 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/18467 Tested-by: build bot (Jenkins) Reviewed-by: Rajat Jain <rajatja(a)google.com> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/18467 for details. -gerrit

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Patch merged into coreboot/master: nb/i945: Clean "Programming DLL Timings" function
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit 44a3066015ec4576ce5b71be5b3fe06e41680fc9 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Feb 23 13:14:44 2017 +0100 nb/i945: Clean "Programming DLL Timings" function As we drive both channels with the same speed, chan0dll and chan1dll are the same. Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/18472 Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18472 for details. -gerrit

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Patch merged into coreboot/master: agesawrapper: Fix endless loop on bettong
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit b2bb6ad2a72a926796a7eaede06ef8acd556c472 Author: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Date: Tue Dec 20 10:08:45 2016 +0100 agesawrapper: Fix endless loop on bettong AGESA AmdInitEarly() reconfigures the lapic timer in a way that conflicts with lapic/apic_timer. This results in an endless loop when printk() is called after AmdInitEarly() and before the apic_timer is initialized. This patch forces a reconfiguration of the timer after AmdInitEarly() is called. Codepath of the endless loop: printk()-> (...)-> uart_tx_byte-> uart8250_mem_tx_byte-> udelay()-> start = lapic_read(LAPIC_TMCCT); do { value = lapic_read(LAPIC_TMCCT); } while ((start - value) < ticks); [lapic_read returns the same value after AmdInitEarly()] Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)gmail.com> Reviewed-on: https://review.coreboot.org/17924 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17924 for details. -gerrit

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Patch merged into coreboot/master: util/me_cleaner: Pull the latest changes from upstream
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit e38f85915f7681f9e52970682f7c476791eb2301 Author: Nicola Corna <nicola(a)corna.info> Date: Wed Feb 22 10:16:32 2017 +0100 util/me_cleaner: Pull the latest changes from upstream Relevant changes (commit 250b2ec): * Fix a bug for ME6 Ignition images. * Fix signature checking for ME11 and later. * Add command line arguments. * Add an option to relocate the FTPR partition to the top of the ME region, recovering most of the ME region space. * Print the image minimum size. * Add write boundary checks, to prevent writes on other regions in case of bugs. The new changes have been tested on multiple platforms by the me_cleaner users. They have been tested also on the author's X220T with coreboot, where the ME region has been shrinked up to 84 kB without any issue. Change-Id: I3bd6b4cba9f5eebc3cd4892dd9f188744a06c42b Signed-off-by: Nicola Corna <nicola(a)corna.info> Reviewed-on: https://review.coreboot.org/18473 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> See https://review.coreboot.org/18473 for details. -gerrit

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Patch merged into coreboot/master: MAINTAINERS: Add myself as me_cleaner maintainer
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit 4f4fc1891b98a7da249f272a3d094460b5b033e2 Author: Nicola Corna <nicola(a)corna.info> Date: Thu Feb 23 16:53:45 2017 +0100 MAINTAINERS: Add myself as me_cleaner maintainer Change-Id: Ia95f6beb1546efdb75a49bccfe293822f0785d7a Signed-off-by: Nicola Corna <nicola(a)corna.info> Reviewed-on: https://review.coreboot.org/18474 Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/18474 for details. -gerrit

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Patch merged into coreboot/master: .gitignore: Add autoport binary
by gerrit＠coreboot.org 02 Mar '17

02 Mar '17

the following patch was just integrated into master: commit 0cf6748e470e32f552c3483fc88a8479b52d9522 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 27 21:54:18 2017 +0100 .gitignore: Add autoport binary Change-Id: I610797d5002b229211e320a814ce14131cc1dfe7 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/18517 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/18517 for details. -gerrit

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coreboot-gerrit March 2017