coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: amd/northbridge/pi: Move CBMEM_INIT to subdirectories
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18432 -gerrit commit ae3c06f877af03785bb1b33e9cf16e42f2e98863 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Feb 8 08:54:16 2017 -0700 amd/northbridge/pi: Move CBMEM_INIT to subdirectories Split the blanket select for LATE_CBMEM_INIT into individual directories. This allows supporting EARLY as it becomes available in any APU generation. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 017b8fa6e9bb76c55ddc8ca73db683996f6fecee) Change-Id: I144bf34f6f4379eba6a0ae2403bbe97a7df11d8b Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00630F01/Kconfig | 1 + src/northbridge/amd/pi/00660F01/Kconfig | 1 + src/northbridge/amd/pi/00670F00/Kconfig | 1 + src/northbridge/amd/pi/00730F01/Kconfig | 1 + src/northbridge/amd/pi/Kconfig | 1 - 5 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00630F01/Kconfig b/src/northbridge/amd/pi/00630F01/Kconfig index 3669826..0dd2058 100644 --- a/src/northbridge/amd/pi/00630F01/Kconfig +++ b/src/northbridge/amd/pi/00630F01/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00630F01 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00630F01 diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig index fdae80f..dc0d870 100644 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ b/src/northbridge/amd/pi/00660F01/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00660F01 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00660F01 diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index a92658a..c8ce668 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,6 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00670F00 diff --git a/src/northbridge/amd/pi/00730F01/Kconfig b/src/northbridge/amd/pi/00730F01/Kconfig index 47c2323..57d6520 100644 --- a/src/northbridge/amd/pi/00730F01/Kconfig +++ b/src/northbridge/amd/pi/00730F01/Kconfig @@ -15,6 +15,7 @@ ## config NORTHBRIDGE_AMD_PI_00730F01 bool + select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00730F01 diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index f5f36f8..08327b5 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_AMD_PI bool default CPU_AMD_PI - select LATE_CBMEM_INIT if NORTHBRIDGE_AMD_PI

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Patch set updated for coreboot: cpu/amd/pi: Allow stoney to use cbmem in heapmanager
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18431 -gerrit commit ea554971c35406f439fdc583c6b9494bebe05649 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 16:40:22 2017 -0700 cpu/amd/pi: Allow stoney to use cbmem in heapmanager Allocate memory for AGESA's heap from cbmem. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit d1f3191d8213eba431299f3cdcd91dc2ade7ca59) Change-Id: I1eff2fddcec13a53618eeb553bace3b0eca16e95 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/heapmanager.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/cpu/amd/pi/heapmanager.c b/src/cpu/amd/pi/heapmanager.c index 7fc8fb8..efbd9e7 100644 --- a/src/cpu/amd/pi/heapmanager.c +++ b/src/cpu/amd/pi/heapmanager.c @@ -37,7 +37,9 @@ void EmptyHeap(void) memset(BiosManagerPtr, 0, BIOS_HEAP_SIZE); } -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__) +#if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) \ + || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00670F00)) \ + && !defined(__PRE_RAM__) #define AGESA_RUNTIME_SIZE 4096 @@ -83,7 +85,9 @@ AGESA_STATUS agesa_AllocateBuffer (UINT32 Func, UINT32 Data, VOID *ConfigPtr) AllocParams = ((AGESA_BUFFER_PARAMS *) ConfigPtr); AllocParams->BufferPointer = NULL; -#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) && !defined(__PRE_RAM__) +#if (IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) \ + || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00670F00)) \ + && !defined(__PRE_RAM__) /* if the allocation is for runtime use simple CBMEM data */ if (Data == HEAP_CALLOUT_RUNTIME) return alloc_cbmem(AllocParams);

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Patch set updated for coreboot: amd/pi/stoney: Simplify UMA calculations
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18430 -gerrit commit d614d5aafb8b08688cd473c93cfca968e6e202f2 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Jan 17 18:27:18 2017 -0500 amd/pi/stoney: Simplify UMA calculations Use the new top of memory functions to ease the UMA base and size. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 781b329effc5242c05991aea438c3e2c80244b0f) Change-Id: Ic83fa766dc4aa912612f0073b7027bf868d2d989 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/northbridge.c | 43 +++++---------------------- 1 file changed, 7 insertions(+), 36 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index c21d030..69478d6 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -37,6 +37,7 @@ #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include "northbridge.h" +#include "memmap.h" #include <cpu/x86/lapic.h> #include <cpu/amd/mtrr.h> @@ -696,50 +697,17 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void) } #endif -#define ONE_MB_SHIFT 20 -#define ONE_GB_SHIFT 30 - static void setup_uma_memory(void) { #if CONFIG_GFXUMA - uint64_t topmem = bsp_topmem(); - uint64_t topmem2 = bsp_topmem2(); - uint32_t sysmem_mb, sysmem_gb; - - /* refer to UMA_AUTO size computation in Family15h BKDG. */ - /* Please reference MemNGetUmaSizeML() */ - /* - * Total system memory UMASize - * >= 6G 1024M - * >= 4G 512M - * >= 2G 256M - * < 2G 128M - */ - - sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; // Ignore 16MB allocated for C6 when finding UMA size - sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; - sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); - printk(BIOS_SPEW, "%s: system memory size %luGB, topmem2 size %lluMB, topmem size %lluMB\n", - __func__, (unsigned long)sysmem_gb, (topmem2 >> ONE_MB_SHIFT), (topmem >> ONE_MB_SHIFT)); - if (sysmem_gb >= 6) { - uma_memory_size = 1024 << ONE_MB_SHIFT; - } else if (sysmem_gb >= 4) { - uma_memory_size = 512 << ONE_MB_SHIFT; - } else if (sysmem_gb >= 2) { - uma_memory_size = 256 << ONE_MB_SHIFT; - } else { - uma_memory_size = 128 << ONE_MB_SHIFT; - } - uma_memory_base = topmem - uma_memory_size; /* TOP_MEM1 */ + uma_memory_size = uma_size_auto(); + uma_memory_base = uma_base_auto(); printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n", __func__, uma_memory_size, uma_memory_base); - - /* TODO: TOP_MEM2 */ #endif } - static void domain_set_resources(device_t dev) { unsigned long mmio_basek; @@ -751,7 +719,6 @@ static void domain_set_resources(device_t dev) struct hw_mem_hole_info mem_hole; u32 reset_memhole = 1; #endif - pci_tolm = 0xffffffffUL; for (link = dev->link_list; link; link = link->next) { pci_tolm = find_pci_tolm(link); @@ -838,12 +805,16 @@ static void domain_set_resources(device_t dev) ramtop = limitk * 1024; } +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) #if CONFIG_GFXUMA set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); #else set_top_of_ram(ramtop); #endif +#else /* IS_ENABLED(CONFIG_LATE_CBMEM_INIT) */ + uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); +#endif for (link = dev->link_list; link; link = link->next) { if (link->children) {

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Patch set updated for coreboot: amd/pi/stoney: Add memmap file
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18428 -gerrit commit 9583cf001f0f21d9be36ccb7de701d32b78c5e4c Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 8 14:36:46 2017 -0500 amd/pi/stoney: Add memmap file In preparation for supporting EARLY_CBMEM_INIT, add a new file that will contain cbmem_top() and that can be used in all stages. Later patches will also be able to use the support routines. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 4fec9f6754675bbe0c8fbfc031c5c5665dace34b) Change-Id: I8ddaa8359536081752fb8e47e49f4d5958416620 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/Makefile.inc | 3 + src/northbridge/amd/pi/00670F00/memmap.c | 101 +++++++++++++++++++++++++++ src/northbridge/amd/pi/00670F00/memmap.h | 25 +++++++ 3 files changed, 129 insertions(+) diff --git a/src/northbridge/amd/pi/00670F00/Makefile.inc b/src/northbridge/amd/pi/00670F00/Makefile.inc index 7107d84..46617b9 100644 --- a/src/northbridge/amd/pi/00670F00/Makefile.inc +++ b/src/northbridge/amd/pi/00670F00/Makefile.inc @@ -16,3 +16,6 @@ romstage-y += dimmSpd.c ramstage-y += northbridge.c + +romstage-y += memmap.c +ramstage-y += memmap.c \ No newline at end of file diff --git a/src/northbridge/amd/pi/00670F00/memmap.c b/src/northbridge/amd/pi/00670F00/memmap.c new file mode 100644 index 0000000..02bfc13 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/memmap.c @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cbmem.h> +#include <cpu/amd/mtrr.h> +#include "Porting.h" +#include <AMD.h> +#include "amdlib.h" +#include "memmap.h" + +static uint32_t installed_dram(void) +{ + uint64_t topmem, topmem2; + uint32_t sysmem_mb, sysmem_gb; + AMD_CONFIG_PARAMS StdHeader; + + LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader); + LibAmdMsrRead (TOP_MEM2, &topmem2, &StdHeader); + + if (!topmem && !topmem2) + return 0; + + sysmem_mb = (topmem + (16ull << ONE_MB_SHIFT)) >> ONE_MB_SHIFT; + sysmem_mb += topmem2 ? ((topmem2 >> ONE_MB_SHIFT) - 4096) : 0; + sysmem_gb = sysmem_mb >> (ONE_GB_SHIFT - ONE_MB_SHIFT); + + return sysmem_gb; +} + +/* + * Return the size likely assigned to UMA when UMA_AUTO is specified. + * This is the only setting the wrapper currently implements. Refer to the + * BKDG for Family 15h Model 70h-7Fh Procesors (PID #55072) to find the + * following recommended configurations: + * Total system memory UMASize + * 6G+ 1024M + * 4G 512M + * 2G 256M + */ +uint32_t uma_size_auto(void) +{ + uint32_t sysmem_gb = installed_dram(); + + if (sysmem_gb >= 6) + return 1024 << ONE_MB_SHIFT; + if (sysmem_gb >= 4) + return 512 << ONE_MB_SHIFT; + if (sysmem_gb >= 2) + return 256 << ONE_MB_SHIFT; + if (sysmem_gb > 0) + return 128 << ONE_MB_SHIFT; + return 0; +} + +/* + * The BinaryPI image is compiled to always assign UMA below 4GB. It will + * also adjust TOM/TOM2 for the C6 storage, as well as the audio controller. + */ +uint32_t uma_base_auto(void) +{ + uint64_t topmem; + AMD_CONFIG_PARAMS StdHeader; + + LibAmdMsrRead (TOP_MEM, &topmem, &StdHeader); + + if (!topmem) + return 0; + + return (uint32_t)topmem - uma_size_auto(); +} + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +unsigned long get_top_of_ram(void) +{ + AMD_CONFIG_PARAMS StdHeader; + UINT64 MsrReg; + + LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); + return (unsigned long)MsrReg; +} +#endif + +#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +void *cbmem_top(void) +{ + return (void *)uma_base_auto(); +} +#endif diff --git a/src/northbridge/amd/pi/00670F00/memmap.h b/src/northbridge/amd/pi/00670F00/memmap.h new file mode 100644 index 0000000..01fcdc5 --- /dev/null +++ b/src/northbridge/amd/pi/00670F00/memmap.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef NORTHBRIDGE_AMD_MEMMAP_H +#define NORTHBRIDGE_AMD_MEMMAP_H + +#define ONE_MB_SHIFT 20 +#define ONE_GB_SHIFT 30 + +uint32_t uma_base_auto(void); +uint32_t uma_size_auto(void); + +#endif /* NORTHBRIDGE_AMD_MEMMAP_H */

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Patch set updated for coreboot: amd/pi/00670F00: Add generic romstage
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18495 -gerrit commit abb2eb4dc23240a6ba035a8855c8169d534bce14 Author: Marc Jones <marcj303(a)gmail.com> Date: Thu Feb 23 11:39:50 2017 -0700 amd/pi/00670F00: Add generic romstage Move the generic romstage code to the Stoney Ridge cpu. Change-Id: If66ac0e4b3c088f138b9282546ed1ec2d861dd74 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/Makefile.inc | 1 + src/cpu/amd/pi/00670F00/romstage.c | 56 +++++++++++++++++++++++++++++++++++ src/cpu/amd/pi/00670F00/romstage.h | 17 +++++++++++ src/mainboard/amd/gardenia/romstage.c | 36 ++-------------------- 4 files changed, 77 insertions(+), 33 deletions(-) diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc index 6c6a2b8..ae10485 100644 --- a/src/cpu/amd/pi/00670F00/Makefile.inc +++ b/src/cpu/amd/pi/00670F00/Makefile.inc @@ -14,6 +14,7 @@ # romstage-y += fixme.c +romstage-y += romstage.c ramstage-y += fixme.c ramstage-y += chip_name.c ramstage-y += model_15_init.c diff --git a/src/cpu/amd/pi/00670F00/romstage.c b/src/cpu/amd/pi/00670F00/romstage.c new file mode 100644 index 0000000..e305a05 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/romstage.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> +#include <cpu/amd/pi/00670F00/romstage.h> +#include <console/console.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <program_loading.h> + +void cache_as_ram_stage_main(void) +{ + post_code(0x37); + mainboard_romstage_entry(); + + post_code(0x49); + disable_cache_as_ram(); + + post_code(0x50); + run_ramstage(); + post_code(0x54); /* Should never see this post code. */ + die("ERROR - Failed to load ramstage!"); +} + +/* Entry from the mainboard. */ +void romstage_common(void) +{ + post_code(0x38); + AGESAWRAPPER(amdinitreset); + printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); + + post_code(0x39); + AGESAWRAPPER(amdinitearly); + + post_code(0x40); + AGESAWRAPPER(amdinitpost); + + post_code(0x41); + AGESAWRAPPER(amdinitenv); +} diff --git a/src/cpu/amd/pi/00670F00/romstage.h b/src/cpu/amd/pi/00670F00/romstage.h new file mode 100644 index 0000000..79e6863 --- /dev/null +++ b/src/cpu/amd/pi/00670F00/romstage.h @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +void mainboard_romstage_entry(void); +void romstage_common(void); diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 940b51a..22f079e 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -13,39 +13,9 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <arch/acpi.h> -#include <arch/io.h> -#include <arch/stages.h> -#include <cpu/amd/car.h> -#include <cpu/amd/pi/car.h> -#include <northbridge/amd/pi/agesawrapper.h> -#include <northbridge/amd/pi/agesawrapper_call.h> -#include <southbridge/amd/pi/hudson/hudson.h> +#include <cpu/amd/pi/00670F00/romstage.h> -void cache_as_ram_stage_main(void) +void mainboard_romstage_entry(void) { - - // TODO: Move all generic functions to PI generic romstage - post_code(0x37); - AGESAWRAPPER(amdinitreset); - - post_code(0x38); - printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); - - post_code(0x39); - AGESAWRAPPER(amdinitearly); - - post_code(0x40); - AGESAWRAPPER(amdinitpost); - - post_code(0x41); - AGESAWRAPPER(amdinitenv); - - disable_cache_as_ram(); - - post_code(0x50); - copy_and_run(); - - post_code(0x54); /* Should never see this post code. */ + romstage_common(); }

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Patch set updated for coreboot: mainboard/amd/gardenia: Remove S3 support
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18494 -gerrit commit 5b2bfee85e2a5c4bd85c9bb1df1798d500766f0b Author: Marc Jones <marcj303(a)gmail.com> Date: Thu Feb 23 22:06:01 2017 -0700 mainboard/amd/gardenia: Remove S3 support S3 is not yet supported for Stoney Ridge. Remove it until the support is written. Change-Id: I35e6c5f7ad1de7f51b018543d2f7ce82182f11e4 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/mainboard.c | 3 --- src/mainboard/amd/gardenia/romstage.c | 32 +++++++------------------------- 2 files changed, 7 insertions(+), 28 deletions(-) diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index 7ebe087..acc9b7c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -84,9 +84,6 @@ static void gardenia_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 1d2d05b..940b51a 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -19,48 +19,30 @@ #include <arch/stages.h> #include <cpu/amd/car.h> #include <cpu/amd/pi/car.h> -#include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> void cache_as_ram_stage_main(void) { -#if CONFIG_HAVE_ACPI_RESUME - void *resume_backup_memory; -#endif + // TODO: Move all generic functions to PI generic romstage post_code(0x37); AGESAWRAPPER(amdinitreset); + post_code(0x38); printk(BIOS_DEBUG, "Got past agesawrapper_amdinitreset\n"); post_code(0x39); AGESAWRAPPER(amdinitearly); - int s3resume = acpi_is_wakeup_s3(); - if (!s3resume) { - post_code(0x40); - AGESAWRAPPER(amdinitpost); - post_code(0x41); - AGESAWRAPPER(amdinitenv); - /* TODO: Disable cache is not ok. */ - disable_cache_as_ram(); - } else { /* S3 detect */ - printk(BIOS_INFO, "S3 detected\n"); - - post_code(0x60); - AGESAWRAPPER(amdinitresume); - AGESAWRAPPER(amds3laterestore); + post_code(0x40); + AGESAWRAPPER(amdinitpost); - post_code(0x61); - prepare_for_resume(); - } + post_code(0x41); + AGESAWRAPPER(amdinitenv); - if (s3resume || acpi_is_wakeup_s4()) { - outb(0xEE, PM_INDEX); - outb(0x8, PM_DATA); - } + disable_cache_as_ram(); post_code(0x50); copy_and_run();

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Patch set updated for coreboot: amd/pi/mainboards: Consolidate early duplicated code
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18434 -gerrit commit e359b085fbae188a6b116c7ee2e2198bcff4f7dc Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Feb 9 09:15:05 2017 -0700 amd/pi/mainboards: Consolidate early duplicated code Make a common entry function for cache_as_ram_main for use with the PI-based mainboards. The new function drives the typical setup, BIST checking, product reporting, and other common functions. This work takes hints from commit e6af4be. Add a new car.c file that contains the early steps. This has weak functions to hook for southbridge and mainboard setup. Some APUs also get BIST bits masked off. This patch is intended to prepare for an upcoming change that will split the CAR setup from the teardown, so that CAR setup may be used in verstage. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 9d1d92826216dee35f80ec40d722a3e8a587e996) Change-Id: Id10580ecc439df10df26ca99881772f328e7bdd0 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00660F01/fixme.c | 7 ++ src/cpu/amd/pi/00670F00/fixme.c | 7 ++ src/cpu/amd/pi/Makefile.inc | 2 + src/cpu/amd/pi/car.c | 88 +++++++++++++++++++++++ src/cpu/amd/pi/car.h | 30 ++++++++ src/mainboard/amd/bettong/romstage.c | 30 +------- src/mainboard/amd/db-ft3b-lc/Makefile.inc | 1 + src/mainboard/amd/db-ft3b-lc/early_mainboard.c | 31 ++++++++ src/mainboard/amd/db-ft3b-lc/romstage.c | 39 +--------- src/mainboard/amd/gardenia/romstage.c | 29 +------- src/mainboard/amd/lamar/Makefile.inc | 2 + src/mainboard/amd/lamar/early_mainboard.c | 44 ++++++++++++ src/mainboard/amd/lamar/romstage.c | 48 +------------ src/mainboard/amd/olivehillplus/Makefile.inc | 1 + src/mainboard/amd/olivehillplus/early_mainboard.c | 44 ++++++++++++ src/mainboard/amd/olivehillplus/romstage.c | 47 +----------- src/mainboard/bap/ode_e21XX/Makefile.inc | 1 + src/mainboard/bap/ode_e21XX/early_mainboard.c | 37 ++++++++++ src/mainboard/bap/ode_e21XX/romstage.c | 43 +---------- src/mainboard/pcengines/apu2/Makefile.inc | 1 + src/mainboard/pcengines/apu2/early_mainboard.c | 67 +++++++++++++++++ src/mainboard/pcengines/apu2/romstage.c | 74 +------------------ src/southbridge/amd/pi/hudson/early_setup.c | 11 +++ 23 files changed, 388 insertions(+), 296 deletions(-) diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 6770287..973b0a7 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -16,6 +16,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" +#include <cpu/amd/pi/car.h> void amd_initcpuio(void) { @@ -85,3 +86,9 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); } + +unsigned long car_bist_mask_bist(unsigned long bist) +{ + /* Mask bit 31. One result of Silicon Observation */ + return bist & 0x7FFFFFFF; +} diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 86f5acf..5e9ac79 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -16,6 +16,7 @@ #include <cpu/x86/mtrr.h> #include <northbridge/amd/pi/agesawrapper.h> #include "amdlib.h" +#include <cpu/amd/pi/car.h> void amd_initcpuio(void) { @@ -89,3 +90,9 @@ void amd_initmmio(void) 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); } + +unsigned long car_bist_mask_bist(unsigned long bist) +{ + /* Mask bit 31. One result of Silicon Observation */ + return bist & 0x7FFFFFFF; +} diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 0e31d9f..ce60833 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,6 +18,8 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 +romstage-y += car.c + romstage-y += s3_resume.c ramstage-y += s3_resume.c ramstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c new file mode 100644 index 0000000..62c5338 --- /dev/null +++ b/src/cpu/amd/pi/car.c @@ -0,0 +1,88 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/early_variables.h> +#include <console/console.h> +#include <cpu/x86/lapic.h> +#include <cpu/x86/bist.h> +#include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> +#include <northbridge/amd/pi/agesawrapper.h> +#include <timestamp.h> + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + +#if IS_ENABLED(CONFIG_COLLECT_TIMESTAMPS) + /* Initialize timestamp book keeping only once. */ + timestamp_init(timestamp_get()); +#endif + + post_code(0x30); + + /* Must come first to enable PCI MMCONF. */ + amd_initmmio(); + + if (!cpu_init_detectedx && boot_cpu()){ + /* Call into pre-console init code then initialize console. */ + post_code(0x31); + car_sb_pre_console_init(); + + post_code(0x32); + car_mainboard_pre_console_init(); + + post_code(0x33); + console_init(); + } + + /* Halt if there was a built in self test failure */ + post_code(0x34); + report_bist_failure(car_bist_mask_bist(bist)); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + post_code(0x35); + car_sb_post_console_init(); + post_code(0x36); + car_mainboard_post_console_init(); + + cache_as_ram_stage_main(); +} + +unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist) +{ + return bist; +} + +void __attribute__((weak)) car_mainboard_pre_console_init(void) +{ +} + +void __attribute__((weak)) car_sb_pre_console_init(void) +{ +} + +void __attribute__((weak)) car_mainboard_post_console_init(void) +{ +} + +void __attribute__((weak)) car_sb_post_console_init(void) +{ +} diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h new file mode 100644 index 0000000..98da75d --- /dev/null +++ b/src/cpu/amd/pi/car.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef PI_SPLIT_CAR_H +#define PI_SPLIT_CAR_H + +/* Early initialization immediately after CAR setup */ +void cache_as_ram_stage_main(void); + +unsigned long car_bist_mask_bist(unsigned long bist); +void car_mainboard_pre_console_init(void); +void car_sb_pre_console_init(void); + +void car_mainboard_post_console_init(void); +void car_sb_post_console_init(void); + +#endif diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index 6b12afc..c881337 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -17,45 +17,19 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - -#if IS_ENABLED(CONFIG_HUDSON_UART) - configure_hudson_uart(); -#endif - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); diff --git a/src/mainboard/amd/db-ft3b-lc/Makefile.inc b/src/mainboard/amd/db-ft3b-lc/Makefile.inc index 97c761f..01d99ac 100644 --- a/src/mainboard/amd/db-ft3b-lc/Makefile.inc +++ b/src/mainboard/amd/db-ft3b-lc/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/db-ft3b-lc/early_mainboard.c b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c new file mode 100644 index 0000000..7d471eb --- /dev/null +++ b/src/mainboard/amd/db-ft3b-lc/early_mainboard.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 79cc0f9..e67f1fb 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -26,49 +26,14 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index eca9d3b..1d2d05b 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -17,44 +17,19 @@ #include <arch/acpi.h> #include <arch/io.h> #include <arch/stages.h> -#include <cpu/x86/lapic.h> -#include <cpu/x86/bist.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <cpu/amd/pi/s3_resume.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <southbridge/amd/pi/hudson/hudson.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; #if CONFIG_HAVE_ACPI_RESUME void *resume_backup_memory; #endif - amd_initmmio(); - hudson_lpc_port80(); - hudson_lpc_decode(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - -#if IS_ENABLED(CONFIG_HUDSON_UART) - configure_hudson_uart(); -#endif - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist & 0x7FFFFFFF); /* Mask bit 31. One result of Silicon Observation */ - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); diff --git a/src/mainboard/amd/lamar/Makefile.inc b/src/mainboard/amd/lamar/Makefile.inc index 37c1dce..794c6dc 100644 --- a/src/mainboard/amd/lamar/Makefile.inc +++ b/src/mainboard/amd/lamar/Makefile.inc @@ -13,6 +13,8 @@ # GNU General Public License for more details. # +romstage-y += early_mainboard.c + romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/amd/lamar/early_mainboard.c b/src/mainboard/amd/lamar/early_mainboard.c new file mode 100644 index 0000000..65aace1 --- /dev/null +++ b/src/mainboard/amd/lamar/early_mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> +#include <southbridge/amd/common/amd_defs.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include "superio/fintek/f81216h/f81216h.h" + +#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) + + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + outb(0x24, 0xCD6); + outb(0x01, 0xCD7); + *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ + *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ + + f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); +} diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index bda8c0f..9204e90 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -21,11 +21,11 @@ #include <arch/io.h> #include <arch/stages.h> #include <device/pnp_def.h> -#include <arch/cpu.h> #include <cpu/x86/lapic.h> #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> @@ -34,53 +34,9 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> #include "cbmem.h" -#include "superio/fintek/f81216h/f81216h.h" -#define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1) - -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_decode(); - - outb(0x24, 0xCD6); - outb(0x01, 0xCD7); - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ - *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */ - - hudson_lpc_port80(); - - if (!cpu_init_detectedx) { - post_code(0x30); - f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); post_code(0x38); diff --git a/src/mainboard/amd/olivehillplus/Makefile.inc b/src/mainboard/amd/olivehillplus/Makefile.inc index 37c1dce..c1ac631 100644 --- a/src/mainboard/amd/olivehillplus/Makefile.inc +++ b/src/mainboard/amd/olivehillplus/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/amd/olivehillplus/early_mainboard.c b/src/mainboard/amd/olivehillplus/early_mainboard.c new file mode 100644 index 0000000..d394c9a --- /dev/null +++ b/src/mainboard/amd/olivehillplus/early_mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); +} + +void car_mainboard_post_console_init(void) +{ + /* + * This refers to LpcClkDrvSth settling time. Without this setting, processor + * initialization is slow or incorrect, so this wait has been replicated from + * earlier development boards. + */ + { + int i; + for(i = 0; i < 200000; i++) inb(0xCD6); + } +} diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 534a8e5..02fa3d1 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -26,6 +26,7 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> #include <cpu/x86/bist.h> @@ -33,52 +34,8 @@ #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - - /* - * This refers to LpcClkDrvSth settling time. Without this setting, processor - * initialization is slow or incorrect, so this wait has been replicated from - * earlier development boards. - */ - { - int i; - for(i = 0; i < 200000; i++) inb(0xCD6); - } - post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/bap/ode_e21XX/Makefile.inc b/src/mainboard/bap/ode_e21XX/Makefile.inc index b0ce627..f6a27ad 100644 --- a/src/mainboard/bap/ode_e21XX/Makefile.inc +++ b/src/mainboard/bap/ode_e21XX/Makefile.inc @@ -15,6 +15,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/bap/ode_e21XX/early_mainboard.c b/src/mainboard/bap/ode_e21XX/early_mainboard.c new file mode 100644 index 0000000..b7ffbbb --- /dev/null +++ b/src/mainboard/bap/ode_e21XX/early_mainboard.c @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> +#include <superio/fintek/common/fintek.h> +#include <superio/fintek/f81866d/f81866d.h> + +#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 5deeaa8..b82b13f 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -26,53 +26,14 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> #include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -#include <superio/fintek/common/fintek.h> -#include <superio/fintek/f81866d/f81866d.h> - -#define SERIAL_DEV1 PNP_DEV(0x4e, F81866D_SP1) -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* Must come first to enable PCI MMCONF. */ - amd_initmmio(); - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); diff --git a/src/mainboard/pcengines/apu2/Makefile.inc b/src/mainboard/pcengines/apu2/Makefile.inc index 77c6d78..2936f36 100644 --- a/src/mainboard/pcengines/apu2/Makefile.inc +++ b/src/mainboard/pcengines/apu2/Makefile.inc @@ -16,6 +16,7 @@ romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c romstage-y += gpio_ftns.c +romstage-y += early_mainboard.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c diff --git a/src/mainboard/pcengines/apu2/early_mainboard.c b/src/mainboard/pcengines/apu2/early_mainboard.c new file mode 100644 index 0000000..9bd4ba3 --- /dev/null +++ b/src/mainboard/pcengines/apu2/early_mainboard.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 - 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <cpu/amd/pi/car.h> +#include <southbridge/amd/pi/hudson/hudson.h> +#include <northbridge/amd/pi/agesawrapper_call.h> +#include <Fch/Fch.h> +#include "gpio_ftns.h" + +static void early_lpc_init(void) +{ + u32 setting = 0x0; + + // + // Configure output disabled, value low, pull up/down disabled + // + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting); + // + // Configure output enabled, value low, pull up/down disabled + // + setting = 0x1 << GPIO_OUTPUT_ENABLE; + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting); + // + // Configure output enabled, value high, pull up/down disabled + // + setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE; + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting); + configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting); +} + +void car_mainboard_pre_console_init(void) +{ + /* + * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for + * LpcClk[1:0]". This following register setting has been + * replicated in every reference design since Parmer, so it is + * believed to be required even though it is not documented in + * the SoC BKDGs. Without this setting, there is no serial + * output. + */ + outb(0xD2, 0xcd6); + outb(0x00, 0xcd7); + + early_lpc_init(); + + hudson_clk_output_48Mhz(); +} diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index f8ed63c..9dbf06c 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -26,54 +26,13 @@ #include <console/console.h> #include <commonlib/loglevel.h> #include <cpu/amd/car.h> +#include <cpu/amd/pi/car.h> #include <northbridge/amd/pi/agesawrapper.h> #include <northbridge/amd/pi/agesawrapper_call.h> -#include <cpu/x86/bist.h> -#include <cpu/x86/lapic.h> -#include <southbridge/amd/pi/hudson/hudson.h> #include <cpu/amd/pi/s3_resume.h> -#include <Fch/Fch.h> -#include "gpio_ftns.h" - -static void early_lpc_init(void); -void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +void cache_as_ram_stage_main(void) { - u32 val; - - /* - * In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for - * LpcClk[1:0]". This following register setting has been - * replicated in every reference design since Parmer, so it is - * believed to be required even though it is not documented in - * the SoC BKDGs. Without this setting, there is no serial - * output. - */ - outb(0xD2, 0xcd6); - outb(0x00, 0xcd7); - - amd_initmmio(); - - hudson_lpc_port80(); - - if (!cpu_init_detectedx && boot_cpu()) { - post_code(0x30); - early_lpc_init(); - - hudson_clk_output_48Mhz(); - post_code(0x31); - console_init(); - } - - /* Halt if there was a built in self test failure */ - post_code(0x34); - report_bist_failure(bist); - - /* Load MPB */ - val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); - post_code(0x37); AGESAWRAPPER(amdinitreset); @@ -114,32 +73,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x54); /* Should never see this post code. */ } - - -static void early_lpc_init(void) -{ - u32 setting = 0x0; - - // - // Configure output disabled, value low, pull up/down disabled - // - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_32, Function0, GPIO_32, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_49, Function2, GPIO_49, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_50, Function2, GPIO_50, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_71, Function0, GPIO_71, setting); - // - // Configure output enabled, value low, pull up/down disabled - // - setting = 0x1 << GPIO_OUTPUT_ENABLE; - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_57, Function1, GPIO_57, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_58, Function1, GPIO_58, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_59, Function3, GPIO_59, setting); - // - // Configure output enabled, value high, pull up/down disabled - // - setting = 0x1 << GPIO_OUTPUT_ENABLE | 0x1 << GPIO_OUTPUT_VALUE; - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_51, Function2, GPIO_51, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_55, Function3, GPIO_55, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_64, Function2, GPIO_64, setting); - configure_gpio(ACPI_MMIO_BASE, IOMUX_GPIO_68, Function0, GPIO_68, setting); -} diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 553add9..32abaff 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -26,6 +26,7 @@ #include "hudson.h" #include "pci_devs.h" #include <Fch/Fch.h> +#include <cpu/amd/pi/car.h> #if IS_ENABLED(CONFIG_HUDSON_UART) @@ -57,6 +58,16 @@ void configure_hudson_uart(void) #endif +void car_sb_pre_console_init(void) +{ + hudson_lpc_port80(); + hudson_lpc_decode(); + +#if IS_ENABLED(CONFIG_HUDSON_UART) + configure_hudson_uart(); +#endif +} + void hudson_pci_port80(void) { u8 byte;

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Patch set updated for coreboot: amd/pi/hudson: Add alternate method for including amdfw
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18435 -gerrit commit a76bb05986a56bee1dddaed6b590ace3df8b4b64 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Jan 7 18:17:32 2017 -0500 amd/pi/hudson: Add alternate method for including amdfw For systems using Chrome OS, place the amdfw outside of cbfs control. The firmware must go to a fixed position at an offset of 0x20000 into the flash device. Potentially improve by adding a warning or error message for the condition when sizeof(amdfw) + sizeof(cbfs and metadata) > sizeof(flash). Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 2d9d631b39d7850576438a5b0979936bd33893e1) Change-Id: I38029bc03e5db260424cca293b1a7bceea4d0d75 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/Kconfig | 7 +++++++ src/southbridge/amd/pi/hudson/Makefile.inc | 13 +++++++++++++ 2 files changed, 20 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index f6e3355..0afeeec 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -220,3 +220,10 @@ config HUDSON_UART controller 0 registers range from FEDC_6000h to FEDC_6FFFh. UART controller 1 registers range from FEDC_8000h to FEDC_8FFFh. + +config AMDFW_OUTSIDE_CBFS + def_bool n + help + The AMDFW (PSP) is typically locatable in cbfs. Select this + option to manually attach the generated amdfw.rom at an + offset of 0x20000 from the bottom of the coreboot ROM image. diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 24a757c..2153c62 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -264,7 +264,20 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ --flashsize $(CONFIG_ROM_SIZE) \ --output $@ +ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) +PHONY+=add_amdfw +INTERMEDIATE+=add_amdfw + +add_amdfw: $(obj)/coreboot.pre $(obj)/amdfw.rom + printf " DD Adding AMD Firmware\n" + dd if=$(obj)/amdfw.rom \ + of=$(obj)/coreboot.pre conv=notrunc bs=1 seek=131072 >/dev/null 2>&1 + +else # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) + cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom apu/amdfw-position := $(HUDSON_FWM_POSITION) apu/amdfw-type := raw + +endif # ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y)

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Patch set updated for coreboot: amd/pi/hudson/acpi: Only declare S3 if it is supported
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18493 -gerrit commit 588a0d391379584357c52f068e83b82531c298ec Author: Marc Jones <marcj303(a)gmail.com> Date: Wed Feb 22 16:21:49 2017 -0700 amd/pi/hudson/acpi: Only declare S3 if it is supported Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME is set. Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/acpi/sleepstates.asl | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl index 912c0df..d93f068 100644 --- a/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl +++ b/src/southbridge/amd/pi/hudson/acpi/sleepstates.asl @@ -23,9 +23,11 @@ If (LAnd(SSFG, 0x01)) { If (LAnd(SSFG, 0x02)) { Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ } +#if CONFIG_HAVE_ACPI_RESUME If (LAnd(SSFG, 0x04)) { Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ } +#endif If (LAnd(SSFG, 0x08)) { Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ }

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New patch to review for coreboot: nb/intel/i945: Fix PEG port on 945gc
by Arthur Heymans 02 Mar '17

02 Mar '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18549 -gerrit commit 0387e40763288c1d5495b481e73dd8415f949015 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Mar 2 23:51:09 2017 +0100 nb/intel/i945: Fix PEG port on 945gc Vendor bios leaves UPMC1 untouched. Not running PCIEx16 init which is valid for 945gm seems to fix all issues and instabilities related to the PEG port. Change-Id: I6da8aa7714073f4b34df5ae3c1eb4c19e27ddc97 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/early_init.c | 3 ++- src/northbridge/intel/i945/raminit.c | 20 +++++++++++--------- 2 files changed, 13 insertions(+), 10 deletions(-) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 81a6c83..e7b460b 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -935,7 +935,8 @@ void i945_late_initialization(int s3resume) i945_setup_dmi_rcrb(); - i945_setup_pci_express_x16(); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) + i945_setup_pci_express_x16(); i945_setup_root_complex_topology(); diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 8fe5f24..52bb355 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -2524,17 +2524,19 @@ static void sdram_power_management(struct sys_info *sysinfo) reg32 |= (1 << 12) | (1 << 11); MCHBAR32(C1DRC1) = reg32; - if (i945_silicon_revision()>1) { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + if (IS_ENABLED(CONFIG_NORTHBRIDGE_INTEL_SUBTYPE_I945GM)) { + if (i945_silicon_revision()>1) { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0); - MCHBAR16(UPMC1) = 0x1010 | peg_bits; - } else { - /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ - u16 peg_bits = (1 << 5) | (1 << 0); + MCHBAR16(UPMC1) = 0x1010 | peg_bits; + } else { + /* FIXME bits 5 and 0 only if PCIe graphics is disabled */ + u16 peg_bits = (1 << 5) | (1 << 0); - /* Rev 0 and 1 */ - MCHBAR16(UPMC1) = 0x0010 | peg_bits; + /* Rev 0 and 1 */ + MCHBAR16(UPMC1) = 0x0010 | peg_bits; + } } reg16 = MCHBAR16(UPMC2);

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coreboot-gerrit March 2017