coreboot-gerrit March 2017

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Patch set updated for coreboot: soc/intel/apollolake: Add PM methods to power gate SD card
by Venkateswarlu V Vinjamuri 03 Mar '17

03 Mar '17

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18496 -gerrit commit f14aa35a14e770f8cfbc6caa0097dae99b7b02a1 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Fri Feb 24 15:37:30 2017 -0800 soc/intel/apollolake: Add PM methods to power gate SD card This implements GNVS variable to store the address of GPIO_177. _PS0/_PS3 methods to power gate the sd card controller. BUG=chrome-os-partner:63070 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should enter S0ix and resume with no issue. Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 4 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 1 + src/soc/intel/apollolake/acpi/scs.asl | 51 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.h | 3 ++ src/soc/intel/apollolake/include/soc/nvs.h | 3 +- 5 files changed, 61 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 3c1faa5..6aa985d 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -183,6 +183,10 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Assign address of PERST_0 if GPIO is defined in devicetree */ if (cfg->prt0_gpio != GPIO_PRT0_UDEF) gnvs->prt0 = (uintptr_t)gpio_dwx_address(cfg->prt0_gpio); + + /* Assign Gpio address of SDCARD Card detect */ + gnvs->sdcd = (uintptr_t)gpio_dwx_address(cfg->sdcard_cd_gpio); + } /* Save wake source information for calculating ACPI _SWS values */ diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 657c834..947120d 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -39,6 +39,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x19 - 0x20 - NHLT Address NHLL, 32, // 0x21 - 0x24 - NHLT Length PRT0, 32, // 0x25 - 0x28 - PERST_0 Address + SDCD, 32, // 0x29 - 0x2D - SD_CD Address /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/acpi/scs.asl b/src/soc/intel/apollolake/acpi/scs.asl index 4108017..cc157e2 100644 --- a/src/soc/intel/apollolake/acpi/scs.asl +++ b/src/soc/intel/apollolake/acpi/scs.asl @@ -22,6 +22,9 @@ Scope (\_SB.PCI0) { Field (SBMM, DWordAcc, NoLock, Preserve) { GENR, 32, + Offset (0x08), + , 5, /* 5th bit represents Force Card Detect SD Card */ + GRR3, 1, /* GPPRVRW3 used for SD Card detect Bypass. */ } /* SCC power gate control method, this method must be serialized as @@ -64,4 +67,52 @@ Scope (\_SB.PCI0) { ^^SCPG(1,0x00000041) } } /* Device (SDHA) */ + + /* SD CARD */ + Device (SDC) + { + Name (_ADR, 0x001B0000) + + Name (RBUF, ResourceTemplate () + { + GpioInt (Edge, ActiveBoth, SharedAndWake, PullNone, 0, + "\\_SB.GPO3", 0, ResourceConsumer, , ) {26} + }) + + Method (_CRS, 0x0, NotSerialized) + { + Return (RBUF) + } + + OperationRegion (PCCS, PCI_Config, 0x84, 0x04) + Field (PCCS, WordAcc, NoLock, Preserve) { + PMSR, 32 /* 4h: Power Gating Control */ + } + + Method (_PS0, 0, NotSerialized) + { + /* Store DW0 into local1 */ + Store (\_SB.GPC0 (\SDCD), Local1) + /* Extract rxstate [bit 1] of sdcard card detect pin */ + And (Local1, 0x2, Local1) + /* If the sdcard is present, rxstate is low (GPIO_177). + * If sdcard is not present, rxstate is High. + * Write the inverted value of rxstate to GRR3. + */ + Not (Local1, \_SB.PCI0.GRR3) + + /* Disable power gate by clearing bit 1 and 0 */ + And (^PMSR, 0xFFFFFFFC, ^PMSR) + /* Sleep 2 ms */ + Sleep (2) + } + + Method (_PS3, 0, NotSerialized) + { + /* Enable power gate by restore bit 1 and 0 */ + Store (0, \_SB.PCI0.GRR3) + Or (^PMSR, 0x3, ^PMSR) + } + + } /* Device (SDC) */ } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index d60ffbf..22d3b4e 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -117,6 +117,9 @@ struct soc_intel_apollolake_config { /* GPIO pin for PERST_0 */ uint16_t prt0_gpio; + /* GPIO pin for SDCARD Card Detect */ + uint16_t sdcard_cd_gpio; + /* USB2 eye diagram settings per port */ struct usb2_eye_per_port usb2eye[APOLLOLAKE_USB2_PORT_MAX]; diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 21894ca..1e774b8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -39,7 +39,8 @@ typedef struct global_nvs_t { uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t unused[215]; + uint32_t sdcd; /* 0x29 - 0x2D - SD_CD Address */ + uint8_t unused[211]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch set updated for coreboot: amd/pi/hudson: Move APIC enable to CPU file
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18436 -gerrit commit d6e0e0115d51b37579256484952bae41d23df579 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Feb 12 10:31:15 2017 -0700 amd/pi/hudson: Move APIC enable to CPU file Relocate the enabling of the LAPIC out of the southbridge source and surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD systems). The LAPIC is now enabled for all cores; not only the BSP, and not only when the UART is used. This solves the problem of APs not having their APICs enabled when the timer is expected to be functional, e.g. verstage often uses do_printk_va_list() instead of do_printk() which exits early for APs when CONFIG_SQUELCH_EARLY_SMP=y. The changes were tested with two Gardenia builds, one using verstage and another with CONFIG_SQUELCH_EARLY_SMP=n. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad) Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- src/cpu/amd/pi/00630F01/fixme.c | 6 ++++++ src/cpu/amd/pi/00660F01/fixme.c | 6 ++++++ src/cpu/amd/pi/00670F00/fixme.c | 6 ++++++ src/cpu/amd/pi/00730F01/fixme.c | 6 ++++++ src/southbridge/amd/pi/hudson/early_setup.c | 4 ---- 5 files changed, 24 insertions(+), 4 deletions(-) diff --git a/src/cpu/amd/pi/00630F01/fixme.c b/src/cpu/amd/pi/00630F01/fixme.c index fcdc925..3be3690 100644 --- a/src/cpu/amd/pi/00630F01/fixme.c +++ b/src/cpu/amd/pi/00630F01/fixme.c @@ -77,4 +77,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + } } diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c index 6770287..20353a0 100644 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ b/src/cpu/amd/pi/00660F01/fixme.c @@ -84,4 +84,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + } } diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 86f5acf..e7d7ba5 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -88,4 +88,10 @@ void amd_initmmio(void) MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ 0x800ull; LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); + + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + } } diff --git a/src/cpu/amd/pi/00730F01/fixme.c b/src/cpu/amd/pi/00730F01/fixme.c index fcdf498..674e5c1 100644 --- a/src/cpu/amd/pi/00730F01/fixme.c +++ b/src/cpu/amd/pi/00730F01/fixme.c @@ -89,4 +89,10 @@ void amd_initmmio(void) LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + + if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){ + LibAmdMsrRead(0x1B, &MsrReg, &StdHeader); + MsrReg |= 1 << 11; + LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader); + } } diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 8b56d22..1dc490d 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -34,12 +34,8 @@ void configure_hudson_uart(void) { - msr_t msr; u8 byte; - msr = rdmsr(0x1B); - msr.lo |= 1 << 11; - wrmsr(0x1B, msr); byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); byte |= 1 << 3; write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte);

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Patch set updated for coreboot: amd/pi/hudson: Add early SPI setup
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18442 -gerrit commit af62e04b355ae28d87186e8bdd7ffbcc65635897 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Feb 10 16:03:54 2017 -0700 amd/pi/hudson: Add early SPI setup Add some generic functions that can configure the SPI interface to have faster performance. Given that the hudson files are used across many generations of FCHs, make sure to refer to the appropriate BKDG or RRG before using the functions. Notable differences: * Hudson 1 defines read mode in CNTRL0 differently than later gens * Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows setting FastSpeed as well * Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100 controller Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0) Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/early_setup.c | 53 +++++++++++++++++++++++++++++ src/southbridge/amd/pi/hudson/hudson.h | 4 +++ 2 files changed, 57 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 553add9..8b56d22 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -190,4 +190,57 @@ void hudson_clk_output_48Mhz(void) *memptr = data; } +static u32 hudson_spibase(void) +{ + /* Make sure the base address is predictable */ + device_t dev = PCI_DEV(0, 0x14, 3); + + u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) + & 0xfffffff0; + if (!base){ + base = SPI_BASE_ADDRESS; + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base + | SPI_ROM_ENABLE); + /* PCI_COMMAND_MEMORY is read-only and enabled. */ + } + return base; +} + +void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) +{ + u32 base = hudson_spibase(); + write16((void *)base + SPI100_SPEED_CONFIG, + (norm << SPI_NORM_SPEED_NEW_SH) | + (fast << SPI_FAST_SPEED_NEW_SH) | + (alt << SPI_ALT_SPEED_NEW_SH) | + (tpm << SPI_TPM_SPEED_NEW_SH)); + write16((void *)base + SPI100_ENABLE, SPI_USE_SPI100); +} + +void hudson_disable_4dw_burst(void) +{ + u32 base = hudson_spibase(); + write16((void *)base + SPI100_HOST_PREF_CONFIG, + read16((void *)base + SPI100_HOST_PREF_CONFIG) + & ~SPI_RD4DW_EN_HOST); +} + +/* Hudson 1-3 only. For Hudson 1, call with fast=1 */ +void hudson_set_readspeed(u16 norm, u16 fast) +{ + u32 base = hudson_spibase(); + write16((void *)base + SPI_CNTRL1, (read16((void *)base + SPI_CNTRL1) + & ~SPI_CNTRL1_SPEED_MASK) + | (norm << SPI_NORM_SPEED_SH) + | (fast << SPI_FAST_SPEED_SH)); +} + +void hudson_read_mode(u32 mode) +{ + u32 base = hudson_spibase(); + write32((void *)base + SPI_CNTRL0, + (read32((void *)base + SPI_CNTRL0) + & ~SPI_READ_MODE_MASK) | mode); +} + #endif diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index cb0f273..6e3157d 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -148,6 +148,10 @@ void hudson_lpc_port80(void); void hudson_lpc_decode(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); +void hudson_read_mode(u32 mode); +void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm); +void hudson_disable_4dw_burst(void); +void hudson_set_readspeed(u16 norm, u16 fast); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos);

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Patch set updated for coreboot: amd/pi/hudson: Add SPI definitions to header
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18441 -gerrit commit 6762be1d46e79b73591ab0933f95f9dbb81fb5f4 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 17:29:46 2017 -0700 amd/pi/hudson: Add SPI definitions to header Add defines that will be used later for setting the fastest settings in the SPI controller. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c) Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/hudson.h | 38 ++++++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index fc37467..cb0f273 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -86,6 +86,44 @@ #define DECODE_ENABLE_ACPIUC_PORT BIT(30) #define DECODE_ENABLE_ADLIB_PORT BIT(31) +#define SPI_CNTRL0 0x00 +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +/* Nominal is 16.7MHz on older devices, 33MHz on newer */ +#define SPI_READ_MODE_NOM 0x00000000 +#define SPI_READ_MODE_DUAL112 ( BIT(29) ) +#define SPI_READ_MODE_QUAD114 ( BIT(29) | BIT(18)) +#define SPI_READ_MODE_DUAL122 (BIT(30) ) +#define SPI_READ_MODE_QUAD144 (BIT(30) | BIT(18)) +#define SPI_READ_MODE_NORMAL66 (BIT(30) | BIT(29) ) +/* Nominal and SPI_READ_MODE_FAST_HUDSON1 are the only valid choices for H1 */ +#define SPI_READ_MODE_FAST_HUDSON1 ( BIT(18)) +#define SPI_READ_MODE_FAST (BIT(30) | BIT(29) | BIT(18)) +#define SPI_ARB_ENABLE BIT(19) + +#define SPI_CNTRL1 0x0c +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for hudson and bolton */ +#define SPI_CNTRL1_SPEED_MASK (BIT(15) | BIT(14) | BIT(13) | BIT(12)) +#define SPI_NORM_SPEED_SH 12 +#define SPI_FAST_SPEED_SH 8 + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +#define SPI100_SPEED_CONFIG 0x22 +#define SPI_SPEED_66M (0x0) +#define SPI_SPEED_33M ( BIT(0)) +#define SPI_SPEED_22M ( BIT(1) ) +#define SPI_SPEED_16M ( BIT(1) | BIT(0)) +#define SPI_SPEED_100M (BIT(2) ) +#define SPI_SPEED_800K (BIT(2) | BIT(0)) +#define SPI_NORM_SPEED_NEW_SH 12 +#define SPI_FAST_SPEED_NEW_SH 8 +#define SPI_ALT_SPEED_NEW_SH 4 +#define SPI_TPM_SPEED_NEW_SH 0 + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + static inline int hudson_sata_enable(void) { /* True if IDE or AHCI. */

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Patch set updated for coreboot: amd/pi/hudson: Consolidate BITn definitions
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18440 -gerrit commit 88199f0d7189fbcb5da355f5883103e27b2569ca Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 17:22:36 2017 -0700 amd/pi/hudson: Consolidate BITn definitions Remove unused definitions from a .c file and use the BIT(n) macro found in types.h instead. Convert existing definitions to BIT(n). Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c) Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/southbridge/amd/pi/hudson/hudson.h | 65 +++++++++++++++++----------------- src/southbridge/amd/pi/hudson/sm.c | 35 ------------------ 2 files changed, 33 insertions(+), 67 deletions(-) diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 23d9b31..fc37467 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -17,6 +17,7 @@ #ifndef HUDSON_H #define HUDSON_H +#include <types.h> #include <device/pci_ids.h> #include <device/device.h> #include "chip.h" @@ -52,38 +53,38 @@ #define SPI_BASE_ADDRESS 0xFEC10000 #define LPC_IO_PORT_DECODE_ENABLE 0x44 -#define DECODE_ENABLE_PARALLEL_PORT0 (1 << 0) -#define DECODE_ENABLE_PARALLEL_PORT1 (1 << 1) -#define DECODE_ENABLE_PARALLEL_PORT2 (1 << 2) -#define DECODE_ENABLE_PARALLEL_PORT3 (1 << 3) -#define DECODE_ENABLE_PARALLEL_PORT4 (1 << 4) -#define DECODE_ENABLE_PARALLEL_PORT5 (1 << 5) -#define DECODE_ENABLE_SERIAL_PORT0 (1 << 6) -#define DECODE_ENABLE_SERIAL_PORT1 (1 << 7) -#define DECODE_ENABLE_SERIAL_PORT2 (1 << 8) -#define DECODE_ENABLE_SERIAL_PORT3 (1 << 9) -#define DECODE_ENABLE_SERIAL_PORT4 (1 << 10) -#define DECODE_ENABLE_SERIAL_PORT5 (1 << 11) -#define DECODE_ENABLE_SERIAL_PORT6 (1 << 12) -#define DECODE_ENABLE_SERIAL_PORT7 (1 << 13) -#define DECODE_ENABLE_AUDIO_PORT0 (1 << 14) -#define DECODE_ENABLE_AUDIO_PORT1 (1 << 15) -#define DECODE_ENABLE_AUDIO_PORT2 (1 << 16) -#define DECODE_ENABLE_AUDIO_PORT3 (1 << 17) -#define DECODE_ENABLE_MIDI_PORT0 (1 << 18) -#define DECODE_ENABLE_MIDI_PORT1 (1 << 19) -#define DECODE_ENABLE_MIDI_PORT2 (1 << 20) -#define DECODE_ENABLE_MIDI_PORT3 (1 << 21) -#define DECODE_ENABLE_MSS_PORT0 (1 << 22) -#define DECODE_ENABLE_MSS_PORT1 (1 << 23) -#define DECODE_ENABLE_MSS_PORT2 (1 << 24) -#define DECODE_ENABLE_MSS_PORT3 (1 << 25) -#define DECODE_ENABLE_FDC_PORT0 (1 << 26) -#define DECODE_ENABLE_FDC_PORT1 (1 << 27) -#define DECODE_ENABLE_GAME_PORT (1 << 28) -#define DECODE_ENABLE_KBC_PORT (1 << 29) -#define DECODE_ENABLE_ACPIUC_PORT (1 << 30) -#define DECODE_ENABLE_ADLIB_PORT (1 << 31) +#define DECODE_ENABLE_PARALLEL_PORT0 BIT(0) +#define DECODE_ENABLE_PARALLEL_PORT1 BIT(1) +#define DECODE_ENABLE_PARALLEL_PORT2 BIT(2) +#define DECODE_ENABLE_PARALLEL_PORT3 BIT(3) +#define DECODE_ENABLE_PARALLEL_PORT4 BIT(4) +#define DECODE_ENABLE_PARALLEL_PORT5 BIT(5) +#define DECODE_ENABLE_SERIAL_PORT0 BIT(6) +#define DECODE_ENABLE_SERIAL_PORT1 BIT(7) +#define DECODE_ENABLE_SERIAL_PORT2 BIT(8) +#define DECODE_ENABLE_SERIAL_PORT3 BIT(9) +#define DECODE_ENABLE_SERIAL_PORT4 BIT(10) +#define DECODE_ENABLE_SERIAL_PORT5 BIT(11) +#define DECODE_ENABLE_SERIAL_PORT6 BIT(12) +#define DECODE_ENABLE_SERIAL_PORT7 BIT(13) +#define DECODE_ENABLE_AUDIO_PORT0 BIT(14) +#define DECODE_ENABLE_AUDIO_PORT1 BIT(15) +#define DECODE_ENABLE_AUDIO_PORT2 BIT(16) +#define DECODE_ENABLE_AUDIO_PORT3 BIT(17) +#define DECODE_ENABLE_MIDI_PORT0 BIT(18) +#define DECODE_ENABLE_MIDI_PORT1 BIT(19) +#define DECODE_ENABLE_MIDI_PORT2 BIT(20) +#define DECODE_ENABLE_MIDI_PORT3 BIT(21) +#define DECODE_ENABLE_MSS_PORT0 BIT(22) +#define DECODE_ENABLE_MSS_PORT1 BIT(23) +#define DECODE_ENABLE_MSS_PORT2 BIT(24) +#define DECODE_ENABLE_MSS_PORT3 BIT(25) +#define DECODE_ENABLE_FDC_PORT0 BIT(26) +#define DECODE_ENABLE_FDC_PORT1 BIT(27) +#define DECODE_ENABLE_GAME_PORT BIT(28) +#define DECODE_ENABLE_KBC_PORT BIT(29) +#define DECODE_ENABLE_ACPIUC_PORT BIT(30) +#define DECODE_ENABLE_ADLIB_PORT BIT(31) static inline int hudson_sata_enable(void) { diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index 74367a7..db29d10 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -36,41 +36,6 @@ #define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON #endif -#define BIT0 (1 << 0) -#define BIT1 (1 << 1) -#define BIT2 (1 << 2) -#define BIT3 (1 << 3) -#define BIT4 (1 << 4) -#define BIT5 (1 << 5) -#define BIT6 (1 << 6) -#define BIT7 (1 << 7) - -#define BIT8 (1 << 8 ) -#define BIT9 (1 << 9 ) -#define BIT10 (1 << 10) -#define BIT11 (1 << 11) -#define BIT12 (1 << 12) -#define BIT13 (1 << 13) -#define BIT14 (1 << 14) -#define BIT15 (1 << 15) - -#define BIT16 (1 << 16) -#define BIT17 (1 << 17) -#define BIT18 (1 << 18) -#define BIT19 (1 << 19) -#define BIT20 (1 << 20) -#define BIT21 (1 << 21) -#define BIT22 (1 << 22) -#define BIT23 (1 << 23) -#define BIT24 (1 << 24) -#define BIT25 (1 << 25) -#define BIT26 (1 << 26) -#define BIT27 (1 << 27) -#define BIT28 (1 << 28) -#define BIT29 (1 << 29) -#define BIT30 (1 << 30) -#define BIT31 (1 << 31) - /* * HUDSON enables all USB controllers by default in SMBUS Control. * HUDSON enables SATA by default in SMBUS Control.

1 0

Patch set updated for coreboot: amd/gardenia: Add early_mainboard.c file
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18443 -gerrit commit 5a13ffb0fa86d17fb0be4efdf5fb20391492ab58 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Feb 14 17:18:45 2017 -0700 amd/gardenia: Add early_mainboard.c file Add a file that can speed up the SPI interface to match the populated SPI flash. The board uses an MX25U6435F. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit cfda0166302d2c89aa09d95df84b97eb49b1f4fd) Change-Id: Ibbad1391fb128249a58caa9358ecb5e0ca6382aa Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/mainboard/amd/gardenia/Makefile.inc | 3 +++ src/mainboard/amd/gardenia/early_mainboard.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 31 insertions(+) diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index 72cd042..43c5a04 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -19,3 +19,6 @@ romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c + +verstage-y += early_mainboard.c +romstage-y += early_mainboard.c diff --git a/src/mainboard/amd/gardenia/early_mainboard.c b/src/mainboard/amd/gardenia/early_mainboard.c new file mode 100644 index 0000000..e89484b --- /dev/null +++ b/src/mainboard/amd/gardenia/early_mainboard.c @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/pci_def.h> +#include <cpu/x86/msr.h> +#include <cpu/amd/pi/car.h> +#include <southbridge/amd/pi/hudson/hudson.h> + +void car_mainboard_pre_console_init(void) +{ + hudson_set_spi100(SPI_SPEED_33M, + SPI_SPEED_66M, SPI_SPEED_16M, SPI_SPEED_16M); + hudson_disable_4dw_burst(); + hudson_read_mode(SPI_READ_MODE_QUAD114); +}

1 0

Patch set updated for coreboot: amd/pi: Add verstage support
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18439 -gerrit commit 521b309eaa0c8f335ff5f6aa2037cc2cf106de03 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Thu Feb 9 16:19:34 2017 -0700 amd/pi: Add verstage support This patch takes hints from the work in commits 75c51d9 and 909c512. Give PI-based systems the capability of running a SEPARATE_VERSTAGE. This adds * A verstage.c file to that initiates loading romstage (and verification) * A new entry point in car.c that will be used when there is a separate verstage * Makefile flags and verstage-y additions for cpu and southbridge * Besides AMD binary-PI changes, the x86 lapic timer is also now included into verstage This has been tested on Stoney (00670F000) and Gardenia. Although additional APUs' makefiles are modified, none of those platforms are assumed to support verstage at this time. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 15ce30cbd9d20aa0f5a5516e5f3bee7eab069852) Change-Id: Ie43d87908c2d83b42b95b306419156e85993f7bd Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00630F01/Makefile.inc | 1 + src/cpu/amd/pi/00660F01/Makefile.inc | 1 + src/cpu/amd/pi/00670F00/Makefile.inc | 1 + src/cpu/amd/pi/00730F01/Makefile.inc | 1 + src/cpu/amd/pi/Makefile.inc | 4 ++++ src/cpu/amd/pi/car.c | 6 ++++++ src/cpu/amd/pi/car.h | 3 +++ src/cpu/amd/pi/romstage_after_verstage.S | 23 +++++++++++++++++++++++ src/cpu/amd/pi/verstage.c | 23 +++++++++++++++++++++++ src/cpu/x86/lapic/Makefile.inc | 1 + src/southbridge/amd/pi/hudson/Makefile.inc | 3 +++ src/vendorcode/amd/pi/Makefile.inc | 2 ++ 12 files changed, 69 insertions(+) diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 98a7050..9dce0a8 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index 6c6a2b8..acaf1f4 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c ramstage-y += fixme.c ramstage-y += chip_name.c diff --git a/src/cpu/amd/pi/00670F00/Makefile.inc b/src/cpu/amd/pi/00670F00/Makefile.inc index ae10485..601e062 100644 --- a/src/cpu/amd/pi/00670F00/Makefile.inc +++ b/src/cpu/amd/pi/00670F00/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c romstage-y += romstage.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index 9367b45..57cabb3 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -13,6 +13,7 @@ # GNU General Public License for more details. # +verstage-y += fixme.c romstage-y += fixme.c ramstage-y += fixme.c diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index ce60833..972c11d 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -18,7 +18,11 @@ subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 +verstage-y += verstage.c +verstage-y += car.c + romstage-y += car.c +romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += s3_resume.c ramstage-y += s3_resume.c diff --git a/src/cpu/amd/pi/car.c b/src/cpu/amd/pi/car.c index 62c5338..f66f94f 100644 --- a/src/cpu/amd/pi/car.c +++ b/src/cpu/amd/pi/car.c @@ -66,6 +66,12 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) cache_as_ram_stage_main(); } +void romstage_after_verstage(void) +{ + /* This does not return. */ + cache_as_ram_stage_main(); +} + unsigned long __attribute__((weak)) car_bist_mask_bist(unsigned long bist) { return bist; diff --git a/src/cpu/amd/pi/car.h b/src/cpu/amd/pi/car.h index 98da75d..fdf1420 100644 --- a/src/cpu/amd/pi/car.h +++ b/src/cpu/amd/pi/car.h @@ -17,6 +17,9 @@ #ifndef PI_SPLIT_CAR_H #define PI_SPLIT_CAR_H +/* Entry points from the cache-as-ram assembly code */ +void romstage_after_verstage(void); + /* Early initialization immediately after CAR setup */ void cache_as_ram_stage_main(void); diff --git a/src/cpu/amd/pi/romstage_after_verstage.S b/src/cpu/amd/pi/romstage_after_verstage.S new file mode 100644 index 0000000..a89c20a --- /dev/null +++ b/src/cpu/amd/pi/romstage_after_verstage.S @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "gcccar.inc" + +.text +.global car_stage_entry +car_stage_entry: + call romstage_after_verstage + + #include "after_raminit.S" diff --git a/src/cpu/amd/pi/verstage.c b/src/cpu/amd/pi/verstage.c new file mode 100644 index 0000000..c8551dd --- /dev/null +++ b/src/cpu/amd/pi/verstage.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/amd/pi/car.h> +#include <program_loading.h> + +void cache_as_ram_stage_main(void) +{ + run_romstage(); + /* Will not return to here. */ +} diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc index 9df2c5f..58f67b2 100644 --- a/src/cpu/x86/lapic/Makefile.inc +++ b/src/cpu/x86/lapic/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += lapic.c ramstage-y += lapic_cpu_init.c ramstage-y += secondary.S +verstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c bootblock-y += boot_cpu.c diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 2153c62..4bd599b 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -42,8 +42,10 @@ ramstage-y += sd.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-y += reset.c +verstage-y += reset.c romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +verstage-y += early_setup.c romstage-y += early_setup.c ifeq ($(CONFIG_HUDSON_IMC_FWM), y) romstage-y += imc.c @@ -51,6 +53,7 @@ ramstage-y += imc.c endif ifeq ($(CONFIG_HUDSON_UART), y) +verstage-y += uart.c romstage-y += uart.c ramstage-y += uart.c endif diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 2cd18c1..b782540 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -77,6 +77,7 @@ export AGESA_INC := $(AGESA_INC) export AGESA_CFLAGS := $(AGESA_CFLAGS) CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) +CC_verstage := $(CC_verstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) @@ -139,6 +140,7 @@ $(obj)/agesa/libagesa.a: $(call src-to-obj,libagesa,$(agesa_src_files)) @printf " AGESA $(subst $(obj)/,,$(@))\n" ar rcs $@ $+ +verstage-libs += $(obj)/agesa/libagesa.a romstage-libs += $(obj)/agesa/libagesa.a ramstage-libs += $(obj)/agesa/libagesa.a

1 0

Patch set updated for coreboot: cpu/amd/pi: Change wrapper to use config option
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18438 -gerrit commit 173875b4605f339c7290c6492c69f98dd1e3f717 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Wed Jan 25 15:23:47 2017 -0700 cpu/amd/pi: Change wrapper to use config option Add a check for vboot when locating the binaryPI image. There is currently an ordering problem using cbmem to locate the image when vboot is present. Vboot inserts its locator into the search process so that memory can be checked before flash is queried. For the earliest calls using the wrapper, DRAM has not been set up and cbmem not initialized in romstage. This change prevents an endless loop when vboot searches cbmem. This change has another side effect. When vboot is in effect, the change forces the RO binaryPI to be used even when on either of the RW paths. There is currently no ability to relocate the XIP image for use in a RW region. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 6efe9217c38cf93fd9b38e52cf3ec90fee3d0474) Change-Id: I0c14bd729f8a67bca37cbdbd3a5e266c99c86d54 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/agesawrapper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/northbridge/amd/pi/agesawrapper.c b/src/northbridge/amd/pi/agesawrapper.c index 0fe8eab..543aa80 100644 --- a/src/northbridge/amd/pi/agesawrapper.c +++ b/src/northbridge/amd/pi/agesawrapper.c @@ -603,8 +603,14 @@ const void *agesawrapper_locate_module (const CHAR8 name[8]) const AMD_MODULE_HEADER* module; size_t file_size; +#if IS_ENABLED(CONFIG_VBOOT) + /* Use phys. location in flash and prevent vboot from searching cbmem */ + agesa = (void *)CONFIG_AGESA_BINARY_PI_LOCATION; + file_size = 0x100000; +#else agesa = cbfs_boot_map_with_leak((const char *)CONFIG_CBFS_AGESA_NAME, CBFS_TYPE_RAW, &file_size); +#endif if (!agesa) return NULL; image = LibAmdLocateImage(agesa, agesa + file_size - 1, 4096, name);

1 0

Patch set updated for coreboot: cpu/amd/pi: Split CAR setup for use in multiple stages
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18437 -gerrit commit f49aae095d70e8e6141d9d863ba181a1af423d57 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Jan 17 11:57:31 2017 -0500 cpu/amd/pi: Split CAR setup for use in multiple stages This patch uses hints from commit e6af4be to make CAR setup more standalone. These changes will facilitate establishing CAR outside of romstage in an upcoming separate verstage patch. Move CAR teardown to its own file that will always be in romstage, but isn't required in an earlier stage. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit c648d2a0f88ac1161f5d2002f7b947cb8e56b03f) Change-Id: I9fe53ca1fd6b1edd4d5e072849f3962c8bc95df0 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/after_raminit.S | 49 +++++++++++++++++++++++++++++++++++++++++ src/cpu/amd/pi/cache_as_ram.inc | 33 +++++---------------------- 2 files changed, 54 insertions(+), 28 deletions(-) diff --git a/src/cpu/amd/pi/after_raminit.S b/src/cpu/amd/pi/after_raminit.S new file mode 100644 index 0000000..79cf59b --- /dev/null +++ b/src/cpu/amd/pi/after_raminit.S @@ -0,0 +1,49 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/cache.h> + +/* + * This is the common entry point after DRAM has been initialized. + */ +.global disable_cache_as_ram +disable_cache_as_ram: + /* Save return stack */ + movd 0(%esp), %xmm1 + movd %esp, %xmm0 + + /* Disable cache */ + movl %cr0, %eax + orl $CR0_CacheDisable, %eax + movl %eax, %cr0 + + AMD_DISABLE_STACK + + /* enable cache */ + movl %cr0, %eax + andl $0x9fffffff, %eax + movl %eax, %cr0 + xorl %eax, %eax + + /* Restore the return stack */ + wbinvd + movd %xmm0, %esp + movd %xmm1, (%esp) + ret + +cache_as_ram_setup_out: +#ifdef __x86_64__ +.code64 +#endif diff --git a/src/cpu/amd/pi/cache_as_ram.inc b/src/cpu/amd/pi/cache_as_ram.inc index 24db600..0915c23 100644 --- a/src/cpu/amd/pi/cache_as_ram.inc +++ b/src/cpu/amd/pi/cache_as_ram.inc @@ -33,7 +33,7 @@ */ .code32 -.globl cache_as_ram_setup, disable_cache_as_ram, cache_as_ram_setup_out +.globl cache_as_ram_setup cache_as_ram_setup: @@ -136,31 +136,8 @@ cache_as_ram_setup: stop: jmp stop -disable_cache_as_ram: - /* Save return stack */ - movd 0(%esp), %xmm1 - movd %esp, %xmm0 - - /* Disable cache */ - movl %cr0, %eax - orl $CR0_CacheDisable, %eax - movl %eax, %cr0 - - AMD_DISABLE_STACK - - /* enable cache */ - movl %cr0, %eax - andl $0x9fffffff, %eax - movl %eax, %cr0 - xorl %eax, %eax - - /* Restore the return stack */ - wbinvd - movd %xmm0, %esp - movd %xmm1, (%esp) - ret - -cache_as_ram_setup_out: -#ifdef __x86_64__ -.code64 +/* One will never return from cache_as_ram_main() in verstage so there's + * no such thing as after RAM init. */ +#if !ENV_VERSTAGE +#include "after_raminit.S" #endif

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Patch set updated for coreboot: amd/pi/stoney: Change to early cbmem init
by Marshall Dawson 03 Mar '17

03 Mar '17

Marshall Dawson (marshalldawson3rd(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18433 -gerrit commit 9f4d143cad4a2fdf27700bb65fe06cf15c1d92c0 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sun Jan 29 18:27:02 2017 -0700 amd/pi/stoney: Change to early cbmem init Remove the flexibility of using early or late cbmem init. Use early 100% of the time. Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 4c1b4615516dfbd46a768968c2be017cdeb51ee4) Change-Id: Id1c22a15752a07eebf39530ba8549ef1f74265ec Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/romstage.c | 3 +++ src/northbridge/amd/pi/00670F00/Kconfig | 2 +- src/northbridge/amd/pi/00670F00/memmap.c | 13 ------------- src/northbridge/amd/pi/00670F00/northbridge.c | 9 --------- 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/src/cpu/amd/pi/00670F00/romstage.c b/src/cpu/amd/pi/00670F00/romstage.c index e305a05..79fb351 100644 --- a/src/cpu/amd/pi/00670F00/romstage.c +++ b/src/cpu/amd/pi/00670F00/romstage.c @@ -52,5 +52,8 @@ void romstage_common(void) AGESAWRAPPER(amdinitpost); post_code(0x41); + cbmem_initialize_empty(); + + post_code(0x42); AGESAWRAPPER(amdinitenv); } diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index c8ce668..b47a3e6 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -14,7 +14,7 @@ ## config NORTHBRIDGE_AMD_PI_00670F00 bool - select LATE_CBMEM_INIT + select EARLY_CBMEM_INIT if NORTHBRIDGE_AMD_PI_00670F00 diff --git a/src/northbridge/amd/pi/00670F00/memmap.c b/src/northbridge/amd/pi/00670F00/memmap.c index 02bfc13..982ea62 100644 --- a/src/northbridge/amd/pi/00670F00/memmap.c +++ b/src/northbridge/amd/pi/00670F00/memmap.c @@ -82,20 +82,7 @@ uint32_t uma_base_auto(void) return (uint32_t)topmem - uma_size_auto(); } -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) -unsigned long get_top_of_ram(void) -{ - AMD_CONFIG_PARAMS StdHeader; - UINT64 MsrReg; - - LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); - return (unsigned long)MsrReg; -} -#endif - -#if !IS_ENABLED(CONFIG_LATE_CBMEM_INIT) void *cbmem_top(void) { return (void *)uma_base_auto(); } -#endif diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 69478d6..e1b3862 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -805,16 +805,7 @@ static void domain_set_resources(device_t dev) ramtop = limitk * 1024; } -#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) -#if CONFIG_GFXUMA - set_top_of_ram(uma_memory_base); uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#else - set_top_of_ram(ramtop); -#endif -#else /* IS_ENABLED(CONFIG_LATE_CBMEM_INIT) */ - uma_resource(dev, 7, uma_memory_base >> 10, uma_memory_size >> 10); -#endif for (link = dev->link_list; link; link = link->next) { if (link->children) {

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coreboot-gerrit March 2017