New patch to review for coreboot: mainboard/pcengines/apu2: Add LPC TPM support

[Philipp Deppenwiese]

Philipp Deppenwiese ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18523

-gerrit

commit a3e6fb52977658191b955ac137fe7e25512ac110
Author: Philipp Deppenwiese 
Date:   Wed Mar 1 02:37:36 2017 +0100

mainboard/pcengines/apu2: Add LPC TPM support

APU2 exposes a LPC header which can be used
    in cojunction with a LPC TPM module.

Change-Id: If9312370a5071ffbeb6d83888c75fa69a0c27819
    Signed-off-by: Philipp Deppenwiese 
---
 src/mainboard/pcengines/apu2/Kconfig       | 1 +
 src/mainboard/pcengines/apu2/devicetree.cb | 8 +++++++-
 src/mainboard/pcengines/apu2/romstage.c    | 6 ++++++
 3 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig
index 4303b84..cc815df 100644
--- a/src/mainboard/pcengines/apu2/Kconfig
+++ b/src/mainboard/pcengines/apu2/Kconfig
@@ -28,6 +28,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
    select BOARD_ROMSIZE_KB_8192
    select HUDSON_DISABLE_IMC
    select USE_BLOBS
+	select MAINBOARD_HAS_LPC_TPM

config MAINBOARD_DIR
    string
diff --git a/src/mainboard/pcengines/apu2/devicetree.cb b/src/mainboard/pcengines/apu2/devicetree.cb
index 3c5ec81..248b401 100644
--- a/src/mainboard/pcengines/apu2/devicetree.cb
+++ b/src/mainboard/pcengines/apu2/devicetree.cb
@@ -73,7 +73,13 @@ chip northbridge/amd/pi/00730F01/root_complex
    					device pnp 2e.607 off end
    					device pnp 2e.e off end
    				end # SIO NCT5104D
-					end # LPC 0x439d
+					chip drivers/pc80/tpm
+						register "irq_polarity" = "2"
+						device pnp 0c31.0 on
+							irq 0x70 = 10
+						end
+					end
+				end # LPC 0x439d

device pci 14.7 on  end # SD
    			device pci 16.0 on  end # USB EHCI2 usb[8:7] - muxed with XHCI
diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c
index f8ed63c..d89dca2 100644
--- a/src/mainboard/pcengines/apu2/romstage.c
+++ b/src/mainboard/pcengines/apu2/romstage.c
@@ -33,6 +33,8 @@
 #include <southbridge/amd/pi/hudson/hudson.h>
 #include <cpu/amd/pi/s3_resume.h>
 #include <Fch/Fch.h>
+#include <tpm.h>
+
 #include "gpio_ftns.h"

static void early_lpc_init(void);
@@ -106,6 +108,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
    	prepare_for_resume();
    }

+#if CONFIG_LPC_TPM
+		init_tpm(s3resume);
+#endif
+
    outb(0xEA, 0xCD6);
    outb(0x1, 0xcd7);