Change in coreboot[master]: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/18305 )

Change subject: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions
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Patch Set 28:

(2 comments)

Please, why don't you use SPD-Byte 12 for Refresh Rate?

https://review.coreboot.org/#/c/18305/28/src/northbridge/intel/i945/raminit....
File src/northbridge/intel/i945/raminit.c:

PS28, Line 454: 2
sorry, why is there an offset of 1 ?


PS28, Line 564: sysinfo->refresh = 0;
              : 	if (max_tRR == 15625 * 256 / 2) {
              : 		sysinfo->refresh = 1;
why don't you use SPD Byte 12: Refresh Rate?
(JEDEC_DDR2_SPD_Specification_Rev1.3.pdf)


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Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
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