coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/common/block: Add Intel common UART code
by Aamir Bohra (Code Review) 31 Mar '17

31 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/18952 to look at the new patch set (#8). Change subject: soc/intel/common/block: Add Intel common UART code ...................................................................... soc/intel/common/block: Add Intel common UART code Create Intel Common UART driver code. This code does below UART configuration for bootblock phase. * Program BAR * Configure reset register * Configure clock register Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/uart.h A src/soc/intel/common/block/uart/Kconfig A src/soc/intel/common/block/uart/Makefile.inc A src/soc/intel/common/block/uart/uart.c 4 files changed, 65 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/18952/8 -- To view, visit https://review.coreboot.org/18952 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3843fac88cfb7bbb405be50d69f555b274f0d72a Gerrit-PatchSet: 8 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/skylake: Add LPSS function library
by Aamir Bohra (Code Review) 31 Mar '17

31 Mar '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19001 to look at the new patch set (#5). Change subject: soc/intel/skylake: Add LPSS function library ...................................................................... soc/intel/skylake: Add LPSS function library Add LPSS function library and move common register programming under i2c and uart to lpss.c. Clean up serialio.h and move common register and bit definitions to intelblocks/lpss.h. Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/lpss.h A src/soc/intel/common/block/lpss/Kconfig A src/soc/intel/common/block/lpss/Makefile.inc A src/soc/intel/common/block/lpss/lpss.c M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/bootblock/i2c.c M src/soc/intel/skylake/bootblock/uart.c M src/soc/intel/skylake/include/soc/serialio.h 8 files changed, 99 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/19001/5 -- To view, visit https://review.coreboot.org/19001 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I881da01be8191270d9505737f68a6d2d8cd8cc69 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans (Code Review) 31 Mar '17

31 Mar '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 28: (2 comments) > (2 comments) > > Please, why don't you use SPD-Byte 12 for Refresh Rate? That byte gets decoded into tRR. https://review.coreboot.org/#/c/18305/28/src/northbridge/intel/i945/raminit… File src/northbridge/intel/i945/raminit.c: PS28, Line 454: 2 > sorry, why is there an offset of 1 ? That is how ranks gets decoded. PS28, Line 564: sysinfo->refresh = 0; : if (max_tRR == 15625 * 256 / 2) { : sysinfo->refresh = 1; > why don't you use SPD Byte 12: Refresh Rate? I should make a constant for this to make it more clear. that byte is being used here indirectly (decoded). -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 28 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel: Deduplicate vbt header
by coreboot org (Code Review) 31 Mar '17

31 Mar '17

coreboot org has posted comments on this change. ( https://review.coreboot.org/18903 ) Change subject: nb/intel: Deduplicate vbt header ...................................................................... Patch Set 10: Verified+1 Gigabyte GA-G41M-ES2L: Boot and extended test successful.Asus P5GC-MX: Boot and extended test successful. -- To view, visit https://review.coreboot.org/18903 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Reviewer: lava.coreboot.org <lavacoreboot(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions
by coreboot org (Code Review) 31 Mar '17

31 Mar '17

coreboot org has posted comments on this change. ( https://review.coreboot.org/18305 ) Change subject: [UNTESTED]nb/i945/raminit: Use common ddr2 decode functions ...................................................................... Patch Set 28: Verified-1 Gigabyte GA-G41M-ES2L: Boot and extended test successful.Asus P5GC-MX: Test FAILED.Asus P5GC-MX: BOOT_FAILURE -- To view, visit https://review.coreboot.org/18305 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Gerrit-PatchSet: 28 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel: Deduplicate vbt header
by build bot (Jenkins) (Code Review) 31 Mar '17

31 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18903 ) Change subject: nb/intel: Deduplicate vbt header ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50993/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6961/ : SUCCESS -- To view, visit https://review.coreboot.org/18903 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Reviewer: lava.coreboot.org <lavacoreboot(a)gmail.com> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel: Deduplicate vbt header
by Patrick Rudolph (Code Review) 31 Mar '17

31 Mar '17

Hello Aaron Durbin, Paul Menzel, build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18903 to look at the new patch set (#10). Change subject: nb/intel: Deduplicate vbt header ...................................................................... nb/intel: Deduplicate vbt header Move header and delete duplicates. Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/drivers/intel/gma/intel_bios.h R src/drivers/intel/gma/opregion.h M src/drivers/intel/gma/vbt.c M src/northbridge/intel/fsp_sandybridge/acpi.c D src/northbridge/intel/fsp_sandybridge/gma.h M src/northbridge/intel/fsp_sandybridge/northbridge.h M src/northbridge/intel/haswell/acpi.c D src/northbridge/intel/haswell/gma.h M src/northbridge/intel/haswell/haswell.h D src/northbridge/intel/nehalem/gma.h M src/northbridge/intel/nehalem/nehalem.h M src/northbridge/intel/sandybridge/gma.c M src/northbridge/intel/sandybridge/gma.h M src/northbridge/intel/sandybridge/sandybridge.h M src/soc/intel/common/opregion.c M src/soc/intel/common/opregion.h 16 files changed, 10 insertions(+), 606 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/18903/10 -- To view, visit https://review.coreboot.org/18903 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0e1f5d9082626062f95afe718f6ec62a68f0d828 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Reviewer: lava.coreboot.org <lavacoreboot(a)gmail.com>

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Change in coreboot[master]: arch/x86/acpigen: Allow writing buffers larger than 256 bytes
by Duncan Laurie (Code Review) 31 Mar '17

31 Mar '17

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/18966 ) Change subject: arch/x86/acpigen: Allow writing buffers larger than 256 bytes ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/18966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifaf508ae1d5c0eb2629ca112224bfeae1c644e58 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Cleanup code by using common FAST_SPI module
by Subrata Banik (Code Review) 31 Mar '17

31 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19055 ) Change subject: soc/intel/skylake: Cleanup code by using common FAST_SPI module ...................................................................... Patch Set 1: (10 comments) https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/bootblock/cpu… File src/soc/intel/skylake/bootblock/cpu.c: PS1, Line 30: #include <intelblocks/fast_spi.h> alphabetic order? https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/bootblock/pch… File src/soc/intel/skylake/bootblock/pch.c: PS1, Line 57: PCH_DEV_SPI use device_t local there. https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/finalize.c File src/soc/intel/skylake/finalize.c: PS1, Line 33: #include <intelblocks/fast_spi.h> order? PS1, Line 92: fast_spi_set_opcode_menu(); : fast_spi_lock_bar(); why removed comments as well? PS1, Line 160: fast_spi_set_bios_interface_lock_down(); put comments https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/flash_control… File src/soc/intel/skylake/flash_controller.c: PS1, Line 27: #include <intelblocks/fast_spi_def.h> alphabetic order https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/include/soc/p… File src/soc/intel/skylake/include/soc/pch.h: PS1, Line 38: //u32 pch_read_soft_strap(int id); why commented code? https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/pch.c File src/soc/intel/skylake/pch.c: PS1, Line 27: #include <intelblocks/fast_spi.h> alphabetic order PS1, Line 39: /*u32 pch_read_soft_strap(int id) : { : uint32_t fdoc; : void *spibar = get_fast_spi_bar(); : : fdoc = read32(spibar + SPIBAR_FDOC); : fdoc &= ~0x00007ffc; : write32(spibar + SPIBAR_FDOC, fdoc); : : fdoc |= 0x00004000; : fdoc |= id * 4; : write32(spibar + SPIBAR_FDOC, fdoc); : : return read32(spibar + SPIBAR_FDOD); : }*/ commented code? why? https://review.coreboot.org/#/c/19055/1/src/soc/intel/skylake/romstage/roms… File src/soc/intel/skylake/romstage/romstage.c: PS1, Line 41: #include <intelblocks/fast_spi.h> alphabetic order -- To view, visit https://review.coreboot.org/19055 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4fc90504d322db70ed4ea644b1593cc0605b5fe8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 31 Mar '17

31 Mar '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/18669 ) Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/18669/7/src/soc/intel/common/block/pcr/pcr.c File src/soc/intel/common/block/pcr/pcr.c: PS7, Line 23: uintptr_t reg_addr; : : /* Create an address based off of port id and offset. */ : reg_addr = CONFIG_PCR_BASE_ADDRESS; : reg_addr += ((uintptr_t)pid) << PCR_PORTID_SHIFT; : reg_addr += ((uintptr_t)offset & PCR_REG_MASK); : : return (void *)reg_addr; lets move this below and get rid of same purpose function -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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coreboot-gerrit March 2017