the following patch was just integrated into master:
commit 904538bcc153ee889e6ba26dec7dd5d3b8feeef1
Author: Iru Cai <mytbk920423(a)gmail.com>
Date: Wed Jun 8 22:39:22 2016 +0800
inteltool: add --ahci for printing AHCI registers
According to datasheets for Intel ICH/PCH, it works for chipsets from
ICH7 to 9-series PCH, with PCI device address D31:F2.
Change-Id: If1ddd7208108bda949b5a94894a7bf9e8bfe1e5f
Signed-off-by: Iru Cai <mytbk920423(a)gmail.com>
Reviewed-on: https://review.coreboot.org/15106
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/15106 for details.
-gerrit
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16683
-gerrit
commit 1c984ea3321f5778e91643a2218798157a2b972a
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Sep 21 14:08:41 2016 +0200
google/enguarde: Adapt Kconfig symbol
CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS, so follow suit.
Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/mainboard/google/enguarde/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mainboard/google/enguarde/Kconfig b/src/mainboard/google/enguarde/Kconfig
index 9a422c0..ec528a6 100644
--- a/src/mainboard/google/enguarde/Kconfig
+++ b/src/mainboard/google/enguarde/Kconfig
@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM
config CHROMEOS
- select CHROMEOS_VBNV_CMOS
+ select VBOOT_VBNV_CMOS
select LID_SWITCH
select EC_SOFTWARE_SYNC
select VIRTUAL_DEV_SWITCH
the following patch was just integrated into master:
commit 1ba34323010f075e21ed11d9cf2c97e688441676
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Jun 2 17:58:18 2016 -0500
google/enguarde: Upstream Lenovo N21 Chromebook
Migrate google/enguarde (Lenovo N21 Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-enguarde-5216.201.B
commit cf1f57b [Enguarde: Adjust rx delay for norm.]
TEST=built and booted Linux on enguarde with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I3ccda29d1e095d8b1b36766cda913172f72233a7
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/15444
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/15444 for details.
-gerrit
the following patch was just integrated into master:
commit 776498ac7ec537bab2a65101fd9640c1a7679f51
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Tue Sep 13 22:19:58 2016 +0200
southbridge/sis/sis966/aza.c: Improve code formatting
Change-Id: If5342a2b5bae18b70ea671522efd2691bc9872dc
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/16602
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16602 for details.
-gerrit