coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Use fixed resource for SRAM and IPC1
by Lijian Zhao 21 Sep '16

21 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16648 -gerrit commit 106a045e04cc5c9f20ca7ce4dab51d97c2613d4b Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:15:29 2016 -0700 soc/intel/apollolake: Use fixed resource for SRAM and IPC1 Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- 3rdparty/chromeec | 2 +- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/iomap.h | 4 ++ src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/pmc.c | 11 +++++ src/soc/intel/apollolake/pmutil.c | 3 +- src/soc/intel/apollolake/sram.c | 57 ++++++++++++++++++++++++++ 7 files changed, 76 insertions(+), 3 deletions(-) diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 83b6d69..388a7fa 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 83b6d69732f782e2b295153f959ec36d4a56c024 +Subproject commit 388a7fa8cff831dcb5f25a3ea4bd67de898d865a diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3c45cbe..4f867e1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -71,6 +71,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smi.c +ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 2045434..131d131 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -32,6 +32,10 @@ /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 #define PMC_BAR1 0xfe044000 +#define PMC_BAR0_SIZE (8 * KiB) + +#define PMC_SRAM_BASE_0 0xfe900000 +#define PMC_SRAM_SIZE_0 (8 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index cd56fdd..130263b 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -24,6 +24,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ +#define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 20c9492..4544e0d 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -39,6 +39,11 @@ static void read_resources(device_t dev) struct resource *res; pci_dev_read_resources(dev); + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_BAR0; + res->size = PMC_BAR0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = ACPI_PMIO_BASE; res->size = ACPI_PMIO_SIZE; @@ -58,6 +63,12 @@ static void set_resources(device_t dev) pci_dev_set_resources(dev); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " PMC BAR"); + res = find_resource(dev, PCI_BASE_ADDRESS_4); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_IO; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 56bb33d..80aaf71 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -34,8 +34,7 @@ static uintptr_t read_pmc_mmio_bar(void) { - uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0); - return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + return PMC_BAR0; } uintptr_t get_pmc_mmio_bar(void) diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c new file mode 100644 index 0000000..7da3ae4 --- /dev/null +++ b/src/soc/intel/apollolake/sram.c @@ -0,0 +1,57 @@ +#include <device/pci_ids.h> +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <soc/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/iomap.h> + +static void read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_SRAM_BASE_0; + res->size = PMC_SRAM_SIZE_0; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_resources(device_t dev) +{ + struct resource *res; + pci_dev_set_resources(dev); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 0"); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_SRAM, +};

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Patch set updated for coreboot: soc/intel/apollolake: Use fixed resource for SRAM and IPC1
by Lijian Zhao 21 Sep '16

21 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16648 -gerrit commit bdbffbbb8ba4444e8f39aa5f4e2f14c9459e927c Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:15:29 2016 -0700 soc/intel/apollolake: Use fixed resource for SRAM and IPC1 Intel telemetry support will require PMC IPC1 and SRAM devices to be operated in ACPI mode. Then using fixed resources for those two devices will help the resource assignment in DSDT stage. BUG=chrome-os-partner:57364 BRANCH=None TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I8f0983a90728b9148a124ae3443ec29cd7b344ce Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- 3rdparty/chromeec | 2 +- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/iomap.h | 4 ++ src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/pmc.c | 11 +++++ src/soc/intel/apollolake/pmutil.c | 3 +- src/soc/intel/apollolake/sram.c | 57 ++++++++++++++++++++++++++ 7 files changed, 76 insertions(+), 3 deletions(-) diff --git a/3rdparty/chromeec b/3rdparty/chromeec index 83b6d69..388a7fa 160000 --- a/3rdparty/chromeec +++ b/3rdparty/chromeec @@ -1 +1 @@ -Subproject commit 83b6d69732f782e2b295153f959ec36d4a56c024 +Subproject commit 388a7fa8cff831dcb5f25a3ea4bd67de898d865a diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 3c45cbe..4f867e1 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -71,6 +71,7 @@ ramstage-y += pmutil.c ramstage-y += pmc.c ramstage-y += reset.c ramstage-y += smi.c +ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 2045434..131d131 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -32,6 +32,10 @@ /* Accesses to these BARs are hardcoded in FSP */ #define PMC_BAR0 0xfe042000 #define PMC_BAR1 0xfe044000 +#define PMC_BAR0_SIZE (8 * KiB) + +#define PMC_SRAM_BASE_0 0xfe900000 +#define PMC_SRAM_SIZE_0 (8 * KiB) /* Temporary BAR for SPI until PCI enumeration assigns a BAR in ramstage. */ #define PRERAM_SPI_BASE_ADDRESS 0xfe010000 diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index cd56fdd..130263b 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -24,6 +24,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_P2SB 0x5a92 /* 00:0d.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_PMC 0x5a94 /* 00:0d.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ +#define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index c583144..7bbcc47 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -39,6 +39,11 @@ static void read_resources(device_t dev) struct resource *res; pci_dev_read_resources(dev); + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_BAR0; + res->size = PMC_BAR0_SIZE; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + res = new_resource(dev, PCI_BASE_ADDRESS_4); res->base = ACPI_PMIO_BASE; res->size = ACPI_PMIO_SIZE; @@ -58,6 +63,12 @@ static void set_resources(device_t dev) pci_dev_set_resources(dev); + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " PMC BAR"); + res = find_resource(dev, PCI_BASE_ADDRESS_4); pci_write_config32(dev, res->index, res->base); dev->command |= PCI_COMMAND_IO; diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 39edc45..1250d90 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -32,8 +32,7 @@ static uintptr_t read_pmc_mmio_bar(void) { - uint32_t bar = pci_read_config32(PMC_DEV, PCI_BASE_ADDRESS_0); - return bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + return PMC_BAR0; } uintptr_t get_pmc_mmio_bar(void) diff --git a/src/soc/intel/apollolake/sram.c b/src/soc/intel/apollolake/sram.c new file mode 100644 index 0000000..7da3ae4 --- /dev/null +++ b/src/soc/intel/apollolake/sram.c @@ -0,0 +1,57 @@ +#include <device/pci_ids.h> +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <soc/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/iomap.h> + +static void read_resources(device_t dev) +{ + struct resource *res; + pci_dev_read_resources(dev); + + res = new_resource(dev, PCI_BASE_ADDRESS_0); + res->base = PMC_SRAM_BASE_0; + res->size = PMC_SRAM_SIZE_0; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static void set_resources(device_t dev) +{ + struct resource *res; + pci_dev_set_resources(dev); + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_MEMORY; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " SRAM BAR 0"); +} + +static const struct device_operations device_ops = { + .read_resources = read_resources, + .set_resources = set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_SRAM, +};

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Patch set updated for coreboot: buildgcc: Don't try to build gnat with a different version
by Nico Huber 21 Sep '16

21 Sep '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16676 -gerrit commit 3283090e69b0e403a879e7b0205f7b3291cc0ad5 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 13:01:57 2016 +0200 buildgcc: Don't try to build gnat with a different version Change-Id: I64a33d2cc4793e54a50fa439a4461c40d424b569 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- util/crossgcc/buildgcc | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 8a0127e..af1b84f 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -225,6 +225,25 @@ hostcc_version() { printf "%d.%d" "$(hostcc_major)" "$(hostcc_minor)" } +hostcc_has_gnat1() { + [ -x "$(${CC} -print-prog-name=gnat1)" ] +} + +ada_requested() { + echo "${LANGUAGES}" | grep -q '\<ada\>' +} + +check_gnat() { + if hostcc_has_gnat1; then + if [ "$(hostcc_version)" != "$(buildcc_version)" -a "${BOOTSTRAP}" != "1" ]; then + printf "\n${RED}ERROR:${red} Building the Ada compiler (gnat $(buildcc_version)) " + printf "with a different host compiler\n version ($(hostcc_version)) " + printf "requires bootstrapping (-b).${NC}\n\n" + HALT_FOR_TOOLS=1 + fi + fi +} + check_cc() { if is_package_enabled "GCC"; then if [ "$(hostcc_major)" != "$(buildcc_major)" -a "${BOOTSTRAP}" != "1" ]; then @@ -232,6 +251,9 @@ check_cc() { printf "version ($(hostcc_version)).\n" printf " Bootstrapping (-b) is recommended.${NC}\n\n" fi + if ada_requested; then + check_gnat + fi fi }

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Patch set updated for coreboot: cpu/amd/model_fxx: transition away from device_t
by Antonello Dettori 21 Sep '16

21 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16437 -gerrit commit 650c54cb12ae37bca66a92363b974c966b44f057 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 cpu/amd/model_fxx: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/model_fxx. Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/include/cpu/amd/model_fxx_rev.h | 41 +++++++++++++++++++------------------ 2 files changed, 22 insertions(+), 21 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 63c8823..d38c552 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -342,7 +342,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index be961f2..88945a2 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -73,29 +73,29 @@ static inline int is_e0_later_in_bsp(int nodeid) if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; - if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0 - return !is_cpu_pre_e0(); - } - // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; - dev = PCI_DEV(0, 0x18+nodeid,2); - val_old = pci_read_config32(dev, 0x80); - val = val_old; - val |= (1<<3); - pci_write_config32(dev, 0x80, val); - val = pci_read_config32(dev, 0x80); - e0_later = !!(val & (1<<3)); - if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed - pci_write_config32(dev, 0x80, val_old); // restore it - } - - return e0_later; + if (nodeid==0) { // we don't need to do that for node 0 in core0/node0 + return !is_cpu_pre_e0(); + } + // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 + pci_devfn_t dev; + dev = PCI_DEV(0, 0x18+nodeid,2); + val_old = pci_read_config32(dev, 0x80); + val = val_old; + val |= (1<<3); + pci_write_config32(dev, 0x80, val); + val = pci_read_config32(dev, 0x80); + e0_later = !!(val & (1<<3)); + if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed + pci_write_config32(dev, 0x80, val_old); // restore it + } + + return e0_later; } static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 0; dev = PCI_DEV(0, 0x18+nodeid, 3); @@ -105,8 +105,9 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { - uint32_t dword; - device_t dev; + uint32_t dword; + pci_devfn_t dev; + if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; dev = PCI_DEV(0, 0x18+nodeid, 3);

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Patch merged into coreboot/master: buildgcc: Warn when building GCC with a different major version
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit 156d87c024697161333087e155e656efeb070bcc Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 12:59:53 2016 +0200 buildgcc: Warn when building GCC with a different major version GCC build instruction recommend to bootstrap a native compiler first. Not sure, when that is really necessary. A major version change seems reasonable. Change-Id: I80a9ec25739b7d33a1d1c7b4b2140d19d89a99ae Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16675 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16675 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Add functions to test GCC versions
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit aee7f46cd3177e469f008a4a48a7b253cb9b7c2a Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 12:55:19 2016 +0200 buildgcc: Add functions to test GCC versions Just add some helpers that show parts (major, major.minor) of the GCC version to be built (buildcc_*) and of the host compiler (hostcc_*). They will be used in follow-up commits. Change-Id: I37c12ad1a2d08645f40a9f0f0a479c8d7cc3e127 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16674 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16674 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Show excessive arguments and bail out
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit bd74d561adceab2a02629b7439cdb34f18e41c02 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 14:16:43 2016 +0200 buildgcc: Show excessive arguments and bail out Also remove a dead line that checks for unknown options: We already let `getopt` check that. Change-Id: I0e829b266e192757d6e455ee4cc608315bb4b7be Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16681 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16681 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Check exit status of `getopt`
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit 78df0bf46deba1685ba1283e2575f90e62710cd5 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 14:11:53 2016 +0200 buildgcc: Check exit status of `getopt` We accidentally checked the status of `eval` instead. Change-Id: I1ba258944184ed707ed1f176e528d8266656cb59 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16680 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16680 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Fix GNU getopt usage
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit cc414dd47fd227962bded5605d6a277bb7b05939 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 13:59:38 2016 +0200 buildgcc: Fix GNU getopt usage Looks like this never worked correctly: There are three argument formats to GNU getopt and none of them matches what we fed it. The missing double dash before the `set` arguments proves that we always called it with parameters that `getopt` did NOT parse. Change-Id: Ib8343976ef31774b18567a9fc9745a9f58dd287a Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16679 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16679 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Fix option arguments
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit 152e78e79421224c42aa09b875792f8583c3ccb3 Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 15:38:40 2016 +0200 buildgcc: Fix option arguments As we support `getopt` versions that don't know long options, every option arguments needs a short option. Also add the long options `--urls` and `--nocolor` to the `getopt` string. Change-Id: I11c393c3d90c7a16cdda119594221c85f902ed40 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16682 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16682 for details. -gerrit

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coreboot-gerrit September 2016