coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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1340 discussions

Patch merged into coreboot/master: buildgcc: Ask the user to install gnat if it's missing
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit 04a1f6a3bce5d73ad7c43bced4683c0faffc368b Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 13:07:49 2016 +0200 buildgcc: Ask the user to install gnat if it's missing Change-Id: Ib840eac29fc8cedfaef4847fd9700bd4a70300ba Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16677 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16677 for details. -gerrit

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Patch merged into coreboot/master: buildgcc: Don't try to build gnat with a different version
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit 75797166cef66a84f38856f74a671968c6a7cd1f Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 13:01:57 2016 +0200 buildgcc: Don't try to build gnat with a different version Change-Id: I64a33d2cc4793e54a50fa439a4461c40d424b569 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16676 Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/16676 for details. -gerrit

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New patch to review for coreboot: mainboard/nvidia/l1_2pvv: Use tabs for indents
by HAOUAS Elyes 21 Sep '16

21 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16687 -gerrit commit 8ed4d8d72d1306b1c275ad6c55cf78c12f3d73f1 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 21 21:42:08 2016 +0200 mainboard/nvidia/l1_2pvv: Use tabs for indents Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nvidia/l1_2pvv/devicetree.cb | 356 ++++++++++++++--------------- 1 file changed, 178 insertions(+), 178 deletions(-) diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb index 5709db7..53beae9 100644 --- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb +++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb @@ -1,180 +1,180 @@ chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end end

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New patch to review for coreboot: mainboard/lippert: Use tabs for indents
by HAOUAS Elyes 21 Sep '16

21 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16686 -gerrit commit 0a35c3b5d6e3db83a2d9b6c1b47164352429739a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 21 21:14:02 2016 +0200 mainboard/lippert: Use tabs for indents Change-Id: If16d55e4ba0702176dc61524915d215ea46c14ba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lippert/frontrunner/irq_tables.c | 2 +- src/mainboard/lippert/frontrunner/romstage.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lippert/frontrunner/irq_tables.c b/src/mainboard/lippert/frontrunner/irq_tables.c index a8f7e36..25e2dcb 100644 --- a/src/mainboard/lippert/frontrunner/irq_tables.c +++ b/src/mainboard/lippert/frontrunner/irq_tables.c @@ -38,5 +38,5 @@ static const struct irq_routing_table intel_irq_routing_table = { }; unsigned long write_pirq_routing_table(unsigned long addr) { - return copy_pirq_routing_table(addr, &intel_irq_routing_table); + return copy_pirq_routing_table(addr, &intel_irq_routing_table); } diff --git a/src/mainboard/lippert/frontrunner/romstage.c b/src/mainboard/lippert/frontrunner/romstage.c index 15286e6..8120704 100644 --- a/src/mainboard/lippert/frontrunner/romstage.c +++ b/src/mainboard/lippert/frontrunner/romstage.c @@ -102,7 +102,7 @@ void main(unsigned long bist) outb( 0x87, 0x4E); //enter SuperIO configuration mode outb( 0x87, 0x4E); - outb(0x20, 0x4e); + outb(0x20, 0x4e); temp = inb(0x4f); printk(BIOS_DEBUG, "%02x", temp); if (temp != 0x52){

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New patch to review for coreboot: mainboard/lippert/frontrunner-af: Use tabs for indents
by HAOUAS Elyes 21 Sep '16

21 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16685 -gerrit commit e32cd7a26efe8cc17d2f404d58ffd6075c3e317f Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 21 21:07:42 2016 +0200 mainboard/lippert/frontrunner-af: Use tabs for indents Change-Id: Id8b60d32d5bdaaa6c693dcf5db992ed975cc2400 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lippert/frontrunner-af/acpi/usb.asl | 2 +- src/mainboard/lippert/frontrunner-af/dsdt.asl | 32 +++++++++++------------ 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl index 86f7825..0951451 100644 --- a/src/mainboard/lippert/frontrunner-af/acpi/usb.asl +++ b/src/mainboard/lippert/frontrunner-af/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } diff --git a/src/mainboard/lippert/frontrunner-af/dsdt.asl b/src/mainboard/lippert/frontrunner-af/dsdt.asl index 5de4310..1106988 100644 --- a/src/mainboard/lippert/frontrunner-af/dsdt.asl +++ b/src/mainboard/lippert/frontrunner-af/dsdt.asl @@ -1559,8 +1559,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1604,19 +1604,19 @@ DefinitionBlock ( } #endif CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ @@ -1648,7 +1648,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */

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New patch to review for coreboot: mainboard/lippert/toucan-af: Use tabs for indents
by HAOUAS Elyes 21 Sep '16

21 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16684 -gerrit commit 3cd22cab24bbbcb6c9541b82d1b3d45f3773675a Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 21 20:58:19 2016 +0200 mainboard/lippert/toucan-af: Use tabs for indents Change-Id: Ibd1fa89b450d52691dfef5616712f03fd675f123 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/lippert/toucan-af/acpi/usb.asl | 2 +- src/mainboard/lippert/toucan-af/dsdt.asl | 32 ++++++++++++++-------------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/src/mainboard/lippert/toucan-af/acpi/usb.asl b/src/mainboard/lippert/toucan-af/acpi/usb.asl index 86f7825..0951451 100644 --- a/src/mainboard/lippert/toucan-af/acpi/usb.asl +++ b/src/mainboard/lippert/toucan-af/acpi/usb.asl @@ -23,7 +23,7 @@ DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001 */ Method(UCOC, 0) { Sleep(20) - Store(0x13,CMTI) + Store(0x13,CMTI) Store(0,GPSL) } diff --git a/src/mainboard/lippert/toucan-af/dsdt.asl b/src/mainboard/lippert/toucan-af/dsdt.asl index 525a45e..72cb821 100644 --- a/src/mainboard/lippert/toucan-af/dsdt.asl +++ b/src/mainboard/lippert/toucan-af/dsdt.asl @@ -1558,8 +1558,8 @@ DefinitionBlock ( PEBM ) #endif - /* memory space for PCI BARs below 4GB */ - Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) }) /* End Name(_SB.PCI0.CRES) */ Method(_CRS, 0) { @@ -1603,19 +1603,19 @@ DefinitionBlock ( } #endif CreateDWordField(CRES, ^MMIO._BAS, MM1B) - CreateDWordField(CRES, ^MMIO._LEN, MM1L) - /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ - Store(TOM1, MM1B) - ShiftLeft(0x10000000, 4, Local0) - Subtract(Local0, TOM1, Local0) - Store(Local0, MM1L) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) Return(CRES) /* note to change the Name buffer */ } /* end of Method(_SB.PCI0._CRS) */ @@ -1647,7 +1647,7 @@ DefinitionBlock ( /* On older chips, clear PciExpWakeDisEn */ /*if (LLessEqual(\SBRI, 0x13)) { - * Store(0,\PWDE) + * Store(0,\PWDE) * } */ } /* End Method(_SB._INI) */

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Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao 21 Sep '16

21 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649 -gerrit commit b9a8e4136bc64ff26dc81fe48691fdef83470914 Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:48:19 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support A dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 60 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000..182dd42 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 + +Device (IPC1) +{ + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR) + Memory32Fixed (ReadWrite, 0x0,0x4,MDAT) + Memory32Fixed (ReadWrite, 0x0,0x4,MINF) + IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f..11c27ea 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "xhci.asl" +/* PMC IPC */ +#include "pmc_ipc.asl" + /* LPC */ #include "lpc.asl"

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Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao 21 Sep '16

21 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649 -gerrit commit 5925a6880fef22e1fc2d549e6c65faad5d5b1189 Author: Lijian Zhao <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:48:19 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support A dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 60 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000..182dd42 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 + +Device (IPC1) +{ + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR) + Memory32Fixed (ReadWrite, 0x0,0x4,MDAT) + Memory32Fixed (ReadWrite, 0x0,0x4,MINF) + IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f..11c27ea 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "xhci.asl" +/* PMC IPC */ +#include "pmc_ipc.asl" + /* LPC */ #include "lpc.asl"

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao 21 Sep '16

21 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649 -gerrit commit ab492523b5684c06de360fe43c53ec789e4f6b41 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:48:19 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support A dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver. The ACPI mode entry includes resources for PMC_IPC1, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successfully and check with dmesg to see the driver has been loaded successfully without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 60 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000..182dd42 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 + +Device (IPC1) +{ + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR) + Memory32Fixed (ReadWrite, 0x0,0x4,MDAT) + Memory32Fixed (ReadWrite, 0x0,0x4,MINF) + IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f..11c27ea 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "xhci.asl" +/* PMC IPC */ +#include "pmc_ipc.asl" + /* LPC */ #include "lpc.asl"

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add pmc_ipc device support
by Lijian Zhao 21 Sep '16

21 Sep '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649 -gerrit commit ec27f9c50e19e3af1d51a47f6911e623cb517d59 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Tue Sep 6 18:48:19 2016 -0700 soc/intel/apollolake: Add pmc_ipc device support Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and Punit Mailbox. BRANCH=None BUG=chrome-os-partner:57364 TEST=Boot up into OS successully and check with dmesg to see the driver had been loadded success without errors. Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 +++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++ 2 files changed, 60 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl new file mode 100644 index 0000000..182dd42 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl @@ -0,0 +1,57 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/iomap.h> + +#define MAILBOX_DATA 0x7080 +#define MAILBOX_INTF 0x7084 +#define PMIO_LENGTH 0x80 + +Device (IPC1) +{ + Name (_HID, "INT34D2") + Name (_CID, "INT34D2") + Name (_DDN, "Intel(R) IPC1 Controller") + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR) + Memory32Fixed (ReadWrite, 0x0,0x4,MDAT) + Memory32Fixed (ReadWrite, 0x0,0x4,MINF) + IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH, + 0x04, PMIO_LENGTH) + Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR) + Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , ) + { + PMC_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^IBAR._BAS, IBAS) + Store (PMC_BAR0, IBAS) + + CreateDwordField (^RBUF, ^MDAT._BAS, MDBA) + Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA) + CreateDwordField (^RBUF, ^MINF._BAS, MIBA) + Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA) + + CreateDwordField (^RBUF, ^SBAR._BAS, SBAS) + Store (PMC_SRAM_BASE_0, SBAS) + + Return (^RBUF) + } +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f..11c27ea 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -31,6 +31,9 @@ #include "xhci.asl" +/* PMC IPC */ +#include "pmc_ipc.asl" + /* LPC */ #include "lpc.asl"

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coreboot-gerrit September 2016