coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

1 participants
1340 discussions

New patch to review for coreboot: libpayload: mvmap2315: Introduce timer driver
by hakim giydan 22 Sep '16

22 Sep '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16692 -gerrit commit 8810812f6fd61fbaef8a6e51cb73def48f8b683f Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Sep 21 15:50:39 2016 -0700 libpayload: mvmap2315: Introduce timer driver Testing: booted successfully. Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/timer/Kconfig | 13 ++++++++++++ payloads/libpayload/drivers/timer/mvmap2315.c | 30 +++++++++++++++++++++++++++ 3 files changed, 44 insertions(+) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 75f08f2..899c5d2 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -57,6 +57,7 @@ libc-$(CONFIG_LP_TIMER_BG4CD) += timer/bg4cd.c libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c libc-$(CONFIG_LP_TIMER_CYGNUS) += timer/cygnus.c libc-$(CONFIG_LP_TIMER_ARMADA38X) += timer/armada38x.c +libc-$(CONFIG_LP_TIMER_MVMAP2315) += timer/mvmap2315.c # Video console drivers libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 0b981b0..b3ab6ec 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -61,6 +61,9 @@ config TIMER_IMG_PISTACHIO config TIMER_MTK bool "Timer for MediaTek MT8173" +config TIMER_MVMAP2315 + bool "Timer for Marvell MVMAP2315" + endchoice config TIMER_MCT_HZ @@ -108,6 +111,16 @@ config ARMADA38X_TIMER_REG default 0xF1020314 depends on TIMER_ARMADA38X +config MVMAP2315_TIMER_FREQ + int "Hardware timer frequency" + depends on TIMER_MVMAP2315 + default 1000000 + +config MVMAP2315_TIMER_REG + hex "Timer register address" + depends on TIMER_MVMAP2315 + default 0xE1020004 + config IPROC_PERIPH_GLB_TIM_REG_BASE hex "Cygnus timer base address" depends on TIMER_CYGNUS diff --git a/payloads/libpayload/drivers/timer/mvmap2315.c b/payloads/libpayload/drivers/timer/mvmap2315.c new file mode 100644 index 0000000..e288f52 --- /dev/null +++ b/payloads/libpayload/drivers/timer/mvmap2315.c @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <libpayload.h> + +static u32 *reg = (void *)CONFIG_LP_MVMAP2315_TIMER_REG; + +uint64_t timer_hz(void) +{ + return CONFIG_LP_MVMAP2315_TIMER_FREQ; +} + +uint64_t timer_raw_value(void) +{ + /* invert count to change from down to up count */ + return ~readl(reg); +}

1 0

Patch set updated for coreboot: Kconfig: Change symbol override from warning to notice
by Martin Roth 21 Sep '16

21 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16691 -gerrit commit ec722de64c9037c4a9590db12537d50fba29493b Author: Martin Roth <martinroth(a)google.com> Date: Wed Sep 21 14:27:26 2016 -0600 Kconfig: Change symbol override from warning to notice Overriding symbols within a .config is pretty common when doing automated builds with various different options. The warning text makes it sound like this is an issue, so change it to say 'notice' instead. We could get rid of it completely, but it's not a bad thing to know that we have two copies of the same symbol in the .config. BUG=chrome-os-partner:54059 TEST=copy a disabled kconfig option to the end and set it to y. See notice text instead of warning. Change-Id: I9f575b2275233f638e42676263348c807e6515bd Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/kconfig/confdata.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 436d735..453c510 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -42,6 +42,17 @@ static void conf_warning(const char *fmt, ...) conf_warnings++; } +static void conf_notice(const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:notice: ", conf_filename, conf_lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); + conf_warnings++; +} + static void conf_default_message_callback(const char *fmt, va_list ap) { printf("#\n# "); @@ -337,7 +348,7 @@ load: sym->type = S_BOOLEAN; } if (sym->flags & def_flags) { - conf_warning("override: reassigning to symbol %s", sym->name); + conf_notice("override: reassigning to symbol %s", sym->name); } switch (sym->type) { case S_BOOLEAN: @@ -374,7 +385,7 @@ load: sym->type = S_OTHER; } if (sym->flags & def_flags) { - conf_warning("override: reassigning to symbol %s", sym->name); + conf_notice("override: reassigning to symbol %s", sym->name); } if (conf_set_sym_val(sym, def, def_flags, p)) continue; @@ -397,7 +408,7 @@ setsym: break; case yes: if (cs->def[def].tri != no) - conf_warning("override: %s changes choice state", sym->name); + conf_notice("override: %s changes choice state", sym->name); cs->def[def].val = sym; break; }

1 0

New patch to review for coreboot: Kconfig: Change symbol override from warning to notice
by Martin Roth 21 Sep '16

21 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16691 -gerrit commit 8ed4f3dd2808050d87839fa9e6bb002f47237b2e Author: Martin Roth <martinroth(a)google.com> Date: Wed Sep 21 14:27:26 2016 -0600 Kconfig: Change symbol override from warning to notice Overriding symbols within a .config is pretty common when doing automated builds with various different options. The warning text makes it sound like this is an issue, so change it to say 'notice' instead. We could get rid of it completely, but it's not a bad thing to know that we have two copies of the same symbol in the .config. Change-Id: I9f575b2275233f638e42676263348c807e6515bd Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/kconfig/confdata.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/util/kconfig/confdata.c b/util/kconfig/confdata.c index 436d735..453c510 100644 --- a/util/kconfig/confdata.c +++ b/util/kconfig/confdata.c @@ -42,6 +42,17 @@ static void conf_warning(const char *fmt, ...) conf_warnings++; } +static void conf_notice(const char *fmt, ...) +{ + va_list ap; + va_start(ap, fmt); + fprintf(stderr, "%s:%d:notice: ", conf_filename, conf_lineno); + vfprintf(stderr, fmt, ap); + fprintf(stderr, "\n"); + va_end(ap); + conf_warnings++; +} + static void conf_default_message_callback(const char *fmt, va_list ap) { printf("#\n# "); @@ -337,7 +348,7 @@ load: sym->type = S_BOOLEAN; } if (sym->flags & def_flags) { - conf_warning("override: reassigning to symbol %s", sym->name); + conf_notice("override: reassigning to symbol %s", sym->name); } switch (sym->type) { case S_BOOLEAN: @@ -374,7 +385,7 @@ load: sym->type = S_OTHER; } if (sym->flags & def_flags) { - conf_warning("override: reassigning to symbol %s", sym->name); + conf_notice("override: reassigning to symbol %s", sym->name); } if (conf_set_sym_val(sym, def, def_flags, p)) continue; @@ -397,7 +408,7 @@ setsym: break; case yes: if (cs->def[def].tri != no) - conf_warning("override: %s changes choice state", sym->name); + conf_notice("override: %s changes choice state", sym->name); cs->def[def].val = sym; break; }

1 0

New patch to review for coreboot: southbridge/broadcom/bcm5785: transition away from device_t
by Antonello Dettori 21 Sep '16

21 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16690 -gerrit commit 8000ee886e9d815949499792d61a019390e33041 Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 southbridge/broadcom/bcm5785: transition away from device_t Replace the use of the old device_t definition inside southbridge/broadcom/bcm5785. Change-Id: I091b07439ff918efa52cf8f8270484131fd0cec5 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/southbridge/broadcom/bcm5785/early_setup.c | 10 +++++----- src/southbridge/broadcom/bcm5785/early_smbus.c | 2 +- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/src/southbridge/broadcom/bcm5785/early_setup.c b/src/southbridge/broadcom/bcm5785/early_setup.c index 8aba58c..6ee4f6b 100644 --- a/src/southbridge/broadcom/bcm5785/early_setup.c +++ b/src/southbridge/broadcom/bcm5785/early_setup.c @@ -20,7 +20,7 @@ static void bcm5785_enable_lpc(void) { uint8_t byte; - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0234), 0); @@ -39,7 +39,7 @@ static void bcm5785_enable_lpc(void) static void bcm5785_enable_wdt_port_cf9(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; @@ -65,7 +65,7 @@ static void bcm5785_enable_wdt_port_cf9(void) unsigned get_sbdn(unsigned bus) { - device_t dev; + pci_devfn_t dev; /* Find the device. * There can only be one bcm5785 on a hypertransport chain/bus. @@ -130,7 +130,7 @@ void soft_reset(void) static void bcm5785_enable_msg(void) { - device_t dev; + pci_devfn_t dev; uint32_t dword; uint32_t dword_old; uint8_t byte; @@ -158,7 +158,7 @@ static void bcm5785_early_setup(void) { uint8_t byte; uint32_t dword; - device_t dev; + pci_devfn_t dev; //F0 // enable device on bcm5785 at first diff --git a/src/southbridge/broadcom/bcm5785/early_smbus.c b/src/southbridge/broadcom/bcm5785/early_smbus.c index f37aed9..c702c65 100644 --- a/src/southbridge/broadcom/bcm5785/early_smbus.c +++ b/src/southbridge/broadcom/bcm5785/early_smbus.c @@ -20,7 +20,7 @@ static void enable_smbus(void) { - device_t dev; + pci_devfn_t dev; dev = pci_locate_device(PCI_ID(0x1166, 0x0205), 0); // 0x0201? if (dev == PCI_DEV_INVALID) {

1 0

New patch to review for coreboot: northbridge/via/cn700: transition away from device_t
by Antonello Dettori 21 Sep '16

21 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16689 -gerrit commit a52299f8573c0ef4f344132cf8fbcc50b2e3edbb Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 northbridge/via/cn700: transition away from device_t Replace the use of the old device_t definition inside northbridge/via/cn700. Change-Id: Ib7761697daad3c459f3568e5158f925199bcd919 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/northbridge/via/cn700/raminit.c | 8 ++++---- src/northbridge/via/cn700/raminit.h | 2 +- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/src/northbridge/via/cn700/raminit.c b/src/northbridge/via/cn700/raminit.c index e4384ce..9cfd952 100644 --- a/src/northbridge/via/cn700/raminit.c +++ b/src/northbridge/via/cn700/raminit.c @@ -34,7 +34,7 @@ #define DUMPNORTH() #endif -static void do_ram_command(device_t dev, u8 command) +static void do_ram_command(pci_devfn_t dev, u8 command) { u8 reg; @@ -58,7 +58,7 @@ static void do_ram_command(device_t dev, u8 command) * * @param dev The northbridge's CPU Host Interface (D0F2). */ -static void c7_cpu_setup(device_t dev) +static void c7_cpu_setup(pci_devfn_t dev) { /* Host bus interface registers (D0F2 0x50-0x67) */ /* Request phase control */ @@ -376,7 +376,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl) static void sdram_set_post(const struct mem_controller *ctrl) { - device_t dev = ctrl->d0f3; + pci_devfn_t dev = ctrl->d0f3; /* Enable multipage mode. */ pci_write_config8(dev, 0x69, 0x03); @@ -389,7 +389,7 @@ static void sdram_set_post(const struct mem_controller *ctrl) pci_write_config16(dev, 0xa4, 0x0010); } -static void sdram_enable(device_t dev, u8 *rank_address) +static void sdram_enable(pci_devfn_t dev, u8 *rank_address) { u8 i; diff --git a/src/northbridge/via/cn700/raminit.h b/src/northbridge/via/cn700/raminit.h index 7286508..80e085f 100644 --- a/src/northbridge/via/cn700/raminit.h +++ b/src/northbridge/via/cn700/raminit.h @@ -20,7 +20,7 @@ #define DIMM_SOCKETS 1 /* Only one works, for now. */ struct mem_controller { - device_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0; + pci_devfn_t d0f0, d0f2, d0f3, d0f4, d0f7, d1f0; u8 channel0[DIMM_SOCKETS]; };

1 0

New patch to review for coreboot: biostar/am1ml: transition away from device_t
by Antonello Dettori 21 Sep '16

21 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16688 -gerrit commit aa50dc92948000f97485d6321cfd6f0e55aec18d Author: Antonello Dettori <dev(a)dettori.io> Date: Fri Sep 2 09:12:20 2016 +0200 biostar/am1ml: transition away from device_t Replace the use of the old device_t definition inside mainboard/biostar/am1ml. Change-Id: Iba2fff5617c62152355b54e446517ad36108aa31 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/mainboard/biostar/am1ml/romstage.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index 12d9eee..d7da2bb 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -110,7 +110,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { u32 val, t32; u8 byte; - device_t dev; + pci_devfn_t dev; u32 *addr32; /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for

1 0

Patch set updated for coreboot: cpu/amd/model_fxx: transition away from device_t
by Antonello Dettori 21 Sep '16

21 Sep '16

Antonello Dettori (dev(a)dettori.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16437 -gerrit commit a0ec3313be44a553f77e56472ac8c635914c336a Author: Antonello Dettori <dev(a)dettori.io> Date: Sat Sep 3 10:45:33 2016 +0200 cpu/amd/model_fxx: transition away from device_t Replace the use of the old device_t definition inside cpu/amd/model_fxx. Change-Id: Iac7571956ed2fb927a6b8cc88514e533f40490d0 Signed-off-by: Antonello Dettori <dev(a)dettori.io> --- src/cpu/amd/model_fxx/init_cpus.c | 2 +- src/include/cpu/amd/model_fxx_rev.h | 42 +++++++++++++++++++------------------ 2 files changed, 23 insertions(+), 21 deletions(-) diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index 63c8823..d38c552 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -342,7 +342,7 @@ static u32 init_cpus(u32 cpu_init_detectedx) static u32 is_core0_started(u32 nodeid) { u32 htic; - device_t device; + pci_devfn_t device; device = PCI_DEV(0, 0x18 + nodeid, 0); htic = pci_read_config32(device, HT_INIT_CONTROL); htic &= HTIC_INIT_Detect; diff --git a/src/include/cpu/amd/model_fxx_rev.h b/src/include/cpu/amd/model_fxx_rev.h index be961f2..a9bfc71 100644 --- a/src/include/cpu/amd/model_fxx_rev.h +++ b/src/include/cpu/amd/model_fxx_rev.h @@ -73,29 +73,30 @@ static inline int is_e0_later_in_bsp(int nodeid) if (IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; - if (nodeid == 0) { // we don't need to do that for node 0 in core0/node0 - return !is_cpu_pre_e0(); - } - // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 - device_t dev; - dev = PCI_DEV(0, 0x18+nodeid,2); - val_old = pci_read_config32(dev, 0x80); - val = val_old; - val |= (1<<3); - pci_write_config32(dev, 0x80, val); - val = pci_read_config32(dev, 0x80); - e0_later = !!(val & (1<<3)); - if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed - pci_write_config32(dev, 0x80, val_old); // restore it - } - - return e0_later; + if (nodeid==0) { // we don't need to do that for node 0 in core0/node0 + return !is_cpu_pre_e0(); + } + // d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0 + pci_devfn_t dev; + dev = PCI_DEV(0, 0x18+nodeid,2); + val_old = pci_read_config32(dev, 0x80); + val = val_old; + val |= (1<<3); + pci_write_config32(dev, 0x80, val); + val = pci_read_config32(dev, 0x80); + e0_later = !!(val & (1<<3)); + if (e0_later) { // pre_e0 bit 3 always be 0 and can not be changed + pci_write_config32(dev, 0x80, val_old); // restore it + } + + return e0_later; + } static inline int is_cpu_f0_in_bsp(int nodeid) { uint32_t dword; - device_t dev; + pci_devfn_t dev; if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 0; dev = PCI_DEV(0, 0x18+nodeid, 3); @@ -105,8 +106,9 @@ static inline int is_cpu_f0_in_bsp(int nodeid) static inline int is_cpu_pre_f2_in_bsp(int nodeid) { - uint32_t dword; - device_t dev; + uint32_t dword; + pci_devfn_t dev; + if (!IS_ENABLED(CONFIG_K8_REV_F_SUPPORT)) return 1; dev = PCI_DEV(0, 0x18+nodeid, 3);

1 0

Patch set updated for coreboot: Build system: Remove IASL_WARNINGS_ARE_ERRORS option
by Martin Roth 21 Sep '16

21 Sep '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16606 -gerrit commit 8862b71a00b5ce0165682f8f0c7cb6ba453a4dcd Author: Martin Roth <martinroth(a)google.com> Date: Wed Sep 14 18:11:01 2016 -0700 Build system: Remove IASL_WARNINGS_ARE_ERRORS option All systems are building with IASL warnings as errors enabled. Remove the option to disable it. Remove the notification at the end of the build. Change-Id: I5c6218c182fdf173b4026fd010d939a5fa36040e Signed-off-by: Martin Roth <martinroth(a)google.com> --- Makefile.inc | 8 -------- src/Kconfig | 13 ------------- 2 files changed, 21 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index ffe6015..d6c7476 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -238,11 +238,7 @@ cbfs-files-$(if $(2),$(2),y) += $(CONFIG_CBFS_PREFIX)/$(1).aml $(obj)/$(1).aml: $(src)/mainboard/$(MAINBOARDDIR)/$(1).asl $(obj)/config.h @printf " IASL $$(subst $(top)/,,$$(@))\n" $(CC_ramstage) -x assembler-with-cpp -E -MMD -MT $$(@) $$(CPPFLAGS_ramstage) -D__ACPI__ -P -include $(src)/include/kconfig.h -I$(obj) -I$(src) -I$(src)/include -I$(src)/arch/$(ARCHDIR-$(ARCH-ramstage-y))/include -I$(src)/mainboard/$(MAINBOARDDIR) $$< -o $$@ -ifeq ($(CONFIG_IASL_WARNINGS_ARE_ERRORS),y) cd $$(dir $$@); $(IASL) -we -p $$(notdir $$@) $$(notdir $$@) -else - cd $$(dir $$@); $(IASL) -p $$(notdir $$@) $$(notdir $$@) -endif if [ -z "$$$$($(IASL) -d $$@ 2>&1 | grep 'ACPI Warning')" ]; then echo " IASL $$@ disassembled correctly."; true; else echo "Error: Could not correctly disassemble $$@"; $(IASL) -d $$@; false; fi endef @@ -895,10 +891,6 @@ endif mv $@.tmp $@ @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) -ifeq ($(CONFIG_IASL_WARNINGS_ARE_ERRORS),) - @printf "\n***** WARNING: IASL warnings as errors is disabled! *****\n" - @printf "***** Please fix the ASL for this platform. *****\n\n" -endif cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf diff --git a/src/Kconfig b/src/Kconfig index a43a979..f6c022e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1146,19 +1146,6 @@ config WARNINGS_ARE_ERRORS bool default y -# TODO: Remove this when all platforms are fixed. -config IASL_WARNINGS_ARE_ERRORS - def_bool y - help - Select to Fail the build if a IASL generates a warning. - This will be defaulted to disabled for the platforms that - currently fail. This allows the REST of the platforms to - have this check enabled while we're working to get those - boards fixed. - - DO NOT ADD TO ANY ADDITIONAL PLATFORMS INSTEAD OF FIXING - THE ASL. - # The four POWER_BUTTON_DEFAULT_ENABLE, POWER_BUTTON_DEFAULT_DISABLE, # POWER_BUTTON_FORCE_ENABLE and POWER_BUTTON_FORCE_DISABLE options are # mutually exclusive. One of these options must be selected in the

1 0

Patch merged into coreboot/master: buildgcc: Build gnat by default if host compiler seems compatible
by gerrit＠coreboot.org 21 Sep '16

21 Sep '16

the following patch was just integrated into master: commit 66c2c1a2d4eed1aa4d3aad70b8790db5a4536beb Author: Nico Huber <nico.huber(a)secunet.com> Date: Tue Sep 20 13:09:29 2016 +0200 buildgcc: Build gnat by default if host compiler seems compatible Change-Id: I2a13e188ddb0b7d64d3c0ec979a1a493bf160afc Signed-off-by: Nico Huber <nico.huber(a)secunet.com> Reviewed-on: https://review.coreboot.org/16678 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/16678 for details. -gerrit

1 0

Patch set updated for coreboot: mainboard/nvidia/l1_2pvv: Use tabs for indents
by HAOUAS Elyes 21 Sep '16

21 Sep '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16687 -gerrit commit f7c353e88196181c5abe7bda2809ceb92882d529 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Sep 21 21:42:08 2016 +0200 mainboard/nvidia/l1_2pvv: Use tabs for indents Change-Id: I4171e9bbf14c9aa65f698feabd78aa8fbf2a105f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/nvidia/l1_2pvv/devicetree.cb | 358 ++++++++++++++--------------- 1 file changed, 179 insertions(+), 179 deletions(-) diff --git a/src/mainboard/nvidia/l1_2pvv/devicetree.cb b/src/mainboard/nvidia/l1_2pvv/devicetree.cb index 5709db7..d713e3f 100644 --- a/src/mainboard/nvidia/l1_2pvv/devicetree.cb +++ b/src/mainboard/nvidia/l1_2pvv/devicetree.cb @@ -1,180 +1,180 @@ -chip northbridge/amd/amdk8/root_complex # Root complex - device cpu_cluster 0 on # (L)APIC cluster - chip cpu/amd/socket_F # CPU socket - device lapic 0 on end # Local APIC of the CPU - end - end - device domain 0 on # PCI domain - subsystemid 0x1022 0x2b80 inherit - chip northbridge/amd/amdk8 # Northbridge / RAM controller - device pci 18.0 on # Link 0 == LDT 0 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on # LPC - chip superio/winbond/w83627ehg # Super I/O - device pnp 2e.0 off # Floppy - io 0x60 = 0x3f0 - irq 0x70 = 6 - drq 0x74 = 2 - end - device pnp 2e.1 off # Parallel port - io 0x60 = 0x378 - irq 0x70 = 7 - end - device pnp 2e.2 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 2e.3 off # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - device pnp 2e.5 on # PS/2 keyboard & mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 - irq 0x72 = 12 - end - device pnp 2e.106 off # Serial flash interface (SFI) - io 0x60 = 0x100 - end - device pnp 2e.007 off # GPIO 1 - end - device pnp 2e.107 off # Game port - io 0x60 = 0x220 - end - device pnp 2e.207 off # MIDI - io 0x62 = 0x300 - irq 0x70 = 9 - end - device pnp 2e.307 off # GPIO 6 - end - device pnp 2e.8 off # WDTO#, PLED - end - device pnp 2e.009 off # GPIO 2 - end - device pnp 2e.109 off # GPIO 3 - end - device pnp 2e.209 off # GPIO 4 - end - device pnp 2e.309 off # GPIO 5 - end - device pnp 2e.a off end # ACPI - device pnp 2e.b on # Hardware monitor - io 0x60 = 0x290 - irq 0x70 = 5 - end - end - end - device pci 1.1 on # SM 0 - chip drivers/generic/generic # DIMM 0-0-0 - device i2c 50 on end - end - chip drivers/generic/generic # DIMM 0-0-1 - device i2c 51 on end - end - chip drivers/generic/generic # DIMM 0-1-0 - device i2c 52 on end - end - chip drivers/generic/generic # DIMM 0-1-1 - device i2c 53 on end - end - chip drivers/generic/generic # DIMM 1-0-0 - device i2c 54 on end - end - chip drivers/generic/generic # DIMM 1-0-1 - device i2c 55 on end - end - chip drivers/generic/generic # DIMM 1-1-0 - device i2c 56 on end - end - chip drivers/generic/generic # DIMM 1-1-1 - device i2c 57 on end - end - end - device pci 1.1 on # SM 1 - # PCI device SMBus address will - # depend on addon PCI device, do - # we need to scan_smbus_bus? - # chip drivers/generic/generic # PCIXA slot 1 - # device i2c 50 on end - # end - # chip drivers/generic/generic # PCIXB slot 1 - # device i2c 51 on end - # end - # chip drivers/generic/generic # PCIXB slot 2 - # device i2c 52 on end - # end - # chip drivers/generic/generic # PCI slot 1 - # device i2c 53 on end - # end - # chip drivers/generic/generic # Master MCP55 PCI-E - # device i2c 54 on end - # end - # chip drivers/generic/generic # Slave MCP55 PCI-E - # device i2c 55 on end - # end - chip drivers/generic/generic # MAC EEPROM - device i2c 51 on end - end - end - device pci 2.0 on end # USB 1.1 - device pci 2.1 on end # USB 2 - device pci 4.0 on end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 on end # PCI - device pci 6.1 on end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 off end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.0 on end # Link 1 - device pci 18.0 on # Link 2 == LDT 2 - chip southbridge/nvidia/mcp55 # Southbridge - device pci 0.0 on end # HT - device pci 1.0 on end # LPC - device pci 1.1 on end # SM 0 - device pci 2.0 off end # USB 1.1 - device pci 2.1 off end # USB 2 - device pci 4.0 off end # IDE - device pci 5.0 on end # SATA 0 - device pci 5.1 on end # SATA 1 - device pci 5.2 on end # SATA 2 - device pci 6.0 off end # PCI - device pci 6.1 off end # AZA - device pci 8.0 on end # NIC - device pci 9.0 on end # NIC - device pci a.0 on end # PCI E 5 - device pci b.0 off end # PCI E 4 - device pci c.0 off end # PCI E 3 - device pci d.0 on end # PCI E 2 - device pci e.0 on end # PCI E 1 - device pci f.0 on end # PCI E 0 - register "ide0_enable" = "1" - register "sata0_enable" = "1" - register "sata1_enable" = "1" - # 1: SMBus under 2e.8, 2: SM0 3: SM1 - register "mac_eeprom_smbus" = "3" - register "mac_eeprom_addr" = "0x51" - end - end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - end - end +chip northbridge/amd/amdk8/root_complex # Root complex + device cpu_cluster 0 on # (L)APIC cluster + chip cpu/amd/socket_F # CPU socket + device lapic 0 on end # Local APIC of the CPU + end + end + device domain 0 on # PCI domain + subsystemid 0x1022 0x2b80 inherit + chip northbridge/amd/amdk8 # Northbridge / RAM controller + device pci 18.0 on # Link 0 == LDT 0 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on # LPC + chip superio/winbond/w83627ehg # Super I/O + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 off # Parallel port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.2 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.5 on # PS/2 keyboard & mouse + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.106 off # Serial flash interface (SFI) + io 0x60 = 0x100 + end + device pnp 2e.007 off # GPIO 1 + end + device pnp 2e.107 off # Game port + io 0x60 = 0x220 + end + device pnp 2e.207 off # MIDI + io 0x62 = 0x300 + irq 0x70 = 9 + end + device pnp 2e.307 off # GPIO 6 + end + device pnp 2e.8 off # WDTO#, PLED + end + device pnp 2e.009 off # GPIO 2 + end + device pnp 2e.109 off # GPIO 3 + end + device pnp 2e.209 off # GPIO 4 + end + device pnp 2e.309 off # GPIO 5 + end + device pnp 2e.a off end # ACPI + device pnp 2e.b on # Hardware monitor + io 0x60 = 0x290 + irq 0x70 = 5 + end + end + end + device pci 1.1 on # SM 0 + chip drivers/generic/generic # DIMM 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic # DIMM 0-0-1 + device i2c 51 on end + end + chip drivers/generic/generic # DIMM 0-1-0 + device i2c 52 on end + end + chip drivers/generic/generic # DIMM 0-1-1 + device i2c 53 on end + end + chip drivers/generic/generic # DIMM 1-0-0 + device i2c 54 on end + end + chip drivers/generic/generic # DIMM 1-0-1 + device i2c 55 on end + end + chip drivers/generic/generic # DIMM 1-1-0 + device i2c 56 on end + end + chip drivers/generic/generic # DIMM 1-1-1 + device i2c 57 on end + end + end + device pci 1.1 on # SM 1 + # PCI device SMBus address will + # depend on addon PCI device, do + # we need to scan_smbus_bus? + # chip drivers/generic/generic # PCIXA slot 1 + # device i2c 50 on end + # end + # chip drivers/generic/generic # PCIXB slot 1 + # device i2c 51 on end + # end + # chip drivers/generic/generic # PCIXB slot 2 + # device i2c 52 on end + # end + # chip drivers/generic/generic # PCI slot 1 + # device i2c 53 on end + # end + # chip drivers/generic/generic # Master MCP55 PCI-E + # device i2c 54 on end + # end + # chip drivers/generic/generic # Slave MCP55 PCI-E + # device i2c 55 on end + # end + chip drivers/generic/generic # MAC EEPROM + device i2c 51 on end + end + end + device pci 2.0 on end # USB 1.1 + device pci 2.1 on end # USB 2 + device pci 4.0 on end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 on end # PCI + device pci 6.1 on end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 off end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.0 on end # Link 1 + device pci 18.0 on # Link 2 == LDT 2 + chip southbridge/nvidia/mcp55 # Southbridge + device pci 0.0 on end # HT + device pci 1.0 on end # LPC + device pci 1.1 on end # SM 0 + device pci 2.0 off end # USB 1.1 + device pci 2.1 off end # USB 2 + device pci 4.0 off end # IDE + device pci 5.0 on end # SATA 0 + device pci 5.1 on end # SATA 1 + device pci 5.2 on end # SATA 2 + device pci 6.0 off end # PCI + device pci 6.1 off end # AZA + device pci 8.0 on end # NIC + device pci 9.0 on end # NIC + device pci a.0 on end # PCI E 5 + device pci b.0 off end # PCI E 4 + device pci c.0 off end # PCI E 3 + device pci d.0 on end # PCI E 2 + device pci e.0 on end # PCI E 1 + device pci f.0 on end # PCI E 0 + register "ide0_enable" = "1" + register "sata0_enable" = "1" + register "sata1_enable" = "1" + # 1: SMBus under 2e.8, 2: SM0 3: SM1 + register "mac_eeprom_smbus" = "3" + register "mac_eeprom_addr" = "0x51" + end + end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + end + end end

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit September 2016