Patch merged into coreboot/master: northbridge/amdk8: Improve code formatting
by gerrit＠coreboot.org 21 Sep '16
by gerrit＠coreboot.org 21 Sep '16
21 Sep '16
the following patch was just integrated into master:
commit b6a6bb53938c7e9f92237f22c52a02ab08a9d247
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 10:26:28 2016 -0600
northbridge/amdk8: Improve code formatting
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/16644
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/16644 for details.
-gerrit
1
0
Patch merged into coreboot/master: northbridge/amd/amdmct: Improve code formatting
by gerrit＠coreboot.org 21 Sep '16
by gerrit＠coreboot.org 21 Sep '16
21 Sep '16
the following patch was just integrated into master:
commit e1606731b63bedd12398acb57a115aa5d280811e
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 10:25:41 2016 -0600
northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/16643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16643 for details.
-gerrit
1
0
Patch merged into coreboot/master: google/enguarde: Adapt to current tree
by gerrit＠coreboot.org 21 Sep '16
by gerrit＠coreboot.org 21 Sep '16
21 Sep '16
the following patch was just integrated into master:
commit 8aa20193a6dc12ba6cf740b1ad41023475d69698
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Sep 21 14:08:41 2016 +0200
google/enguarde: Adapt to current tree
Some changes were made in upstream in the meantime that broke the build:
- CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS
- recovery_move_enabled() -> vboot_recovery_mode_enabled()
- chromeos.asl was replaced by an acpi generator
Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/16683 for details.
-gerrit
1
0
Patch set updated for coreboot: northbridge/amdk8: Improve code formatting
by Martin Roth 21 Sep '16
by Martin Roth 21 Sep '16
21 Sep '16
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16644
-gerrit
commit 3aa03d743d8fbdbb7b95925709f8439291a64e0a
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 10:26:28 2016 -0600
northbridge/amdk8: Improve code formatting
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/northbridge/amd/amdk8/acpi.c | 26 ++--
src/northbridge/amd/amdk8/coherent_ht.c | 124 ++++++++---------
src/northbridge/amd/amdk8/debug.c | 10 +-
src/northbridge/amd/amdk8/early_ht.c | 4 +-
src/northbridge/amd/amdk8/exit_from_self.c | 2 +-
src/northbridge/amd/amdk8/f.h | 6 +-
src/northbridge/amd/amdk8/get_sblk_pci1234.c | 8 +-
src/northbridge/amd/amdk8/incoherent_ht.c | 72 +++++-----
src/northbridge/amd/amdk8/misc_control.c | 12 +-
src/northbridge/amd/amdk8/northbridge.c | 30 ++--
src/northbridge/amd/amdk8/raminit.c | 40 +++---
src/northbridge/amd/amdk8/raminit_f.c | 182 ++++++++++++-------------
src/northbridge/amd/amdk8/raminit_f_dqs.c | 160 +++++++++++-----------
src/northbridge/amd/amdk8/setup_resource_map.c | 8 +-
src/northbridge/amd/amdk8/util.asl | 14 +-
15 files changed, 349 insertions(+), 349 deletions(-)
diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c
index 992a85e..906dc0b 100644
--- a/src/northbridge/amd/amdk8/acpi.c
+++ b/src/northbridge/amd/amdk8/acpi.c
@@ -101,7 +101,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
*/
if ((basek+sizek)<1024) return;
- if (basek<1024) {
+ if (basek < 1024) {
sizek -= 1024 - basek;
basek = 1024;
}
@@ -158,29 +158,29 @@ static unsigned long acpi_fill_slit(unsigned long current)
p += 8;
#if 0
- for (i=0;i<sysconf.hc_possible_num;i++) {
- if ((sysconf.pci1234[i]&1) !=1 ) continue;
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
+ if ((sysconf.pci1234[i]&1) !=1) continue;
outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
}
#endif
- for (i=0;i<nodes;i++) {
- for (j=0;j<nodes; j++) {
- if (i==j) {
+ for (i = 0; i < nodes; i++) {
+ for (j = 0; j < nodes; j++) {
+ if (i == j) {
p[i*nodes+j] = 10;
} else {
#if 0
int k;
u8 latency_factor = 0;
int k_start, k_end;
- if (i<j) {
+ if (i < j) {
k_start = i;
k_end = j;
} else {
k_start = j;
k_end = i;
}
- for (k=k_start;k<=k_end; k++) {
+ for (k = k_start; k <= k_end; k++) {
if (outer_node[k]) {
latency_factor = 1;
break;
@@ -238,10 +238,10 @@ static void k8acpi_write_HT(void) {
acpigen_write_name("HCLK");
acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) {
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
acpigen_write_dword(sysconf.pci1234[i]);
}
- for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
acpigen_write_dword(0x0);
}
@@ -250,10 +250,10 @@ static void k8acpi_write_HT(void) {
acpigen_write_name("HCDN");
acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) {
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
acpigen_write_dword(sysconf.hcdn[i]);
}
- for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
acpigen_write_dword(0x20202020);
}
acpigen_pop_len();
@@ -268,7 +268,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
acpigen_write_name(name);
acpigen_write_package(dlen);
- for (i=0; i<dlen; i++) {
+ for (i = 0; i < dlen; i++) {
dword = pci_read_config32(dev, offset+i*4);
acpigen_write_dword(dword);
}
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 7e33feb..887a23b 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -139,7 +139,7 @@ static void disable_probes(void)
printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... ");
- val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
+ val = pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
@@ -193,7 +193,7 @@ static void enable_routing(u8 node)
/* Enable routing table */
printk(BIOS_SPEW, "Enabling routing table for node %d", node);
- val=pci_read_config32(NODE_HT(node), 0x6c);
+ val = pci_read_config32(NODE_HT(node), 0x6c);
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
@@ -241,7 +241,7 @@ static void rename_temp_node(u8 node)
printk(BIOS_SPEW, "Renaming current temporary node to %d", node);
- val=pci_read_config32(NODE_HT(7), 0x60);
+ val = pci_read_config32(NODE_HT(7), 0x60);
val &= (~7); /* clear low bits. */
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
@@ -401,7 +401,7 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo
uint8_t linkn;
uint32_t val;
val = 1;
- for (linkn = 0; linkn<3; linkn++) {
+ for (linkn = 0; linkn < 3; linkn++) {
uint8_t regpos;
uint32_t reg;
regpos = 0x98 + 0x20 * linkn;
@@ -423,10 +423,10 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
if (((source &1)!=(dest &1))
#if CROSS_BAR_47_56
- && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
+ && ((source < 4)||(source > 5)) //(6,7) (7,6) should still be here
//(6,5) (7,4) should be here
#endif
- ){
+ ) {
val |= (1<<16);
} else {
/*for CROSS_BAR_47_56 47, 56, should be here too
@@ -437,7 +437,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
}
- fill_row(temp,dest, val );
+ fill_row(temp,dest, val);
}
#if CROSS_BAR_47_56
@@ -453,7 +453,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num)
{
int i;
- for (i=0; i<num; i+=3) {
+ for (i = 0; i < num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
@@ -470,7 +470,7 @@ static void opt_broadcast_rt_plus_group(const u8 *conn, int num)
{
int i;
- for (i=0; i<num; i+=3) {
+ for (i = 0; i < num; i+=3) {
opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
}
}
@@ -535,7 +535,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
#if !CROSS_BAR_47_56
u8 gateway;
u8 diff;
- if (source<dest) {
+ if (source < dest) {
gateway = source + 2;
} else {
gateway = source - 2;
@@ -552,7 +552,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
diff = ((source&1)!=(dest &1));
#endif
- if (diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
+ if (diff && (val_s!=(val&0xff))) { /* use another connect as response*/
val_s -= val & 0xff;
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
uint8_t byte;
@@ -562,14 +562,14 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
byte = val_s;
byte = get_linkn_last_count(byte);
if ((byte>>2)>1) { /* make sure not the corner*/
- if (source<dest) {
+ if (source < dest) {
val_s-=link_connection(temp, source-2); /* -down*/
} else {
#if CROSS_BAR_47_56
#if 0
- if (source==7) {
+ if (source == 7) {
val_s-=link_connection(temp, 6); // for 7,2 via 5
- } else if (source==6){
+ } else if (source == 6) {
val_s-=link_connection(temp, 7); // for 6,3 via 4
} else
#endif
@@ -614,10 +614,10 @@ static void setup_row_indirect_group(const u8 *conn, int num)
int i;
#if !CROSS_BAR_47_56
- for (i=0; i<num; i+=2) {
+ for (i = 0; i < num; i+=2) {
setup_row_indirect(conn[i], conn[i+1]);
#else
- for (i=0; i<num; i+=4) {
+ for (i = 0; i < num; i+=4) {
setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
#endif
@@ -641,10 +641,10 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
int i;
#if !CROSS_BAR_47_56
- for (i=0; i<num; i+=2) {
+ for (i = 0; i < num; i+=2) {
setup_remote_row_indirect(conn[i], conn[i+1]);
#else
- for (i=0; i<num; i+=4) {
+ for (i = 0; i < num; i+=4) {
setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
#endif
}
@@ -658,7 +658,7 @@ static void setup_uniprocessor(void)
printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
- if (tmp>0) return;
+ if (tmp > 0) return;
#endif
disable_probes();
}
@@ -668,10 +668,10 @@ static int optimize_connection_group(const u8 *opt_conn, int num)
{
int needs_reset = 0;
int i;
- for (i=0; i<num; i+=2) {
+ for (i = 0; i < num; i+=2) {
needs_reset = optimize_connection(
NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
- NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
+ NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])));
}
return needs_reset;
}
@@ -689,7 +689,7 @@ static unsigned setup_smp2(void)
val = get_row(0,0);
byte = (val>>16) & 0xfe;
- if (byte<0x2) { /* no coherent connection so get out.*/
+ if (byte < 0x2) { /* no coherent connection so get out.*/
nodes = 1;
return nodes;
}
@@ -717,7 +717,7 @@ static unsigned setup_smp2(void)
val = get_row(7,1);
byte = (val>>16) & 0xfe;
byte = get_linkn_last_count(byte);
- if ((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
+ if ((byte>>2) == 3) { /* Oh! we need to treat it as node2. So use another link*/
val = get_row(0,0);
byte = (val>>16) & 0xfe;
#if TRY_HIGH_FIRST == 1
@@ -760,14 +760,14 @@ static unsigned setup_smp4(void)
u8 byte;
uint32_t val;
- nodes=4;
+ nodes = 4;
/* Setup and check temporary connection from Node 0 to Node 2 */
val = get_row(0,0);
byte = ((val>>16) & 0xfe) - link_connection(0,1);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have two coherent for 4p and above*/
+ if ((byte>>2) == 0) { /* We should have two coherent for 4p and above*/
nodes = 2;
return nodes;
}
@@ -841,7 +841,7 @@ static unsigned setup_smp4(void)
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
/* We need to find out which link is to node3 */
- if ((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
+ if ((byte>>2) == 2) { /* one to node3, one to node0, one to node4*/
val = get_row(7,3);
if ((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
val = get_row(2,2);
@@ -865,7 +865,7 @@ static unsigned setup_smp4(void)
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent links on node 3 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(3,5) link=", byte);
setup_remote_row_direct(3, 5, byte);
@@ -875,7 +875,7 @@ static unsigned setup_smp4(void)
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent link on node 2 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(2,4) link=", byte);
setup_row_direct(2, 4, byte);
@@ -931,14 +931,14 @@ static unsigned setup_smp6(void)
u8 byte;
uint32_t val;
- nodes=6;
+ nodes = 6;
/* Setup and check temporary connection from Node 0 to Node 4 through 2*/
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
+ if ((byte>>2) == 0) { /* We should have three coherent link on node 2 for 6p and above*/
nodes = 4;
return nodes;
}
@@ -948,7 +948,7 @@ static unsigned setup_smp6(void)
val = get_row(3,3);
byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
+ if ((byte>>2) == 0) { /* We should have three coherent links on node 3 for 6p and above*/
nodes = 4;
return nodes;
}
@@ -975,7 +975,7 @@ static unsigned setup_smp6(void)
setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte,byte+2);
}
verify_connection(7);
@@ -1003,7 +1003,7 @@ static unsigned setup_smp6(void)
enable_routing(4);
setup_temp_row(0,1);
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
verify_connection(7);
@@ -1031,7 +1031,7 @@ static unsigned setup_smp6(void)
#if CONFIG_MAX_PHYSICAL_CPUS > 6
/* We need to find out which link is to node5 */
- if ((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
+ if ((byte>>2) == 2) { /* one to node5, one to node2, one to node6*/
val = get_row(7,5);
if ((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
val = get_row(4,4);
@@ -1054,7 +1054,7 @@ static unsigned setup_smp6(void)
val = get_row(7,5);
byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent links on node 5 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(5,7) link=", byte);
setup_remote_row_direct(5, 7, byte);
@@ -1065,7 +1065,7 @@ static unsigned setup_smp6(void)
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent link on node 4 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(4,6) link=", byte);
setup_row_direct(4, 6, byte);
@@ -1115,7 +1115,7 @@ static unsigned setup_smp6(void)
/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
* It will be done by clear_dead_links
*/
- for (byte=0; byte<4; byte++) {
+ for (byte = 0; byte < 4; byte++) {
clear_temp_row(byte);
}
#endif
@@ -1134,7 +1134,7 @@ static unsigned setup_smp8(void)
u8 byte;
uint32_t val;
- nodes=8;
+ nodes = 8;
/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
val = get_row(4,4);
@@ -1143,7 +1143,7 @@ static unsigned setup_smp8(void)
#else
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte); /* Max link to 6*/
- if ((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
+ if ((byte>>2) == 0) { /* We should have two or three coherent links on node 4 for 8p*/
nodes = 6;
return nodes;
}
@@ -1170,7 +1170,7 @@ static unsigned setup_smp8(void)
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
+ if ((byte>>2) == 0) { /* We should have three coherent links on node 5 for 6p and above*/
nodes = 6;
return nodes;
}
@@ -1203,7 +1203,7 @@ static unsigned setup_smp8(void)
setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
- for (byte=0; byte<6; byte+=2) {
+ for (byte = 0; byte < 6; byte+=2) {
setup_temp_row(byte,byte+2);
}
verify_connection(7);
@@ -1241,7 +1241,7 @@ static unsigned setup_smp8(void)
setup_row_direct(5, 6, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(5,6);
@@ -1249,7 +1249,7 @@ static unsigned setup_smp8(void)
verify_connection(7);
val = get_row(7,6); // to chect it if it is node6 before renaming
- if ( (val>>16) == 1) { // it is real node 7 so swap it
+ if ((val>>16) == 1) { // it is real node 7 so swap it
/* We need to recompute link to 6 */
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
@@ -1262,7 +1262,7 @@ static unsigned setup_smp8(void)
setup_row_direct(5, 6, byte);
#if 0
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
#endif
@@ -1282,7 +1282,7 @@ static unsigned setup_smp8(void)
#if !CROSS_BAR_47_56
setup_temp_row(0,1);
- for (byte=0; byte<6; byte+=2) {
+ for (byte = 0; byte < 6; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
@@ -1302,7 +1302,7 @@ static unsigned setup_smp8(void)
setup_row_direct(4, 7, byte);
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte,byte+2);
}
@@ -1327,7 +1327,7 @@ static unsigned setup_smp8(void)
setup_row_direct(5, 7, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
@@ -1511,7 +1511,7 @@ static unsigned verify_mp_capabilities(unsigned nodes)
mask = 0x06; /* BigMPCap */
- for (node=0; node<nodes; node++) {
+ for (node = 0; node < nodes; node++) {
mask &= pci_read_config32(NODE_MC(node), 0xe8);
}
@@ -1525,7 +1525,7 @@ static unsigned verify_mp_capabilities(unsigned nodes)
break;
#endif
case 0x00: /* Non SMP */
- if (nodes >1 ) {
+ if (nodes >1) {
printk(BIOS_ERR, "Going back to UP\n");
return 1;
}
@@ -1542,7 +1542,7 @@ static void clear_dead_routes(unsigned nodes)
int last_row;
int node, row;
#if CONFIG_MAX_PHYSICAL_CPUS == 8
- if (nodes==8) return;/* don't touch (7,7)*/
+ if (nodes == 8) return;/* don't touch (7,7)*/
#endif
last_row = nodes;
if (nodes == 1) {
@@ -1555,9 +1555,9 @@ static void clear_dead_routes(unsigned nodes)
}
/* Update the local row */
- for ( node=0; node<nodes; node++) {
+ for (node = 0; node < nodes; node++) {
uint32_t val = 0;
- for (row =0; row<nodes; row++) {
+ for (row =0; row < nodes; row++) {
val |= get_row(node, row);
}
fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
@@ -1571,7 +1571,7 @@ static unsigned verify_dualcore(unsigned nodes)
unsigned node, totalcpus, tmp;
totalcpus = 0;
- for (node=0; node<nodes; node++) {
+ for (node = 0; node < nodes; node++) {
tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
totalcpus += (tmp + 1);
}
@@ -1626,7 +1626,7 @@ static void coherent_ht_finalize(unsigned nodes)
/* Only respond to real CPU pci configuration cycles
* and optimize the HT settings
*/
- val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
+ val = pci_read_config32(dev, HT_TRANSACTION_CONTROL);
val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
(HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
(HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
@@ -1666,14 +1666,14 @@ static int apply_cpu_errata_fixes(unsigned nodes)
if ((cmd & (3 << 0)) != 2) {
cmd &= ~(3<<0);
cmd |= (2<<0);
- pci_write_config32(dev, 0x70, cmd );
+ pci_write_config32(dev, 0x70, cmd);
needs_reset = 1;
}
cmd = pci_read_config32(dev, 0x7c);
if ((cmd & (3 << 4)) != 0) {
cmd &= ~(3<<4);
cmd |= (0<<4);
- pci_write_config32(dev, 0x7c, cmd );
+ pci_write_config32(dev, 0x7c, cmd);
needs_reset = 1;
}
/* Clock Power/Timing Low */
@@ -1694,7 +1694,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
cmd_ref = 0x04e20707; /* Registered */
cmd = pci_read_config32(dev, 0xd4);
if (cmd != cmd_ref) {
- pci_write_config32(dev, 0xd4, cmd_ref );
+ pci_write_config32(dev, 0xd4, cmd_ref);
needs_reset = 1; /* Needed? */
}
}
@@ -1765,14 +1765,14 @@ static int optimize_link_coherent_ht(void)
nodes = get_nodes();
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- if (nodes>1) {
+ if (nodes > 1) {
needs_reset |= optimize_connection(
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
- NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
+ NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)));
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
- if (nodes>2) {
+ if (nodes > 2) {
/* optimize physical connections - by LYH */
static const u8 opt_conn4[] = {
0,2,
@@ -1784,7 +1784,7 @@ static int optimize_link_coherent_ht(void)
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
- if (nodes>4) {
+ if (nodes > 4) {
static const uint8_t opt_conn6[] ={
2, 4,
3, 5,
@@ -1797,7 +1797,7 @@ static int optimize_link_coherent_ht(void)
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
- if (nodes>6) {
+ if (nodes > 6) {
static const uint8_t opt_conn8[] ={
4, 6,
#if CROSS_BAR_47_56
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 18fc858..a8431f4 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -71,7 +71,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
int j;
printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config32_index_wait(dev, index_reg, i);
- for (j=0;j<4;j++) {
+ for (j = 0; j < 4; j++) {
printk(BIOS_DEBUG, " %02x", val & 0xff);
val >>= 8;
}
@@ -185,7 +185,7 @@ static void dump_smbus_registers(void)
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
- if ( smbus_read_byte(device, 0) < 0 ) continue;
+ if (smbus_read_byte(device, 0) < 0) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;
@@ -211,7 +211,7 @@ static inline void dump_io_resources(unsigned port)
int i;
udelay(2000);
printk(BIOS_DEBUG, "%04x:\n", port);
- for (i=0;i<256;i++) {
+ for (i = 0; i < 256; i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
printk(BIOS_DEBUG, "%02x:", i);
@@ -229,8 +229,8 @@ static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
- if ((i & 0xf)==0) {
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index d07da2a..638511a 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -64,7 +64,7 @@ static void enumerate_ht_chain(void)
pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f.
+ if (next_unitid >= 0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f.
if (!end_used) {
next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
@@ -127,7 +127,7 @@ out:
;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
+ if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
uint16_t flags;
dev = PCI_DEV(0,real_last_unitid, 0);
flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS);
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index 858a0c0..6da042f 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -144,7 +144,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
dcm =
pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
} while (((dcm & DCM_MemClrStatus) ==
- 0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
+ 0) /* || ((dcm & DCM_DramEnabled) == 0) */);
if (loops >= TIMEOUT_LOOPS) {
printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index ce039af..a679150 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -537,9 +537,9 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
if (sysinfo->nodes == 1) return; // in case only one CPU installed
- for (i=1; i<sysinfo->nodes; i++) {
+ for (i = 1; i < sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->mem_trained[i]==0x00) continue;
+ if (sysinfo->mem_trained[i]== 0x00) continue;
mask |= (1<<i);
@@ -564,7 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
i%=sysinfo->nodes;
}
- for (i=0; i<sysinfo->nodes; i++) {
+ for (i = 0; i < sysinfo->nodes; i++) {
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index 9cf4083..764b6d1 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -211,7 +211,7 @@ void get_sblk_pci1234(void)
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
- for (j=0;j<4;j++) {
+ for (j = 0; j < 4; j++) {
uint32_t dwordx;
dwordx = pci_read_config32(dev, 0xe0 + j*4);
dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
@@ -225,7 +225,7 @@ void get_sblk_pci1234(void)
/* We need to find out the number of HC
* for exact match
*/
- for (i=1;i<sysconf.hc_possible_num;i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
@@ -234,7 +234,7 @@ void get_sblk_pci1234(void)
}
/* For 0xff0 match or same node */
- for (i=1;i<sysconf.hc_possible_num;i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
@@ -244,7 +244,7 @@ void get_sblk_pci1234(void)
}
}
- for (i=1;i<sysconf.hc_possible_num;i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((sysconf.pci1234[i] & 1) != 1) {
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index bc50b66..9fa0034 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -374,7 +374,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid) {
- if (next_unitid>= (bus ? 0x20:0x18) ) {
+ if (next_unitid >= (bus ? 0x20:0x18)) {
if (!end_used) {
next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
@@ -428,9 +428,9 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
/* Remeber the location of the last device */
udev = dev;
upos = pos;
- uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
+ uoffs = (offs != PCI_HT_SLAVE0_OFFS) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
- } while (last_unitid != next_unitid );
+ } while (last_unitid != next_unitid);
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
out:
@@ -438,7 +438,7 @@ out:
end_of_chain: ;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if (offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
+ if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
uint16_t flags;
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
@@ -448,7 +448,7 @@ end_of_chain: ;
#if CONFIG_RAMINIT_SYSINFO
// Here need to change the dev in the array
int i;
- for (i=0;i<sysinfo->link_pair_num;i++)
+ for (i = 0; i < sysinfo->link_pair_num; i++)
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
if (link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
@@ -514,9 +514,9 @@ static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt
link_type = dword & 0xff;
- if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+ if ((link_type & 7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/
dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc);
- dword &= ~( 0xff<<(linkn *8) );
+ dword &= ~(0xff<<(linkn *8));
dword |= val << (linkn *8);
if (dword != dword_old) {
@@ -551,10 +551,10 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
devn = offset_unit_id(i == 0) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
- reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
- if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) {
+ reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
+ if ((reg & 0xffff) == PCI_VENDOR_ID_AMD) {
val = 0x25;
- } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) {
+ } else if ((reg & 0xffff) == PCI_VENDOR_ID_NVIDIA) {
val = 0x25;//???
} else {
continue;
@@ -581,9 +581,9 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt,
dword = pci_read_config32(dev, regpos);
link_type = dword & 0xff;
- if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+ if ((link_type & 0x7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/
regpos = 0x90 + (linkn * 0x20);
- dword = pci_read_config32(dev, regpos );
+ dword = pci_read_config32(dev, regpos);
if (dword != val) {
pci_write_config32(dev, regpos, val);
@@ -615,8 +615,8 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,
busn = (reg & 0xff0000)>>16; //busn
for (devn = 0; devn < 0x20; devn++) {
- reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
- if ( (reg & 0xffff) == vendorid ) {
+ reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
+ if ((reg & 0xffff) == vendorid) {
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
break;
}
@@ -659,14 +659,14 @@ static int ht_setup_chains(uint8_t ht_c_num)
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
//We need setup 0x94, 0xb4, and 0xd4 according to the reg
- devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
- regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
+ devpos = ((reg & 0xf0)>>4)+0x18; // nodeid;it will decide 0x18 or 0x19
+ regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4;
busn = (reg & 0xff0000)>>16;
- dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
+ dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ;
dword &= ~(0xffff<<8);
dword |= (reg & 0xffff0000)>>8;
- pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
+ pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, offset_unit_id(i == 0));
@@ -712,29 +712,29 @@ static int ht_setup_chains_x(void)
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
- /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
- print_linkn_in("SBLink=", ((reg>>8) & 3) );
+ /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */
+ print_linkn_in("SBLink=", ((reg>>8) & 3));
#if CONFIG_RAMINIT_SYSINFO
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
#endif
- tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
+ tempreg = 3 | (0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
- next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
+ next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
- tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
+ tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
- tempreg = 3 | ( 3<<4) | (0<<12); //base
+ tempreg = 3 | (3<<4) | (0<<12); //base
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg);
next_io_base = 0x3+0x1;
#endif
/* clean others */
- for (ht_c_num=1;ht_c_num<4; ht_c_num++) {
+ for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if CONFIG_K8_ALLOCATE_IO_RANGE
@@ -744,11 +744,11 @@ static int ht_setup_chains_x(void)
#endif
}
- for (nodeid=0; nodeid<nodes; nodeid++) {
+ for (nodeid = 0; nodeid < nodes; nodeid++) {
pci_devfn_t dev;
uint8_t linkn;
dev = PCI_DEV(0, 0x18+nodeid,0);
- for (linkn = 0; linkn<3; linkn++) {
+ for (linkn = 0; linkn < 3; linkn++) {
unsigned regpos;
regpos = 0x98 + 0x20 * linkn;
reg = pci_read_config32(dev, regpos);
@@ -756,7 +756,7 @@ static int ht_setup_chains_x(void)
print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
tempreg = 3 | (nodeid <<4) | (linkn<<8);
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
- for (ht_c_num=0;ht_c_num<4; ht_c_num++) {
+ for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if (((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
break;
@@ -774,7 +774,7 @@ static int ht_setup_chains_x(void)
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
+ tempreg = 3 /*| (3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
next_io_base += 0x3+0x1;
#endif
@@ -783,11 +783,11 @@ static int ht_setup_chains_x(void)
}
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
- for (nodeid = 1; nodeid<nodes; nodeid++) {
+ for (nodeid = 1; nodeid < nodes; nodeid++) {
int i;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x18+nodeid,1);
- for (i = 0; i< 4; i++) {
+ for (i = 0; i < 4; i++) {
unsigned regpos;
regpos = 0xe0 + i * 4;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
@@ -796,13 +796,13 @@ static int ht_setup_chains_x(void)
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
- for (i = 0; i< 4; i++) {
+ for (i = 0; i < 4; i++) {
unsigned regpos;
regpos = 0xc4 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
- for (i = 0; i< 4; i++) {
+ for (i = 0; i < 4; i++) {
unsigned regpos;
regpos = 0xc0 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
@@ -812,8 +812,8 @@ static int ht_setup_chains_x(void)
}
/* recount ht_c_num*/
- uint8_t i=0;
- for (ht_c_num=0;ht_c_num<4; ht_c_num++) {
+ uint8_t i = 0;
+ for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if (((reg & 0xf) != 0x0)) {
i++;
@@ -841,7 +841,7 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
- for (i=0; i< link_pair_num; i++) {
+ for (i = 0; i < link_pair_num; i++) {
struct link_pair_st *link_pair= &sysinfo->link_pair[i];
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index a2b4651..3cbeb04 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -120,7 +120,7 @@ static void misc_control_init(struct device *dev)
*/
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
- pci_write_config32(dev, 0x44, cmd );
+ pci_write_config32(dev, 0x44, cmd);
#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
@@ -129,11 +129,11 @@ static void misc_control_init(struct device *dev)
*/
cmd = pci_read_config32(dev, 0x80);
cmd &= ~(1<<0);
- pci_write_config32(dev, 0x80, cmd );
+ pci_write_config32(dev, 0x80, cmd);
cmd = pci_read_config32(dev, 0x84);
cmd &= ~(1<<24);
cmd &= ~(1<<8);
- pci_write_config32(dev, 0x84, cmd );
+ pci_write_config32(dev, 0x84, cmd);
/* Errata 66
* Limit the number of downstream posted requests to 1
@@ -142,14 +142,14 @@ static void misc_control_init(struct device *dev)
if ((cmd & (3 << 0)) != 2) {
cmd &= ~(3<<0);
cmd |= (2<<0);
- pci_write_config32(dev, 0x70, cmd );
+ pci_write_config32(dev, 0x70, cmd);
needs_reset = 1;
}
cmd = pci_read_config32(dev, 0x7c);
if ((cmd & (3 << 4)) != 0) {
cmd &= ~(3<<4);
cmd |= (0<<4);
- pci_write_config32(dev, 0x7c, cmd );
+ pci_write_config32(dev, 0x7c, cmd);
needs_reset = 1;
}
/* Clock Power/Timing Low */
@@ -175,7 +175,7 @@ static void misc_control_init(struct device *dev)
}
cmd = pci_read_config32(dev, 0xd4);
if (cmd != cmd_ref) {
- pci_write_config32(dev, 0xd4, cmd_ref );
+ pci_write_config32(dev, 0xd4, cmd_ref);
needs_reset = 1; /* Needed? */
}
}
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index d80c565..fbd4da8 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -42,7 +42,7 @@ struct amdk8_sysconf_t sysconf;
#define MAX_FX_DEVS 8
static device_t __f0_dev[MAX_FX_DEVS];
static device_t __f1_dev[MAX_FX_DEVS];
-static unsigned fx_devs=0;
+static unsigned fx_devs = 0;
static void get_fx_devs(void)
{
@@ -178,7 +178,7 @@ static void amdk8_scan_chain(struct bus *link)
config_busses &= 0x000fc88;
config_busses |=
(3 << 0) | /* rw enable, no device compare */
- (( nodeid & 7) << 4) |
+ ((nodeid & 7) << 4) |
((link->link_num & 3) << 8) |
((link->secondary) << 16) |
(0xff << 24);
@@ -489,8 +489,8 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate )
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate)
)
#endif
break;
@@ -505,7 +505,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
/* allocate a temp resource for the legacy VGA buffer */
resource = new_resource(dev, IOINDEX(4, link->link_num));
- if (!resource){
+ if (!resource) {
printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
return;
}
@@ -697,7 +697,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
*/
if (mem_hole.node_id==-1) {
u32 limitk_pri = 0;
- for (i=0; i<8; i++) {
+ for (i = 0; i < 8; i++) {
u32 base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
@@ -738,7 +738,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
hole_sizek = (4*1024*1024) - hole_startk;
- for (i=7;i>node_id;i--) {
+ for (i = 7; i > node_id; i--) {
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
@@ -775,7 +775,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
carry_over = (4*1024*1024) - hole_startk;
- for (i=7;i>node_id;i--) {
+ for (i = 7; i > node_id; i--) {
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
@@ -970,11 +970,11 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
/* See if I need to split the region to accommodate pci memory space */
- if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -984,7 +984,7 @@ static void amdk8_domain_set_resources(device_t dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if (reset_memhole)
#if !CONFIG_K8_REV_F_SUPPORT
- if (!is_cpu_pre_e0() )
+ if (!is_cpu_pre_e0())
#endif
sizek += hoist_memory(mmio_basek,i);
#endif
@@ -1210,7 +1210,7 @@ static void cpu_bus_scan(device_t dev)
// ----> you can mixed single core e0 and dual core e0 at any sequence
// That is the typical case
- if (j == 0 ){
+ if (j == 0) {
#if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
@@ -1222,10 +1222,10 @@ static void cpu_bus_scan(device_t dev)
if (e0_later_single_core) {
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
- j=1;
+ j = 1;
}
- if (siblings > j ) {
+ if (siblings > j) {
}
else {
siblings = j;
@@ -1243,7 +1243,7 @@ static void cpu_bus_scan(device_t dev)
jj = siblings;
}
- for (j = 0; j <=jj; j++ ) {
+ for (j = 0; j <= jj; j++) {
u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
if (sysconf.enabled_apic_ext_id) {
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index aab9fa7..7fbe4ec 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -645,7 +645,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
value = spd_read_byte(device, 5); /* number of physical banks */
if (value < 0) goto hw_err;
if (value == 1) goto out;
- if ((value != 2) && (value != 4 )) {
+ if ((value != 2) && (value != 4)) {
goto val_err;
}
#if CONFIG_QRANK_DIMM_SUPPORT
@@ -760,7 +760,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map &= ~(0xf << (index * 4));
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz.rank == 4) {
- map &= ~(0xf << ( (index + 2) * 4));
+ map &= ~(0xf << ((index + 2) * 4));
}
#endif
@@ -771,7 +771,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map |= (sz.side1 - (25 + 3)) << (index *4);
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz.rank == 4) {
- map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
+ map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4);
}
#endif
}
@@ -779,7 +779,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz.rank == 4) {
- map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
+ map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4);
}
#endif
}
@@ -824,7 +824,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
limit = (limit_k << 2);
limit &= 0xffff0000;
limit -= 0x00010000;
- limit |= ( 0 << 8) | (node_id << 0);
+ limit |= (0 << 8) | (node_id << 0);
base = (base_k << 2);
base &= 0xffff0000;
base |= (0 << 8) | (1<<1) | (1<<0);
@@ -940,8 +940,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
}
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
- cs_mode =( value >> ((index>>1)*4)) & 0xf;
- if (cs_mode == 0 ) continue;
+ cs_mode =(value >> ((index>>1)*4)) & 0xf;
+ if (cs_mode == 0) continue;
if (common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
@@ -960,7 +960,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
}
/* Find the bits of csbase that we need to interleave on */
- if (is_cpu_pre_d0()){
+ if (is_cpu_pre_d0()) {
csbase_inc = 1 << csbase_low_shift[common_cs_mode];
if (is_dual_channel(ctrl)) {
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
@@ -974,8 +974,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
else {
csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
if (is_dual_channel(ctrl)) {
- if ( (bits==3) && (common_cs_mode > 8)) {
-// printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n");
+ if ((bits == 3) && (common_cs_mode > 8)) {
+// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n");
return 0;
}
csbase_inc <<=1;
@@ -1223,7 +1223,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
5, /* *Physical Banks */
6, /* *Module Data Width low */
7, /* *Module Data Width high */
- 9, /* *Cycle time at highest CAS Latency CL=X */
+ 9, /* *Cycle time at highest CAS Latency CL = X */
11, /* *SDRAM Type */
13, /* *SDRAM Width */
17, /* *Logical Banks */
@@ -1390,7 +1390,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_
/*
Following table comes directly from BKDG (unbuffered DIMM support)
- [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty
+ [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1 = present 0 = empty
X uses same layout but 1 means double rank 0 is single rank/empty
Following tables come from BKDG the ch{0_0,1_0,0_1,1_1} maps to
@@ -1674,7 +1674,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
#if 0
/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/
if (!is_cpu_pre_e0()) {
- if (min_cycle_time==0x50) {
+ if (min_cycle_time == 0x50) {
value |= 1<<31;
}
}
@@ -1927,7 +1927,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
dimm = 1<<(DCL_x4DIMM_SHIFT+i);
#if CONFIG_QRANK_DIMM_SUPPORT
- if (rank==4) {
+ if (rank == 4) {
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}
#endif
@@ -2239,7 +2239,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
carry_over = (4*1024*1024) - hole_startk;
- for (ii=controllers - 1;ii>i;ii--) {
+ for (ii = controllers - 1; ii > i; ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
@@ -2294,7 +2294,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
* we need to decrease it.
*/
uint32_t basek_pri;
- for (i=0; i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -2315,7 +2315,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
#endif
/* Find node number that needs the memory hole configured */
- for (i=0; i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -2480,7 +2480,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
4. if all ready enable node_interleaving in f1 0x40..... of every node
- 5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
+ 5. for node interleaving we need to set mem hole to every node (need recalcute hole offset in f0 for every node)
*/
}
@@ -2495,7 +2495,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
int i;
int j;
struct mem_controller *ctrl;
- for (i=0;i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
@@ -2505,7 +2505,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
if (spd_addr == (void *)0) continue;
- for (j=0;j<DIMM_SOCKETS;j++) {
+ for (j = 0; j < DIMM_SOCKETS; j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 67f3433..4ef621c 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -222,7 +222,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
/* DRAM Control Register
* F2:0x78
- * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
+ * [ 3: 0] RdPtrInit (Read Pointer Initial Value)
* 0x03-0x00: reserved
* [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
* 000 = reserved
@@ -361,7 +361,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 01 = 3 bus clocks
* 10 = 4 bus clocks
* 11 = 5 bus clocks
- * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
+ * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel A,
* BIOS should set it to reduce the power consumption)
* Bit F(1207) M2 Package S1g1 Package
* 0 N/A MA1_CLK1 N/A
@@ -400,22 +400,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 10 = 2 bus clocks
* 11 = 3 bus clocks
* [13:12] Twrwr (Write to Write Timing)
- * 00 = 1 bus clocks ( 0 idle cycle on the bus)
- * 01 = 2 bus clocks ( 1 idle cycle on the bus)
- * 10 = 3 bus clocks ( 2 idle cycles on the bus)
+ * 00 = 1 bus clocks (0 idle cycle on the bus)
+ * 01 = 2 bus clocks (1 idle cycle on the bus)
+ * 10 = 3 bus clocks (2 idle cycles on the bus)
* 11 = Reserved
- * [15:14] Trdrd ( Read to Read Timing)
- * 00 = 2 bus clocks ( 1 idle cycle on the bus)
- * 01 = 3 bus clocks ( 2 idle cycles on the bus)
- * 10 = 4 bus clocks ( 3 idle cycles on the bus)
- * 11 = 5 bus clocks ( 4 idle cycles on the bus)
+ * [15:14] Trdrd (Read to Read Timing)
+ * 00 = 2 bus clocks (1 idle cycle on the bus)
+ * 01 = 3 bus clocks (2 idle cycles on the bus)
+ * 10 = 4 bus clocks (3 idle cycles on the bus)
+ * 11 = 5 bus clocks (4 idle cycles on the bus)
* [17:16] Tref (Refresh Rate)
* 00 = Undefined behavior
* 01 = Reserved
* 10 = Refresh interval of 7.8 microseconds
* 11 = Refresh interval of 3.9 microseconds
* [19:18] Reserved
- * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
+ * [22:20] Trfc0 (Auto-Refresh Row Cycle Time for the Logical DIMM0,
* based on DRAM density and speed)
* 000 = 75 ns (all speeds, 256Mbit)
* 001 = 105 ns (all speeds, 512Mbit)
@@ -425,11 +425,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 101 = reserved
* 110 = reserved
* 111 = reserved
- * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
+ * [25:23] Trfc1 (Auto-Refresh Row Cycle Time for the Logical DIMM1,
* based on DRAM density and speed)
- * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
+ * [28:26] Trfc2 (Auto-Refresh Row Cycle Time for the Logical DIMM2,
* based on DRAM density and speed)
- * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
+ * [31:29] Trfc3 (Auto-Refresh Row Cycle Time for the Logical DIMM3,
* based on DRAM density and speed)
*/
PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
@@ -438,7 +438,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* [ 0: 0] InitDram (Initialize DRAM)
* 1 = write 1 cause DRAM controller to execute the DRAM
* initialization, when done it read to 0
- * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
+ * [ 1: 1] ExitSelfRef (Exit Self Refresh Command)
* 1 = write 1 causes the DRAM controller to bring the DRAMs out
* for self refresh mode
* [ 3: 2] Reserved
@@ -448,19 +448,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 10 = 150 ohms
* 11 = 50 ohms
* [ 6: 6] Reserved
- * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
+ * [ 7: 7] DramDrvWeak (DRAM Drivers Weak Mode)
* 0 = Normal drive strength mode.
* 1 = Weak drive strength mode
* [ 8: 8] ParEn (Parity Enable)
* 1 = Enable address parity computation output, PAR,
* and enables the parity error input, ERR
* [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
- * 1 = Enable high temperature ( two times normal )
+ * 1 = Enable high temperature (two times normal)
* self refresh rate
- * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
+ * [10:10] BurstLength32 (DRAM Burst Length Set for 32 Bytes)
* 0 = 64-byte mode
* 1 = 32-byte mode
- * [11:11] Width128 ( Width of DRAM interface)
+ * [11:11] Width128 (Width of DRAM interface)
* 0 = the controller DRAM interface is 64-bits wide
* 1 = the controller DRAM interface is 128-bits wide
* [12:12] X4Dimm (DIMM 0 is x4)
@@ -469,19 +469,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* [15:15] X4Dimm (DIMM 3 is x4)
* 0 = DIMM is not x4
* 1 = x4 DIMM present
- * [16:16] UnBuffDimm ( Unbuffered DIMMs)
+ * [16:16] UnBuffDimm (Unbuffered DIMMs)
* 0 = Buffered DIMMs
* 1 = Unbuffered DIMMs
* [18:17] Reserved
- * [19:19] DimmEccEn ( DIMM ECC Enable )
+ * [19:19] DimmEccEn (DIMM ECC Enable)
* 1 = ECC checking is being enabled for all DIMMs on the DRAM
- * controller ( Through F3 0x44[EccEn])
+ * controller (Through F3 0x44[EccEn])
* [31:20] Reserved
*/
PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
/* DRAM Config High Register
* F2:0x94
- * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
+ * [ 0: 2] MemClkFreq (Memory Clock Frequency)
* 000 = 200MHz
* 001 = 266MHz
* 010 = 333MHz
@@ -490,25 +490,25 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* [ 3: 3] MemClkFreqVal (Memory Clock Frequency Valid)
* 1 = BIOS need to set the bit when setting up MemClkFreq to
* the proper value
- * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
+ * [ 7: 4] MaxAsyncLat (Maximum Asynchronous Latency)
* 0000 = 0 ns
* ...
* 1111 = 15 ns
* [11: 8] Reserved
- * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
+ * [12:12] RDqsEn (Read DQS Enable) This bit is only be set if x8
* registered DIMMs are present in the system
* 0 = DM pins function as data mask pins
* 1 = DM pins function as read DQS pins
* [13:13] Reserved
- * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
+ * [14:14] DisDramInterface (Disable the DRAM interface) When this bit
* is set, the DRAM controller is disabled, and interface in low power
* state
* 0 = Enabled (default)
* 1 = Disabled
- * [15:15] PowerDownEn ( Power Down Mode Enable )
+ * [15:15] PowerDownEn (Power Down Mode Enable)
* 0 = Disabled (default)
* 1 = Enabled
- * [16:16] PowerDown ( Power Down Mode )
+ * [16:16] PowerDown (Power Down Mode)
* 0 = Channel CKE Control
* 1 = Chip Select CKE Control
* [17:17] FourRankSODimm (Four Rank SO-DIMM)
@@ -526,17 +526,17 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* i.e., these signals are driven for two MEMCLK cycles
* rather than one
* [21:21] Reserved
- * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
+ * [22:22] BankSwizzleMode (Bank Swizzle Mode),
* 0 = Disabled (default)
* 1 = Enabled
* [23:23] Reserved
- * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
+ * [27:24] DcqBypassMax (DRAM Controller Queue Bypass Maximum)
* 0000 = No bypass; the oldest request is never bypassed
* 0001 = The oldest request may be bypassed no more than 1 time
* ...
* 1111 = The oldest request may be bypassed no more than 15\
* times
- * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
+ * [31:28] FourActWindow (Four Bank Activate Window) , not more than
* 4 banks in a 8 bank device are activated
* 0000 = No tFAW window restriction
* 0001 = 8 MEMCLK cycles
@@ -552,11 +552,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* when set, this bit indicates that the memory clear function
* is complete. Only clear by reset. BIOS should not write or
* read the DRAM until this bit is set by hardware
- * [ 1: 1] DisableJitter ( Disable Jitter)
+ * [ 1: 1] DisableJitter (Disable Jitter)
* When set the DDR compensation circuit will not change the
* values unless the change is more than one step from the
* current value
- * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
+ * [ 3: 2] RdWrQByp (Read/Write Queue Bypass Count)
* 00 = 2
* 01 = 4
* 10 = 8
@@ -565,11 +565,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 1 When bit enables support for mismatched DIMMs when using
* 128-bit DRAM interface, the Width128 no effect, only for
* AM2 and s1g1
- * [ 5: 5] DCC_EN ( Dynamic Idle Cycle Counter Enable)
+ * [ 5: 5] DCC_EN (Dynamic Idle Cycle Counter Enable)
* When set to 1, indicates that each entry in the page tables
* dynamically adjusts the idle cycle limit based on page
* Conflict/Page Miss (PC/PM) traffic
- * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
+ * [ 8: 6] ILD_lmt (Idle Cycle Limit)
* 000 = 0 cycles
* 001 = 4 cycles
* 010 = 8 cycles
@@ -578,16 +578,16 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 101 = 64 cycles
* 110 = 128 cycles
* 111 = 256 cycles
- * [ 9: 9] DramEnabled ( DRAM Enabled)
+ * [ 9: 9] DramEnabled (DRAM Enabled)
* When Set, this bit indicates that the DRAM is enabled, this
* bit is set by hardware after DRAM initialization or on an exit
* from self refresh. The DRAM controller is initialized after the
- * hardware-controlled initialization process ( initiated by the
+ * hardware-controlled initialization process (initiated by the
* F2 0x90[DramInit]) completes or when the BIOS-controlled
* initialization process completes (F2 0x7c(EnDramInit] is
* written from 1 to 0)
* [23:10] Reserved
- * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
+ * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel B,
* BIOS should set it to reduce the power consumption)
* Bit F(1207) M2 Package S1g1 Package
* 0 N/A MA1_CLK1 N/A
@@ -785,7 +785,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
rank == 4 two side , and four ranks total
Some one side two ranks, because of stacked
*/
- if ((value != 1) && (value != 2) && (value != 4 )) {
+ if ((value != 1) && (value != 2) && (value != 4)) {
goto val_err;
}
sz->rank = value;
@@ -797,9 +797,9 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
if (value < 0) goto hw_err;
value &= 0xff;
value = log2(value);
- if (value <=4 ) value += 8; // add back to 1G to high
+ if (value <= 4) value += 8; // add back to 1G to high
value += (27-5); // make 128MB to the real lines
- if ( value != (sz->per_rank)) {
+ if (value != (sz->per_rank)) {
printk(BIOS_ERR, "Bad RANK Size --\n");
goto val_err;
}
@@ -836,12 +836,12 @@ static void set_dimm_size(const struct mem_controller *ctrl,
/* Make certain side1 of the dimm is at least 128MB */
if (sz->per_rank >= 27) {
- base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
+ base0 = (1 << ((sz->per_rank - 27) + 19)) | 1;
}
/* Make certain side2 of the dimm is at least 128MB */
if (sz->rank > 1) { // 2 ranks or 4 ranks
- base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
+ base1 = (1 << ((sz->per_rank - 27) + 19)) | 1;
}
/* Double the size if we are using dual channel memory */
@@ -954,7 +954,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
map &= ~(0xf << (index * 4));
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
- map &= ~(0xf << ( (index + 2) * 4));
+ map &= ~(0xf << ((index + 2) * 4));
}
#endif
@@ -965,7 +965,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
map |= temp_map << (index*4);
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
- map |= temp_map << ( (index + 2) * 4);
+ map |= temp_map << ((index + 2) * 4);
}
#endif
}
@@ -1018,7 +1018,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
limit = (limit_k << 2);
limit &= 0xffff0000;
limit -= 0x00010000;
- limit |= ( 0 << 8) | (node_id << 0);
+ limit |= (0 << 8) | (node_id << 0);
base = (base_k << 2);
base &= 0xffff0000;
base |= (0 << 8) | (1<<1) | (1<<0);
@@ -1136,7 +1136,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
}
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
- cs_mode =( value >> ((index>>1)*4)) & 0xf;
+ cs_mode =(value >> ((index>>1)*4)) & 0xf;
if (common_cs_mode == 0xff) {
common_cs_mode = cs_mode;
}
@@ -1351,8 +1351,8 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
if (is_opteron(ctrl)) {
#if 0
- if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
- meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffered dimm
+ if (registered != (meminfo->dimm_mask & ((1 << DIMM_SOCKETS)-1))) {
+ meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm
// die("Mixed buffered and registered dimms not supported");
}
//By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
@@ -1647,7 +1647,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
/* Check for FID control support */
struct cpuid_result cpuid1;
cpuid1 = cpuid(0x80000007);
- if ( cpuid1.edx & 0x02 ) {
+ if (cpuid1.edx & 0x02) {
/* Use current FID */
unsigned fid_cur;
msr = rdmsr(0xc0010042);
@@ -1663,9 +1663,9 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
index = fid_start>>25;
}
- if (index>12) return divisor;
+ if (index > 12) return divisor;
- if (i>3) return divisor;
+ if (i > 3) return divisor;
return dv_a[index * 4+i];
@@ -1748,7 +1748,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig
printk_raminit("\t\tvalue2: %08x\n", value);
/* Only increase the latency if we decrease the clock */
- if (value >= *min_cycle_time ) {
+ if (value >= *min_cycle_time) {
if (value < new_cycle_time) {
new_cycle_time = value;
new_latency = latency;
@@ -1763,7 +1763,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig
}
- if (new_latency > 6){
+ if (new_latency > 6) {
return 1;
}
@@ -2052,7 +2052,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_
static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
unsigned TT_REG,
- unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
+ unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX)
{
unsigned clocks, old_clocks;
uint32_t dtl;
@@ -2181,7 +2181,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl,
value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
if (value < 0) return -1;
- if (value == 1 ) {
+ if (value == 1) {
value = 3;
} else {
value = 2;
@@ -2267,7 +2267,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
mask_single_rank |= 1<<i;
}
- if (meminfo->sz[i].col==10) {
+ if (meminfo->sz[i].col == 10) {
mask_page_1k |= 1<<i;
}
@@ -2278,17 +2278,17 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
rank = meminfo->sz[i].rank;
#endif
- if (value==4) {
+ if (value == 4) {
mask_x4 |= (1<<i);
#if CONFIG_QRANK_DIMM_SUPPORT
- if (rank==4) {
+ if (rank == 4) {
mask_x4 |= 1<<(i+2);
}
#endif
- } else if (value==16) {
+ } else if (value == 16) {
mask_x16 |= (1<<i);
#if CONFIG_QRANK_DIMM_SUPPORT
- if (rank==4) {
+ if (rank == 4) {
mask_x16 |= 1<<(i+2);
}
#endif
@@ -2340,7 +2340,7 @@ static void set_DramTerm(const struct mem_controller *ctrl,
if (param->divisor == 100) { //DDR2 800
if (meminfo->is_Width128) {
- if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
+ if (count_ones(meminfo->dimm_mask & 0x0f) == 2) {
odt = 3; //50 ohms
}
}
@@ -2503,7 +2503,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
-#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */
static void set_SlowAccessMode(const struct mem_controller *ctrl)
{
uint32_t dch;
@@ -2524,23 +2524,23 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
{
uint32_t dword;
uint32_t dwordx;
-#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */
unsigned SlowAccessMode = 0;
#endif
-#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
+#if CONFIG_DIMM_SUPPORT == 0x0104 /* DDR2 and REG */
long dimm_mask = meminfo->dimm_mask & 0x0f;
/* for REG DIMM */
dword = 0x00111222;
dwordx = 0x002f0000;
switch (meminfo->memclk_set) {
case DCH_MemClkFreq_266MHz:
- if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
+ if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
dwordx = 0x002f2700;
}
break;
case DCH_MemClkFreq_333MHz:
- if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
+ if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
dwordx = 0x002f2f00;
}
@@ -2553,7 +2553,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
#endif
-#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
+#if CONFIG_DIMM_SUPPORT == 0x0204 /* DDR2 and SO-DIMM, S1G1 */
dword = 0x00111222;
dwordx = 0x002F2F00;
@@ -2593,7 +2593,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
}
#endif
-#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
+#if CONFIG_DIMM_SUPPORT == 0x0004 /* DDR2 and unbuffered */
long dimm_mask = meminfo->dimm_mask & 0x0f;
/* for UNBUF DIMM */
dword = 0x00111222;
@@ -2609,7 +2609,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
if (dimm_mask == 0x03) {
SlowAccessMode = 1;
dword = 0x00111322;
- if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
+ if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) {
switch (meminfo->single_rank_mask) {
case 0x03:
dwordx = 0x00002f00; //x8 single Rank
@@ -2620,14 +2620,14 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
default:
dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
}
- } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
+ } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
- } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
+ } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
}
} else {
- if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
+ if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
dwordx = 0x002f2f00;
} else {
dwordx = 0x002b2f00;
@@ -2639,7 +2639,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
if (dimm_mask == 0x03) {
SlowAccessMode = 1;
dword = 0x00111322;
- if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
+ if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) {
switch (meminfo->single_rank_mask) {
case 0x03:
dwordx = 0x00302220; //x8 single Rank
@@ -2676,7 +2676,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
printk_raminit("\tAddr Timing= %08x\n", dwordx);
#endif
-#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */
if (SlowAccessMode) {
set_SlowAccessMode(ctrl);
}
@@ -2707,7 +2707,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
static void set_RDqsEn(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
-#if CONFIG_CPU_SOCKET_TYPE==0x10
+#if CONFIG_CPU_SOCKET_TYPE == 0x10
//only need to set for reg and x8
uint32_t dch;
@@ -2749,7 +2749,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl,
for (i = 0; i < DIMM_SOCKETS; i++) {
int rc;
if (!(meminfo->dimm_mask & (1 << i)) &&
- !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
+ !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) {
continue;
}
printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
@@ -2911,17 +2911,17 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
carry_over = (4*1024*1024) - hole_startk;
- for (ii=controllers - 1;ii>i;ii--) {
+ for (ii = controllers - 1; ii > i; ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
- limit += (carry_over << 2 );
- base += (carry_over << 2 );
+ limit += (carry_over << 2);
+ base += (carry_over << 2);
for (j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
- pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
+ pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base);
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
@@ -2966,7 +2966,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
/* We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some */
uint32_t basek_pri;
- for (i=0; i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -2985,7 +2985,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
#endif
/* find node index that need do set hole */
- for (i=0; i < controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -3038,7 +3038,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
/* if no memory installed, disabled the interface */
- if (sysinfo->meminfo[i].dimm_mask==0x00){
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) {
dch |= DCH_DisDramInterface;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
@@ -3046,7 +3046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
dch |= DCH_MemClkFreqVal;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
/* address timing and Output driver comp Control */
- set_misc_timing(ctrl+i, sysinfo->meminfo+i );
+ set_misc_timing(ctrl+i, sysinfo->meminfo+i);
}
}
@@ -3108,7 +3108,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
if (!sysinfo->ctrl_present[ i ])
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "Initializing memory: ");
int loops = 0;
@@ -3127,7 +3127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
/* Wait until it is safe to touch memory */
do {
dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
- } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
+ } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/);
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
if (cpu_f0_f1[i]) {
@@ -3136,7 +3136,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
- if (tsc.lo<tsc0[i].lo) {
+ if (tsc.lo < tsc0[i].lo) {
tsc.hi--;
}
tsc.lo -= tsc0[i].lo;
@@ -3176,7 +3176,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00)
+ if (sysinfo->meminfo[i].dimm_mask == 0x00)
continue;
sysinfo->mem_trained[i] = 0x80; // mem need to be trained
@@ -3226,7 +3226,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
int i;
int j;
struct mem_controller *ctrl;
- for (i=0;i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
@@ -3236,7 +3236,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
if (spd_addr == (void *)0) continue;
- for (j=0;j<DIMM_SOCKETS;j++) {
+ for (j = 0; j < DIMM_SOCKETS; j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 9f0b8db..2d05951 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -58,10 +58,10 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct
{
int i;
- sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3));
+ sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid << 3));
- for (i=0;i<8; i++) {
- sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2));
+ for (i = 0; i < 8; i++) {
+ sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i << 2));
}
sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0);
@@ -90,9 +90,9 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_id
hole_reg = sysinfo->hole_reg[nodeid];
if (hole_reg & 1) {
unsigned hole_startk;
- hole_startk = (hole_reg & (0xff<<24)) >> 10;
- if ( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) {
- dword += ((4*1024*1024 - hole_startk)<<2);
+ hole_startk = (hole_reg & (0xff << 24)) >> 10;
+ if ((dword >= (hole_startk << 2)) && (dword < ((4*1024*1024) << 2))) {
+ dword += ((4*1024*1024 - hole_startk) << 2);
}
}
#endif
@@ -197,12 +197,12 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n
static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b)
{
uint8_t *buf;
- if (p==1) { buf = buf_b; }
+ if (p == 1) { buf = buf_b; }
else { buf = buf_a; }
- set_FSBASE (addr>>24);
+ set_FSBASE (addr >> 24);
- WriteLNTestPattern(addr<<8, buf, 1);
+ WriteLNTestPattern(addr << 8, buf, 1);
}
static void Read1LTestPattern(unsigned addr)
@@ -214,7 +214,7 @@ static void Read1LTestPattern(unsigned addr)
/* 1st move causes read fill (to exclusive or shared)*/
__asm__ volatile (
"movl %%fs:(%1), %0\n\t"
- :"=b"(value): "a" (addr<<8)
+ :"=b"(value): "a" (addr << 8)
);
}
@@ -243,7 +243,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
unsigned result = DQS_FAIL;
if (Pass == DQS_FIRST_PASS) {
- if (pattern==1) {
+ if (pattern == 1) {
test_buf = (uint32_t *)TestPattern1;
}
else {
@@ -254,9 +254,9 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
test_buf = (uint32_t *)TestPattern2;
}
- set_FSBASE(addr>>24);
+ set_FSBASE(addr >> 24);
- addr_lo = addr<<8;
+ addr_lo = addr << 8;
if (is_Width128 && (channel == 1)) {
addr_lo += 8; //second channel
@@ -285,13 +285,13 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4);
print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4);
- if (value == value_test){
+ if (value == value_test) {
result = DQS_PASS;
}
}
if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted
- if (result==DQS_PASS) {
+ if (result == DQS_PASS) {
result = DQS_FAIL;
}
else {
@@ -314,7 +314,7 @@ static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly)
reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
- reg &= ~(DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
+ reg &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
reg |= ((dly - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, reg);
@@ -327,8 +327,8 @@ static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly)
static void SetTargetWTIO(unsigned addr)
{
msr_t msr;
- msr.hi = addr>>24;
- msr.lo = addr<<8;
+ msr.hi = addr >> 24;
+ msr.lo = addr << 8;
wrmsr(0xc0010016, msr); //IORR0 BASE
msr.hi = 0xff;
@@ -354,7 +354,7 @@ static void proc_CLFLUSH(unsigned addr)
__asm__ volatile (
/* clflush fs:[eax] */
"clflush %%fs:(%0)\n\t"
- ::"a" (addr<<8)
+ ::"a" (addr << 8)
);
}
@@ -409,7 +409,7 @@ static uint16_t get_exact_T1000(unsigned i)
/* Check for FID control support */
struct cpuid_result cpuid1;
cpuid1 = cpuid(0x80000007);
- if ( cpuid1.edx & 0x02 ) {
+ if (cpuid1.edx & 0x02) {
/* Use current FID */
unsigned fid_cur;
msr = rdmsr(0xc0010042);
@@ -425,7 +425,7 @@ static uint16_t get_exact_T1000(unsigned i)
index = fid_start>>25;
}
- if (index>12) return T1000_a[i];
+ if (index > 12) return T1000_a[i];
return TT_a[index * 4+i];
@@ -437,14 +437,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl)
uint32_t dword;
dword = 0x00000000;
- for (i=1; i<=3; i++) {
+ for (i = 1; i <= 3; i++) {
/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */
pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
}
dword = 0x2f2f2f2f;
- for (i=5; i<=7; i++) {
+ for (i = 5; i <= 7; i++) {
/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */
pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
@@ -554,14 +554,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
// SetupRcvrPattern
buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0));
buf_b = buf_a + 128; //??
- if (Pass==DQS_FIRST_PASS) {
- for (i=0;i<16;i++) {
+ if (Pass == DQS_FIRST_PASS) {
+ for (i = 0; i < 16; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPattern0[i];
*((uint32_t *)(buf_b + i*4)) = TestPattern1[i];
}
}
else {
- for (i=0;i<16;i++) {
+ for (i = 0; i < 16; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPattern2[i];
*((uint32_t *)(buf_b + i*4)) = TestPattern2[i];
}
@@ -581,13 +581,13 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
channel = 1;
}
- for ( ; (channel < 2) && (!Errors); channel++)
+ for (; (channel < 2) && (!Errors); channel++)
{
print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1);
/* for each rank */
/* there are four receiver pairs, loosely associated with CS */
- for ( receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
+ for (receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
{
unsigned index=(receiver>>1) * 3 + 0x10;
@@ -642,7 +642,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver];
}
- while ( RcvrEnDly < 0xaf) { // Sweep Delay value here
+ while (RcvrEnDly < 0xaf) { // Sweep Delay value here
print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3);
if (RcvrEnDly & 1) {
@@ -841,7 +841,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay);
#endif
- return (CTLRMaxDelay==0xae)?1:0;
+ return (CTLRMaxDelay == 0xae)?1:0;
}
@@ -859,14 +859,14 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel,
index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2);
shift = bytelane;
- while (shift>3) {
+ while (shift > 3) {
shift-=4;
}
shift <<= 3; // 8 bit
dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index);
- dword &= ~(0x3f<<shift);
- dword |= (dqs_delay<<shift);
+ dword &= ~(0x3f << shift);
+ dword |= (dqs_delay << shift);
pci_write_config32_index_wait(ctrl->f2, 0x98, index, dword);
}
@@ -879,13 +879,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe
dword = 0;
dqs_delay &= 0xff;
- for (i=0;i<4;i++) {
- dword |= dqs_delay<<(i*8);
+ for (i = 0; i < 4; i++) {
+ dword |= dqs_delay << (i*8);
}
index = 1 + channel * 0x20 + direction * 4;
- for (i=0; i<2; i++) {
+ for (i = 0; i < 2; i++) {
pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword);
}
@@ -898,7 +898,7 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d)
if (size_d & 1) { //need round up
min_d++;
}
- return ( min_d + (size_d>>1));
+ return (min_d + (size_d>>1));
}
static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay)
@@ -1026,10 +1026,10 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo)
);
}
-static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern )
+static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern)
{
- if (pattern == 0){
+ if (pattern == 0) {
FlushDQSTestPattern_L9(addr_lo);
}
else {
@@ -1056,7 +1056,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign
}
bytelane = 0;
- for (i=0;i<9*64/4;i++) {
+ for (i = 0; i < 9*64/4; i++) {
__asm__ volatile (
"movl %%fs:(%1), %0\n\t"
:"=b"(value): "a" (addr_lo)
@@ -1066,9 +1066,9 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign
print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7);
print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7);
- for (j=0;j<4*8;j+=8) {
+ for (j = 0; j < 4*8; j+=8) {
if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) {
- bitmap &= ~(1<<bytelane);
+ bitmap &= ~(1 << bytelane);
}
bytelane++;
@@ -1116,7 +1116,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
- for (DQSDelay=0; DQSDelay<48; DQSDelay++) {
+ for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) {
MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS)
}
@@ -1135,25 +1135,25 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
if (Direction == DQS_READDIR) {
print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read so write at first", 0, 4);
- WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a);
+ WriteDQSTestPattern(TestAddr << 8, Pattern, buf_a);
}
- for (DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){
+ for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5);
if (MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes
SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay);
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
if (Direction == DQS_WRITEDIR) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5);
- WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a);
+ WriteDQSTestPattern(TestAddr << 8, Pattern, buf_a);
}
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5);
- ReadDQSTestPattern(TestAddr<<8, Pattern);
+ ReadDQSTestPattern(TestAddr << 8, Pattern);
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
- MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass
+ MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr << 8, Pattern, buf_a); //0: fail, 1=pass
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
SetTargetWTIO(TestAddr);
- FlushDQSTestPattern(TestAddr<<8, Pattern);
+ FlushDQSTestPattern(TestAddr << 8, Pattern);
ResetTargetWTIO();
}
}
@@ -1166,8 +1166,8 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
RnkDlySeqPassMax = 0;
RnkDlyFilterMax = 0;
RnkDlyFilterMin = 0;
- for (DQSDelay=0; DQSDelay<48; DQSDelay++) {
- if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) {
+ for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) {
+ if (MutualCSPassW[DQSDelay] & (1 << ByteLane)) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5);
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
@@ -1176,7 +1176,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
if (LastTest == DQS_FAIL) {
RnkDlySeqPassMin = DQSDelay; //start sequential run
}
- if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){
+ if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) {
RnkDlyFilterMin = RnkDlySeqPassMin;
RnkDlyFilterMax = RnkDlySeqPassMax;
}
@@ -1194,7 +1194,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
else {
print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4);
print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4);
- if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){
+ if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW) {
Errors |= SB_SMALLDQS;
}
else {
@@ -1371,15 +1371,15 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
//SetupDqsPattern
buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf));
- if (is_Width128){
+ if (is_Width128) {
pattern = 1;
- for (i=0;i<16*18;i++) {
+ for (i = 0; i < 16*18; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i];
}
}
else {
pattern = 0;
- for (i=0; i<16*9;i++) {
+ for (i = 0; i < 16*9; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i];
}
@@ -1397,7 +1397,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
channel = 1;
}
- while ( (channel<2) && (!Errors)) {
+ while ((channel < 2) && (!Errors)) {
print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1);
for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) {
unsigned err;
@@ -1417,7 +1417,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
}
channel++;
- if (!is_Width128){
+ if (!is_Width128) {
//FIXME: 64MuxMode??
channel++; // skip channel if 64-bit mode
}
@@ -1458,7 +1458,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte
DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a);
DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a);
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay = DQSDelay0 - DQSDelay1;
InterFactor = 0xff - InterFactor;
}
@@ -1470,7 +1470,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte
DQSDelay >>= 8; // /255
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay += DQSDelay1;
}
else {
@@ -1496,11 +1496,11 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info
ByteLane = 8;
for (channel = 0; channel < 2; channel++) {
- for (i=0;i<2;i++) {
+ for (i = 0; i < 2; i++) {
Direction = direction[i];
lane0 = 4; lane1 = 5; ratio = 0;
dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a);
- print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2);
+ print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2);
SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay);
save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay);
}
@@ -1546,7 +1546,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
uint32_t dword;
@@ -1568,7 +1568,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
dword = tsc1[i].lo + tsc0[i].lo;
- if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) {
+ if ((dword < tsc1[i].lo) || (dword < tsc0[i].lo)) {
tsc1[i].hi++;
}
tsc1[i].lo = dword;
@@ -1583,7 +1583,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
if (!cpu_f0_f1[i]) continue;
@@ -1591,7 +1591,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
do {
tsc = rdtsc();
- } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo)));
+ } while ((tsc1[i].hi > tsc.hi) || ((tsc1[i].hi == tsc.hi) && (tsc1[i].lo > tsc.lo)));
print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2);
}
@@ -1661,8 +1661,8 @@ static unsigned int range_to_mtrr(unsigned int reg,
#if CONFIG_MEM_TRAIN_SEQ != 1
printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
- (type==MTRR_TYPE_UNCACHEABLE)?"UC":
- ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
+ (type == MTRR_TYPE_UNCACHEABLE)?"UC":
+ ((type == MTRR_TYPE_WRBACK)?"WB":"Other")
);
#endif
set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits);
@@ -1737,7 +1737,7 @@ static void clear_mtrr_dqs(unsigned tom2_k)
wrmsr(0x258, msr);
//[1M, TOM)
- for (i=0x204;i<0x210;i++) {
+ for (i = 0x204; i < 0x210; i++) {
wrmsr(i, msr);
}
@@ -1755,8 +1755,8 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
{
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
- dword &= ~(1<<bit);
- dword |= ((val & 1) <<bit);
+ dword &= ~(1 << bit);
+ dword |= ((val & 1) << bit);
pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword);
}
@@ -1764,7 +1764,7 @@ static unsigned get_htic_bit(unsigned i, unsigned bit)
{
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
- dword &= (1<<bit);
+ dword &= (1 << bit);
return dword;
}
@@ -1865,7 +1865,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev)
pos = dqs_load_MC_NVRAM_ch(dev, 1, pos);
/* load the maxasync lat here */
pos = s3_load_nvram_early(4, ®, pos);
- reg &= (DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
+ reg &= (DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
reg |= pci_read_config32(dev, DRAM_CONFIG_HIGH);
pci_write_config32(dev, DRAM_CONFIG_HIGH, reg);
}
@@ -1890,7 +1890,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
fill_mem_cs_sysinfo(i, ctrl+i, sysinfo);
}
@@ -1901,7 +1901,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
@@ -1919,7 +1919,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
if (train_DqsPos(ctrl+i, sysinfo)) goto out;
@@ -1932,7 +1932,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
@@ -1948,7 +1948,7 @@ out:
clear_mtrr_dqs(sysinfo->tom2_k);
- for (i=0;i<5;i++) {
+ for (i = 0; i < 5; i++) {
print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo);
}
@@ -2004,7 +2004,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
}
- if (train_DqsRcvrEn(ctrl, 2, sysinfo)){
+ if (train_DqsRcvrEn(ctrl, 2, sysinfo)) {
sysinfo->mem_trained[i]=0x83; //
goto out;
}
@@ -2021,7 +2021,7 @@ out:
#endif
if (v) {
- for (ii=0;ii<4;ii++) {
+ for (ii = 0; ii < 4; ii++) {
print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo);
}
}
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index fa03e4a..e6e79c8 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -50,9 +50,9 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
#if RES_DEBUG
printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i>>2, register_values[i],
- register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
+ register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
- register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
+ register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
);
#endif
switch (register_values[i]) {
@@ -103,7 +103,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
reg = read32(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
- write32( where, reg);
+ write32(where, reg);
}
break;
#endif
@@ -174,7 +174,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max)
reg = read32(where);
reg &= register_values[i+1];
reg |= register_values[i+2];
- write32( where, reg);
+ write32(where, reg);
#if 0
reg = read32(where);
prink(BIOS_DEBUG, " RB %08x\n", reg);
diff --git a/src/northbridge/amd/amdk8/util.asl b/src/northbridge/amd/amdk8/util.asl
index 6a9b69f..83d741e 100644
--- a/src/northbridge/amd/amdk8/util.asl
+++ b/src/northbridge/amd/amdk8/util.asl
@@ -44,9 +44,9 @@ Scope (\_SB)
Method (DADD, 2, NotSerialized)
{
- Store( Arg1, Local0)
- Store( Arg0, Local1)
- Add( ShiftLeft(Local1,16), Local0, Local0)
+ Store(Arg1, Local0)
+ Store(Arg0, Local1)
+ Add(ShiftLeft(Local1,16), Local0, Local0)
Return (Local0)
}
@@ -54,7 +54,7 @@ Scope (\_SB)
Method (GHCE, 1, NotSerialized) // check if the HC enabled
{
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) }
Else { Return (0x00) }
}
@@ -62,7 +62,7 @@ Scope (\_SB)
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+ Store (ShiftRight(And (Local1, 0xf0), 0x04), Local0)
Return (Local0)
}
@@ -70,7 +70,7 @@ Scope (\_SB)
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+ Store (ShiftRight(And (Local1, 0xf00), 0x08), Local0)
Return (Local0)
}
@@ -80,7 +80,7 @@ Scope (\_SB)
Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
- Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+ Store (And (ShiftRight(Local1, Local2), 0xff), Local0)
Return (Local0)
}
1
0
Patch set updated for coreboot: northbridge/amd/amdmct: Improve code formatting
by Martin Roth 21 Sep '16
by Martin Roth 21 Sep '16
21 Sep '16
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16643
-gerrit
commit f7f041532f585d46ee34aa526176dda82c361323
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 10:25:41 2016 -0600
northbridge/amd/amdmct: Improve code formatting
Change-Id: If87718b6c91d79212a9b045f5fda32d69ac4caee
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/northbridge/amd/amdmct/amddefs.h | 4 +-
src/northbridge/amd/amdmct/mct/mct.h | 202 ++++++++++----------
src/northbridge/amd/amdmct/mct/mct_d.c | 234 ++++++++++++------------
src/northbridge/amd/amdmct/mct/mct_d.h | 220 +++++++++++-----------
src/northbridge/amd/amdmct/mct/mct_d_gcc.h | 12 +-
src/northbridge/amd/amdmct/mct/mctardk3.c | 2 +-
src/northbridge/amd/amdmct/mct/mctardk4.c | 2 +-
src/northbridge/amd/amdmct/mct/mctchi_d.c | 4 +-
src/northbridge/amd/amdmct/mct/mctcsi_d.c | 16 +-
src/northbridge/amd/amdmct/mct/mctdqs_d.c | 52 +++---
src/northbridge/amd/amdmct/mct/mctecc_d.c | 30 +--
src/northbridge/amd/amdmct/mct/mctgr.c | 6 +-
src/northbridge/amd/amdmct/mct/mctmtr_d.c | 28 +--
src/northbridge/amd/amdmct/mct/mctndi_d.c | 10 +-
src/northbridge/amd/amdmct/mct/mctpro_d.c | 26 +--
src/northbridge/amd/amdmct/mct/mctsrc.c | 52 +++---
src/northbridge/amd/amdmct/mct/mctsrc1p.c | 2 +-
src/northbridge/amd/amdmct/mct/mctsrc2p.c | 6 +-
src/northbridge/amd/amdmct/mct/mcttmrl.c | 24 +--
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 128 ++++++-------
src/northbridge/amd/amdmct/mct_ddr3/mct_d.h | 220 +++++++++++-----------
src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h | 12 +-
src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c | 2 +-
src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c | 6 +-
src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c | 2 +-
src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 44 ++---
src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 28 +--
src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c | 28 +--
src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c | 10 +-
src/northbridge/amd/amdmct/mct_ddr3/mctrci.c | 4 +-
src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c | 6 +-
src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 56 +++---
src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c | 2 +-
src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c | 6 +-
src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c | 20 +-
src/northbridge/amd/amdmct/mct_ddr3/mctwl.c | 10 +-
src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 82 ++++-----
src/northbridge/amd/amdmct/mct_ddr3/s3utils.c | 110 +++++------
src/northbridge/amd/amdmct/wrappers/mcti.h | 2 +-
src/northbridge/amd/amdmct/wrappers/mcti_d.c | 22 +--
40 files changed, 866 insertions(+), 866 deletions(-)
diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h
index bbdd2ed..9d3e86a 100644
--- a/src/northbridge/amd/amdmct/amddefs.h
+++ b/src/northbridge/amd/amdmct/amddefs.h
@@ -74,8 +74,8 @@
#define AMD_FAM10_REV_D (AMD_HY_D0 | AMD_HY_D1)
#define AMD_DA_Cx (AMD_DA_C2 | AMD_DA_C3)
#define AMD_FAM10_C3 (AMD_RB_C3 | AMD_DA_C3)
-#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0 )
-#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2 )
+#define AMD_DRBH_Cx (AMD_DR_Cx | AMD_HY_D0)
+#define AMD_DRBA23_RBC2 (AMD_DR_BA | AMD_DR_B2 | AMD_DR_B3 | AMD_RB_C2)
#define AMD_DR_DAC2_OR_C3 (AMD_DA_C2 | AMD_DA_C3 | AMD_RB_C3)
#define AMD_FAM15_ALL (AMD_OR_B2 | AMD_OR_C0)
diff --git a/src/northbridge/amd/amdmct/mct/mct.h b/src/northbridge/amd/amdmct/mct/mct.h
index 61b2b2b..3847688 100644
--- a/src/northbridge/amd/amdmct/mct/mct.h
+++ b/src/northbridge/amd/amdmct/mct/mct.h
@@ -23,16 +23,16 @@
#define PT_M2 1
#define PT_S1 2
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
-#define J_MAX 4 /* j loop constraint. 4=CL 6.0 T*/
-#define K_MIN 1 /* k loop constraint. 1=200 MHz*/
-#define K_MAX 4 /* k loop constraint. 9=400 MHz*/
-#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
-#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
-
-#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
+#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/
+#define J_MAX 4 /* j loop constraint. 4 = CL 6.0 T*/
+#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/
+#define K_MAX 4 /* k loop constraint. 9 = 400 MHz*/
+#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/
+#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/
+
+#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/
/* memory initialization (ecc and check-bits).*/
- /* 1=40 ns/64 bytes.*/
+ /* 1 = 40 ns/64 bytes.*/
#define FirstPass 1 /* First pass through RcvEn training*/
#define SecondPass 2 /* Second pass through Rcven training*/
@@ -208,7 +208,7 @@ struct DCTStatStruc { /* A per Node structure*/
/* SPD address of..MB2_CS_L[0,1]*/
/* SPD address of..MA3_CS_L[0,1]*/
/* SPD address of..MB3_CS_L[0,1]*/
- u16 DIMMPresent; /* For each bit n 0..7, 1=DIMM n is present.
+ u16 DIMMPresent; /* For each bit n 0..7, 1 = DIMM n is present.
DIMM# Select Signal
0 MA0_CS_L[0,1]
1 MB0_CS_L[0,1]
@@ -218,14 +218,14 @@ struct DCTStatStruc { /* A per Node structure*/
5 MB2_CS_L[0,1]
6 MA3_CS_L[0,1]
7 MB3_CS_L[0,1]*/
- u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
- u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
- u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
- u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
- u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
- u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
- u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
- u16 DIMM1Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
+ u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/
+ u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/
+ u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/
+ u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/
+ u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/
+ u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/
+ u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/
+ u16 DIMM1Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/
u8 MAload[2]; /* Number of devices loading MAA bus*/
/* Number of devices loading MAB bus*/
u8 MAdimms[2]; /* Number of DIMMs loading CH A*/
@@ -233,16 +233,16 @@ struct DCTStatStruc { /* A per Node structure*/
u8 DATAload[2]; /* Number of ranks loading CH A DATA*/
/* Number of ranks loading CH B DATA*/
u8 DIMMAutoSpeed; /* Max valid Mfg. Speed of DIMMs
- 1=200MHz
- 2=266MHz
- 3=333MHz
- 4=400MHz */
+ 1 = 200MHz
+ 2 = 266MHz
+ 3 = 333MHz
+ 4 = 400MHz */
u8 DIMMCASL; /* Min valid Mfg. CL bitfield
- 0=2.0
- 1=3.0
- 2=4.0
- 3=5.0
- 4=6.0 */
+ 0 = 2.0
+ 1 = 3.0
+ 2 = 4.0
+ 3 = 5.0
+ 4 = 6.0 */
u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
@@ -252,16 +252,16 @@ struct DCTStatStruc { /* A per Node structure*/
u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
u8 Speed; /* Bus Speed (to set Controller)
- 1=200MHz
- 2=266MHz
- 3=333MHz
- 4=400MHz */
+ 1 = 200MHz
+ 2 = 266MHz
+ 3 = 333MHz
+ 4 = 400MHz */
u8 CASL; /* CAS latency DCT setting
- 0=2.0
- 1=3.0
- 2=4.0
- 3=5.0
- 4=6.0 */
+ 0 = 2.0
+ 1 = 3.0
+ 2 = 4.0
+ 3 = 5.0
+ 4 = 6.0 */
u8 Trcd; /* DCT Trcd (busclocks) */
u8 Trp; /* DCT Trp (busclocks) */
u8 Trtp; /* DCT Trtp (busclocks) */
@@ -271,27 +271,27 @@ struct DCTStatStruc { /* A per Node structure*/
u8 Trrd; /* DCT Trrd (busclocks) */
u8 Twtr; /* DCT Twtr (busclocks) */
u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
- 0=75ns (for 256Mb devs)
- 1=105ns (for 512Mb devs)
- 2=127.5ns (for 1Gb devs)
- 3=195ns (for 2Gb devs)
- 4=327.5ns (for 4Gb devs) */
+ 0 = 75ns (for 256Mb devs)
+ 1 = 105ns (for 512Mb devs)
+ 2 = 127.5ns (for 1Gb devs)
+ 3 = 195ns (for 2Gb devs)
+ 4 = 327.5ns (for 4Gb devs) */
/* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
/* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
/* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
- u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
- u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
+ u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */
+ u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */
u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
- 200=200MHz (DDR400)
- 266=266MHz (DDR533)
- 333=333MHz (DDR667)
- 400=400MHz (DDR800) */
+ 200 = 200MHz (DDR400)
+ 266 = 266MHz (DDR533)
+ 333 = 333MHz (DDR667)
+ 400 = 400MHz (DDR800) */
u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
- 1=1T
- 2=2T */
+ 1 = 1T
+ 2 = 2T */
u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
u8 Twrrd; /* DCT Twrrd (busclocks)*/
u8 Twrwr; /* DCT Twrwr (busclocks)*/
@@ -319,9 +319,9 @@ struct DCTStatStruc { /* A per Node structure*/
/* CHB DIMM 0 - 3 Receiver Enable Delay*/
u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
u32 PtrPatternBufB; /*Ptr on stack to aligned DQS testing pattern*/
- u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
+ u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/
u8 ByteLane; /* Current Byte Lane (0..7)*/
- u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
+ u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/
u8 Pattern; /* Current pattern*/
u8 DQSDelay; /* Current DQS delay value*/
u32 TrainErrors; /* Current Training Errors*/
@@ -399,72 +399,72 @@ struct DCTStatStruc { /* A per Node structure*/
===============================================================================*/
/* Platform Configuration */
#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
- 0=NPT L1
- 1=NPT M2
- 2=NPT S1*/
+ 0 = NPT L1
+ 1 = NPT M2
+ 2 = NPT S1*/
#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
- 200=200MHz (DDR400)
- 266=266MHz (DDR533)
- 333=333MHz (DDR667)
- 400=400MHz (DDR800)*/
+ 200 = 200MHz (DDR400)
+ 266 = 266MHz (DDR533)
+ 333 = 333MHz (DDR667)
+ 400 = 400MHz (DDR800)*/
#define NV_ECC_CAP 4 /* Bus ECC capable (1-bits)
- 0=Platform not capable
- 1=Platform is capable*/
+ 0 = Platform not capable
+ 1 = Platform is capable*/
#define NV_4RANKType 5 /* Quad Rank DIMM slot type (2-bits)
- 0=Normal
- 1=R4 (4-Rank Registered DIMMs in AMD server configuration)
- 2=S4 (Unbuffered SO-DIMMs)*/
+ 0 = Normal
+ 1 = R4 (4-Rank Registered DIMMs in AMD server configuration)
+ 2 = S4 (Unbuffered SO-DIMMs)*/
#define NV_BYPMAX 6 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
- 4=4 times bypass (normal for non-UMA systems)
- 7=7 times bypass (normal for UMA systems)*/
+ 4 = 4 times bypass (normal for non-UMA systems)
+ 7 = 7 times bypass (normal for UMA systems)*/
#define NV_RDWRQBYP 7 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
- 2=8 times (normal for non-UMA systems)
- 3=16 times (normal for UMA systems)*/
+ 2 = 8 times (normal for non-UMA systems)
+ 3 = 16 times (normal for UMA systems)*/
/* Dram Timing */
#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
- 0=Auto, no user limit
- 1=Auto, user limit provided in NV_MemCkVal
- 2=Manual, user value provided in NV_MemCkVal*/
+ 0 = Auto, no user limit
+ 1 = Auto, user limit provided in NV_MemCkVal
+ 2 = Manual, user value provided in NV_MemCkVal*/
#define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
- 0=200MHz
- 1=266MHz
- 2=333MHz
- 3=400MHz*/
+ 0 = 200MHz
+ 1 = 266MHz
+ 2 = 333MHz
+ 3 = 400MHz*/
/* Dram Configuration */
#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
- 0=normal
- 1=enable all memclocks*/
+ 0 = normal
+ 1 = enable all memclocks*/
#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
- 0=Exit current node init if any DIMM has SPD checksum error
- 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
+ 0 = Exit current node init if any DIMM has SPD checksum error
+ 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
- 0=skip DQS training
- 1=perform DQS training*/
+ 0 = skip DQS training
+ 1 = perform DQS training*/
#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_BurstLen32 25 /* burstLength32 for 64-bit mode (1-bits)
- 0=disable (normal)
- 1=enable (4 beat burst when width is 64-bits)*/
+ 0 = disable (normal)
+ 1 = enable (4 beat burst when width is 64-bits)*/
/* Dram Power */
#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
- 0=per Channel control
- 1=per Chip select control*/
+ 0 = per Channel control
+ 1 = per Chip select control*/
#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
/* Memory Map/Mgt.*/
#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
@@ -472,8 +472,8 @@ struct DCTStatStruc { /* A per Node structure*/
#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
NV_BottomUMA[7:0]=Addr[31:24]*/
#define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
- 0=disable
- 1=enable */
+ 0 = disable
+ 1 = enable */
/* ECC */
#define NV_ECC 50 /* Dram ECC enable*/
@@ -484,14 +484,14 @@ struct DCTStatStruc { /* A per Node structure*/
#define NV_L2BKScrub 56 /* L2 ECC Background Scrubber CTL*/
#define NV_DCBKScrub 57 /* DCache ECC Background Scrubber CTL*/
#define NV_CS_SpareCTL 58 /* Chip Select Spare Control bit 0:
- 0=disable Spare
- 1=enable Spare */
+ 0 = disable Spare
+ 1 = enable Spare */
/*Chip Select Spare Control bit 1-4:
Reserved, must be zero*/
#define NV_Parity 60 /* Parity Enable*/
#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
/* global function */
@@ -505,11 +505,11 @@ void K8FInterleaveBanks(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
void mctInitWithWritetoCS(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
void mctGet_PS_Cfg(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat);
-void Get_ChannelPS_Cfg0( unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload,
+void Get_ChannelPS_Cfg0(unsigned MAAdimms, unsigned Speed, unsigned MAAload, unsigned DATAAload,
unsigned *AddrTmgCTL, unsigned *ODC_CTL);
-void Get_ChannelPS_Cfg1( unsigned MAAdimms, unsigned Speed, unsigned MAAload,
+void Get_ChannelPS_Cfg1(unsigned MAAdimms, unsigned Speed, unsigned MAAload,
unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val);
-void Get_ChannelPS_Cfg2( unsigned MAAdimms, unsigned Speed, unsigned MAAload,
+void Get_ChannelPS_Cfg2(unsigned MAAdimms, unsigned Speed, unsigned MAAload,
unsigned *AddrTmgCTL, unsigned *ODC_CTL, unsigned *val);
u8 MCTDefRet(void);
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.c b/src/northbridge/amd/amdmct/mct/mct_d.c
index 16e67df..87863b1 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct/mct_d.c
@@ -195,7 +195,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
* 1. Complete Hypertransport Bus Configuration
* 2. SMBus Controller Initialized
* 3. Checksummed or Valid NVRAM bits
- * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs
+ * 4. MCG_CTL=-1, MC4_CTL_EN = 0 for all CPUs
* 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to
* entry
* 6. All var MTRRs reset to zero
@@ -308,7 +308,7 @@ restartinit:
MCTMemClr_D(pMCTstat,pDCTstatA);
}
- mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0) ); // Node 0
+ mct_FinalMCT_D(pMCTstat, (pDCTstatA + 0)); // Node 0
print_tx("mctAutoInitMCT_D Done: Global Status: ", pMCTstat->GStatus);
return;
@@ -434,7 +434,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
}
}
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
SetEccDQSRcvrEn_D(pDCTstat, Channel);
}
@@ -452,7 +452,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
* + 0x100 to next dimm
*/
for (DIMM = 0; DIMM < 2; DIMM++) {
- if (DIMM==0) {
+ if (DIMM == 0) {
index = 0; /* CHA Write Data Timing Low */
} else {
if (pDCTstat->Speed >= 4) {
@@ -461,7 +461,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
break;
}
}
- for (Dir=0;Dir<2;Dir++) {//RD/WR
+ for (Dir = 0; Dir < 2; Dir++) {//RD/WR
p = pDCTstat->CH_D_DIR_B_DQS[Channel][DIMM][Dir];
val = stream_to_int(p); /* CHA Read Data Timing High */
Set_NB32_index_wait(dev, index_reg, index+1, val);
@@ -474,12 +474,12 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
}
}
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
reg = 0x78 + Channel * 0x100;
val = Get_NB32(dev, reg);
val &= ~(0x3ff<<22);
val |= ((u32) pDCTstat->CH_MaxRdLat[Channel] << 22);
- val &= ~(1<<DqsRcvEnTrain);
+ val &= ~(1 << DqsRcvEnTrain);
Set_NB32(dev, reg, val); /* program MaxRdLatency to correspond with current delay*/
}
}
@@ -497,7 +497,7 @@ static void ResetNBECCstat_D(struct MCTStatStruc *pMCTstat,
* or normal ECC memory conditioning.
*/
- //FIXME: this function depends on pDCTstat Array ( with Node id ) - Is this really a problem?
+ //FIXME: this function depends on pDCTstat Array (with Node id) - Is this really a problem?
u32 dev;
u8 Node;
@@ -592,9 +592,9 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
limit = pDCTstat->DCTSysLimit;
} else if (base == BottomIO) {
/* SW Node Hoist */
- pMCTstat->GStatus |= 1<<GSB_SpIntRemapHole;
- pDCTstat->Status |= 1<<SB_SWNodeHole;
- pMCTstat->GStatus |= 1<<GSB_SoftHole;
+ pMCTstat->GStatus |= 1 << GSB_SpIntRemapHole;
+ pDCTstat->Status |= 1 << SB_SWNodeHole;
+ pMCTstat->GStatus |= 1 << GSB_SoftHole;
pMCTstat->HoleBase = base;
limit -= base;
base = _4GB_RJ8;
@@ -650,7 +650,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
val = Get_NB32(dev, reg);
Set_NB32(devx, reg, val);
reg += 4;
- } while ( reg < 0x80);
+ } while (reg < 0x80);
} else {
break; /* stop at first absent Node */
}
@@ -672,7 +672,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
u8 Node;
struct DCTStatStruc *pDCTstat;
- if (!mctGet_NVbits(NV_DQSTrainCTL)){
+ if (!mctGet_NVbits(NV_DQSTrainCTL)) {
// FIXME: callback to wrapper: mctDoWarmResetMemClr_D
} else { // NV_DQSTrainCTL == 1
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -723,7 +723,7 @@ static void MCTMemClrSync_D(struct MCTStatStruc *pMCTstat,
u8 Node;
struct DCTStatStruc *pDCTstat;
- if (!mctGet_NVbits(NV_DQSTrainCTL)){
+ if (!mctGet_NVbits(NV_DQSTrainCTL)) {
// callback to wrapper: mctDoWarmResetMemClr_D
} else { // NV_DQSTrainCTL == 1
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -745,7 +745,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
u32 reg;
/* Ensure that a memory clear operation has completed on one node */
- if (pDCTstat->DCTSysLimit){
+ if (pDCTstat->DCTSysLimit) {
reg = 0x110;
do {
@@ -834,7 +834,7 @@ static void DCTInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTst
u32 reg_off = dct * 0x100;
val = 1<<DisDramInterface;
Set_NB32(pDCTstat->dev_dct, reg_off+0x94, val);
- /*To maximize power savings when DisDramInterface=1b,
+ /*To maximize power savings when DisDramInterface = 1b,
all of the MemClkDis bits should also be set.*/
val = 0xFF000000;
Set_NB32(pDCTstat->dev_dct, reg_off+0x88, val);
@@ -887,7 +887,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
dev = pDCTstat->dev_dct;
val = Get_NB32(dev, 0x94 + reg_off);
- if (val & (1<<MemClkFreqVal)) {
+ if (val & (1 << MemClkFreqVal)) {
print_t("\t\t\tStartupDCT_D: MemClkFreqVal\n");
byte = mctGet_NVbits(NV_DQSTrainCTL);
if (byte == 1) {
@@ -997,7 +997,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
pDCTstat->CASL = pDCTstat->DIMMCASL;
/* if "manual" memclock mode */
- if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
+ if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 2)
pDCTstat->Speed = mctGet_NVbits(NV_MemCkVal) + 1;
}
@@ -1013,10 +1013,10 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
Trc = 0;
Twr = 0;
Twtr = 0;
- for (i=0; i < 4; i++)
+ for (i = 0; i < 4; i++)
Trfc[i] = 0;
- for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
+ for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
LDIMM = i >> 1;
if (pDCTstat->DIMMValid & (1 << i)) {
smbaddr = Get_DIMMAddress_D(pDCTstat, dct + i);
@@ -1062,13 +1062,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
if (Trc < val)
Trc = val;
- /* dev density=rank size/#devs per rank */
+ /* dev density = rank size/#devs per rank */
byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
val = ((byte >> 5) | (byte << 3)) & 0xFF;
val <<= 2;
- byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density=2^(rows+columns+banks) */
+ byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0xFE; /* dev density = 2^(rows+columns+banks) */
if (byte == 4) {
val >>= 4;
} else if (byte == 8) {
@@ -1094,7 +1094,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
if (byte == 5)
DDR2_1066 = 1;
Tk40 = Get_40Tk_D(byte);
- Tk10 = Tk40>>2;
+ Tk10 = Tk40 >> 2;
/* Notes:
1. All secondary time values given in SPDs are in binary with units of ns.
@@ -1260,7 +1260,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
/* Trfc0-Trfc3 */
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
pDCTstat->Trfc[i] = Trfc[i];
mctAdjustAutoCycTmg_D();
@@ -1277,7 +1277,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
else
val -= Bias_TrcdT;
- DramTimingLo |= val<<4;
+ DramTimingLo |= val << 4;
val = pDCTstat->Trp;
if (DDR2_1066)
@@ -1286,27 +1286,27 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
val -= Bias_TrpT;
val <<= 1;
}
- DramTimingLo |= val<<7;
+ DramTimingLo |= val << 7;
val = pDCTstat->Trtp;
val -= Bias_TrtpT;
- DramTimingLo |= val<<11;
+ DramTimingLo |= val << 11;
val = pDCTstat->Tras;
if (DDR2_1066)
val -= Bias_TrasT_1066;
else
val -= Bias_TrasT;
- DramTimingLo |= val<<12;
+ DramTimingLo |= val << 12;
val = pDCTstat->Trc;
val -= Bias_TrcT;
- DramTimingLo |= val<<16;
+ DramTimingLo |= val << 16;
if (!DDR2_1066) {
val = pDCTstat->Twr;
val -= Bias_TwrT;
- DramTimingLo |= val<<20;
+ DramTimingLo |= val << 20;
}
val = pDCTstat->Trrd;
@@ -1314,7 +1314,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
val -= Bias_TrrdT_1066;
else
val -= Bias_TrrdT;
- DramTimingLo |= val<<22;
+ DramTimingLo |= val << 22;
DramTimingHi = 0; /* Dram Timing Low init */
@@ -1323,13 +1323,13 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
val -= Bias_TwtrT_1066;
else
val -= Bias_TwtrT;
- DramTimingHi |= val<<8;
+ DramTimingHi |= val << 8;
val = 2;
- DramTimingHi |= val<<16;
+ DramTimingHi |= val << 16;
val = 0;
- for (i=4;i>0;i--) {
+ for (i = 4; i > 0; i--) {
val <<= 3;
val |= Trfc[i-1];
}
@@ -1385,7 +1385,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
proposedFreq = 533; /* Rev F0 programmable max memclock is */
/*Get User defined limit if "limit" mode */
- if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
+ if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1);
if (word < proposedFreq)
proposedFreq = word;
@@ -1426,9 +1426,9 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
CL1min = 0xFF;
T1min = 0xFF;
- for (k=K_MAX; k >= K_MIN; k--) {
+ for (k = K_MAX; k >= K_MIN; k--) {
for (j = J_MIN; j <= J_MAX; j++) {
- if (Sys_Capability_D(pMCTstat, pDCTstat, j, k) ) {
+ if (Sys_Capability_D(pMCTstat, pDCTstat, j, k)) {
/* 1. check to see if DIMMi is populated.
2. check if DIMMi supports CLj and Tjk */
for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {
@@ -1480,7 +1480,7 @@ static u8 PlatformSpec_D(struct MCTStatStruc *pMCTstat,
mctGet_PS_Cfg_D(pMCTstat, pDCTstat, 1);
}
- if ( pDCTstat->_2Tmode == 2) {
+ if (pDCTstat->_2Tmode == 2) {
dev = pDCTstat->dev_dct;
reg = 0x94 + 0x100 * dct; /* Dram Configuration Hi */
val = Get_NB32(dev, reg);
@@ -1547,20 +1547,20 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
if (pDCTstat->Speed == 3) {
if (pDCTstat->MAdimms[dct] == 4)
DramConfigLo |= 1 << 5; /* 50 Ohms ODT */
- } else if (pDCTstat->Speed == 4){
+ } else if (pDCTstat->Speed == 4) {
if (pDCTstat->MAdimms[dct] != 1)
DramConfigLo |= 1 << 5; /* 50 Ohms ODT */
}
} else {
// FIXME: Skip for Ax versions
if (pDCTstat->MAdimms[dct] == 4) {
- if ( pDCTstat->DimmQRPresent != 0) {
+ if (pDCTstat->DimmQRPresent != 0) {
if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 4)) {
DramConfigLo |= 1 << 5; /* 50 Ohms ODT */
}
} else if (pDCTstat->MAdimms[dct] == 4) {
if (pDCTstat->Speed == 4) {
- if ( pDCTstat->DimmQRPresent != 0) {
+ if (pDCTstat->DimmQRPresent != 0) {
DramConfigLo |= 1 << 5; /* 50 Ohms ODT */
}
}
@@ -1604,7 +1604,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
if (mctGet_NVbits(NV_ECC_CAP))
if (Status & (1 << SB_ECCDIMMs))
- if ( mctGet_NVbits(NV_ECC))
+ if (mctGet_NVbits(NV_ECC))
DramConfigLo |= 1 << DimmEcEn;
DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct);
@@ -1633,7 +1633,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
DramConfigHi |= 1 << BankSwizzleMode; /* recommended setting (default) */
/* Check for Quadrank DIMM presence */
- if ( pDCTstat->DimmQRPresent != 0) {
+ if (pDCTstat->DimmQRPresent != 0) {
byte = mctGet_NVbits(NV_4RANKType);
if (byte == 2)
DramConfigHi |= 1 << 17; /* S4 (4-Rank SO-DIMMs) */
@@ -1641,7 +1641,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */
}
- if (0) /* call back not needed mctOverrideDcqBypMax_D ) */
+ if (0) /* call back not needed mctOverrideDcqBypMax_D) */
val = mctGet_NVbits(NV_BYPMAX);
else
val = 0x0f; // recommended setting (default)
@@ -1676,14 +1676,14 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
1. We will assume that MemClkDis field has been preset prior to this
point.
2. We will only set MemClkDis bits if a DIMM is NOT present AND if:
- NV_AllMemClks <>0 AND SB_DiagClks ==0 */
+ NV_AllMemClks <>0 AND SB_DiagClks == 0 */
/* Dram Timing Low (owns Clock Enable bits) */
DramTimingLo = Get_NB32(dev, 0x88 + reg_off);
if (mctGet_NVbits(NV_AllMemClks) == 0) {
/* Special Jedec SPD diagnostic bit - "enable all clocks" */
- if (!(pDCTstat->Status & (1<<SB_DiagClks))) {
+ if (!(pDCTstat->Status & (1 << SB_DiagClks))) {
const u8 *p;
byte = mctGet_NVbits(NV_PACK_TYPE);
if (byte == PT_L1)
@@ -1697,9 +1697,9 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
while (dword < MAX_DIMMS_SUPPORTED) {
val = p[dword];
print_tx("DramTimingLo: val=", val);
- if (!(pDCTstat->DIMMValid & (1<<val)))
+ if (!(pDCTstat->DIMMValid & (1 << val)))
/*disable memclk*/
- DramTimingLo |= 1<<(dword+24);
+ DramTimingLo |= 1 << (dword+24);
dword++ ;
}
}
@@ -1763,7 +1763,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
if ((pDCTstat->Status & (1 << SB_64MuxedMode)) && ChipSel >=4)
byte -= 3;
- if (pDCTstat->DIMMValid & (1<<byte)) {
+ if (pDCTstat->DIMMValid & (1 << byte)) {
smbaddr = Get_DIMMAddress_D(pDCTstat, (ChipSel + dct));
byte = mctRead_SPD(smbaddr, SPD_ROWSZ);
@@ -1795,7 +1795,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
/* 13 Rows is smallest dev size */
byte |= Rows - 13; /* CCCBRR internal encode */
- for (dword=0; dword < 12; dword++) {
+ for (dword = 0; dword < 12; dword++) {
if (byte == Tab_BankAddr[dword])
break;
}
@@ -1803,14 +1803,14 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
if (dword < 12) {
/* bit no. of CS field in address mapping reg.*/
- dword <<= (ChipSel<<1);
+ dword <<= (ChipSel << 1);
BankAddrReg |= dword;
/* Mask value=(2pow(rows+cols+banks+3)-1)>>8,
or 2pow(rows+cols+banks-5)-1*/
csMask = 0;
- byte = Rows + Cols; /* cl=rows+cols*/
+ byte = Rows + Cols; /* cl = rows+cols*/
if (Banks == 8)
byte -= 2; /* 3 banks - 5 */
else
@@ -1824,19 +1824,19 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
csMask--;
/*set ChipSelect population indicator even bits*/
- pDCTstat->CSPresent |= (1<<ChipSel);
+ pDCTstat->CSPresent |= (1 << ChipSel);
if (Ranks >= 2)
/*set ChipSelect population indicator odd bits*/
pDCTstat->CSPresent |= 1 << (ChipSel + 1);
- reg = 0x60+(ChipSel<<1) + reg_off; /*Dram CS Mask Register */
+ reg = 0x60+(ChipSel << 1) + reg_off; /*Dram CS Mask Register */
val = csMask;
val &= 0x1FF83FE0; /* Mask out reserved bits.*/
Set_NB32(dev, reg, val);
}
} else {
- if (pDCTstat->DIMMSPDCSE & (1<<ChipSel))
- pDCTstat->CSTestFail |= (1<<ChipSel);
+ if (pDCTstat->DIMMSPDCSE & (1 << ChipSel))
+ pDCTstat->CSTestFail |= (1 << ChipSel);
} /* if DIMMValid*/
} /* while ChipSel*/
@@ -1881,7 +1881,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
/* Check Symmetry of Channel A and Channel B DIMMs
(must be matched for 128-bit mode).*/
- for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) {
+ for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) {
if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) {
smbaddr = Get_DIMMAddress_D(pDCTstat, i);
smbaddr1 = Get_DIMMAddress_D(pDCTstat, i+1);
@@ -1889,35 +1889,35 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
byte = mctRead_SPD(smbaddr, SPD_ROWSZ) & 0x1f;
byte1 = mctRead_SPD(smbaddr1, SPD_ROWSZ) & 0x1f;
if (byte != byte1) {
- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
break;
}
byte = mctRead_SPD(smbaddr, SPD_COLSZ) & 0x1f;
byte1 = mctRead_SPD(smbaddr1, SPD_COLSZ) & 0x1f;
if (byte != byte1) {
- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
break;
}
byte = mctRead_SPD(smbaddr, SPD_BANKSZ);
byte1 = mctRead_SPD(smbaddr1, SPD_BANKSZ);
if (byte != byte1) {
- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
break;
}
byte = mctRead_SPD(smbaddr, SPD_DEVWIDTH) & 0x7f;
byte1 = mctRead_SPD(smbaddr1, SPD_DEVWIDTH) & 0x7f;
if (byte != byte1) {
- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
break;
}
byte = mctRead_SPD(smbaddr, SPD_DMBANKS) & 7; /* #ranks-1 */
byte1 = mctRead_SPD(smbaddr1, SPD_DMBANKS) & 7; /* #ranks-1 */
if (byte != byte1) {
- pDCTstat->ErrStatus |= (1<<SB_DimmMismatchO);
+ pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
break;
}
@@ -1952,7 +1952,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
_DSpareEn = 0;
- /* CS Sparing 1=enabled, 0=disabled */
+ /* CS Sparing 1 = enabled, 0 = disabled */
if (mctGet_NVbits(NV_CS_SpareCTL) & 1) {
if (MCT_DIMM_SPARE_NO_WARM) {
/* Do no warm-reset DIMM spare */
@@ -1967,7 +1967,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
pDCTstat->ErrStatus |= 1 << SB_SpareDis;
}
} else {
- if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */
+ if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */
word = pDCTstat->CSPresent;
val = bsf(word);
word &= ~(1 << val);
@@ -1981,13 +1981,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
}
nxtcsBase = 0; /* Next available cs base ADDR[39:8] */
- for (p=0; p < MAX_DIMMS_SUPPORTED; p++) {
+ for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) {
BiggestBank = 0;
for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */
if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */
reg = 0x40 + (q << 2) + reg_off; /* Base[q] reg.*/
val = Get_NB32(dev, reg);
- if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */
+ if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */
reg = 0x60 + ((q << 1) & 0xc) + reg_off; /*Mask[q] reg.*/
val = Get_NB32(dev, reg);
val >>= 19;
@@ -2003,7 +2003,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
} /*if bank present */
} /* while q */
if (BiggestBank !=0) {
- curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/
+ curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/
/* DRAM CS Base b Address Register offset */
reg = 0x40 + (b << 2) + reg_off;
if (_DSpareEn) {
@@ -2022,7 +2022,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
}
/* bank present but disabled?*/
- if ( pDCTstat->CSTestFail & (1 << p)) {
+ if (pDCTstat->CSTestFail & (1 << p)) {
/* DRAM CS Base b Address Register offset */
reg = (p << 2) + 0x40 + reg_off;
val = 1 << TestFail;
@@ -2102,8 +2102,8 @@ static u8 Dimm_Supports_D(struct DCTStatStruc *pDCTstat,
byte = mctRead_SPD(DIMMi, word); /* DIMMi speed */
if (Tk < byte) {
ret = 1;
- } else if (byte == 0){
- pDCTstat->ErrStatus |= 1<<SB_NoCycTime;
+ } else if (byte == 0) {
+ pDCTstat->ErrStatus |= 1 << SB_NoCycTime;
ret = 1;
} else {
ret = 0; /* DIMM is capable! */
@@ -2121,12 +2121,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
/* Check DIMMs present, verify checksum, flag SDRAM type,
* build population indicator bitmaps, and preload bus loading
* of DIMMs into DCTStatStruc.
- * MAAload=number of devices on the "A" bus.
- * MABload=number of devices on the "B" bus.
- * MAAdimms=number of DIMMs on the "A" bus slots.
- * MABdimms=number of DIMMs on the "B" bus slots.
- * DATAAload=number of ranks on the "A" bus slots.
- * DATABload=number of ranks on the "B" bus slots.
+ * MAAload = number of devices on the "A" bus.
+ * MABload = number of devices on the "B" bus.
+ * MAAdimms = number of DIMMs on the "A" bus slots.
+ * MABdimms = number of DIMMs on the "B" bus slots.
+ * DATAAload = number of ranks on the "A" bus slots.
+ * DATABload = number of ranks on the "B" bus slots.
*/
u16 i, j, k;
@@ -2159,7 +2159,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
print_tx("\t DIMMPresence: smbaddr=", smbaddr);
if (smbaddr) {
Checksum = 0;
- for (Index=0; Index < 64; Index++){
+ for (Index = 0; Index < 64; Index++) {
int status;
status = mctRead_SPD(smbaddr, Index);
if (status < 0)
@@ -2184,7 +2184,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
pDCTstat->ErrCode = SC_StopError;
} else {
/*if NV_SPDCHK_RESTRT is set to 1, ignore faulty SPD checksum*/
- pDCTstat->ErrStatus |= 1<<SB_DIMMChkSum;
+ pDCTstat->ErrStatus |= 1 << SB_DIMMChkSum;
byte = mctRead_SPD(smbaddr, SPD_TYPE);
if (byte == JED_DDR2SDRAM)
pDCTstat->DIMMValid |= 1 << i;
@@ -2250,17 +2250,17 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
/*Check if SPD diag bit 'analysis probe installed' is set */
byte = mctRead_SPD(smbaddr, SPD_ATTRIB);
- if ( byte & JED_PROBEMSK )
- pDCTstat->Status |= 1<<SB_DiagClks;
+ if (byte & JED_PROBEMSK)
+ pDCTstat->Status |= 1 << SB_DiagClks;
byte = mctRead_SPD(smbaddr, SPD_DMBANKS);
- if (!(byte & (1<< SPDPLBit)))
+ if (!(byte & (1 << SPDPLBit)))
pDCTstat->DimmPlPresent |= 1 << i;
byte &= 7;
byte++; /* ranks */
if (byte > 2) {
/* if any DIMMs are QR, we have to make two passes through DIMMs*/
- if ( pDCTstat->DimmQRPresent == 0) {
+ if (pDCTstat->DimmQRPresent == 0) {
MaxDimms <<= 1;
}
if (i < DimmSlots) {
@@ -2274,7 +2274,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
if (devwidth == 16)
bytex = 4;
else if (devwidth == 4)
- bytex=16;
+ bytex = 16;
if (byte == 2)
bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/
@@ -2322,28 +2322,28 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
if (RegDIMMPresent != 0) {
if ((RegDIMMPresent ^ pDCTstat->DIMMValid) !=0) {
/* module type DIMM mismatch (reg'ed, unbuffered) */
- pDCTstat->ErrStatus |= 1<<SB_DimmMismatchM;
+ pDCTstat->ErrStatus |= 1 << SB_DimmMismatchM;
pDCTstat->ErrCode = SC_StopError;
} else{
/* all DIMMs are registered */
- pDCTstat->Status |= 1<<SB_Registered;
+ pDCTstat->Status |= 1 << SB_Registered;
}
}
if (pDCTstat->DimmECCPresent != 0) {
- if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) {
+ if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) {
/* all DIMMs are ECC capable */
- pDCTstat->Status |= 1<<SB_ECCDIMMs;
+ pDCTstat->Status |= 1 << SB_ECCDIMMs;
}
}
if (pDCTstat->DimmPARPresent != 0) {
if ((pDCTstat->DimmPARPresent ^ pDCTstat->DIMMValid) == 0) {
/*all DIMMs are Parity capable */
- pDCTstat->Status |= 1<<SB_PARDIMMs;
+ pDCTstat->Status |= 1 << SB_PARDIMMs;
}
}
} else {
/* no DIMMs present or no DIMMs that qualified. */
- pDCTstat->ErrStatus |= 1<<SB_NoDimms;
+ pDCTstat->ErrStatus |= 1 << SB_NoDimms;
pDCTstat->ErrCode = SC_StopError;
}
@@ -2418,7 +2418,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
} else {
/* Configure DCT1 if unganged and enabled*/
if (!pDCTstat->GangedMode) {
- if ( pDCTstat->DIMMValidDCT[1] > 0) {
+ if (pDCTstat->DIMMValidDCT[1] > 0) {
print_t("\tmct_initDCT: DCTInit_D 1\n");
err_code = pDCTstat->ErrCode; /* save DCT0 errors */
pDCTstat->ErrCode = 0;
@@ -2497,7 +2497,7 @@ static u8 mct_setMode(struct MCTStatStruc *pMCTstat,
if (byte != bytex) {
pDCTstat->ErrStatus &= ~(1 << SB_DimmMismatchO);
} else {
- if ( mctGet_NVbits(NV_Unganged) )
+ if (mctGet_NVbits(NV_Unganged))
pDCTstat->ErrStatus |= (1 << SB_DimmMismatchO);
if (!(pDCTstat->ErrStatus & (1 << SB_DimmMismatchO))) {
@@ -2595,7 +2595,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
i_start = dct;
i_end = dct + 1;
}
- for (i=i_start; i<i_end; i++) {
+ for (i = i_start; i < i_end; i++) {
index_reg = 0x98 + (i * 0x100);
Set_NB32_index_wait(dev, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A Output Driver Compensation Control */
Set_NB32_index_wait(dev, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A Output Driver Compensation Control */
@@ -2615,7 +2615,7 @@ static void mct_SyncDCTsReady(struct DCTStatStruc *pDCTstat)
print_tx("mct_SyncDCTsReady: Node ", pDCTstat->Node_ID);
dev = pDCTstat->dev_dct;
- if ((pDCTstat->DIMMValidDCT[0] ) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */
+ if ((pDCTstat->DIMMValidDCT[0]) || (pDCTstat->DIMMValidDCT[1])) { /* This Node has dram */
do {
val = Get_NB32(dev, 0x110);
} while (!(val & (1 << DramEnabled)));
@@ -2629,7 +2629,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct)
{
if (!pDCTstat->GangedMode) {
- if (dct == 0 ) {
+ if (dct == 0) {
pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct];
if (pDCTstat->DIMMValidDCT[dct] == 0)
pDCTstat->ErrCode = SC_StopError;
@@ -2648,7 +2648,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
{
u8 ret;
- if ( dct == 0) {
+ if (dct == 0) {
SPDCalcWidth_D(pMCTstat, pDCTstat);
ret = mct_setMode(pMCTstat, pDCTstat);
} else {
@@ -2752,7 +2752,7 @@ static u8 mct_DIMMPresence(struct MCTStatStruc *pMCTstat,
{
u8 ret;
- if ( dct == 0)
+ if (dct == 0)
ret = DIMMPresence_D(pMCTstat, pDCTstat);
else
ret = pDCTstat->ErrCode;
@@ -2777,7 +2777,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat,
pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0];
Set_OtherTiming(pMCTstat, pDCTstat, 0);
}
- if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) {
+ if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) {
pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1];
Set_OtherTiming(pMCTstat, pDCTstat, 1);
}
@@ -3022,8 +3022,8 @@ static u8 Check_DqsRcvEn_Diff(struct DCTStatStruc *pDCTstat,
if (index == 0x12)
ecc_reg = 1;
- for (i=0; i < 8; i+=2) {
- if ( pDCTstat->DIMMValid & (1 << i)) {
+ for (i = 0; i < 8; i+=2) {
+ if (pDCTstat->DIMMValid & (1 << i)) {
val = Get_NB32_index_wait(dev, index_reg, index);
byte = val & 0xFF;
if (byte < Smallest_0)
@@ -3153,8 +3153,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
if (index == 0x12)
ecc_reg = 1;
- for (i=0; i < 8; i+=2) {
- if ( pDCTstat->DIMMValid & (1 << i)) {
+ for (i = 0; i < 8; i+=2) {
+ if (pDCTstat->DIMMValid & (1 << i)) {
val = Get_NB32_index_wait(dev, index_reg, index);
val &= 0x00E000E0;
byte = (val >> 5) & 0xFF;
@@ -3192,11 +3192,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
Smallest = 3;
Largest = 0;
- for (i=0; i < 2; i++) {
+ for (i = 0; i < 2; i++) {
val = Get_NB32_index_wait(dev, index_reg, index);
val &= 0x60606060;
val >>= 5;
- for (j=0; j < 4; j++) {
+ for (j = 0; j < 4; j++) {
byte = val & 0xFF;
if (byte < Smallest)
Smallest = byte;
@@ -3308,14 +3308,14 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
/* Copy dram map from F1x40/44,F1x48/4c,
to F1x120/124(Node0),F1x120/124(Node1),...*/
- for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) {
+ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
pDCTstat = pDCTstatA + Node;
devx = pDCTstat->dev_map;
/* get base/limit from Node0 */
reg = 0x40 + (Node << 3); /* Node0/Dram Base 0 */
val = Get_NB32(dev, reg);
- Drambase = val >> ( 16 + 3);
+ Drambase = val >> (16 + 3);
reg = 0x44 + (Node << 3); /* Node0/Dram Base 0 */
val = Get_NB32(dev, reg);
@@ -3335,7 +3335,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
val |= Dramlimit;
Set_NB32(devx, reg, val);
- if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) {
+ if (pMCTstat->GStatus & (1 << GSB_HWHole)) {
reg = 0xF0;
val = Get_NB32(devx, reg);
val |= (1 << DramMemHoistValid);
@@ -3476,7 +3476,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
val = Get_NB32_index_wait(dev, index_reg, 0x00);
dword = 0;
- for (i=0; i < 6; i++) {
+ for (i = 0; i < 6; i++) {
switch (i) {
case 0:
case 4:
@@ -3652,8 +3652,8 @@ static void mct_BeforeDramInit_Prod_D(struct MCTStatStruc *pMCTstat,
u32 dev = pDCTstat->dev_dct;
// FIXME: skip for Ax
- if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
- for (i=0; i < 2; i++) {
+ if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
+ for (i = 0; i < 2; i++) {
reg_off = 0x100 * i;
Set_NB32(dev, 0x98 + reg_off, 0x0D000030);
Set_NB32(dev, 0x9C + reg_off, 0x00000806);
@@ -3667,7 +3667,7 @@ static void mct_AdjustDelayRange_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 *dqs_pos)
{
// FIXME: Skip for Ax
- if ((pDCTstat->Speed == 3) || ( pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
+ if ((pDCTstat->Speed == 3) || (pDCTstat->Speed == 2)) { // MemClkFreq = 667MHz or 533MHz
*dqs_pos = 32;
}
}
@@ -3737,7 +3737,7 @@ void mct_ClrClToNB_D(struct MCTStatStruc *pMCTstat,
msr = BU_CFG2;
_RDMSR(msr, &lo, &hi);
if (!pDCTstat->ClToNB_flag)
- lo &= ~(1<<ClLinesToNbDis);
+ lo &= ~(1 << ClLinesToNbDis);
_WRMSR(msr, lo, hi);
}
@@ -3783,10 +3783,10 @@ void mct_SetDramConfigHi_D(struct DCTStatStruc *pDCTstat, u32 dct,
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
- * - a) Disable Compensation (F2[1, 0]9C_x08[30] )
+ * - a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
* c) Do frequency change
- * d) Enable Compensation (F2[1, 0]9C_x08[30] )
+ * d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0
@@ -3970,7 +3970,7 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
if (pDCTstat->LogicalCPUID & (AMD_DR_B2 | AMD_DR_B3)) {
mct_Wait(10000); /* Wait 50 us*/
val = Get_NB32(dev, 0x110);
- if ( val & (1 << DramEnabled)) {
+ if (val & (1 << DramEnabled)) {
/* If 50 us expires while DramEnable =0 then do the following */
val = Get_NB32(dev, 0x90 + reg_off);
val &= ~(1 << Width128); /* Program Width128 = 0 */
@@ -3990,9 +3990,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
/* ==========================================================
* 6-bit Bank Addressing Table
- * RR=rows-13 binary
- * B=Banks-2 binary
- * CCC=Columns-9 binary
+ * RR = rows-13 binary
+ * B = Banks-2 binary
+ * CCC = Columns-9 binary
* ==========================================================
* DCT CCCBRR Rows Banks Columns 64-bit CS Size
* Encoding
diff --git a/src/northbridge/amd/amdmct/mct/mct_d.h b/src/northbridge/amd/amdmct/mct/mct_d.h
index b580457..4e1a909 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d.h
@@ -30,16 +30,16 @@
#define PT_S1 2
#define PT_GR 3
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
-#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/
-#define K_MIN 1 /* k loop constraint. 1=200 MHz*/
-#define K_MAX 5 /* k loop constraint. 5=533 MHz*/
-#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
-#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
-
-#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
+#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/
+#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/
+#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/
+#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/
+#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/
+#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/
+
+#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/
/* memory initialization (ecc and check-bits).*/
- /* 1=40 ns/64 bytes.*/
+ /* 1 = 40 ns/64 bytes.*/
#define FirstPass 1 /* First pass through RcvEn training*/
#define SecondPass 2 /* Second pass through Rcven training*/
@@ -289,7 +289,7 @@ struct DCTStatStruc { /* A per Node structure*/
/* DCTStatStruct_F - start */
u8 Node_ID; /* Node ID of current controller*/
uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */
- uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */
+ uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */
uint8_t stopDCT; /* Set if the DCT will be stopped */
u8 ErrCode; /* Current error condition of Node
0= no error
@@ -306,7 +306,7 @@ struct DCTStatStruc { /* A per Node structure*/
/* SPD address of..MB2_CS_L[0,1]*/
/* SPD address of..MA3_CS_L[0,1]*/
/* SPD address of..MB3_CS_L[0,1]*/
- u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present.
+ u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present.
DIMM# Select Signal
0 MA0_CS_L[0,1]
1 MB0_CS_L[0,1]
@@ -316,15 +316,15 @@ struct DCTStatStruc { /* A per Node structure*/
5 MB2_CS_L[0,1]
6 MA3_CS_L[0,1]
7 MB3_CS_L[0,1]*/
- u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
- u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */
- u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
- u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
- u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
- u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
- u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
- u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
- u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
+ u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/
+ u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */
+ u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/
+ u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/
+ u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/
+ u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/
+ u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/
+ u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/
+ u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/
u8 MAload[2]; /* Number of devices loading MAA bus*/
/* Number of devices loading MAB bus*/
u8 MAdimms[2]; /*Number of DIMMs loading CH A*/
@@ -332,17 +332,17 @@ struct DCTStatStruc { /* A per Node structure*/
u8 DATAload[2]; /*Number of ranks loading CH A DATA*/
/* Number of ranks loading CH B DATA*/
u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs
- 1=200MHz
- 2=266MHz
- 3=333MHz
- 4=400MHz
- 5=533MHz*/
+ 1 = 200MHz
+ 2 = 266MHz
+ 3 = 333MHz
+ 4 = 400MHz
+ 5 = 533MHz*/
u8 DIMMCASL; /* Min valid Mfg. CL bitfield
- 0=2.0
- 1=3.0
- 2=4.0
- 3=5.0
- 4=6.0 */
+ 0 = 2.0
+ 1 = 3.0
+ 2 = 4.0
+ 3 = 5.0
+ 4 = 6.0 */
u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
@@ -352,16 +352,16 @@ struct DCTStatStruc { /* A per Node structure*/
u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
u8 Speed; /* Bus Speed (to set Controller)
- 1=200MHz
- 2=266MHz
- 3=333MHz
- 4=400MHz */
+ 1 = 200MHz
+ 2 = 266MHz
+ 3 = 333MHz
+ 4 = 400MHz */
u8 CASL; /* CAS latency DCT setting
- 0=2.0
- 1=3.0
- 2=4.0
- 3=5.0
- 4=6.0 */
+ 0 = 2.0
+ 1 = 3.0
+ 2 = 4.0
+ 3 = 5.0
+ 4 = 6.0 */
u8 Trcd; /* DCT Trcd (busclocks) */
u8 Trp; /* DCT Trp (busclocks) */
u8 Trtp; /* DCT Trtp (busclocks) */
@@ -371,27 +371,27 @@ struct DCTStatStruc { /* A per Node structure*/
u8 Trrd; /* DCT Trrd (busclocks) */
u8 Twtr; /* DCT Twtr (busclocks) */
u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
- 0=75ns (for 256Mb devs)
- 1=105ns (for 512Mb devs)
- 2=127.5ns (for 1Gb devs)
- 3=195ns (for 2Gb devs)
- 4=327.5ns (for 4Gb devs) */
+ 0 = 75ns (for 256Mb devs)
+ 1 = 105ns (for 512Mb devs)
+ 2 = 127.5ns (for 1Gb devs)
+ 3 = 195ns (for 2Gb devs)
+ 4 = 327.5ns (for 4Gb devs) */
/* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
/* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
/* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
- u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
- u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
+ u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */
+ u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */
u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
- 200=200MHz (DDR400)
- 266=266MHz (DDR533)
- 333=333MHz (DDR667)
- 400=400MHz (DDR800) */
+ 200 = 200MHz (DDR400)
+ 266 = 266MHz (DDR533)
+ 333 = 333MHz (DDR667)
+ 400 = 400MHz (DDR800) */
u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
- 1=1T
- 2=2T */
+ 1 = 1T
+ 2 = 2T */
u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
u8 Twrrd; /* DCT Twrrd (busclocks)*/
u8 Twrwr; /* DCT Twrwr (busclocks)*/
@@ -415,9 +415,9 @@ struct DCTStatStruc { /* A per Node structure*/
/* CHB Byte 0-7 Read DQS Delay */
u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/
- u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
+ u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/
u8 ByteLane; /* Current Byte Lane (0..7)*/
- u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
+ u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/
u8 Pattern; /* Current pattern*/
u8 DQSDelay; /* Current DQS delay value*/
u32 TrainErrors; /* Current Training Errors*/
@@ -483,15 +483,15 @@ struct DCTStatStruc { /* A per Node structure*/
u8 WrDatGrossH;
u8 DqsRcvEnGrossL;
// NOTE: Not used - u8 NodeSpeed /* Bus Speed (to set Controller)
- /* 1=200MHz */
- /* 2=266MHz */
- /* 3=333MHz */
+ /* 1 = 200MHz */
+ /* 2 = 266MHz */
+ /* 3 = 333MHz */
// NOTE: Not used - u8 NodeCASL /* CAS latency DCT setting
- /* 0=2.0 */
- /* 1=3.0 */
- /* 2=4.0 */
- /* 3=5.0 */
- /* 4=6.0 */
+ /* 0 = 2.0 */
+ /* 1 = 3.0 */
+ /* 2 = 4.0 */
+ /* 3 = 5.0 */
+ /* 4 = 6.0 */
u8 TrwtWB;
u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/
u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/
@@ -575,7 +575,7 @@ struct DCTStatStruc { /* A per Node structure*/
#define SB_SWNodeHole 7 /* Remapping of Node Base on this Node to create a gap.*/
#define SB_HWHole 8 /* Memory Hole created on this Node using HW remapping.*/
#define SB_Over400MHz 9 /* DCT freq >= 400MHz flag*/
-#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/
+#define SB_DQSPos_Pass2 10 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/
#define SB_DQSRcvLimit 11 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/
#define SB_ExtConfig 12 /* Indicator the default setting for extend PCI configuration support*/
@@ -587,73 +587,73 @@ struct DCTStatStruc { /* A per Node structure*/
===============================================================================*/
/*Platform Configuration*/
#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
- 0=NPT L1
- 1=NPT M2
- 2=NPT S1*/
+ 0 = NPT L1
+ 1 = NPT M2
+ 2 = NPT S1*/
#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
- 200=200MHz (DDR400)
- 266=266MHz (DDR533)
- 333=333MHz (DDR667)
- 400=400MHz (DDR800)*/
+ 200 = 200MHz (DDR400)
+ 266 = 266MHz (DDR533)
+ 333 = 333MHz (DDR667)
+ 400 = 400MHz (DDR800)*/
#define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */
#define NV_ECC_CAP 5 /* Bus ECC capable (1-bits)
- 0=Platform not capable
- 1=Platform is capable*/
+ 0 = Platform not capable
+ 1 = Platform is capable*/
#define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits)
- 0=Normal
- 1=R4 (4-Rank Registered DIMMs in AMD server configuration)
- 2=S4 (Unbuffered SO-DIMMs)*/
+ 0 = Normal
+ 1 = R4 (4-Rank Registered DIMMs in AMD server configuration)
+ 2 = S4 (Unbuffered SO-DIMMs)*/
#define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
- 4=4 times bypass (normal for non-UMA systems)
- 7=7 times bypass (normal for UMA systems)*/
+ 4 = 4 times bypass (normal for non-UMA systems)
+ 7 = 7 times bypass (normal for UMA systems)*/
#define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
- 2=8 times (normal for non-UMA systems)
- 3=16 times (normal for UMA systems)*/
+ 2 = 8 times (normal for non-UMA systems)
+ 3 = 16 times (normal for UMA systems)*/
/*Dram Timing*/
#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
- 0=Auto, no user limit
- 1=Auto, user limit provided in NV_MemCkVal
- 2=Manual, user value provided in NV_MemCkVal*/
+ 0 = Auto, no user limit
+ 1 = Auto, user limit provided in NV_MemCkVal
+ 2 = Manual, user value provided in NV_MemCkVal*/
#define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
- 0=200MHz
- 1=266MHz
- 2=333MHz
- 3=400MHz*/
+ 0 = 200MHz
+ 1 = 266MHz
+ 2 = 333MHz
+ 3 = 400MHz*/
/*Dram Configuration*/
#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
- 0=normal
- 1=enable all memclocks*/
+ 0 = normal
+ 1 = enable all memclocks*/
#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
- 0=Exit current node init if any DIMM has SPD checksum error
- 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
+ 0 = Exit current node init if any DIMM has SPD checksum error
+ 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
- 0=skip DQS training
- 1=perform DQS training*/
+ 0 = skip DQS training
+ 1 = perform DQS training*/
#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits)
- 0=disable (normal)
- 1=enable (4 beat burst when width is 64-bits)*/
+ 0 = disable (normal)
+ 1 = enable (4 beat burst when width is 64-bits)*/
/*Dram Power*/
#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
- 0=per Channel control
- 1=per Chip select control*/
+ 0 = per Channel control
+ 1 = per Chip select control*/
#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
/*Memory Map/Mgt.*/
#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
@@ -661,8 +661,8 @@ struct DCTStatStruc { /* A per Node structure*/
#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
NV_BottomUMA[7:0]=Addr[31:24]*/
#define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
- 0=disable
- 1=enable */
+ 0 = disable
+ 1 = enable */
/*ECC*/
#define NV_ECC 50 /* Dram ECC enable*/
@@ -674,13 +674,13 @@ struct DCTStatStruc { /* A per Node structure*/
#define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/
#define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/
#define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0:
- 0=disable Spare
- 1=enable Spare */
+ 0 = disable Spare
+ 1 = enable Spare */
/* Chip Select Spare Control bit 1-4:
Reserved, must be zero*/
#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_Unganged 62
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits)
diff --git a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
index fd39b38..fbfe988 100644
--- a/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
+++ b/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
@@ -39,7 +39,7 @@ static inline void _RDTSC(u32 *lo, u32 *hi)
__asm__ volatile (
"rdtsc"
: "=a" (*lo), "=d"(*hi)
- );
+ );
}
@@ -61,7 +61,7 @@ static u32 bsr(u32 x)
u8 i;
u32 ret = 0;
- for (i=31; i>0; i--) {
+ for (i = 31; i > 0; i--) {
if (x & (1<<i)) {
ret = i;
break;
@@ -78,7 +78,7 @@ static u32 bsf(u32 x)
u8 i;
u32 ret = 32;
- for (i=0; i<32; i++) {
+ for (i = 0; i < 32; i++) {
if (x & (1<<i)) {
ret = i;
break;
@@ -88,9 +88,9 @@ static u32 bsf(u32 x)
return ret;
}
-#define _MFENCE asm volatile ( "mfence")
+#define _MFENCE asm volatile ("mfence")
-#define _SFENCE asm volatile ( "sfence" )
+#define _SFENCE asm volatile ("sfence")
/* prevent speculative execution of following instructions */
#define _EXECFENCE asm volatile ("outb %al, $0xed")
@@ -343,7 +343,7 @@ static u32 stream_to_int(u8 const *p)
val = 0;
- for (i=3; i>=0; i--) {
+ for (i = 3; i >= 0; i--) {
val <<= 8;
valx = *(p+i);
val |= valx;
diff --git a/src/northbridge/amd/amdmct/mct/mctardk3.c b/src/northbridge/amd/amdmct/mct/mctardk3.c
index 327acbc..e290333 100644
--- a/src/northbridge/amd/amdmct/mct/mctardk3.c
+++ b/src/northbridge/amd/amdmct/mct/mctardk3.c
@@ -187,7 +187,7 @@ static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
}
while (*p != 0xFF) {
- if ((MAAdimms == *(p+10)) || (*(p+10 ) == 0xFE)) {
+ if ((MAAdimms == *(p+10)) || (*(p+10) == 0xFE)) {
if ((*p == Speed) || (*p == 0xFE)) {
if (MAAload <= *(p+1)) {
*AddrTmgCTL = stream_to_int((u8*)(p+2));
diff --git a/src/northbridge/amd/amdmct/mct/mctardk4.c b/src/northbridge/amd/amdmct/mct/mctardk4.c
index cac2342..7e1d91a 100644
--- a/src/northbridge/amd/amdmct/mct/mctardk4.c
+++ b/src/northbridge/amd/amdmct/mct/mctardk4.c
@@ -96,7 +96,7 @@ static const u8 Table_ATC_ODC_D_Ax[] = {
};
-static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
+static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
u8 *CMDmode)
{
diff --git a/src/northbridge/amd/amdmct/mct/mctchi_d.c b/src/northbridge/amd/amdmct/mct/mctchi_d.c
index d5956b1..705bd91 100644
--- a/src/northbridge/amd/amdmct/mct/mctchi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctchi_d.c
@@ -37,7 +37,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
/* call back to wrapper not needed ManualChannelInterleave_D(); */
/* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */
// FIXME: Check for Cx
- DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */
+ DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */
beforeInterleaveChannels_D(pDCTstatA, &enabled);
if (DctSelIntLvAddr & 1) {
@@ -71,7 +71,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
if (dct1_size == dct0_size) {
dct1_size = 0;
DctSelHi = 0x04; /* DctSelHiRngEn = 0 */
- } else if (dct1_size > dct0_size ) {
+ } else if (dct1_size > dct0_size) {
dct1_size = dct0_size;
DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */
}
diff --git a/src/northbridge/amd/amdmct/mct/mctcsi_d.c b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
index e8d26da..4841b73 100644
--- a/src/northbridge/amd/amdmct/mct/mctcsi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctcsi_d.c
@@ -45,11 +45,11 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
ChipSel = 0; /* Find out if current configuration is capable */
while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) {
- reg = 0x40+(ChipSel<<2) + reg_off; /* Dram CS Base 0 */
+ reg = 0x40+(ChipSel << 2) + reg_off; /* Dram CS Base 0 */
val = Get_NB32(dev, reg);
- if ( val & (1<<CSEnable)) {
+ if (val & (1 << CSEnable)) {
EnChipSels++;
- reg = 0x60+((ChipSel>>1)<<2)+reg_off; /*Dram CS Mask 0 */
+ reg = 0x60+((ChipSel >> 1) << 2)+reg_off; /*Dram CS Mask 0 */
val = Get_NB32(dev, reg);
val >>= 19;
val &= 0x3ff;
@@ -62,7 +62,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
break;
reg = 0x80 + reg_off; /*Dram Bank Addressing */
val = Get_NB32(dev, reg);
- val >>= (ChipSel>>1)<<2;
+ val >>= (ChipSel >> 1) << 2;
val &= 0x0f;
if (EnChipSels == 1)
BankEncd = val;
@@ -80,14 +80,14 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
if (DoIntlv) {
if (!_CsIntCap) {
- pDCTstat->ErrStatus |= 1<<SB_BkIntDis;
+ pDCTstat->ErrStatus |= 1 << SB_BkIntDis;
DoIntlv = 0;
}
}
if (DoIntlv) {
val = Tab_int_D[BankEncd];
- if (pDCTstat->Status & (1<<SB_128bitmode))
+ if (pDCTstat->Status & (1 << SB_128bitmode))
val++;
AddrLoMask = (EnChipSels - 1) << val;
@@ -100,7 +100,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
BitDelta = bsf(AddrHiMask) - bsf(AddrLoMask);
for (ChipSel = 0; ChipSel < MAX_CS_SUPPORTED; ChipSel++) {
- reg = 0x40+(ChipSel<<2) + reg_off; /*Dram CS Base 0 */
+ reg = 0x40+(ChipSel << 2) + reg_off; /*Dram CS Base 0 */
val = Get_NB32(dev, reg);
if (val & 3) {
val_lo = val & AddrLoMask;
@@ -116,7 +116,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
if (ChipSel & 1)
continue;
- reg = 0x60 + ((ChipSel>>1)<<2) + reg_off; /*Dram CS Mask 0 */
+ reg = 0x60 + ((ChipSel >> 1) << 2) + reg_off; /*Dram CS Mask 0 */
val = Get_NB32(dev, reg);
val_lo = val & AddrLoMask;
val_hi = val & AddrHiMask;
diff --git a/src/northbridge/amd/amdmct/mct/mctdqs_d.c b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
index 67ff823..e0c7761 100644
--- a/src/northbridge/amd/amdmct/mct/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctdqs_d.c
@@ -221,12 +221,12 @@ static void SetEccDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
u8 channel;
u8 direction;
- for (channel = 0; channel < 2; channel++){
+ for (channel = 0; channel < 2; channel++) {
for (direction = 0; direction < 2; direction++) {
pDCTstat->Channel = channel; /* Channel A or B */
pDCTstat->Direction = direction; /* Read or write */
CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel);
- print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2);
+ print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2);
pDCTstat->ByteLane = 8;
StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel);
@@ -251,7 +251,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
DQSDelay1 = pDCTstat->DQSDelay;
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay = DQSDelay0 - DQSDelay1;
} else {
DQSDelay = DQSDelay1 - DQSDelay0;
@@ -263,7 +263,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
DQSDelay >>= 8; // /256
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay = DQSDelay1 - DQSDelay;
} else {
DQSDelay += DQSDelay1;
@@ -320,7 +320,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
if (pDCTstat->DIMMValidDCT[Channel] == 0) /* mct_BeforeTrainDQSRdWrPos_D */
continue;
- for ( DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) {
+ for (DQSWrDelay = 0; DQSWrDelay < dqsWrDelay_end; DQSWrDelay++) {
pDCTstat->DQSDelay = DQSWrDelay;
pDCTstat->Direction = DQS_WRITEDIR;
mct_SetDQSDelayAllCSR_D(pMCTstat, pDCTstat, cs_start);
@@ -362,7 +362,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
for (Receiver = cs_start; Receiver < (cs_start + 2); Receiver += 2) {
printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_DIR_B_DQS[Channel][Receiver >> 1][Dir];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
val = p[i];
printk(BIOS_DEBUG, "%02x ", val);
}
@@ -383,7 +383,7 @@ static void TrainDQSRdWrPos_D(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(addr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -411,11 +411,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat,
buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0));
if (pDCTstat->Status & (1 << SB_128bitmode)) {
pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */
- for (i=0; i<16*18; i++)
+ for (i = 0; i < 16*18; i++)
buf[i] = TestPatternJD1b_D[i];
} else {
pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */
- for (i=0; i<16*9; i++)
+ for (i = 0; i < 16*9; i++)
buf[i] = TestPatternJD1a_D[i];
}
pDCTstat->PtrPatternBufA = (u32)buf;
@@ -458,10 +458,10 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
dqsDelay_end = 32;
}
- /* Bitmapped status per delay setting, 0xff=All positions
+ /* Bitmapped status per delay setting, 0xff = All positions
* passing (1= PASS). Set the entire array.
*/
- for (DQSDelay=0; DQSDelay<64; DQSDelay++) {
+ for (DQSDelay = 0; DQSDelay < 64; DQSDelay++) {
MutualCSPassW[DQSDelay] = 0xFF;
}
@@ -481,7 +481,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
}
print_debug_dqs("\t\t\t\tTrainDQSPos: 12 TestAddr ", TestAddr, 4);
- SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */
+ SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */
if (pDCTstat->Direction == DQS_READDIR) {
print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read ", 0, 4);
@@ -504,7 +504,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", pDCTstat->Pattern, 5);
ReadDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8);
/* print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5); */
- tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0=fail, 1=pass */
+ tmp = CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8); /* 0 = fail, 1 = pass */
if (mct_checkFenceHoleAdjust_D(pMCTstat, pDCTstat, DQSDelay, ChipSel, &tmp)) {
goto skipLocMiddle;
@@ -538,7 +538,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
if (LastTest == DQS_FAIL) {
RnkDlySeqPassMin = DQSDelay; //start sequential run
}
- if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){
+ if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) {
RnkDlyFilterMin = RnkDlySeqPassMin;
RnkDlyFilterMax = RnkDlySeqPassMax;
}
@@ -552,7 +552,7 @@ static void TrainDQSPos_D(struct MCTStatStruc *pMCTstat,
Errors |= 1 << SB_NODQSPOS; /* no passing window */
} else {
print_debug_dqs_pair("\t\t\t\tTrainDQSPos: 34 RnkDlyFilter: ", RnkDlyFilterMin, " ", RnkDlyFilterMax, 4);
- if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)){
+ if (((RnkDlyFilterMax - RnkDlyFilterMin) < MIN_DQS_WNDW)) {
Errors |= 1 << SB_SMALLDQS;
} else {
u8 middle_dqs;
@@ -631,7 +631,7 @@ static u8 MiddleDQS_D(u8 min, u8 max)
size = max-min;
if (size % 2)
size++; // round up if the size isn't even.
- return ( min + (size >> 1));
+ return (min + (size >> 1));
}
@@ -679,10 +679,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat,
reg_off = 0;
}
- if (ChipSel < MAX_CS_SUPPORTED){
+ if (ChipSel < MAX_CS_SUPPORTED) {
reg = 0x40 + (ChipSel << 2) + reg_off;
val = Get_NB32(dev, reg);
- if (val & ( 1 << 0))
+ if (val & (1 << 0))
ret = 1;
}
@@ -775,8 +775,8 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS
}
bytelane = 0; /* bytelane counter */
- bitmap = 0xFF; /* bytelane test bitmap, 1=pass */
- for (i=0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
+ bitmap = 0xFF; /* bytelane test bitmap, 1 = pass */
+ for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
value = read32_fs(addr_lo);
value_test = *test_buf;
@@ -797,7 +797,7 @@ static u8 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStatS
if (!bitmap)
break;
- if (bytelane == 0){
+ if (bytelane == 0) {
if (pattern == 1) { //dual channel
addr_lo += 8; //skip over other channel's data
test_buf += 2;
@@ -815,7 +815,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat,
u32 addr_lo)
{
/* Flush functions in mct_gcc.h */
- if (pDCTstat->Pattern == 0){
+ if (pDCTstat->Pattern == 0) {
FlushDQSTestPattern_L9(addr_lo);
} else {
FlushDQSTestPattern_L18(addr_lo);
@@ -1036,7 +1036,7 @@ static void mct_SetDQSDelayAllCSR_D(struct MCTStatStruc *pMCTstat,
for (ChipSel = cs_start; ChipSel < (cs_start + 2); ChipSel++) {
- if ( mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) {
+ if (mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, pDCTstat->Channel, ChipSel)) {
for (ByteLane = 0; ByteLane < 8; ByteLane++) {
pDCTstat->ByteLane = ByteLane;
mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel);
@@ -1088,9 +1088,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
val &= ~0x0F;
- /* unganged mode DCT0+DCT1, sys addr of DCT1=node
+ /* unganged mode DCT0+DCT1, sys addr of DCT1 = node
* base+DctSelBaseAddr+local ca base*/
- if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) {
+ if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) {
reg = 0x110;
dword = Get_NB32(dev, reg);
dword &= 0xfffff800;
@@ -1104,7 +1104,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
val += dword;
}
} else {
- /* sys addr=node base+local cs base */
+ /* sys addr = node base+local cs base */
val += pDCTstat->DCTSysBase;
/* New stuff */
diff --git a/src/northbridge/amd/amdmct/mct/mctecc_d.c b/src/northbridge/amd/amdmct/mct/mctecc_d.c
index 5c1dc3a..9b22c84 100644
--- a/src/northbridge/amd/amdmct/mct/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctecc_d.c
@@ -40,7 +40,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
*
* Conditions for setting background scrubber.
* 1. node is present
- * 2. node has dram functioning (WE=RE=1)
+ * 2. node has dram functioning (WE = RE = 1)
* 3. all eccdimms (or bit 17 of offset 90,fn 2)
* 4. no chip-select gap exists
*
@@ -121,10 +121,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
val = Get_NB32(dev, reg);
/* WE/RE is checked */
- if ((val & 3)==3) { /* Node has dram populated */
+ if ((val & 3) == 3) { /* Node has dram populated */
/* Negate 'all nodes/dimms ECC' flag if non ecc
memory populated */
- if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) {
+ if (pDCTstat->Status & (1 << SB_ECCDIMMs)) {
LDramECC = isDramECCEn_D(pDCTstat);
if (pDCTstat->ErrCode != SC_RunningOK) {
pDCTstat->Status &= ~(1 << SB_ECCDIMMs);
@@ -161,9 +161,9 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
}
if (AllECC)
- pMCTstat->GStatus |= 1<<GSB_ECCDIMMs;
+ pMCTstat->GStatus |= 1 << GSB_ECCDIMMs;
else
- pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs);
+ pMCTstat->GStatus &= ~(1 << GSB_ECCDIMMs);
/* Program the Dram BKScrub CTL to the proper (user selected) value.*/
/* Reset MC4_STS. */
@@ -172,11 +172,11 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
pDCTstat = pDCTstatA + Node;
LDramECC = 0;
if (NodePresent_D(Node)) { /* If Node is present */
- reg = 0x40+(Node<<3); /* Dram Base Node 0 + index */
+ reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */
val = Get_NB32(pDCTstat->dev_map, reg);
curBase = val & 0xffff0000;
/*WE/RE is checked because memory config may have been */
- if ((val & 3)==3) { /* Node has dram populated */
+ if ((val & 3) == 3) { /* Node has dram populated */
if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */
dev = pDCTstat->dev_nbmisc;
val = curBase << 8;
@@ -184,7 +184,7 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
val |= (1<<0); /* enable redirection */
}
Set_NB32(dev, 0x5C, val); /* Dram Scrub Addr Low */
- val = curBase>>24;
+ val = curBase >> 24;
Set_NB32(dev, 0x60, val); /* Dram Scrub Addr High */
Set_NB32(dev, 0x58, OF_ScrubCTL); /*Scrub Control */
@@ -236,16 +236,16 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat;
pDCTstat = pDCTstatA + Node;
if (NodePresent_D(Node)) { /* If Node is present*/
- reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/
+ reg = 0x40+(Node << 3); /* Dram Base Node 0 + index*/
val = Get_NB32(pDCTstat->dev_map, reg);
/*WE/RE is checked because memory config may have been*/
- if ((val & 3)==3) { /* Node has dram populated*/
- if ( isDramECCEn_D(pDCTstat)) {
+ if ((val & 3) == 3) { /* Node has dram populated*/
+ if (isDramECCEn_D(pDCTstat)) {
/*if ECC is enabled on this dram*/
dev = pDCTstat->dev_nbmisc;
reg = 0x44; /* MCA NB Configuration*/
val = Get_NB32(dev, reg);
- val |= (1<<SyncOnUcEccEn);
+ val |= (1 << SyncOnUcEccEn);
Set_NB32(dev, reg, val);
}
} /* Node has Dram*/
@@ -300,11 +300,11 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat)
} else {
ch_end = 2;
}
- for (i=0; i<ch_end; i++) {
- if (pDCTstat->DIMMValidDCT[i] > 0){
+ for (i = 0; i < ch_end; i++) {
+ if (pDCTstat->DIMMValidDCT[i] > 0) {
reg = 0x90 + i * 0x100; /* Dram Config Low */
val = Get_NB32(dev, reg);
- if (val & (1<<DimmEcEn)) {
+ if (val & (1 << DimmEcEn)) {
/* set local flag 'dram ecc capable' */
isDimmECCEn = 1;
break;
diff --git a/src/northbridge/amd/amdmct/mct/mctgr.c b/src/northbridge/amd/amdmct/mct/mctgr.c
index a13d4e2..41a479b 100644
--- a/src/northbridge/amd/amdmct/mct/mctgr.c
+++ b/src/northbridge/amd/amdmct/mct/mctgr.c
@@ -31,12 +31,12 @@ u32 mct_AdjustMemClkDis_GR(struct DCTStatStruc *pDCTstat, u32 dct,
DramTimingLo = val;
/* Dram Timing Low (owns Clock Enable bits) */
NewDramTimingLo = Get_NB32(dev, 0x88 + reg_off);
- if (mctGet_NVbits(NV_AllMemClks)==0) {
+ if (mctGet_NVbits(NV_AllMemClks) == 0) {
/*Special Jedec SPD diagnostic bit - "enable all clocks"*/
if (!(pDCTstat->Status & (1<<SB_DiagClks))) {
- for (i=0; i<MAX_DIMMS_SUPPORTED; i++) {
+ for (i = 0; i < MAX_DIMMS_SUPPORTED; i++) {
val = Tab_GRCLKDis[i];
- if (val<8) {
+ if (val < 8) {
if (!(pDCTstat->DIMMValidDCT[dct] & (1<<val))) {
/* disable memclk */
NewDramTimingLo |= (1<<(i+1));
diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index 5e91947..deb0f8a 100644
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -35,11 +35,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space.
- * Bottom40bIO=top of memory, right justified 8 bits
+ * Bottom40bIO = top of memory, right justified 8 bits
* (defines dram versus IO space type)
- * Bottom32bIO=sub 4GB top of memory, right justified 8 bits
+ * Bottom32bIO = sub 4GB top of memory, right justified 8 bits
* (defines dram versus IO space type)
- * Cache32bTOP=sub 4GB top of WB cacheable memory,
+ * Cache32bTOP = sub 4GB top of WB cacheable memory,
* right justified 8 bits
*/
@@ -83,8 +83,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
*/
addr = 0x204; /* MTRR phys base 2*/
/* use TOP_MEM as limit*/
- /* Limit=TOP_MEM|TOM2*/
- /* Base=0*/
+ /* Limit = TOP_MEM|TOM2*/
+ /* Base = 0*/
print_tx("\t CPUMemTyping: Cache32bTOP:", Cache32bTOP);
SetMTRRrangeWB_D(0, &Cache32bTOP, &addr);
/* Base */
@@ -115,10 +115,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
addr = 0xC0010010; /* SYS_CFG */
_RDMSR(addr, &lo, &hi);
if (Bottom40bIO) {
- lo |= (1<<21); /* MtrrTom2En=1 */
+ lo |= (1<<21); /* MtrrTom2En = 1 */
lo |= (1<<22); /* Tom2ForceMemTypeWB */
} else {
- lo &= ~(1<<21); /* MtrrTom2En=0 */
+ lo &= ~(1<<21); /* MtrrTom2En = 0 */
lo &= ~(1<<22); /* Tom2ForceMemTypeWB */
}
_WRMSR(addr, lo, hi);
@@ -151,7 +151,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
* next set bit in a forward or backward sequence of bits (as a function
* of the Limit). We start with the ascending path, to ensure that
* regions are naturally aligned, then we switch to the descending path
- * to maximize MTRR usage efficiency. Base=0 is a special case where we
+ * to maximize MTRR usage efficiency. Base = 0 is a special case where we
* start with the descending path. Correct Mask for region is
* 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1
*/
@@ -177,17 +177,17 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
curSize = valx;
valx += curBase;
}
- curLimit = valx; /*eax=curBase, edx=curLimit*/
+ curLimit = valx; /*eax = curBase, edx = curLimit*/
valx = val>>24;
val <<= 8;
/* now program the MTRR */
val |= MtrrType; /* set cache type (UC or WB)*/
_WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/
- val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/
+ val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/
valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */
val <<= 8;
- val |= ( 1 << 11); /* set MTRR valid*/
+ val |= (1 << 11); /* set MTRR valid*/
addr++;
_WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/
val = curLimit;
@@ -217,9 +217,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
/*======================================================================
* Adjust temp top of memory down to accommodate UMA memory start
*======================================================================*/
- /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits
+ /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits
* (defines dram versus IO space type)
- * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */
+ * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */
Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8;
@@ -238,7 +238,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
addr = 0x200;
lo = 0;
hi = lo;
- while ( addr < 0x20C) {
+ while (addr < 0x20C) {
_WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */
addr++; /* next MTRR pair addr */
}
diff --git a/src/northbridge/amd/amdmct/mct/mctndi_d.c b/src/northbridge/amd/amdmct/mct/mctndi_d.c
index 32c3199..389d56b 100644
--- a/src/northbridge/amd/amdmct/mct/mctndi_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctndi_d.c
@@ -72,7 +72,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
NodesWmem++;
Base &= 0xFFFF0000; /* Base[39:8] */
- if (pDCTstat->Status & (1 << SB_HWHole )) {
+ if (pDCTstat->Status & (1 << SB_HWHole)) {
/* to get true amount of dram,
* subtract out memory hole if HW dram remapping */
@@ -87,7 +87,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114);
if (DctSelBase) {
DctSelBase <<= 8;
- if ( pDCTstat->Status & (1 << SB_HWHole)) {
+ if (pDCTstat->Status & (1 << SB_HWHole)) {
if (DctSelBase >= 0x1000000) {
DctSelBase -= HWHoleSz;
}
@@ -104,7 +104,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
MemSize &= 0xFFFF0000;
MemSize += 0x00010000;
MemSize -= Base;
- if ( pDCTstat->Status & (1 << SB_HWHole)) {
+ if (pDCTstat->Status & (1 << SB_HWHole)) {
MemSize -= HWHoleSz;
}
if (Node == 0) {
@@ -144,7 +144,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
if (DoIntlv) {
MCTMemClr_D(pMCTstat,pDCTstatA);
/* Program Interleaving enabled on Node 0 map only.*/
- MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */
+ MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */
Dct0MemSize <<= bsf(Nodes);
MemSize0 += HWHoleSz;
Base = ((Nodes - 1) << 8) | 3;
@@ -185,7 +185,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
HoleBase = pMCTstat->HoleBase;
if (Dct0MemSize >= HoleBase) {
val = HWHoleSz;
- if ( Node == 0) {
+ if (Node == 0) {
val += Dct0MemSize;
}
} else {
diff --git a/src/northbridge/amd/amdmct/mct/mctpro_d.c b/src/northbridge/amd/amdmct/mct/mctpro_d.c
index 95afebf..6802a76 100644
--- a/src/northbridge/amd/amdmct/mct/mctpro_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctpro_d.c
@@ -36,13 +36,13 @@ u32 OtherTiming_A_D(struct DCTStatStruc *pDCTstat, u32 val)
{
/* Bug#10695:One MEMCLK Bubble Writes Don't Do X4 X8 Switching Correctly
* Solution: BIOS should set DRAM Timing High[Twrwr] > 00b
- * ( F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B
+ * (F2x[1, 0]8C[1:0] > 00b). Silicon Status: Fixed in Rev B
* FIXME: check if this is still required.
*/
uint64_t tmp;
tmp = pDCTstat->LogicalCPUID;
if ((tmp == AMD_DR_A0A) || (tmp == AMD_DR_A1B) || (tmp == AMD_DR_A2)) {
- if (!(val & (3<<12) ))
+ if (!(val & (3<<12)))
val |= 1<<12;
}
return val;
@@ -69,7 +69,7 @@ void mct_ForceAutoPrecharge_D(struct DCTStatStruc *pDCTstat, u32 dct)
val |= 1<<BurstLength32;
Set_NB32(dev, reg, val);
- reg = 0x88 + reg_off; /* cx=Dram Timing Lo */
+ reg = 0x88 + reg_off; /* cx = Dram Timing Lo */
val = Get_NB32(dev, reg);
val |= 0x000F0000; /* Trc = 0Fh */
Set_NB32(dev, reg, val);
@@ -89,7 +89,7 @@ void mct_EndDQSTraining_D(struct MCTStatStruc *pMCTstat,
* NOTE -- this has been documented with a note at the end of this
* section in the BKDG (although, admittedly, the note does not really
* stand out).
- * Silicon Status: Fixed in Rev B ( confirm)
+ * Silicon Status: Fixed in Rev B (confirm)
* FIXME: check this.
*/
@@ -149,14 +149,14 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat,
dev = pDCTstat->dev_dct;
index = 0;
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
index_reg = 0x98 + 0x100 * Channel;
val = Get_NB32_index_wait(dev, index_reg, 0x0d004007);
val |= 0x3ff;
Set_NB32_index_wait(dev, index_reg, 0x0d0f4f07, val);
}
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
if (pDCTstat->GangedMode && Channel)
break;
reg_off = 0x100 * Channel;
@@ -167,11 +167,11 @@ void mct_BeforeDQSTrain_Samp_D(struct MCTStatStruc *pMCTstat,
Set_NB32(dev, reg, val);
}
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
reg_off = 0x100 * Channel;
val = 0;
index_reg = 0x98 + reg_off;
- for ( index = 0x30; index < (0x45 + 1); index++) {
+ for (index = 0x30; index < (0x45 + 1); index++) {
Set_NB32_index_wait(dev, index_reg, index, val);
}
}
@@ -211,7 +211,7 @@ u32 Modify_D3CMP(struct DCTStatStruc *pDCTstat, u32 dct, u32 value)
index = 0x0D004201;
val = Get_NB32_index_wait(dev, index_reg, index);
value &= ~(1<<27);
- value |= ((val>>10) & 1) << 27;
+ value |= ((val >> 10) & 1) << 27;
}
return value;
}
@@ -254,10 +254,10 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct)
/* 3 * (Fn2xD4[NBFid]+4)/(2^NbDid)/(3+Fn2x94[MemClkFreq]) */
msr = 0xC0010071;
_RDMSR(msr, &lo, &hi);
- NbDid = (lo>>22) & 1;
+ NbDid = (lo >> 22) & 1;
val = Get_NB32(pDCTstat->dev_dct, 0x94 + 0x100 * dct);
- valx = ((val & 0x07) + 3)<<NbDid;
+ valx = ((val & 0x07) + 3) << NbDid;
print_tx("MemClk:", valx >> NbDid);
val = Get_NB32(pDCTstat->dev_nbmisc, 0xd4);
@@ -265,7 +265,7 @@ u32 CheckNBCOFAutoPrechg(struct DCTStatStruc *pDCTstat, u32 dct)
print_tx("NB COF:", valy >> NbDid);
val = valy/valx;
- if ((val==3) && (valy%valx)) /* 3 < NClk/MemClk < 4 */
+ if ((val == 3) && (valy % valx)) /* 3 < NClk/MemClk < 4 */
ret = 1;
return ret;
@@ -296,7 +296,7 @@ void mct_BeforeDramInit_D(struct DCTStatStruc *pDCTstat, u32 dct)
}
dev = pDCTstat->dev_dct;
index = 0x0D00E001;
- for (ch=ch_start; ch<ch_end; ch++) {
+ for (ch = ch_start; ch < ch_end; ch++) {
index_reg = 0x98 + 0x100 * ch;
val = Get_NB32_index(dev, index_reg, 0x0D00E001);
val &= ~(0xf0);
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc.c b/src/northbridge/amd/amdmct/mct/mctsrc.c
index 510cf0d..a87cea8 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc.c
@@ -86,7 +86,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat,
p_A = (u32 *)SetupDqsPattern_1PassB(pass);
p_B = (u32 *)SetupDqsPattern_1PassA(pass);
- for (i=0;i<16;i++) {
+ for (i = 0; i < 16; i++) {
buf_a[i] = p_A[i];
buf_b[i] = p_B[i];
}
@@ -161,7 +161,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
print_t("TrainRcvrEn: 1\n");
cr4 = read_cr4();
- if (cr4 & ( 1 << 9)) { /* save the old value */
+ if (cr4 & (1 << 9)) { /* save the old value */
_SSE2 = 1;
}
cr4 |= (1 << 9); /* OSFXSR enable SSE2 */
@@ -261,7 +261,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
if (Pass == FirstPass) {
pDCTstat->DqsRcvEn_Pass = 0;
} else {
- pDCTstat->DqsRcvEn_Pass=0xFF;
+ pDCTstat->DqsRcvEn_Pass = 0xFF;
}
pDCTstat->DqsRcvEn_Saved = 0;
@@ -446,7 +446,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(msr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -456,7 +456,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
{
u8 Channel;
printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
@@ -472,10 +472,10 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n");
for (Channel = 0; Channel < 2; Channel++) {
printk(BIOS_DEBUG, "Channel: %02x\n", Channel);
- for (Receiver = 0; Receiver<8; Receiver+=2) {
+ for (Receiver = 0; Receiver < 8; Receiver+=2) {
printk(BIOS_DEBUG, "\t\tReceiver: %02x: ", Receiver);
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver>>1];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
val = p[i];
printk(BIOS_DEBUG, "%02x ", val);
}
@@ -494,7 +494,7 @@ static void dqsTrainRcvrEn_SW(struct MCTStatStruc *pMCTstat,
u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct)
{
- if (pDCTstat->DIMMValidDCT[dct] == 0 ) {
+ if (pDCTstat->DIMMValidDCT[dct] == 0) {
return 8;
} else {
return 0;
@@ -526,7 +526,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
ch_end = 2;
}
- for (ch=0; ch<ch_end; ch++) {
+ for (ch = 0; ch < ch_end; ch++) {
reg = 0x78 + 0x100 * ch;
val = Get_NB32(dev, reg);
val &= ~(1 << DqsRcvEnTrain);
@@ -562,14 +562,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u8 RcvrEnDly,
/* DimmOffset not needed for CH_D_B_RCVRDLY array */
- for (i=0; i < 8; i++) {
+ for (i = 0; i < 8; i++) {
if (FinalValue) {
/*calculate dimm offset */
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
RcvrEnDly = p[i];
}
- /* if flag=0, set DqsRcvEn value to reg. */
+ /* if flag = 0, set DqsRcvEn value to reg. */
/* get the register index from table */
index = Table_DQSRcvEn_Offset[i >> 1];
index += Addl_Index; /* DIMMx DqsRcvEn byte0 */
@@ -661,7 +661,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u8 DQ
valx = (val + 3) << 2;
val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4);
- SubTotal *= ((val & 0x1f) + 4 ) * 3;
+ SubTotal *= ((val & 0x1f) + 4) * 3;
SubTotal /= valx;
if (SubTotal % valx) { /* round up */
@@ -723,7 +723,7 @@ static u8 mct_SavePassRcvEnDly_D(struct DCTStatStruc *pDCTstat,
mask_Saved &= mask_Pass;
p = pDCTstat->CH_D_B_RCVRDLY[Channel][receiver>>1];
}
- for (i=0; i < 8; i++) {
+ for (i = 0; i < 8; i++) {
/* cmp per byte lane */
if (mask_Pass & (1 << i)) {
if (!(mask_Saved & (1 << i))) {
@@ -757,7 +757,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
if (Pass == FirstPass) {
- if (pattern==1) {
+ if (pattern == 1) {
test_buf = (u8 *)TestPattern1_D;
} else {
test_buf = (u8 *)TestPattern0_D;
@@ -769,13 +769,13 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
SetUpperFSbase(addr);
addr <<= 8;
- if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) {
+ if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) {
addr += 8; /* second channel */
test_buf += 8;
}
print_debug_dqs_pair("\t\t\t\t\t\t test_buf = ", (u32)test_buf, " | addr_lo = ", addr, 4);
- for (i=0; i<8; i++) {
+ for (i = 0; i < 8; i++) {
value = read32_fs(addr);
print_debug_dqs_pair("\t\t\t\t\t\t\t\t ", test_buf[i], " | ", value, 4);
@@ -790,7 +790,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
if (Pass == FirstPass) {
/* if first pass, at least one byte lane pass
- * ,then DQS_PASS=1 and will set to related reg.
+ * ,then DQS_PASS = 1 and will set to related reg.
*/
if (pDCTstat->DqsRcvEn_Pass != 0) {
result = DQS_PASS;
@@ -800,7 +800,7 @@ static u8 mct_CompareTestPatternQW0_D(struct MCTStatStruc *pMCTstat,
} else {
/* if second pass, at least one byte lane fail
- * ,then DQS_FAIL=1 and will set to related reg.
+ * ,then DQS_FAIL = 1 and will set to related reg.
*/
if (pDCTstat->DqsRcvEn_Pass != 0xFF) {
result = DQS_FAIL;
@@ -843,7 +843,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
* Read Position is 1/2 Memclock Delay
*/
u8 i;
- for (i=0;i<2; i++){
+ for (i = 0; i < 2; i++) {
InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i);
}
}
@@ -867,8 +867,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
// FIXME: add Cx support
dword = 0x00000000;
- for (i=1; i<=3; i++) {
- for (j=0; j<dn; j++)
+ for (i = 1; i <= 3; i++) {
+ for (j = 0; j < dn; j++)
/* DIMM0 Write Data Timing Low */
/* DIMM0 Write ECC Timing */
Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword);
@@ -876,14 +876,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
/* errata #180 */
dword = 0x2f2f2f2f;
- for (i=5; i<=6; i++) {
- for (j=0; j<dn; j++)
+ for (i = 5; i <= 6; i++) {
+ for (j = 0; j < dn; j++)
/* DIMM0 Read DQS Timing Control Low */
Set_NB32_index_wait(dev, index_reg, i + 0x100 * j, dword);
}
dword = 0x0000002f;
- for (j=0; j<dn; j++)
+ for (j = 0; j < dn; j++)
/* DIMM0 Read DQS ECC Timing Control */
Set_NB32_index_wait(dev, index_reg, 7 + 0x100 * j, dword);
}
@@ -969,7 +969,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
if (!pDCTstat->NodePresent)
break;
if (pDCTstat->DCTSysLimit) {
- for (i=0; i<2; i++)
+ for (i = 0; i < 2; i++)
CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
}
}
@@ -1081,5 +1081,5 @@ void mct_Wait(u32 cycles)
saved = lo;
do {
_RDMSR(msr, &lo, &hi);
- } while (lo - saved < cycles );
+ } while (lo - saved < cycles);
}
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc1p.c b/src/northbridge/amd/amdmct/mct/mctsrc1p.c
index e059e1e..c1b1133 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc1p.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc1p.c
@@ -50,7 +50,7 @@ static u8 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel,
MaxValue = 0;
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
- for (i=0; i < 8; i++) {
+ for (i = 0; i < 8; i++) {
/* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/
val = p[i];
/* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/
diff --git a/src/northbridge/amd/amdmct/mct/mctsrc2p.c b/src/northbridge/amd/amdmct/mct/mctsrc2p.c
index bd3c503..c7c92ac 100644
--- a/src/northbridge/amd/amdmct/mct/mctsrc2p.c
+++ b/src/northbridge/amd/amdmct/mct/mctsrc2p.c
@@ -62,7 +62,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
bn = 8;
// print_tx("mct_Get_Start_RcvrEnDly_Pass: Channel:", Channel);
// print_tx("mct_Get_Start_RcvrEnDly_Pass: Receiver:", Receiver);
- for ( i=0;i<bn; i++) {
+ for (i = 0; i < bn; i++) {
val = p[i];
// print_tx("mct_Get_Start_RcvrEnDly_Pass: i:", i);
// print_tx("mct_Get_Start_RcvrEnDly_Pass: val:", val);
@@ -100,7 +100,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
//FIXME: which byte?
p_1 = pDCTstat->B_RCVRDLY_1;
// p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1];
- for (i=0; i<bn; i++) {
+ for (i = 0; i < bn; i++) {
val = p[i];
/* left edge */
if (val != (RcvrEnDlyLimit - 1)) {
@@ -120,7 +120,7 @@ u8 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
}
} else {
- for (i=0; i < bn; i++) {
+ for (i = 0; i < bn; i++) {
val = p[i];
/* Add 1/2 Memlock delay */
//val += Pass1MemClkDly;
diff --git a/src/northbridge/amd/amdmct/mct/mcttmrl.c b/src/northbridge/amd/amdmct/mct/mcttmrl.c
index 0eb3c61..1095259 100644
--- a/src/northbridge/amd/amdmct/mct/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct/mcttmrl.c
@@ -149,7 +149,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1);
pDCTstat->Channel = Channel;
- if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel)
+ if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel)
break; /*if ganged mode, skip DCT 1 */
TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid);
@@ -164,7 +164,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */
mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly);
ReadMaxRdLat1CLTestPattern_D(TestAddr0);
- if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS)
+ if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS)
break;
SetTargetWTIO_D(TestAddr0);
FlushMaxRdLatTestPattern_D(TestAddr0);
@@ -185,7 +185,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(addr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -195,7 +195,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
{
u8 Channel;
printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
printk(BIOS_DEBUG, "Channel: %02x: %02x\n", Channel, pDCTstat->CH_MaxRdLat[Channel]);
}
}
@@ -213,7 +213,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) {
Channel = 0; // for safe
- for (i=0; i<2; i++)
+ for (i = 0; i < 2; i++)
pDCTstat->CH_MaxRdLat[i] = MaxRdLatVal;
} else {
pDCTstat->CH_MaxRdLat[Channel] = MaxRdLatVal;
@@ -223,7 +223,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
reg = 0x78 + Channel * 0x100;
val = Get_NB32(dev, reg);
val &= ~(0x3ff<<22);
- val |= MaxRdLatVal<<22;
+ val |= MaxRdLatVal << 22;
/* program MaxRdLatency to correspond with current delay */
Set_NB32(dev, reg, val);
@@ -244,10 +244,10 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr)
u8 ret = DQS_PASS;
SetUpperFSbase(addr);
- addr_lo = addr<<8;
+ addr_lo = addr << 8;
_EXECFENCE;
- for (i=0; i<(16*3); i++) {
+ for (i = 0; i < (16*3); i++) {
val = read32_fs(addr_lo);
val_test = test_buf[i];
@@ -292,11 +292,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat,
*valid = 0;
for (ch = ch_start; ch < ch_end; ch++) {
- for (d=0; d<4; d++) {
- for (Byte = 0; Byte<bn; Byte++) {
+ for (d = 0; d < 4; d++) {
+ for (Byte = 0; Byte < bn; Byte++) {
u8 tmp;
tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte];
- if (tmp>Max) {
+ if (tmp > Max) {
Max = tmp;
Channel_Max = Channel;
d_Max = d;
@@ -382,7 +382,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat,
val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4);
- val = ((val & 0x1f) + 4 ) * 3;
+ val = ((val & 0x1f) + 4) * 3;
/* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */
valxx = val << 2;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
index 08d8d43..da2a4fe 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
@@ -2625,7 +2625,7 @@ static void mctAutoInitMCT_D(struct MCTStatStruc *pMCTstat,
* 1. BSP in Big Real Mode
* 2. Stack at SS:SP, located somewhere between A000:0000 and F000:FFFF
* 3. Checksummed or Valid NVRAM bits
- * 4. MCG_CTL=-1, MC4_CTL_EN=0 for all CPUs
+ * 4. MCG_CTL = -1, MC4_CTL_EN = 0 for all CPUs
* 5. MCi_STS from shutdown/warm reset recorded (if desired) prior to entry
* 6. All var MTRRs reset to zero
* 7. State of NB_CFG.DisDatMsk set properly on all CPUs
@@ -3819,7 +3819,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
}
}
}
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
SetEccDQSRcvrEn_D(pDCTstat, Channel);
}
@@ -3859,7 +3859,7 @@ static void LoadDQSSigTmgRegs_D(struct MCTStatStruc *pMCTstat,
}
}
- for (Channel = 0; Channel<2; Channel++) {
+ for (Channel = 0; Channel < 2; Channel++) {
reg = 0x78;
val = Get_NB32_DCT(dev, Channel, reg);
val &= ~(0x3ff<<22);
@@ -3993,7 +3993,7 @@ static void HTMemMapInit_D(struct MCTStatStruc *pMCTstat,
val = Get_NB32(dev, reg);
Set_NB32(devx, reg, val);
reg += 4;
- } while ( reg < 0x80);
+ } while (reg < 0x80);
} else {
break; /* stop at first absent Node */
}
@@ -4015,7 +4015,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
uint32_t dword;
struct DCTStatStruc *pDCTstat;
- if (!mctGet_NVbits(NV_DQSTrainCTL)){
+ if (!mctGet_NVbits(NV_DQSTrainCTL)) {
/* FIXME: callback to wrapper: mctDoWarmResetMemClr_D */
} else { /* NV_DQSTrainCTL == 1 */
for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
@@ -4080,7 +4080,7 @@ static void DCTMemClr_Sync_D(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "%s: Start\n", __func__);
/* Ensure that a memory clear operation has completed on one node */
- if (pDCTstat->DCTSysLimit){
+ if (pDCTstat->DCTSysLimit) {
printk(BIOS_DEBUG, "%s: Waiting for memory clear to complete", __func__);
do {
dword = Get_NB32(dev, 0x110);
@@ -4223,7 +4223,7 @@ static void DCTFinalInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *p
dword &= ~(1 << ParEn);
Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x90, dword);
- /* To maximize power savings when DisDramInterface=1b,
+ /* To maximize power savings when DisDramInterface = 1b,
* all of the MemClkDis bits should also be set.
*/
Set_NB32_DCT(pDCTstat->dev_dct, dct, 0x88, 0xff000000);
@@ -4369,16 +4369,16 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
Trc = 0;
Twr = 0;
Twtr = 0;
- for (i=0; i < 2; i++)
+ for (i = 0; i < 2; i++)
Etr[i] = 0;
- for (i=0; i < 4; i++)
+ for (i = 0; i < 4; i++)
Trfc[i] = 0;
Tfaw = 0;
- for ( i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
+ for (i = 0; i< MAX_DIMMS_SUPPORTED; i++) {
LDIMM = i >> 1;
if (pDCTstat->DIMMValid & (1 << i)) {
- val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB=Dividend/Divisor */
+ val = pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDivisor]; /* MTB = Dividend/Divisor */
MTB16x = ((pDCTstat->spd_data.spd_bytes[dct + i][SPD_MTBDividend] & 0xff) << 4);
MTB16x /= val; /* transfer to MTB*16 */
@@ -4574,7 +4574,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
pDCTstat->Twtr = val;
/* Trfc0-Trfc3 */
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
pDCTstat->Trfc[i] = Trfc[i];
/* Tfaw */
@@ -4647,7 +4647,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
Set_NB32_DCT(dev, dct, 0x204, dword); /* DRAM Timing 1 */
/* Trfc0-Trfc3 */
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
if (pDCTstat->Trfc[i] == 0x0)
pDCTstat->Trfc[i] = 0x1;
dword = Get_NB32_DCT(dev, dct, 0x208); /* DRAM Timing 2 */
@@ -4714,7 +4714,7 @@ static void SPD2ndTiming(struct MCTStatStruc *pMCTstat,
DramTimingHi |= val<<16;
val = 0;
- for (i=4;i>0;i--) {
+ for (i = 4; i > 0; i--) {
val <<= 3;
val |= Trfc[i-1];
}
@@ -4850,7 +4850,7 @@ static void GetPresetmaxF_D(struct MCTStatStruc *pMCTstat,
proposedFreq = 800; /* Rev F0 programmable max memclock is */
/*Get User defined limit if "limit" mode */
- if ( mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
+ if (mctGet_NVbits(NV_MCTUSRTMGMODE) == 1) {
word = Get_Fk_D(mctGet_NVbits(NV_MemCkVal) + 1);
if (word < proposedFreq)
proposedFreq = word;
@@ -4984,7 +4984,7 @@ static void SPDGetTCL_D(struct MCTStatStruc *pMCTstat,
determine the desired CAS Latency. If tCKproposed is not a standard JEDEC
value (2.5, 1.875, 1.5, or 1.25 ns) then tCKproposed must be adjusted to the
next lower standard tCK value for calculating CLdesired.
- CLdesired = ceiling ( tAAmin(all) / tCKproposed )
+ CLdesired = ceiling (tAAmin(all) / tCKproposed)
where tAAmin is defined in Byte 16. The ceiling function requires that the
quotient be rounded up always. */
CLdesired = tAAmin16x / tCKproposed16x;
@@ -5163,7 +5163,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
if (mctGet_NVbits(NV_ECC_CAP))
if (Status & (1 << SB_ECCDIMMs))
- if ( mctGet_NVbits(NV_ECC))
+ if (mctGet_NVbits(NV_ECC))
DramConfigLo |= 1 << DimmEcEn;
DramConfigLo = mct_DisDllShutdownSR(pMCTstat, pDCTstat, DramConfigLo, dct);
@@ -5210,7 +5210,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
DramConfigHi |= 1 << 18; /* R4 (4-Rank Registered DIMMs) */
}
- if (0) /* call back not needed mctOverrideDcqBypMax_D ) */
+ if (0) /* call back not needed mctOverrideDcqBypMax_D) */
val = mctGet_NVbits(NV_BYPMAX);
else
val = 0x0f; /* recommended setting (default) */
@@ -5224,7 +5224,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
1. We will assume that MemClkDis field has been preset prior to this
point.
2. We will only set MemClkDis bits if a DIMM is NOT present AND if:
- NV_AllMemClks <>0 AND SB_DiagClks ==0 */
+ NV_AllMemClks <>0 AND SB_DiagClks == 0 */
/* Dram Timing Low (owns Clock Enable bits) */
DramTimingLo = Get_NB32_DCT(dev, dct, 0x88);
@@ -5253,7 +5253,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
dword = 0;
byte = 0xFF;
while (dword < MAX_CS_SUPPORTED) {
- if (pDCTstat->CSPresent & (1<<dword)){
+ if (pDCTstat->CSPresent & (1<<dword)) {
/* re-enable clocks for the enabled CS */
val = p[dword];
byte &= ~val;
@@ -5330,11 +5330,11 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
if (pDCTstat->DIMMValid & (1<<byte)) {
byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Addressing];
- Rows = (byte >> 3) & 0x7; /* Rows:0b=12-bit,... */
- Cols = byte & 0x7; /* Cols:0b=9-bit,... */
+ Rows = (byte >> 3) & 0x7; /* Rows:0b = 12-bit,... */
+ Cols = byte & 0x7; /* Cols:0b = 9-bit,... */
byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Density];
- Banks = (byte >> 4) & 7; /* Banks:0b=3-bit,... */
+ Banks = (byte >> 4) & 7; /* Banks:0b = 3-bit,... */
byte = pDCTstat->spd_data.spd_bytes[ChipSel + dct][SPD_Organization];
Ranks = ((byte >> 3) & 7) + 1;
@@ -5351,7 +5351,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
byte |= Rows << 3; /* RRRBCC internal encode */
- for (dword=0; dword < 13; dword++) {
+ for (dword = 0; dword < 13; dword++) {
if (byte == Tab_BankAddr[dword])
break;
}
@@ -5367,7 +5367,7 @@ static void SPDSetBanks_D(struct MCTStatStruc *pMCTstat,
or 2pow(rows+cols+banks-5)-1*/
csMask = 0;
- byte = Rows + Cols; /* cl=rows+cols*/
+ byte = Rows + Cols; /* cl = rows+cols*/
byte += 21; /* row:12+col:9 */
byte -= 2; /* 3 banks - 5 */
@@ -5435,7 +5435,7 @@ static void SPDCalcWidth_D(struct MCTStatStruc *pMCTstat,
/* Check Symmetry of Channel A and Channel B DIMMs
(must be matched for 128-bit mode).*/
- for (i=0; i < MAX_DIMMS_SUPPORTED; i += 2) {
+ for (i = 0; i < MAX_DIMMS_SUPPORTED; i += 2) {
if ((pDCTstat->DIMMValid & (1 << i)) && (pDCTstat->DIMMValid & (1<<(i+1)))) {
byte = pDCTstat->spd_data.spd_bytes[i][SPD_Addressing] & 0x7;
byte1 = pDCTstat->spd_data.spd_bytes[i + 1][SPD_Addressing] & 0x7;
@@ -5498,7 +5498,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
_DSpareEn = 0;
- /* CS Sparing 1=enabled, 0=disabled */
+ /* CS Sparing 1 = enabled, 0 = disabled */
if (mctGet_NVbits(NV_CS_SpareCTL) & 1) {
if (MCT_DIMM_SPARE_NO_WARM) {
/* Do no warm-reset DIMM spare */
@@ -5513,7 +5513,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
pDCTstat->ErrStatus |= 1 << SB_SpareDis;
}
} else {
- if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1=enabled, 0=disabled */
+ if (!mctGet_NVbits(NV_DQSTrainCTL)) { /*DQS Training 1 = enabled, 0 = disabled */
word = pDCTstat->CSPresent;
val = bsf(word);
word &= ~(1 << val);
@@ -5527,13 +5527,13 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
}
nxtcsBase = 0; /* Next available cs base ADDR[39:8] */
- for (p=0; p < MAX_DIMMS_SUPPORTED; p++) {
+ for (p = 0; p < MAX_DIMMS_SUPPORTED; p++) {
BiggestBank = 0;
for (q = 0; q < MAX_CS_SUPPORTED; q++) { /* from DIMMS to CS */
if (pDCTstat->CSPresent & (1 << q)) { /* bank present? */
reg = 0x40 + (q << 2); /* Base[q] reg.*/
val = Get_NB32_DCT(dev, dct, reg);
- if (!(val & 3)) { /* (CSEnable|Spare==1)bank is enabled already? */
+ if (!(val & 3)) { /* (CSEnable|Spare == 1)bank is enabled already? */
reg = 0x60 + (q << 1); /*Mask[q] reg.*/
val = Get_NB32_DCT(dev, dct, reg);
val >>= 19;
@@ -5549,7 +5549,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
} /*if bank present */
} /* while q */
if (BiggestBank !=0) {
- curcsBase = nxtcsBase; /* curcsBase=nxtcsBase*/
+ curcsBase = nxtcsBase; /* curcsBase = nxtcsBase*/
/* DRAM CS Base b Address Register offset */
reg = 0x40 + (b << 2);
if (_DSpareEn) {
@@ -5579,7 +5579,7 @@ static void StitchMemory_D(struct MCTStatStruc *pMCTstat,
}
/* bank present but disabled?*/
- if ( pDCTstat->CSTestFail & (1 << p)) {
+ if (pDCTstat->CSTestFail & (1 << p)) {
/* DRAM CS Base b Address Register offset */
reg = (p << 2) + 0x40;
val = 1 << TestFail;
@@ -5611,12 +5611,12 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
/* Check DIMMs present, verify checksum, flag SDRAM type,
* build population indicator bitmaps, and preload bus loading
* of DIMMs into DCTStatStruc.
- * MAAload=number of devices on the "A" bus.
- * MABload=number of devices on the "B" bus.
- * MAAdimms=number of DIMMs on the "A" bus slots.
- * MABdimms=number of DIMMs on the "B" bus slots.
- * DATAAload=number of ranks on the "A" bus slots.
- * DATABload=number of ranks on the "B" bus slots.
+ * MAAload = number of devices on the "A" bus.
+ * MABload = number of devices on the "B" bus.
+ * MAAdimms = number of DIMMs on the "A" bus slots.
+ * MABdimms = number of DIMMs on the "B" bus slots.
+ * DATAAload = number of ranks on the "A" bus slots.
+ * DATABload = number of ranks on the "B" bus slots.
*/
u16 i, j, k;
u8 smbaddr;
@@ -5747,7 +5747,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
byte &= 7;
if (byte == 3) { /* 4ranks */
/* if any DIMMs are QR, we have to make two passes through DIMMs*/
- if ( pDCTstat->DimmQRPresent == 0) {
+ if (pDCTstat->DimmQRPresent == 0) {
MaxDimms <<= 1;
}
if (i < DimmSlots) {
@@ -5767,7 +5767,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
else if (devwidth == 2)
bytex = 4;
- byte++; /* al+1=rank# */
+ byte++; /* al+1 = rank# */
if (byte == 2)
bytex <<= 1; /*double Addr bus load value for dual rank DIMMs*/
@@ -5847,7 +5847,7 @@ static u8 DIMMPresence_D(struct MCTStatStruc *pMCTstat,
}
}
if (pDCTstat->DimmECCPresent != 0) {
- if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid )== 0) {
+ if ((pDCTstat->DimmECCPresent ^ pDCTstat->DIMMValid) == 0) {
/* all DIMMs are ECC capable */
pDCTstat->Status |= 1<<SB_ECCDIMMs;
}
@@ -5961,7 +5961,7 @@ static void mct_initDCT(struct MCTStatStruc *pMCTstat,
val &= ~(1 << ParEn);
Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x90, val);
- /* To maximize power savings when DisDramInterface=1b,
+ /* To maximize power savings when DisDramInterface = 1b,
* all of the MemClkDis bits should also be set.
*/
Set_NB32_DCT(pDCTstat->dev_dct, 1, 0x88, 0xff000000);
@@ -6119,7 +6119,7 @@ static u8 mct_PlatformSpec(struct MCTStatStruc *pMCTstat,
i_start = dct;
i_end = dct + 1;
}
- for (i=i_start; i<i_end; i++) {
+ for (i = i_start; i < i_end; i++) {
index_reg = 0x98;
Set_NB32_index_wait_DCT(dev, i, index_reg, 0x00, pDCTstat->CH_ODC_CTL[i]); /* Channel A/B Output Driver Compensation Control */
Set_NB32_index_wait_DCT(dev, i, index_reg, 0x04, pDCTstat->CH_ADDR_TMG[i]); /* Channel A/B Output Driver Compensation Control */
@@ -6152,7 +6152,7 @@ static void mct_AfterGetCLT(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat, u8 dct)
{
if (!pDCTstat->GangedMode) {
- if (dct == 0 ) {
+ if (dct == 0) {
pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[dct];
if (pDCTstat->DIMMValidDCT[dct] == 0)
pDCTstat->ErrCode = SC_StopError;
@@ -6172,7 +6172,7 @@ static u8 mct_SPDCalcWidth(struct MCTStatStruc *pMCTstat,
u8 ret;
u32 val;
- if ( dct == 0) {
+ if (dct == 0) {
SPDCalcWidth_D(pMCTstat, pDCTstat);
ret = mct_setMode(pMCTstat, pDCTstat);
} else {
@@ -6313,7 +6313,7 @@ static void mct_OtherTiming(struct MCTStatStruc *pMCTstat,
pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[0];
Set_OtherTiming(pMCTstat, pDCTstat, 0);
}
- if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode ) {
+ if (pDCTstat->DIMMValidDCT[1] && !pDCTstat->GangedMode) {
pDCTstat->DIMMValid = pDCTstat->DIMMValidDCT[1];
Set_OtherTiming(pMCTstat, pDCTstat, 1);
}
@@ -6568,8 +6568,8 @@ static u16 Get_DqsRcvEnGross_MaxMin(struct DCTStatStruc *pDCTstat,
if (index == 0x12)
ecc_reg = 1;
- for (i=0; i < 8; i+=2) {
- if ( pDCTstat->DIMMValid & (1 << i)) {
+ for (i = 0; i < 8; i+=2) {
+ if (pDCTstat->DIMMValid & (1 << i)) {
val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index);
val &= 0x00E000E0;
byte = (val >> 5) & 0xFF;
@@ -6607,11 +6607,11 @@ static u16 Get_WrDatGross_MaxMin(struct DCTStatStruc *pDCTstat,
Smallest = 3;
Largest = 0;
- for (i=0; i < 2; i++) {
+ for (i = 0; i < 2; i++) {
val = Get_NB32_index_wait_DCT(dev, dct, index_reg, index);
val &= 0x60606060;
val >>= 5;
- for (j=0; j < 4; j++) {
+ for (j = 0; j < 4; j++) {
byte = val & 0xFF;
if (byte < Smallest)
Smallest = byte;
@@ -6774,7 +6774,7 @@ static void mct_FinalMCT_D(struct MCTStatStruc *pMCTstat,
/* ClrClToNB_D postponed until we're done executing from ROM */
mct_ClrWbEnhWsbDis_D(pMCTstat, pDCTstat);
- /* set F3x8C[DisFastTprWr] on all DR, if L3Size=0 */
+ /* set F3x8C[DisFastTprWr] on all DR, if L3Size = 0 */
if (pDCTstat->LogicalCPUID & AMD_DR_ALL) {
if (!(cpuid_edx(0x80000006) & 0xFFFC0000)) {
val = Get_NB32(pDCTstat->dev_nbmisc, 0x8C);
@@ -6948,7 +6948,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
/* Copy dram map from F1x40/44,F1x48/4c,
to F1x120/124(Node0),F1x120/124(Node1),...*/
- for (Node=0; Node < MAX_NODES_SUPPORTED; Node++) {
+ for (Node = 0; Node < MAX_NODES_SUPPORTED; Node++) {
pDCTstat = pDCTstatA + Node;
devx = pDCTstat->dev_map;
@@ -6975,7 +6975,7 @@ static void mct_HTMemMapExt(struct MCTStatStruc *pMCTstat,
val |= Dramlimit;
Set_NB32(devx, reg, val);
- if ( pMCTstat->GStatus & ( 1 << GSB_HWHole)) {
+ if (pMCTstat->GStatus & (1 << GSB_HWHole)) {
reg = 0xF0;
val = Get_NB32(devx, reg);
val |= (1 << DramMemHoistValid);
@@ -7328,7 +7328,7 @@ static void InitPhyCompensation(struct MCTStatStruc *pMCTstat,
} else {
dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x00);
dword = 0;
- for (i=0; i < 6; i++) {
+ for (i = 0; i < 6; i++) {
switch (i) {
case 0:
case 4:
@@ -7668,7 +7668,7 @@ static void mct_ProgramODT_D(struct MCTStatStruc *pMCTstat,
dword = 0x00000800;
else
dword = 0x00000000;
- for (i=0; i < 2; i++) {
+ for (i = 0; i < 2; i++) {
Set_NB32_DCT(dev, i, 0x98, 0x0D000030);
Set_NB32_DCT(dev, i, 0x9C, dword);
Set_NB32_DCT(dev, i, 0x98, 0x4D040F30);
@@ -7958,11 +7958,11 @@ void ProgDramMRSReg_D(struct MCTStatStruc *pMCTstat,
DramMRS |= mct_DramTermDyn_RDimm(pMCTstat, pDCTstat, byte);
}
- /* Qoff=0, output buffers enabled */
+ /* Qoff = 0, output buffers enabled */
/* Tcwl */
DramMRS |= (pDCTstat->Speed - 4) << 20;
- /* ASR=1, auto self refresh */
- /* SRT=0 */
+ /* ASR = 1, auto self refresh */
+ /* SRT = 0 */
DramMRS |= 1 << 18;
}
@@ -7989,10 +7989,10 @@ void mct_SetDramConfigHi_D(struct MCTStatStruc *pMCTstat,
* Solution: From the bug report:
* 1. A software-initiated frequency change should be wrapped into the
* following sequence :
- * - a) Disable Compensation (F2[1, 0]9C_x08[30] )
+ * - a) Disable Compensation (F2[1, 0]9C_x08[30])
* b) Reset the Begin Compensation bit (D3CMP->COMP_CONFIG[0]) in all the compensation engines
* c) Do frequency change
- * d) Enable Compensation (F2[1, 0]9C_x08[30] )
+ * d) Enable Compensation (F2[1, 0]9C_x08[30])
* 2. A software-initiated Disable Compensation should always be
* followed by step b) of the above steps.
* Silicon Status: Fixed In Rev B0
@@ -8275,9 +8275,9 @@ static void AfterDramInit_D(struct DCTStatStruc *pDCTstat, u8 dct) {
/* ==========================================================
* 6-bit Bank Addressing Table
- * RR=rows-13 binary
- * B=Banks-2 binary
- * CCC=Columns-9 binary
+ * RR = rows-13 binary
+ * B = Banks-2 binary
+ * CCC = Columns-9 binary
* ==========================================================
* DCT CCCBRR Rows Banks Columns 64-bit CS Size
* Encoding
@@ -8311,7 +8311,7 @@ uint8_t crcCheck(struct DCTStatStruc *pDCTstat, uint8_t dimm)
for (Index = 0; Index < byte_use; Index ++) {
byte = pDCTstat->spd_data.spd_bytes[dimm][Index];
CRC ^= byte << 8;
- for (i=0; i<8; i++) {
+ for (i = 0; i < 8; i++) {
if (CRC & 0x8000) {
CRC <<= 1;
CRC ^= 0x1021;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
index e1d9da5..c42e452 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.h
@@ -33,16 +33,16 @@
#define PT_C3 5
#define PT_FM2 6
-#define J_MIN 0 /* j loop constraint. 1=CL 2.0 T*/
-#define J_MAX 5 /* j loop constraint. 5=CL 7.0 T*/
-#define K_MIN 1 /* k loop constraint. 1=200 MHz*/
-#define K_MAX 5 /* k loop constraint. 5=533 MHz*/
-#define CL_DEF 2 /* Default value for failsafe operation. 2=CL 4.0 T*/
-#define T_DEF 1 /* Default value for failsafe operation. 1=5ns (cycle time)*/
-
-#define BSCRate 1 /* reg bit field=rate of dram scrubber for ecc*/
+#define J_MIN 0 /* j loop constraint. 1 = CL 2.0 T*/
+#define J_MAX 5 /* j loop constraint. 5 = CL 7.0 T*/
+#define K_MIN 1 /* k loop constraint. 1 = 200 MHz*/
+#define K_MAX 5 /* k loop constraint. 5 = 533 MHz*/
+#define CL_DEF 2 /* Default value for failsafe operation. 2 = CL 4.0 T*/
+#define T_DEF 1 /* Default value for failsafe operation. 1 = 5ns (cycle time)*/
+
+#define BSCRate 1 /* reg bit field = rate of dram scrubber for ecc*/
/* memory initialization (ecc and check-bits).*/
- /* 1=40 ns/64 bytes.*/
+ /* 1 = 40 ns/64 bytes.*/
#define FirstPass 1 /* First pass through RcvEn training*/
#define SecondPass 2 /* Second pass through Rcven training*/
@@ -336,7 +336,7 @@ struct DCTStatStruc { /* A per Node structure*/
/* DCTStatStruct_F - start */
u8 Node_ID; /* Node ID of current controller */
uint8_t Internal_Node_ID; /* Internal Node ID of the current controller */
- uint8_t Dual_Node_Package; /* 1=Dual node package (G34) */
+ uint8_t Dual_Node_Package; /* 1 = Dual node package (G34) */
uint8_t stopDCT[2]; /* Set if the DCT will be stopped */
u8 ErrCode; /* Current error condition of Node
0= no error
@@ -353,7 +353,7 @@ struct DCTStatStruc { /* A per Node structure*/
/* SPD address of..MB2_CS_L[0,1]*/
/* SPD address of..MA3_CS_L[0,1]*/
/* SPD address of..MB3_CS_L[0,1]*/
- u16 DIMMPresent; /*For each bit n 0..7, 1=DIMM n is present.
+ u16 DIMMPresent; /*For each bit n 0..7, 1 = DIMM n is present.
DIMM# Select Signal
0 MA0_CS_L[0,1]
1 MB0_CS_L[0,1]
@@ -363,15 +363,15 @@ struct DCTStatStruc { /* A per Node structure*/
5 MB2_CS_L[0,1]
6 MA3_CS_L[0,1]
7 MB3_CS_L[0,1]*/
- u16 DIMMValid; /* For each bit n 0..7, 1=DIMM n is valid and is/will be configured*/
- u16 DIMMMismatch; /* For each bit n 0..7, 1=DIMM n is mismatched, channel B is always considered the mismatch */
- u16 DIMMSPDCSE; /* For each bit n 0..7, 1=DIMM n SPD checksum error*/
- u16 DimmECCPresent; /* For each bit n 0..7, 1=DIMM n is ECC capable.*/
- u16 DimmPARPresent; /* For each bit n 0..7, 1=DIMM n is ADR/CMD Parity capable.*/
- u16 Dimmx4Present; /* For each bit n 0..7, 1=DIMM n contains x4 data devices.*/
- u16 Dimmx8Present; /* For each bit n 0..7, 1=DIMM n contains x8 data devices.*/
- u16 Dimmx16Present; /* For each bit n 0..7, 1=DIMM n contains x16 data devices.*/
- u16 DIMM2Kpage; /* For each bit n 0..7, 1=DIMM n contains 1K page devices.*/
+ u16 DIMMValid; /* For each bit n 0..7, 1 = DIMM n is valid and is/will be configured*/
+ u16 DIMMMismatch; /* For each bit n 0..7, 1 = DIMM n is mismatched, channel B is always considered the mismatch */
+ u16 DIMMSPDCSE; /* For each bit n 0..7, 1 = DIMM n SPD checksum error*/
+ u16 DimmECCPresent; /* For each bit n 0..7, 1 = DIMM n is ECC capable.*/
+ u16 DimmPARPresent; /* For each bit n 0..7, 1 = DIMM n is ADR/CMD Parity capable.*/
+ u16 Dimmx4Present; /* For each bit n 0..7, 1 = DIMM n contains x4 data devices.*/
+ u16 Dimmx8Present; /* For each bit n 0..7, 1 = DIMM n contains x8 data devices.*/
+ u16 Dimmx16Present; /* For each bit n 0..7, 1 = DIMM n contains x16 data devices.*/
+ u16 DIMM2Kpage; /* For each bit n 0..7, 1 = DIMM n contains 1K page devices.*/
u8 MAload[2]; /* Number of devices loading MAA bus*/
/* Number of devices loading MAB bus*/
u8 MAdimms[2]; /*Number of DIMMs loading CH A*/
@@ -379,17 +379,17 @@ struct DCTStatStruc { /* A per Node structure*/
u8 DATAload[2]; /*Number of ranks loading CH A DATA*/
/* Number of ranks loading CH B DATA*/
u8 DIMMAutoSpeed; /*Max valid Mfg. Speed of DIMMs
- 1=200MHz
- 2=266MHz
- 3=333MHz
- 4=400MHz
- 5=533MHz*/
+ 1 = 200MHz
+ 2 = 266MHz
+ 3 = 333MHz
+ 4 = 400MHz
+ 5 = 533MHz*/
u8 DIMMCASL; /* Min valid Mfg. CL bitfield
- 0=2.0
- 1=3.0
- 2=4.0
- 3=5.0
- 4=6.0 */
+ 0 = 2.0
+ 1 = 3.0
+ 2 = 4.0
+ 3 = 5.0
+ 4 = 6.0 */
u16 DIMMTrcd; /* Minimax Trcd*40 (ns) of DIMMs*/
u16 DIMMTrp; /* Minimax Trp*40 (ns) of DIMMs*/
u16 DIMMTrtp; /* Minimax Trtp*40 (ns) of DIMMs*/
@@ -399,16 +399,16 @@ struct DCTStatStruc { /* A per Node structure*/
u16 DIMMTrrd; /* Minimax Trrd*40 (ns) of DIMMs*/
u16 DIMMTwtr; /* Minimax Twtr*40 (ns) of DIMMs*/
u8 Speed; /* Bus Speed (to set Controller)
- 1=200MHz
- 2=266MHz
- 3=333MHz
- 4=400MHz */
+ 1 = 200MHz
+ 2 = 266MHz
+ 3 = 333MHz
+ 4 = 400MHz */
u8 CASL; /* CAS latency DCT setting
- 0=2.0
- 1=3.0
- 2=4.0
- 3=5.0
- 4=6.0 */
+ 0 = 2.0
+ 1 = 3.0
+ 2 = 4.0
+ 3 = 5.0
+ 4 = 6.0 */
u8 Trcd; /* DCT Trcd (busclocks) */
u8 Trp; /* DCT Trp (busclocks) */
u8 Trtp; /* DCT Trtp (busclocks) */
@@ -418,27 +418,27 @@ struct DCTStatStruc { /* A per Node structure*/
u8 Trrd; /* DCT Trrd (busclocks) */
u8 Twtr; /* DCT Twtr (busclocks) */
u8 Trfc[4]; /* DCT Logical DIMM0 Trfc
- 0=75ns (for 256Mb devs)
- 1=105ns (for 512Mb devs)
- 2=127.5ns (for 1Gb devs)
- 3=195ns (for 2Gb devs)
- 4=327.5ns (for 4Gb devs) */
+ 0 = 75ns (for 256Mb devs)
+ 1 = 105ns (for 512Mb devs)
+ 2 = 127.5ns (for 1Gb devs)
+ 3 = 195ns (for 2Gb devs)
+ 4 = 327.5ns (for 4Gb devs) */
/* DCT Logical DIMM1 Trfc (see Trfc0 for format) */
/* DCT Logical DIMM2 Trfc (see Trfc0 for format) */
/* DCT Logical DIMM3 Trfc (see Trfc0 for format) */
- u16 CSPresent; /* For each bit n 0..7, 1=Chip-select n is present */
- u16 CSTestFail; /* For each bit n 0..7, 1=Chip-select n is present but disabled */
+ u16 CSPresent; /* For each bit n 0..7, 1 = Chip-select n is present */
+ u16 CSTestFail; /* For each bit n 0..7, 1 = Chip-select n is present but disabled */
u32 DCTSysBase; /* BASE[39:8] (system address) of this Node's DCTs. */
u32 DCTHoleBase; /* If not zero, BASE[39:8] (system address) of dram hole for HW remapping. Dram hole exists on this Node's DCTs. */
u32 DCTSysLimit; /* LIMIT[39:8] (system address) of this Node's DCTs */
u16 PresetmaxFreq; /* Maximum OEM defined DDR frequency
- 200=200MHz (DDR400)
- 266=266MHz (DDR533)
- 333=333MHz (DDR667)
- 400=400MHz (DDR800) */
+ 200 = 200MHz (DDR400)
+ 266 = 266MHz (DDR533)
+ 333 = 333MHz (DDR667)
+ 400 = 400MHz (DDR800) */
u8 _2Tmode; /* 1T or 2T CMD mode (slow access mode)
- 1=1T
- 2=2T */
+ 1 = 1T
+ 2 = 2T */
u8 TrwtTO; /* DCT TrwtTO (busclocks)*/
u8 Twrrd; /* DCT Twrrd (busclocks)*/
u8 Twrwr; /* DCT Twrwr (busclocks)*/
@@ -462,9 +462,9 @@ struct DCTStatStruc { /* A per Node structure*/
/* CHB Byte 0-7 Read DQS Delay */
u32 PtrPatternBufA; /* Ptr on stack to aligned DQS testing pattern*/
u32 PtrPatternBufB; /* Ptr on stack to aligned DQS testing pattern*/
- u8 Channel; /* Current Channel (0= CH A, 1=CH B)*/
+ u8 Channel; /* Current Channel (0= CH A, 1 = CH B)*/
u8 ByteLane; /* Current Byte Lane (0..7)*/
- u8 Direction; /* Current DQS-DQ training write direction (0=read, 1=write)*/
+ u8 Direction; /* Current DQS-DQ training write direction (0 = read, 1 = write)*/
u8 Pattern; /* Current pattern*/
u8 DQSDelay; /* Current DQS delay value*/
u32 TrainErrors; /* Current Training Errors*/
@@ -545,15 +545,15 @@ struct DCTStatStruc { /* A per Node structure*/
u8 WrDatGrossH;
u8 DqsRcvEnGrossL;
/* NOTE: Not used - u8 NodeSpeed */ /* Bus Speed (to set Controller) */
- /* 1=200MHz */
- /* 2=266MHz */
- /* 3=333MHz */
+ /* 1 = 200MHz */
+ /* 2 = 266MHz */
+ /* 3 = 333MHz */
/* NOTE: Not used - u8 NodeCASL */ /* CAS latency DCT setting */
- /* 0=2.0 */
- /* 1=3.0 */
- /* 2=4.0 */
- /* 3=5.0 */
- /* 4=6.0 */
+ /* 0 = 2.0 */
+ /* 1 = 3.0 */
+ /* 2 = 4.0 */
+ /* 3 = 5.0 */
+ /* 4 = 6.0 */
u8 TrwtWB;
u8 CurrRcvrCHADelay; /* for keep current RcvrEnDly of chA*/
u16 T1000; /* get the T1000 figure (cycle time (ns)*1K)*/
@@ -852,7 +852,7 @@ struct amd_s3_persistent_data {
#define SB_SWNodeHole 8 /* Remapping of Node Base on this Node to create a gap.*/
#define SB_HWHole 9 /* Memory Hole created on this Node using HW remapping.*/
#define SB_Over400MHz 10 /* DCT freq >= 400MHz flag*/
-#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq>=400MHz*/
+#define SB_DQSPos_Pass2 11 /* Using for TrainDQSPos DIMM0/1, when freq >= 400MHz*/
#define SB_DQSRcvLimit 12 /* Using for DQSRcvEnTrain to know we have reached to upper bound.*/
#define SB_ExtConfig 13 /* Indicator the default setting for extend PCI configuration support*/
@@ -862,73 +862,73 @@ struct amd_s3_persistent_data {
===============================================================================*/
/*Platform Configuration*/
#define NV_PACK_TYPE 0 /* CPU Package Type (2-bits)
- 0=NPT L1
- 1=NPT M2
- 2=NPT S1*/
+ 0 = NPT L1
+ 1 = NPT M2
+ 2 = NPT S1*/
#define NV_MAX_NODES 1 /* Number of Nodes/Sockets (4-bits)*/
#define NV_MAX_DIMMS 2 /* Number of DIMM slots for the specified Node ID (4-bits)*/
#define NV_MAX_MEMCLK 3 /* Maximum platform demonstrated Memclock (10-bits)
- 200=200MHz (DDR400)
- 266=266MHz (DDR533)
- 333=333MHz (DDR667)
- 400=400MHz (DDR800)*/
+ 200 = 200MHz (DDR400)
+ 266 = 266MHz (DDR533)
+ 333 = 333MHz (DDR667)
+ 400 = 400MHz (DDR800)*/
#define NV_MIN_MEMCLK 4 /* Minimum platform demonstrated Memclock (10-bits) */
#define NV_ECC_CAP 5 /* Bus ECC capable (1-bits)
- 0=Platform not capable
- 1=Platform is capable*/
+ 0 = Platform not capable
+ 1 = Platform is capable*/
#define NV_4RANKType 6 /* Quad Rank DIMM slot type (2-bits)
- 0=Normal
- 1=R4 (4-Rank Registered DIMMs in AMD server configuration)
- 2=S4 (Unbuffered SO-DIMMs)*/
+ 0 = Normal
+ 1 = R4 (4-Rank Registered DIMMs in AMD server configuration)
+ 2 = S4 (Unbuffered SO-DIMMs)*/
#define NV_BYPMAX 7 /* Value to set DcqBypassMax field (See Function 2, Offset 94h, [27:24] of BKDG for field definition).
- 4=4 times bypass (normal for non-UMA systems)
- 7=7 times bypass (normal for UMA systems)*/
+ 4 = 4 times bypass (normal for non-UMA systems)
+ 7 = 7 times bypass (normal for UMA systems)*/
#define NV_RDWRQBYP 8 /* Value to set RdWrQByp field (See Function 2, Offset A0h, [3:2] of BKDG for field definition).
- 2=8 times (normal for non-UMA systems)
- 3=16 times (normal for UMA systems)*/
+ 2 = 8 times (normal for non-UMA systems)
+ 3 = 16 times (normal for UMA systems)*/
/*Dram Timing*/
#define NV_MCTUSRTMGMODE 10 /* User Memclock Mode (2-bits)
- 0=Auto, no user limit
- 1=Auto, user limit provided in NV_MemCkVal
- 2=Manual, user value provided in NV_MemCkVal*/
+ 0 = Auto, no user limit
+ 1 = Auto, user limit provided in NV_MemCkVal
+ 2 = Manual, user value provided in NV_MemCkVal*/
#define NV_MemCkVal 11 /* Memory Clock Value (2-bits)
- 0=200MHz
- 1=266MHz
- 2=333MHz
- 3=400MHz*/
+ 0 = 200MHz
+ 1 = 266MHz
+ 2 = 333MHz
+ 3 = 400MHz*/
/*Dram Configuration*/
#define NV_BankIntlv 20 /* Dram Bank (chip-select) Interleaving (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_AllMemClks 21 /* Turn on All DIMM clocks (1-bits)
- 0=normal
- 1=enable all memclocks*/
+ 0 = normal
+ 1 = enable all memclocks*/
#define NV_SPDCHK_RESTRT 22 /* SPD Check control bitmap (1-bits)
- 0=Exit current node init if any DIMM has SPD checksum error
- 1=Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
+ 0 = Exit current node init if any DIMM has SPD checksum error
+ 1 = Ignore faulty SPD checksums (Note: DIMM cannot be enabled)*/
#define NV_DQSTrainCTL 23 /* DQS Signal Timing Training Control
- 0=skip DQS training
- 1=perform DQS training*/
+ 0 = skip DQS training
+ 1 = perform DQS training*/
#define NV_NodeIntlv 24 /* Node Memory Interleaving (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_BurstLen32 25 /* BurstLength32 for 64-bit mode (1-bits)
- 0=disable (normal)
- 1=enable (4 beat burst when width is 64-bits)*/
+ 0 = disable (normal)
+ 1 = enable (4 beat burst when width is 64-bits)*/
/*Dram Power*/
#define NV_CKE_PDEN 30 /* CKE based power down mode (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_CKE_CTL 31 /* CKE based power down control (1-bits)
- 0=per Channel control
- 1=per Chip select control*/
+ 0 = per Channel control
+ 1 = per Chip select control*/
#define NV_CLKHZAltVidC3 32 /* Memclock tri-stating during C3 and Alt VID (1-bits)
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
/*Memory Map/Mgt.*/
#define NV_BottomIO 40 /* Bottom of 32-bit IO space (8-bits)
@@ -936,8 +936,8 @@ struct amd_s3_persistent_data {
#define NV_BottomUMA 41 /* Bottom of shared graphics dram (8-bits)
NV_BottomUMA[7:0]=Addr[31:24]*/
#define NV_MemHole 42 /* Memory Hole Remapping (1-bits)
- 0=disable
- 1=enable */
+ 0 = disable
+ 1 = enable */
/*ECC*/
#define NV_ECC 50 /* Dram ECC enable*/
@@ -949,13 +949,13 @@ struct amd_s3_persistent_data {
#define NV_L3BKScrub 57 /* L3 ECC Background Scrubber CTL*/
#define NV_DCBKScrub 58 /* DCache ECC Background Scrubber CTL*/
#define NV_CS_SpareCTL 59 /* Chip Select Spare Control bit 0:
- 0=disable Spare
- 1=enable Spare */
+ 0 = disable Spare
+ 1 = enable Spare */
/* Chip Select Spare Control bit 1-4:
Reserved, must be zero*/
#define NV_SyncOnUnEccEn 61 /* SyncOnUnEccEn control
- 0=disable
- 1=enable*/
+ 0 = disable
+ 1 = enable*/
#define NV_Unganged 62
#define NV_ChannelIntlv 63 /* Channel Interleaving (3-bits)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
index a7fac8f..74fadde 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d_gcc.h
@@ -37,7 +37,7 @@ static inline void _RDTSC(u32 *lo, u32 *hi)
__asm__ volatile (
"rdtsc"
: "=a" (*lo), "=d"(*hi)
- );
+ );
}
static inline void _cpu_id(u32 addr, u32 *val)
@@ -57,7 +57,7 @@ static u32 bsr(u32 x)
u8 i;
u32 ret = 0;
- for (i=31; i>0; i--) {
+ for (i = 31; i > 0; i--) {
if (x & (1<<i)) {
ret = i;
break;
@@ -73,7 +73,7 @@ static u32 bsf(u32 x)
u8 i;
u32 ret = 32;
- for (i=0; i<32; i++) {
+ for (i = 0; i < 32; i++) {
if (x & (1<<i)) {
ret = i;
break;
@@ -83,9 +83,9 @@ static u32 bsf(u32 x)
return ret;
}
-#define _MFENCE asm volatile ( "mfence")
+#define _MFENCE asm volatile ("mfence")
-#define _SFENCE asm volatile ( "sfence" )
+#define _SFENCE asm volatile ("sfence")
/* prevent speculative execution of following instructions */
#define _EXECFENCE asm volatile ("outb %al, $0xed")
@@ -301,7 +301,7 @@ static u32 stream_to_int(u8 *p)
val = 0;
- for (i=3; i>=0; i--) {
+ for (i = 3; i >= 0; i--) {
val <<= 8;
valx = *(p+i);
val |= valx;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c
index 3f01308..d6480ab 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctardk6.c
@@ -50,7 +50,7 @@ void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
* : ODC_CTL - Output Driver Compensation Control Register Value
* : CMDmode - CMD mode
*/
-static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
+static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
u8 *CMDmode)
{
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
index 6c25f2c..30cf10e 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctchi_d.c
@@ -33,8 +33,8 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
/* call back to wrapper not needed ManualChannelInterleave_D(); */
/* call back - DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv);*/ /* override interleave */
- /* Manually set: typ=5, otherwise typ=7. */
- DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ=5: Hash*: exclusive OR of address bits[20:16, 6]. */
+ /* Manually set: typ = 5, otherwise typ = 7. */
+ DctSelIntLvAddr = mctGet_NVbits(NV_ChannelIntlv); /* typ = 5: Hash*: exclusive OR of address bits[20:16, 6]. */
if (DctSelIntLvAddr & 1) {
DctSelIntLvAddr >>= 1;
@@ -67,7 +67,7 @@ void InterleaveChannels_D(struct MCTStatStruc *pMCTstat,
if (dct1_size == dct0_size) {
dct1_size = 0;
DctSelHi = 0x04; /* DctSelHiRngEn = 0 */
- } else if (dct1_size > dct0_size ) {
+ } else if (dct1_size > dct0_size) {
dct1_size = dct0_size;
DctSelHi = 0x07; /* DctSelHiRngEn = 1, DctSelHi = 1 */
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c
index 3f56765..e42a127 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctcsi_d.c
@@ -45,7 +45,7 @@ void InterleaveBanks_D(struct MCTStatStruc *pMCTstat,
while (DoIntlv && (ChipSel < MAX_CS_SUPPORTED)) {
reg = 0x40+(ChipSel<<2); /* Dram CS Base 0 */
val = Get_NB32_DCT(dev, dct, reg);
- if ( val & (1<<CSEnable)) {
+ if (val & (1<<CSEnable)) {
EnChipSels++;
reg = 0x60+((ChipSel>>1)<<2); /*Dram CS Mask 0 */
val = Get_NB32_DCT(dev, dct, reg);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
index 06a70e6..71a4b79 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c
@@ -247,12 +247,12 @@ static void SetEccDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
u8 channel;
u8 direction;
- for (channel = 0; channel < 2; channel++){
+ for (channel = 0; channel < 2; channel++) {
for (direction = 0; direction < 2; direction++) {
pDCTstat->Channel = channel; /* Channel A or B */
pDCTstat->Direction = direction; /* Read or write */
CalcEccDQSPos_D(pMCTstat, pDCTstat, pDCTstat->CH_EccDQSLike[channel], pDCTstat->CH_EccDQSScale[channel], ChipSel);
- print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2);
+ print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", pDCTstat->DQSDelay, 2);
pDCTstat->ByteLane = 8;
StoreDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
mct_SetDQSDelayCSR_D(pMCTstat, pDCTstat, ChipSel);
@@ -294,7 +294,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
GetDQSDatStrucVal_D(pMCTstat, pDCTstat, ChipSel);
DQSDelay1 = pDCTstat->DQSDelay;
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay = DQSDelay0 - DQSDelay1;
} else {
DQSDelay = DQSDelay1 - DQSDelay0;
@@ -306,7 +306,7 @@ static void CalcEccDQSPos_D(struct MCTStatStruc *pMCTstat,
DQSDelay >>= 8; /* 256 */
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay = DQSDelay1 - DQSDelay;
} else {
DQSDelay += DQSDelay1;
@@ -493,7 +493,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
}
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 14 TestAddr ", TestAddr, 4);
- SetUpperFSbase(TestAddr); /* fs:eax=far ptr to target */
+ SetUpperFSbase(TestAddr); /* fs:eax = far ptr to target */
print_debug_dqs("\t\t\t\tTrainDQSRdWrPos: 12 Receiver ", Receiver, 2);
@@ -556,7 +556,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
ResetTargetWTIO_D();
/* Read and compare pattern */
- bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */
+ bytelane_test_results &= (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */
/* If all lanes have already failed testing bypass remaining re-read attempt(s) */
if (bytelane_test_results == 0x0)
@@ -650,7 +650,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
ResetTargetWTIO_D();
/* Read and compare pattern from the base test address */
- bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0=fail, 1=pass */
+ bytelane_test_results = (CompareDQSTestPattern_D(pMCTstat, pDCTstat, TestAddr << 8) & 0xff); /* [Lane 7 :: Lane 0] 0 = fail, 1 = pass */
/* Store any lanes that passed testing for later use */
for (lane = 0; lane < 8; lane++)
@@ -814,7 +814,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) {
printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD);
p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
val = p[i];
printk(BIOS_DEBUG, " %02x", val);
}
@@ -834,7 +834,7 @@ static void TrainDQSRdWrPos_D_Fam10(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(addr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -1583,7 +1583,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat,
for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) {
printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD);
p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
val = p[i];
printk(BIOS_DEBUG, " %02x", val);
}
@@ -1843,7 +1843,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
for (ReceiverDTD = 0; ReceiverDTD < MAX_CS_SUPPORTED; ReceiverDTD += 2) {
printk(BIOS_DEBUG, "\t\tReceiver: %02x:", ReceiverDTD);
p = pDCTstat->CH_D_DIR_B_DQS[ChannelDTD][ReceiverDTD >> 1][Dir];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
val = p[i];
printk(BIOS_DEBUG, " %02x", val);
}
@@ -1863,7 +1863,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(addr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -1890,11 +1890,11 @@ static void SetupDqsPattern_D(struct MCTStatStruc *pMCTstat,
buf = (u32 *)(((u32)buffer + 0x10) & (0xfffffff0));
if (pDCTstat->Status & (1<<SB_128bitmode)) {
pDCTstat->Pattern = 1; /* 18 cache lines, alternating qwords */
- for (i=0; i<16*18; i++)
+ for (i = 0; i < 16*18; i++)
buf[i] = TestPatternJD1b_D[i];
} else {
pDCTstat->Pattern = 0; /* 9 cache lines, sequential qwords */
- for (i=0; i<16*9; i++)
+ for (i = 0; i < 16*9; i++)
buf[i] = TestPatternJD1a_D[i];
}
pDCTstat->PtrPatternBufA = (u32)buf;
@@ -1966,10 +1966,10 @@ static u8 ChipSelPresent_D(struct MCTStatStruc *pMCTstat,
else
dct = 0;
- if (ChipSel < MAX_CS_SUPPORTED){
+ if (ChipSel < MAX_CS_SUPPORTED) {
reg = 0x40 + (ChipSel << 2);
val = Get_NB32_DCT(dev, dct, reg);
- if (val & ( 1 << 0))
+ if (val & (1 << 0))
ret = 1;
}
@@ -2058,7 +2058,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
}
bytelane = 0; /* bytelane counter */
- bitmap = 0xFFFF; /* bytelane test bitmap, 1=pass */
+ bitmap = 0xFFFF; /* bytelane test bitmap, 1 = pass */
MEn1Results = 0xFFFF;
BeatCnt = 0;
for (i = 0; i < (9 * 64 / 4); i++) { /* sizeof testpattern. /4 due to next loop */
@@ -2102,7 +2102,7 @@ static u16 CompareDQSTestPattern_D(struct MCTStatStruc *pMCTstat, struct DCTStat
if (!bitmap)
break;
- if (bytelane == 0){
+ if (bytelane == 0) {
BeatCnt += 4;
if (!(pDCTstat->Status & (1 << SB_128bitmode))) {
if (BeatCnt == 8) BeatCnt = 0; /* 8 beat burst */
@@ -2132,7 +2132,7 @@ static void FlushDQSTestPattern_D(struct DCTStatStruc *pDCTstat,
u32 addr_lo)
{
/* Flush functions in mct_gcc.h */
- if (pDCTstat->Pattern == 0){
+ if (pDCTstat->Pattern == 0) {
FlushDQSTestPattern_L9(addr_lo);
} else {
FlushDQSTestPattern_L18(addr_lo);
@@ -2349,9 +2349,9 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
val &= ~0xe007c01f;
- /* unganged mode DCT0+DCT1, sys addr of DCT1=node
+ /* unganged mode DCT0+DCT1, sys addr of DCT1 = node
* base+DctSelBaseAddr+local ca base*/
- if ((Channel) && (pDCTstat->GangedMode == 0) && ( pDCTstat->DIMMValidDCT[0] > 0)) {
+ if ((Channel) && (pDCTstat->GangedMode == 0) && (pDCTstat->DIMMValidDCT[0] > 0)) {
reg = 0x110;
dword = Get_NB32(dev, reg);
dword &= 0xfffff800;
@@ -2365,7 +2365,7 @@ u32 mct_GetMCTSysAddr_D(struct MCTStatStruc *pMCTstat,
val += dword;
}
} else {
- /* sys addr=node base+local cs base */
+ /* sys addr = node base+local cs base */
val += pDCTstat->DCTSysBase;
/* New stuff */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
index 5d31849..ca36789 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c
@@ -36,7 +36,7 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat);
*
* Conditions for setting background scrubber.
* 1. node is present
- * 2. node has dram functioning (WE=RE=1)
+ * 2. node has dram functioning (WE = RE = 1)
* 3. all eccdimms (or bit 17 of offset 90,fn 2)
* 4. no chip-select gap exists
*
@@ -152,10 +152,10 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
val = Get_NB32(dev, reg);
/* WE/RE is checked */
- if ((val & 3)==3) { /* Node has dram populated */
+ if ((val & 3) == 3) { /* Node has dram populated */
/* Negate 'all nodes/dimms ECC' flag if non ecc
memory populated */
- if ( pDCTstat->Status & (1<<SB_ECCDIMMs)) {
+ if (pDCTstat->Status & (1 << SB_ECCDIMMs)) {
LDramECC = isDramECCEn_D(pDCTstat);
if (pDCTstat->ErrCode != SC_RunningOK) {
pDCTstat->Status &= ~(1 << SB_ECCDIMMs);
@@ -195,9 +195,9 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
}
if (AllECC)
- pMCTstat->GStatus |= 1<<GSB_ECCDIMMs;
+ pMCTstat->GStatus |= 1 << GSB_ECCDIMMs;
else
- pMCTstat->GStatus &= ~(1<<GSB_ECCDIMMs);
+ pMCTstat->GStatus &= ~(1 << GSB_ECCDIMMs);
/* Program the Dram BKScrub CTL to the proper (user selected) value.*/
/* Reset MC4_STS. */
@@ -206,11 +206,11 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
pDCTstat = pDCTstatA + Node;
LDramECC = 0;
if (NodePresent_D(Node)) { /* If Node is present */
- reg = 0x40+(Node<<3); /* Dram Base Node 0 + index */
+ reg = 0x40+(Node << 3); /* Dram Base Node 0 + index */
val = Get_NB32(pDCTstat->dev_map, reg);
curBase = val & 0xffff0000;
/*WE/RE is checked because memory config may have been */
- if ((val & 3)==3) { /* Node has dram populated */
+ if ((val & 3) == 3) { /* Node has dram populated */
if (isDramECCEn_D(pDCTstat)) { /* if ECC is enabled on this dram */
dev = pDCTstat->dev_nbmisc;
val = curBase << 8;
@@ -322,16 +322,16 @@ static void setSyncOnUnEccEn_D(struct MCTStatStruc *pMCTstat,
struct DCTStatStruc *pDCTstat;
pDCTstat = pDCTstatA + Node;
if (NodePresent_D(Node)) { /* If Node is present*/
- reg = 0x40+(Node<<3); /* Dram Base Node 0 + index*/
+ reg = 0x40+(Node << 3); /* Dram Base Node 0 + index*/
val = Get_NB32(pDCTstat->dev_map, reg);
/*WE/RE is checked because memory config may have been*/
- if ((val & 3)==3) { /* Node has dram populated*/
- if ( isDramECCEn_D(pDCTstat)) {
+ if ((val & 3) == 3) { /* Node has dram populated*/
+ if (isDramECCEn_D(pDCTstat)) {
/*if ECC is enabled on this dram*/
dev = pDCTstat->dev_nbmisc;
reg = 0x44; /* MCA NB Configuration*/
val = Get_NB32(dev, reg);
- val |= (1<<SyncOnUcEccEn);
+ val |= (1 << SyncOnUcEccEn);
Set_NB32(dev, reg, val);
}
} /* Node has Dram*/
@@ -353,11 +353,11 @@ static u8 isDramECCEn_D(struct DCTStatStruc *pDCTstat)
} else {
ch_end = 2;
}
- for (i=0; i<ch_end; i++) {
- if (pDCTstat->DIMMValidDCT[i] > 0){
+ for (i = 0; i < ch_end; i++) {
+ if (pDCTstat->DIMMValidDCT[i] > 0) {
reg = 0x90; /* Dram Config Low */
val = Get_NB32_DCT(dev, i, reg);
- if (val & (1<<DimmEcEn)) {
+ if (val & (1 << DimmEcEn)) {
/* set local flag 'dram ecc capable' */
isDimmECCEn = 1;
break;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
index 8ed2bef..558b3e3 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctmtr_d.c
@@ -34,11 +34,11 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
/* Set temporary top of memory from Node structure data.
* Adjust temp top of memory down to accommodate 32-bit IO space.
- * Bottom40bIO=top of memory, right justified 8 bits
+ * Bottom40bIO = top of memory, right justified 8 bits
* (defines dram versus IO space type)
- * Bottom32bIO=sub 4GB top of memory, right justified 8 bits
+ * Bottom32bIO = sub 4GB top of memory, right justified 8 bits
* (defines dram versus IO space type)
- * Cache32bTOP=sub 4GB top of WB cacheable memory,
+ * Cache32bTOP = sub 4GB top of WB cacheable memory,
* right justified 8 bits
*/
@@ -82,8 +82,8 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
*/
addr = 0x204; /* MTRR phys base 2*/
/* use TOP_MEM as limit*/
- /* Limit=TOP_MEM|TOM2*/
- /* Base=0*/
+ /* Limit = TOP_MEM|TOM2*/
+ /* Base = 0*/
printk(BIOS_DEBUG, "\t CPUMemTyping: Cache32bTOP:%x\n", Cache32bTOP);
SetMTRRrangeWB_D(0, &Cache32bTOP, &addr);
/* Base */
@@ -112,10 +112,10 @@ void CPUMemTyping_D(struct MCTStatStruc *pMCTstat,
addr = 0xC0010010; /* SYS_CFG */
_RDMSR(addr, &lo, &hi);
if (Bottom40bIO) {
- lo |= (1<<21); /* MtrrTom2En=1 */
+ lo |= (1<<21); /* MtrrTom2En = 1 */
lo |= (1<<22); /* Tom2ForceMemTypeWB */
} else {
- lo &= ~(1<<21); /* MtrrTom2En=0 */
+ lo &= ~(1<<21); /* MtrrTom2En = 0 */
lo &= ~(1<<22); /* Tom2ForceMemTypeWB */
}
_WRMSR(addr, lo, hi);
@@ -146,7 +146,7 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
* next set bit in a forward or backward sequence of bits (as a function
* of the Limit). We start with the ascending path, to ensure that
* regions are naturally aligned, then we switch to the descending path
- * to maximize MTRR usage efficiency. Base=0 is a special case where we
+ * to maximize MTRR usage efficiency. Base = 0 is a special case where we
* start with the descending path. Correct Mask for region is
* 2comp(Size-1)-1, which is 2comp(Limit-Base-1)-1
*/
@@ -172,17 +172,17 @@ static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType)
curSize = valx;
valx += curBase;
}
- curLimit = valx; /*eax=curBase, edx=curLimit*/
+ curLimit = valx; /*eax = curBase, edx = curLimit*/
valx = val>>24;
val <<= 8;
/* now program the MTRR */
val |= MtrrType; /* set cache type (UC or WB)*/
_WRMSR(addr, val, valx); /* prog. MTRR with current region Base*/
- val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask=2comp(Size-1)-1*/
+ val = ((~(curSize - 1))+1) - 1; /* Size-1*/ /*Mask = 2comp(Size-1)-1*/
valx = (val >> 24) | (0xff00); /* GH have 48 bits addr */
val <<= 8;
- val |= ( 1 << 11); /* set MTRR valid*/
+ val |= (1 << 11); /* set MTRR valid*/
addr++;
_WRMSR(addr, val, valx); /* prog. MTRR with current region Mask*/
val = curLimit;
@@ -213,9 +213,9 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
/*======================================================================
* Adjust temp top of memory down to accommodate UMA memory start
*======================================================================*/
- /* Bottom32bIO=sub 4GB top of memory, right justified 8 bits
+ /* Bottom32bIO = sub 4GB top of memory, right justified 8 bits
* (defines dram versus IO space type)
- * Cache32bTOP=sub 4GB top of WB cacheable memory, right justified 8 bits */
+ * Cache32bTOP = sub 4GB top of WB cacheable memory, right justified 8 bits */
Bottom32bIO = pMCTstat->Sub4GCacheTop >> 8;
@@ -234,7 +234,7 @@ void UMAMemTyping_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat
addr = 0x200;
lo = 0;
hi = lo;
- while ( addr < 0x20C) {
+ while (addr < 0x20C) {
_WRMSR(addr, lo, hi); /* prog. MTRR with current region Mask */
addr++; /* next MTRR pair addr */
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c
index 9a769ad..bf84171 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctndi_d.c
@@ -68,7 +68,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
NodesWmem++;
Base &= 0xFFFF0000; /* Base[39:8] */
- if (pDCTstat->Status & (1 << SB_HWHole )) {
+ if (pDCTstat->Status & (1 << SB_HWHole)) {
/* to get true amount of dram,
* subtract out memory hole if HW dram remapping */
@@ -83,7 +83,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
DctSelBase = Get_NB32(pDCTstat->dev_dct, 0x114);
if (DctSelBase) {
DctSelBase <<= 8;
- if ( pDCTstat->Status & (1 << SB_HWHole)) {
+ if (pDCTstat->Status & (1 << SB_HWHole)) {
if (DctSelBase >= 0x1000000) {
DctSelBase -= HWHoleSz;
}
@@ -100,7 +100,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
MemSize &= 0xFFFF0000;
MemSize += 0x00010000;
MemSize -= Base;
- if ( pDCTstat->Status & (1 << SB_HWHole)) {
+ if (pDCTstat->Status & (1 << SB_HWHole)) {
MemSize -= HWHoleSz;
}
if (Node == 0) {
@@ -139,7 +139,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
if (DoIntlv) {
MCTMemClr_D(pMCTstat, pDCTstatA);
/* Program Interleaving enabled on Node 0 map only.*/
- MemSize0 <<= bsf(Nodes); /* MemSize=MemSize*2 (or 4, or 8) */
+ MemSize0 <<= bsf(Nodes); /* MemSize = MemSize*2 (or 4, or 8) */
Dct0MemSize <<= bsf(Nodes);
MemSize0 += HWHoleSz;
Base = ((Nodes - 1) << 8) | 3;
@@ -180,7 +180,7 @@ void InterleaveNodes_D(struct MCTStatStruc *pMCTstat,
HoleBase = pMCTstat->HoleBase;
if (Dct0MemSize >= HoleBase) {
val = HWHoleSz;
- if ( Node == 0) {
+ if (Node == 0) {
val += Dct0MemSize;
}
} else {
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
index 951a712..ac24c6d 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctrci.c
@@ -336,14 +336,14 @@ void mct_DramControlReg_Init_D(struct MCTStatStruc *pMCTstat,
printk(BIOS_SPEW, "%s: F2xA8: %08x\n", __func__, val);
if (is_fam15h()) {
- for (cw=0; cw <=15; cw ++) {
+ for (cw = 0; cw <=15; cw ++) {
val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw);
mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val);
if ((cw == 2) || (cw == 8) || (cw == 10))
precise_ndelay_fam15(pMCTstat, 6000);
}
} else {
- for (cw=0; cw <=15; cw ++) {
+ for (cw = 0; cw <=15; cw ++) {
mct_Wait(1600);
val = mct_ControlRC(pMCTstat, pDCTstat, dct, MrsChipSel << rc_word_chip_select_lower_bit(), cw);
mct_SendCtrlWrd(pMCTstat, pDCTstat, dct, val);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
index 670d640..18af172 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsdi.c
@@ -912,7 +912,7 @@ static u32 mct_MR1(struct MCTStatStruc *pMCTstat,
/* program MrsAddress[11]=TDQS: based on F2x[1,0]94[RDqsEn] */
if (Get_NB32_DCT(dev, dct, 0x94) & (1 << RDqsEn)) {
u8 bit;
- /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */
+ /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */
bit = (ret >> 21) << 1;
if ((dct & 1) != 0)
bit ++;
@@ -1063,7 +1063,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
printk(BIOS_DEBUG, "%s: Start\n", __func__);
/*1.Program MrsAddress[10]=1
- 2.Set SendZQCmd=1
+ 2.Set SendZQCmd = 1
*/
dword = Get_NB32_DCT(dev, dct, 0x7C);
dword &= ~0xFFFFFF;
@@ -1071,7 +1071,7 @@ static void mct_SendZQCmd(struct DCTStatStruc *pDCTstat, u8 dct)
dword |= 1 << SendZQCmd;
Set_NB32_DCT(dev, dct, 0x7C, dword);
- /* Wait for SendZQCmd=0 */
+ /* Wait for SendZQCmd = 0 */
do {
dword = Get_NB32_DCT(dev, dct, 0x7C);
} while (dword & (1 << SendZQCmd));
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
index 8024179..eac2013 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c
@@ -76,7 +76,7 @@ static void SetupRcvrPattern(struct MCTStatStruc *pMCTstat,
p_A = (u32 *)SetupDqsPattern_1PassB(pass);
p_B = (u32 *)SetupDqsPattern_1PassA(pass);
- for (i=0;i<16;i++) {
+ for (i = 0; i < 16; i++) {
buf_a[i] = p_A[i];
buf_b[i] = p_B[i];
}
@@ -560,7 +560,7 @@ static uint32_t convert_testaddr_and_channel_to_address(struct DCTStatStruc *pDC
SetUpperFSbase(testaddr);
testaddr <<= 8;
- if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel ) {
+ if ((pDCTstat->Status & (1<<SB_128bitmode)) && channel) {
testaddr += 8; /* second channel */
}
@@ -636,7 +636,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
}
cr4 = read_cr4();
- if (cr4 & ( 1 << 9)) { /* save the old value */
+ if (cr4 & (1 << 9)) { /* save the old value */
_SSE2 = 1;
}
cr4 |= (1 << 9); /* OSFXSR enable SSE2 */
@@ -986,7 +986,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
msr.lo &= ~(1<<17); /* restore HWCR.wrap32dis */
wrmsr(HWCR, msr);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -996,7 +996,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
{
u8 ChannelDTD;
printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
- for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
+ for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x: %x\n",
ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
@@ -1013,10 +1013,10 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n");
for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD);
- for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) {
+ for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) {
printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD);
p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
valDTD = p[i];
printk(BIOS_DEBUG, " %03x", valDTD);
}
@@ -1246,7 +1246,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
}
cr4 = read_cr4();
- if (cr4 & ( 1 << 9)) { /* save the old value */
+ if (cr4 & (1 << 9)) { /* save the old value */
_SSE2 = 1;
}
cr4 |= (1 << 9); /* OSFXSR enable SSE2 */
@@ -1500,7 +1500,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(msr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -1510,7 +1510,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
{
u8 ChannelDTD;
printk(BIOS_DEBUG, "TrainRcvrEn: CH_MaxRdLat:\n");
- for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
+ for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x: %x\n",
ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
@@ -1527,10 +1527,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat,
printk(BIOS_DEBUG, "TrainRcvrEn: CH_D_B_RCVRDLY:\n");
for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x\n", ChannelDTD);
- for (ReceiverDTD = 0; ReceiverDTD<8; ReceiverDTD+=2) {
+ for (ReceiverDTD = 0; ReceiverDTD < 8; ReceiverDTD+=2) {
printk(BIOS_DEBUG, "\t\tReceiver:%x:", ReceiverDTD);
p = pDCTstat->CH_D_B_RCVRDLY[ChannelDTD][ReceiverDTD>>1];
- for (i=0;i<8; i++) {
+ for (i = 0; i < 8; i++) {
valDTD = p[i];
printk(BIOS_DEBUG, " %03x", valDTD);
}
@@ -1604,7 +1604,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
ch_end = 2;
cr4 = read_cr4();
- if (cr4 & ( 1 << 9)) { /* save the old value */
+ if (cr4 & (1 << 9)) { /* save the old value */
_SSE2 = 1;
}
cr4 |= (1 << 9); /* OSFXSR enable SSE2 */
@@ -1720,7 +1720,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(msr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -1730,7 +1730,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
{
u8 ChannelDTD;
printk(BIOS_DEBUG, "TrainMaxRdLatency: CH_MaxRdLat:\n");
- for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
+ for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel:%x: %x\n",
ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
@@ -1745,7 +1745,7 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat,
u8 mct_InitReceiver_D(struct DCTStatStruc *pDCTstat, u8 dct)
{
- if (pDCTstat->DIMMValidDCT[dct] == 0 ) {
+ if (pDCTstat->DIMMValidDCT[dct] == 0) {
return 8;
} else {
return 0;
@@ -1766,7 +1766,7 @@ static void mct_DisableDQSRcvEn_D(struct DCTStatStruc *pDCTstat)
ch_end = 2;
}
- for (ch=0; ch<ch_end; ch++) {
+ for (ch = 0; ch < ch_end; ch++) {
reg = 0x78;
val = Get_NB32_DCT(dev, ch, reg);
val &= ~(1 << DqsRcvEnTrain);
@@ -1800,14 +1800,14 @@ void mct_SetRcvrEnDly_D(struct DCTStatStruc *pDCTstat, u16 RcvrEnDly,
}
/* DimmOffset not needed for CH_D_B_RCVRDLY array */
- for (i=0; i < 8; i++) {
+ for (i = 0; i < 8; i++) {
if (FinalValue) {
/*calculate dimm offset */
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
RcvrEnDly = p[i];
}
- /* if flag=0, set DqsRcvEn value to reg. */
+ /* if flag = 0, set DqsRcvEn value to reg. */
/* get the register index from table */
index = Table_DQSRcvEn_Offset[i >> 1];
index += Addl_Index; /* DIMMx DqsRcvEn byte0 */
@@ -1852,7 +1852,7 @@ static void mct_SetMaxLatency_D(struct DCTStatStruc *pDCTstat, u8 Channel, u16 D
uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE);
if ((package_type == PT_L1) /* Socket F (1207) */
|| (package_type == PT_M2) /* Socket AM3 */
- || (package_type == PT_S1)) { /* Socket S1g<x> */
+ || (package_type == PT_S1)) { /* Socket S1g <x> */
cpu_val_n = 10;
cpu_val_p = 11;
} else {
@@ -1950,7 +1950,7 @@ static void mct_InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
* Read Position is 1/2 Memclock Delay
*/
u8 i;
- for (i=0;i<2; i++){
+ for (i = 0; i < 2; i++) {
InitDQSPos4RcvrEn_D(pMCTstat, pDCTstat, i);
}
}
@@ -1972,8 +1972,8 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
/* FIXME: add Cx support */
dword = 0x00000000;
- for (i=1; i<=3; i++) {
- for (j=0; j<dn; j++)
+ for (i = 1; i <= 3; i++) {
+ for (j = 0; j < dn; j++)
/* DIMM0 Write Data Timing Low */
/* DIMM0 Write ECC Timing */
Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword);
@@ -1981,14 +1981,14 @@ static void InitDQSPos4RcvrEn_D(struct MCTStatStruc *pMCTstat,
/* errata #180 */
dword = 0x2f2f2f2f;
- for (i=5; i<=6; i++) {
- for (j=0; j<dn; j++)
+ for (i = 5; i <= 6; i++) {
+ for (j = 0; j < dn; j++)
/* DIMM0 Read DQS Timing Control Low */
Set_NB32_index_wait_DCT(dev, Channel, index_reg, i + 0x100 * j, dword);
}
dword = 0x0000002f;
- for (j=0; j<dn; j++)
+ for (j = 0; j < dn; j++)
/* DIMM0 Read DQS ECC Timing Control */
Set_NB32_index_wait_DCT(dev, Channel, index_reg, 7 + 0x100 * j, dword);
}
@@ -2087,7 +2087,7 @@ void mctSetEccDQSRcvrEn_D(struct MCTStatStruc *pMCTstat,
if (!pDCTstat->NodePresent)
break;
if (pDCTstat->DCTSysLimit) {
- for (i=0; i<2; i++)
+ for (i = 0; i < 2; i++)
CalcEccDQSRcvrEn_D(pMCTstat, pDCTstat, i);
}
}
@@ -2427,5 +2427,5 @@ void mct_Wait(u32 cycles)
saved = lo;
do {
_RDMSR(msr, &lo, &hi);
- } while (lo - saved < cycles );
+ } while (lo - saved < cycles);
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c
index d535735..30cf19b 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc1p.c
@@ -49,7 +49,7 @@ static u16 mct_Average_RcvrEnDly_1Pass(struct DCTStatStruc *pDCTstat, u8 Channel
MaxValue = 0;
p = pDCTstat->CH_D_B_RCVRDLY[Channel][Receiver >> 1];
- for (i=0; i < 8; i++) {
+ for (i = 0; i < 8; i++) {
/* get left value from DCTStatStruc.CHA_D0_B0_RCVRDLY*/
val = p[i];
/* get right value from DCTStatStruc.CHA_D0_B0_RCVRDLY_1*/
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c
index 2f4d4da..7f67824 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc2p.c
@@ -58,7 +58,7 @@ u8 mct_Get_Start_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
u8 bn;
bn = 8;
- for ( i=0;i<bn; i++) {
+ for (i = 0; i < bn; i++) {
val = p[i];
if (val > max) {
@@ -91,7 +91,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
/* FIXME: which byte? */
p_1 = pDCTstat->B_RCVRDLY_1;
/* p_1 = pDCTstat->CH_D_B_RCVRDLY_1[Channel][Receiver>>1]; */
- for (i=0; i<bn; i++) {
+ for (i = 0; i < bn; i++) {
val = p[i];
/* left edge */
if (val != (RcvrEnDlyLimit - 1)) {
@@ -111,7 +111,7 @@ u16 mct_Average_RcvrEnDly_Pass(struct DCTStatStruc *pDCTstat,
pDCTstat->DimmTrainFail &= ~(1<<(Receiver + Channel));
}
} else {
- for (i=0; i < bn; i++) {
+ for (i = 0; i < bn; i++) {
val = p[i];
/* Add 1/2 Memlock delay */
/* val += Pass1MemClkDly; */
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
index 15eb67e..78db68c 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mcttmrl.c
@@ -144,7 +144,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
print_debug_dqs("\tMaxRdLatencyTrain51: Channel ",Channel, 1);
pDCTstat->Channel = Channel;
- if ( (pDCTstat->Status & (1 << SB_128bitmode)) && Channel)
+ if ((pDCTstat->Status & (1 << SB_128bitmode)) && Channel)
break; /*if ganged mode, skip DCT 1 */
TestAddr0 = GetMaxRdLatTestAddr_D(pMCTstat, pDCTstat, Channel, &RcvrEnDly, &valid);
@@ -159,7 +159,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
while (MaxRdLatDly < MAX_RD_LAT) { /* sweep Delay value here */
mct_setMaxRdLatTrnVal_D(pDCTstat, Channel, MaxRdLatDly);
ReadMaxRdLat1CLTestPattern_D(TestAddr0);
- if ( CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS)
+ if (CompareMaxRdLatTestPattern_D(pattern_buf, TestAddr0) == DQS_PASS)
break;
SetTargetWTIO_D(TestAddr0);
FlushMaxRdLatTestPattern_D(TestAddr0);
@@ -180,7 +180,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
lo &= ~(1<<17); /* restore HWCR.wrap32dis */
_WRMSR(addr, lo, hi);
}
- if (!_SSE2){
+ if (!_SSE2) {
cr4 = read_cr4();
cr4 &= ~(1<<9); /* restore cr4.OSFXSR */
write_cr4(cr4);
@@ -190,7 +190,7 @@ static void maxRdLatencyTrain_D(struct MCTStatStruc *pMCTstat,
{
u8 ChannelDTD;
printk(BIOS_DEBUG, "maxRdLatencyTrain: CH_MaxRdLat:\n");
- for (ChannelDTD = 0; ChannelDTD<2; ChannelDTD++) {
+ for (ChannelDTD = 0; ChannelDTD < 2; ChannelDTD++) {
printk(BIOS_DEBUG, "Channel: %02x: %02x\n", ChannelDTD, pDCTstat->CH_MaxRdLat[ChannelDTD][0]);
}
}
@@ -207,7 +207,7 @@ static void mct_setMaxRdLatTrnVal_D(struct DCTStatStruc *pDCTstat,
if (pDCTstat->GangedMode) {
Channel = 0; /* for safe */
- for (i=0; i<2; i++)
+ for (i = 0; i < 2; i++)
pDCTstat->CH_MaxRdLat[i][0] = MaxRdLatVal;
} else {
pDCTstat->CH_MaxRdLat[Channel][0] = MaxRdLatVal;
@@ -239,7 +239,7 @@ static u8 CompareMaxRdLatTestPattern_D(u32 pattern_buf, u32 addr)
addr_lo = addr<<8;
_EXECFENCE;
- for (i=0; i<(16*3); i++) {
+ for (i = 0; i < 16*3; i++) {
val = read32_fs(addr_lo);
val_test = test_buf[i];
@@ -284,11 +284,11 @@ static u32 GetMaxRdLatTestAddr_D(struct MCTStatStruc *pMCTstat,
*valid = 0;
for (ch = ch_start; ch < ch_end; ch++) {
- for (d=0; d<4; d++) {
- for (Byte = 0; Byte<bn; Byte++) {
+ for (d = 0; d < 4; d++) {
+ for (Byte = 0; Byte < bn; Byte++) {
u8 tmp;
tmp = pDCTstat->CH_D_B_RCVRDLY[ch][d][Byte];
- if (tmp>Max) {
+ if (tmp > Max) {
Max = tmp;
Channel_Max = Channel;
d_Max = d;
@@ -371,7 +371,7 @@ u8 mct_GetStartMaxRdLat_D(struct MCTStatStruc *pMCTstat,
valx = (val) << 2; /* SubTotal div 4 to scale 1/4 MemClk back to MemClk */
val = Get_NB32(pDCTstat->dev_nbmisc, 0xD4);
- val = ((val & 0x1f) + 4 ) * 3;
+ val = ((val & 0x1f) + 4) * 3;
/* Calculate 1 MemClk + 1 NCLK delay in NCLKs for margin */
valxx = val << 2;
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
index 44ea6e8..47c5004 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctwl.c
@@ -426,7 +426,7 @@ void SetTargetFreq(struct MCTStatStruc *pMCTstat,
}
}
- /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns=1250ns */
+ /* wait for 500 MCLKs after ExitSelfRef, 500*2.5ns = 1250ns */
mct_Wait(250);
if (pDCTstat->Status & (1 << SB_Registered)) {
@@ -474,9 +474,9 @@ void Restore_OnDimmMirror(struct MCTStatStruc *pMCTstat,
{
if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */
if (pDCTstat->MirrPresU_NumRegR & 0x55)
- Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct=0, set */
+ Modify_OnDimmMirror(pDCTstat, 0, 1); /* dct = 0, set */
if (pDCTstat->MirrPresU_NumRegR & 0xAA)
- Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct=1, set */
+ Modify_OnDimmMirror(pDCTstat, 1, 1); /* dct = 1, set */
}
}
void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat,
@@ -484,8 +484,8 @@ void Clear_OnDimmMirror(struct MCTStatStruc *pMCTstat,
{
if (pDCTstat->LogicalCPUID & (AMD_DR_Bx /* | AMD_RB_C0 */)) { /* We dont support RB-C0 now */
if (pDCTstat->MirrPresU_NumRegR & 0x55)
- Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct=0, clear */
+ Modify_OnDimmMirror(pDCTstat, 0, 0); /* dct = 0, clear */
if (pDCTstat->MirrPresU_NumRegR & 0xAA)
- Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct=1, clear */
+ Modify_OnDimmMirror(pDCTstat, 1, 0); /* dct = 1, clear */
}
}
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
index 5c30bc5..dce6212 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c
@@ -140,15 +140,15 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
*/
if (dct)
{
- Addl_Data_Offset=0x198;
- Addl_Data_Port=0x19C;
+ Addl_Data_Offset = 0x198;
+ Addl_Data_Port = 0x19C;
}
else
{
- Addl_Data_Offset=0x98;
- Addl_Data_Port=0x9C;
+ Addl_Data_Offset = 0x98;
+ Addl_Data_Port = 0x9C;
}
- Addr=0x0D00000C;
+ Addr = 0x0D00000C;
AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr);
while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset,
DctAccessDone, DctAccessDone)) == 0);
@@ -157,7 +157,7 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT
Value = bitTestReset(Value, 4); /* for x8 only */
Value = bitTestReset(Value, 5); /* for hardware WL training */
AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value);
- Addr=0x4D030F0C;
+ Addr = 0x4D030F0C;
AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr);
while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset,
DctAccessDone, DctAccessDone)) == 0);
@@ -397,8 +397,8 @@ u32 swapAddrBits_wl(struct DCTStatStruc *pDCTstat, uint8_t dct, uint32_t MRSValu
tempW &= 0x0A8;
tempW1 &= 0x0150;
MRSValue &= 0xFE07;
- MRSValue |= (tempW<<1);
- MRSValue |= (tempW1>>1);
+ MRSValue |= (tempW << 1);
+ MRSValue |= (tempW1 >> 1);
}
}
return MRSValue;
@@ -438,8 +438,8 @@ u32 swapBankBits(struct DCTStatStruc *pDCTstat, uint8_t dct, u32 MRSValue)
tempW &= 0x01;
tempW1 &= 0x02;
MRSValue = 0;
- MRSValue |= (tempW<<1);
- MRSValue |= (tempW1>>1);
+ MRSValue |= (tempW << 1);
+ MRSValue |= (tempW1 >> 1);
}
}
return MRSValue;
@@ -453,22 +453,22 @@ static uint16_t unbuffered_dimm_nominal_termination_emrs(uint8_t number_of_dimms
if (number_of_dimms == 1) {
if (MaxDimmsInstallable < 3) {
- term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */
+ term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */
} else {
if (rank_count == 1) {
- term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */
+ term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */
} else {
if (rank == 0)
- term = 0x04; /* Rtt_Nom=RZQ/4=60 Ohm */
+ term = 0x04; /* Rtt_Nom = RZQ/4 = 60 Ohm */
else
- term = 0x00; /* Rtt_Nom=OFF */
+ term = 0x00; /* Rtt_Nom = OFF */
}
}
} else {
if (frequency_index < 5)
- term = 0x0044; /* Rtt_Nom=RZQ/6=40 Ohm */
+ term = 0x0044; /* Rtt_Nom = RZQ/6 = 40 Ohm */
else
- term = 0x0204; /* Rtt_Nom=RZQ/8=30 Ohm */
+ term = 0x0204; /* Rtt_Nom = RZQ/8 = 30 Ohm */
}
return term;
@@ -482,15 +482,15 @@ static uint16_t unbuffered_dimm_dynamic_termination_emrs(uint8_t number_of_dimms
if (number_of_dimms == 1) {
if (MaxDimmsInstallable < 3) {
- term = 0x00; /* Rtt_WR=off */
+ term = 0x00; /* Rtt_WR = off */
} else {
if (rank_count == 1)
- term = 0x00; /* Rtt_WR=off */
+ term = 0x00; /* Rtt_WR = off */
else
- term = 0x200; /* Rtt_WR=RZQ/4=60 Ohm */
+ term = 0x200; /* Rtt_WR = RZQ/4 = 60 Ohm */
}
} else {
- term = 0x400; /* Rtt_WR=RZQ/2=120 Ohm */
+ term = 0x400; /* Rtt_WR = RZQ/2 = 120 Ohm */
}
return term;
@@ -558,7 +558,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
tempW = mct_MR1(pMCTstat, pDCTstat, dct, dimm*2+rank) & 0xffff;
tempW &= ~(0x0244);
} else {
- /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */
+ /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */
tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId,
FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn);
if (tempW2)
@@ -618,7 +618,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
}
/* Apply Rtt_Nom to the MRS control word */
- tempW=tempW|tempW1;
+ tempW = tempW|tempW1;
/* All ranks of the target DIMM are set to write levelization mode. */
if (wl)
@@ -702,8 +702,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
{tempW = bitTestSet(tempW, 7);}
if (bitTest(tempW1,18))
{tempW = bitTestSet(tempW, 6);}
- /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */
- tempW=tempW|((tempW1&0x00700000)>>17);
+ /* tempW = tempW|(((tempW1 >> 20) & 0x7 )<< 3); */
+ tempW = tempW|((tempW1&0x00700000) >> 17);
/* workaround for DR-B0 */
if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))
tempW+=0x8;
@@ -720,7 +720,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
}
/* Apply Rtt_WR to the MRS control word */
- tempW=tempW|tempW1;
+ tempW = tempW|tempW1;
tempW = swapAddrBits_wl(pDCTstat, dct, tempW);
if (is_fam15h())
set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT,
@@ -779,14 +779,14 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
/* Program F2x[1, 0]7C[MrsAddress[15:0]] to the required
* DDR3-defined function for write levelization.
*/
- tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level=0, Qoff=0 */
+ tempW = 0;/* DLL_DIS = 0, DIC = 0, AL = 0, TDQS = 0, Level = 0, Qoff = 0 */
/* Retrieve normal settings of the MRS control word and clear Rtt_Nom */
if (is_fam15h()) {
tempW = mct_MR1(pMCTstat, pDCTstat, dct, currDimm*2+rank) & 0xffff;
tempW &= ~(0x0244);
} else {
- /* Set TDQS=1b for x8 DIMM, TDQS=0b for x4 DIMM, when mixed x8 & x4 */
+ /* Set TDQS = 1b for x8 DIMM, TDQS = 0b for x4 DIMM, when mixed x8 & x4 */
tempW2 = get_Bits(pDCTData, dct, pDCTData->NodeId,
FUN_DCT, DRAM_CONFIG_HIGH, RDqsEn, RDqsEn);
if (tempW2)
@@ -811,7 +811,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
}
/* Apply Rtt_Nom to the MRS control word */
- tempW=tempW|tempW1;
+ tempW = tempW|tempW1;
/* Program MrsAddress[5,1]=output driver impedance control (DIC) */
if (is_fam15h()) {
@@ -877,8 +877,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
{tempW = bitTestSet(tempW, 7);}
if (bitTest(tempW1,18))
{tempW = bitTestSet(tempW, 6);}
- /* tempW=tempW|(((tempW1>>20)&0x7)<<3); */
- tempW=tempW|((tempW1&0x00700000)>>17);
+ /* tempW = tempW|(((tempW1 >> 20) & 0x7) << 3); */
+ tempW = tempW|((tempW1&0x00700000) >> 17);
/* workaround for DR-B0 */
if ((pDCTData->LogicalCPUID & AMD_DR_Bx) && (pDCTData->Status[DCT_STATUS_REGISTERED]))
tempW+=0x8;
@@ -895,7 +895,7 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat,
}
/* Apply Rtt_WR to the MRS control word */
- tempW=tempW|tempW1;
+ tempW = tempW|tempW1;
tempW = swapAddrBits_wl(pDCTstat, dct, tempW);
if (is_fam15h())
set_Bits(pDCTData, dct, pDCTData->NodeId, FUN_DCT,
@@ -939,7 +939,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
sMCTStruct *pMCTData = pDCTstat->C_MCTPtr;
sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct];
- u8 WrLvOdt1=0;
+ u8 WrLvOdt1 = 0;
if (is_fam15h()) {
/* On Family15h processors, the value for the specific CS being targetted
@@ -954,7 +954,7 @@ void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
cs = (dimm * 2) + rank;
/* Fetch preprogammed ODT pattern from configuration registers */
- dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs>3)?0x23c:0x238));
+ dword = Get_NB32_DCT(pDCTstat->dev_dct, dct, ((cs > 3)?0x23c:0x238));
if ((cs == 7) || (cs == 3))
WrLvOdt1 = ((dword >> 24) & 0xf);
else if ((cs == 6) || (cs == 2))
@@ -1045,25 +1045,25 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui
}
else
{
- /* Program WrLvOdtEn=1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */
+ /* Program WrLvOdtEn = 1 through set bit 12 of D3CSODT reg offset 0 for Rev.B */
if (dct)
{
- Addl_Data_Offset=0x198;
- Addl_Data_Port=0x19C;
+ Addl_Data_Offset = 0x198;
+ Addl_Data_Port = 0x19C;
}
else
{
- Addl_Data_Offset=0x98;
- Addl_Data_Port=0x9C;
+ Addl_Data_Offset = 0x98;
+ Addl_Data_Port = 0x9C;
}
- Addr=0x0D008000;
+ Addr = 0x0D008000;
AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr);
while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset,
DctAccessDone, DctAccessDone)) == 0);
AmdMemPCIReadBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value);
Value = bitTestSet(Value, 12);
AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Port), 31, 0, &Value);
- Addr=0x4D088F00;
+ Addr = 0x4D088F00;
AmdMemPCIWriteBits(MAKE_SBDFO(0,0,24+(pDCTData->NodeId),FUN_DCT,Addl_Data_Offset), 31, 0, &Addr);
while ((get_Bits(pDCTData,FUN_DCT,pDCTData->NodeId, FUN_DCT, Addl_Data_Offset,
DctAccessDone, DctAccessDone)) == 0);
@@ -1371,7 +1371,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8
while (ByteLane < lane_count)
{
/* This subtract 0xC workaround might be temporary. */
- if ((pDCTData->WLPass==2) && (pDCTData->RegMan1Present & (1<<(dimm*2+dct)))) {
+ if ((pDCTData->WLPass == 2) && (pDCTData->RegMan1Present & (1 << (dimm*2+dct)))) {
tempW = (pDCTData->WLGrossDelay[index+ByteLane] << 5) | pDCTData->WLFineDelay[index+ByteLane];
tempW -= 0xC;
pDCTData->WLGrossDelay[index+ByteLane] = (u8)(tempW >> 5);
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
index 6589a39..97cadcb 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/s3utils.c
@@ -351,12 +351,12 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x11c = pci_read_config32(dev_fn2, 0x11c);
data->f2x1b0 = pci_read_config32(dev_fn2, 0x1b0);
data->f3x44 = pci_read_config32(dev_fn3, 0x44);
- for (i=0; i<16; i++) {
+ for (i = 0; i < 16; i++) {
data->msr0000020[i] = rdmsr_uint64_t(0x00000200 | i);
}
data->msr00000250 = rdmsr_uint64_t(0x00000250);
data->msr00000258 = rdmsr_uint64_t(0x00000258);
- for (i=0; i<8; i++)
+ for (i = 0; i < 8; i++)
data->msr0000026[i] = rdmsr_uint64_t(0x00000260 | (i + 8));
data->msr000002ff = rdmsr_uint64_t(0x000002ff);
data->msrc0010010 = rdmsr_uint64_t(0xc0010010);
@@ -393,7 +393,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x204 = read_config32_dct(dev_fn2, node, channel, 0x204);
data->f2x208 = read_config32_dct(dev_fn2, node, channel, 0x208);
data->f2x20c = read_config32_dct(dev_fn2, node, channel, 0x20c);
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
data->f2x210[i] = read_config32_dct_nbpstate(dev_fn2, node, channel, i, 0x210);
data->f2x214 = read_config32_dct(dev_fn2, node, channel, 0x214);
data->f2x218 = read_config32_dct(dev_fn2, node, channel, 0x218);
@@ -407,7 +407,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x9cx0d0fe003 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe003);
data->f2x9cx0d0fe013 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe013);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_8_0_1f[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f001f | (i << 8));
data->f2x9cx0d0f201f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f201f);
data->f2x9cx0d0f211f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f211f);
@@ -419,11 +419,11 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x9cx0d0fc11f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc11f);
data->f2x9cx0d0fc21f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc21f);
data->f2x9cx0d0f4009 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f4009);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_8_0_02[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0002 | (i << 8));
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_8_0_06[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0006 | (i << 8));
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_8_0_0a[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f000a | (i << 8));
data->f2x9cx0d0f2002 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2002);
@@ -450,7 +450,7 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x9cx0d0fc031 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc031);
data->f2x9cx0d0fc131 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc131);
data->f2x9cx0d0fc231 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fc231);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_0_f_31[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0031 | (i << 8));
data->f2x9cx0d0f8021 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f8021);
@@ -463,8 +463,8 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x94 = read_config32_dct(dev_fn2, node, channel, 0x94);
/* Stage 6 */
- for (i=0; i<9; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 9; i++)
+ for (j = 0; j < 3; j++)
data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4));
data->f2x9cx00 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x00);
data->f2x9cx0a = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0a);
@@ -478,33 +478,33 @@ void copy_mct_data_to_save_variable(struct amd_s3_persistent_data* persistent_da
data->f2x9cx0d0fe007 = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0fe007);
/* Stage 10 */
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
data->f2x9cx10[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x10 + i);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
data->f2x9cx20[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x20 + i);
- for (i=0; i<4; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 4; i++)
+ for (j = 0; j < 3; j++)
data->f2x9cx3_0_0_3_1[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x01 + i) + (0x100 * j));
- for (i=0; i<4; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 4; i++)
+ for (j = 0; j < 3; j++)
data->f2x9cx3_0_0_7_5[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, (0x05 + i) + (0x100 * j));
data->f2x9cx0d = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_f_0_13[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0013 | (i << 8));
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
data->f2x9cx0d0f0_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0030 | (i << 8));
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
data->f2x9cx0d0f2_f_0_30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f2030 | (i << 8));
- for (i=0; i<2; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < 3; j++)
data->f2x9cx0d0f8_8_4_0[i][j] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4));
data->f2x9cx0d0f812f = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x0d0f812f);
/* Stage 11 */
if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
data->f2x9cx30[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x30 + i);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
data->f2x9cx40[i] = read_amd_dct_index_register_dct(dev_fn2, node, channel, 0x98, 0x40 + i);
}
@@ -599,28 +599,28 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
continue;
/* Restore training parameters */
- for (i=0; i<4; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 4; i++)
+ for (j = 0; j < 3; j++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]);
- for (i=0; i<4; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 4; i++)
+ for (j = 0; j < 3; j++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]);
if (IS_ENABLED(CONFIG_DIMM_DDR3)) {
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]);
}
/* Restore MaxRdLatency */
if (is_fam15h()) {
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]);
} else {
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x78, data->f2x78);
@@ -682,7 +682,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x11c, data->f2x11c);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x1b0, data->f2x1b0);
write_config32_dct(PCI_DEV(0, 0x18 + node, 3), node, channel, 0x44, data->f3x44);
- for (i=0; i<16; i++) {
+ for (i = 0; i < 16; i++) {
wrmsr_uint64_t(0x00000200 | i, data->msr0000020[i]);
}
wrmsr_uint64_t(0x00000250, data->msr00000250);
@@ -692,7 +692,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
* destroying CAR while still executing from CAR!
* For now, skip restoration...
*/
- // for (i=0; i<8; i++)
+ // for (i = 0; i < 8; i++)
// wrmsr_uint64_t(0x00000260 | (i + 8), data->msr0000026[i]);
wrmsr_uint64_t(0x000002ff, data->msr000002ff);
wrmsr_uint64_t(0xc0010010, data->msrc0010010);
@@ -760,7 +760,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x204, data->f2x204);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x208, data->f2x208);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x20c, data->f2x20c);
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
write_config32_dct_nbpstate(PCI_DEV(0, 0x18 + node, 2), node, channel, i, 0x210, data->f2x210[i]);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x214, data->f2x214);
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x218, data->f2x218);
@@ -773,7 +773,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
write_config32_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x240, data->f2x240);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe013, data->f2x9cx0d0fe013);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f001f | (i << 8), data->f2x9cx0d0f0_8_0_1f[i]);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f201f, data->f2x9cx0d0f201f);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f211f, data->f2x9cx0d0f211f);
@@ -795,7 +795,7 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc031, data->f2x9cx0d0fc031);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc131, data->f2x9cx0d0fc131);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fc231, data->f2x9cx0d0fc231);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0031 | (i << 8), data->f2x9cx0d0f0_0_f_31[i]);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8021, data->f2x9cx0d0f8021);
@@ -899,8 +899,8 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
if (!persistent_data->node[node].node_present)
continue;
- for (i=0; i<9; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 9; i++)
+ for (j = 0; j < 3; j++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f0_f_8_0_0_8_4_0[i][j]);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x00, data->f2x9cx00);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0a, data->f2x9cx0a);
@@ -920,11 +920,11 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
dword |= (0x3 << 13); /* DisAutoComp, DisablePredriverCal = 1 */
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0fe003, dword);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0006 | (i << 8), data->f2x9cx0d0f0_8_0_06[i]);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f000a | (i << 8), data->f2x9cx0d0f0_8_0_0a[i]);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0002 | (i << 8), (0x8000 | data->f2x9cx0d0f0_8_0_02[i]));
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f8006, data->f2x9cx0d0f8006);
@@ -1024,25 +1024,25 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
if (!persistent_data->node[node].node_present)
continue;
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x10 + i, data->f2x9cx10[i]);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x20 + i, data->f2x9cx20[i]);
- for (i=0; i<4; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 4; i++)
+ for (j = 0; j < 3; j++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x01 + i) + (0x100 * j), data->f2x9cx3_0_0_3_1[i][j]);
- for (i=0; i<4; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 4; i++)
+ for (j = 0; j < 3; j++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, (0x05 + i) + (0x100 * j), data->f2x9cx3_0_0_7_5[i][j]);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d, data->f2x9cx0d);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0013 | (i << 8), data->f2x9cx0d0f0_f_0_13[i]);
- for (i=0; i<9; i++)
+ for (i = 0; i < 9; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0030 | (i << 8), data->f2x9cx0d0f0_f_0_30[i]);
- for (i=0; i<4; i++)
+ for (i = 0; i < 4; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f2030 | (i << 8), data->f2x9cx0d0f2_f_0_30[i]);
- for (i=0; i<2; i++)
- for (j=0; j<3; j++)
+ for (i = 0; i < 2; i++)
+ for (j = 0; j < 3; j++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f0000 | (i << 8) | (j * 4), data->f2x9cx0d0f8_8_4_0[i][j]);
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x0d0f812f, data->f2x9cx0d0f812f);
}
@@ -1056,9 +1056,9 @@ void restore_mct_data_from_save_variable(struct amd_s3_persistent_data* persiste
if (!persistent_data->node[node].node_present)
continue;
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x30 + i, data->f2x9cx30[i]);
- for (i=0; i<12; i++)
+ for (i = 0; i < 12; i++)
write_amd_dct_index_register_dct(PCI_DEV(0, 0x18 + node, 2), node, channel, 0x98, 0x40 + i, data->f2x9cx40[i]);
}
}
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti.h b/src/northbridge/amd/amdmct/wrappers/mcti.h
index 92979ab..5eaff2c 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti.h
+++ b/src/northbridge/amd/amdmct/wrappers/mcti.h
@@ -63,7 +63,7 @@ UPDATE AS NEEDED
#endif
#ifndef MEM_MAX_LOAD_FREQ
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
#define MEM_MAX_LOAD_FREQ 933
#define MEM_MIN_PLATFORM_FREQ_FAM10 400
#define MEM_MIN_PLATFORM_FREQ_FAM15 333
diff --git a/src/northbridge/amd/amdmct/wrappers/mcti_d.c b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
index 143468a..9cb981a 100644
--- a/src/northbridge/amd/amdmct/wrappers/mcti_d.c
+++ b/src/northbridge/amd/amdmct/wrappers/mcti_d.c
@@ -347,7 +347,7 @@ static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
printk(BIOS_DEBUG, "mctGet_MaxLoadFreq: Channel 2: %d DIMM(s) detected\n", ch2_count);
}
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
uint8_t dimm;
for (i = 0; i < MAX_DIMMS_SUPPORTED; i = i + 2) {
@@ -473,7 +473,7 @@ static void mctHookAfterDramInit(void)
{
}
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
static void vErratum372(struct DCTStatStruc *pDCTstat)
{
msr_t msr = rdmsr(NB_CFG_MSR);
@@ -481,8 +481,8 @@ static void vErratum372(struct DCTStatStruc *pDCTstat)
int nbPstate1supported = !(msr.hi & (1 << (NB_GfxNbPstateDis -32)));
// is this the right way to check for NB pstate 1 or DDR3-1333 ?
- if (((pDCTstat->PresetmaxFreq==1333)||(nbPstate1supported))
- &&(!pDCTstat->GangedMode)) {
+ if (((pDCTstat->PresetmaxFreq == 1333)||(nbPstate1supported))
+ && (!pDCTstat->GangedMode)) {
/* DisableCf8ExtCfg */
msr.hi &= ~(3 << (51 - 32));
wrmsr(NB_CFG_MSR, msr);
@@ -491,15 +491,15 @@ static void vErratum372(struct DCTStatStruc *pDCTstat)
static void vErratum414(struct DCTStatStruc *pDCTstat)
{
- int dct=0;
+ int dct = 0;
for (; dct < 2 ; dct++) {
int dRAMConfigHi = Get_NB32(pDCTstat->dev_dct,0x94 + (0x100 * dct));
- int powerDown = dRAMConfigHi & (1 << PowerDownEn );
- int ddr3 = dRAMConfigHi & (1 << Ddr3Mode );
+ int powerDown = dRAMConfigHi & (1 << PowerDownEn);
+ int ddr3 = dRAMConfigHi & (1 << Ddr3Mode);
int dRAMMRS = Get_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct));
int pchgPDModeSel = dRAMMRS & (1 << PchgPDModeSel);
- if (powerDown && ddr3 && pchgPDModeSel )
- Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel) );
+ if (powerDown && ddr3 && pchgPDModeSel)
+ Set_NB32(pDCTstat->dev_dct,0x84 + (0x100 * dct), dRAMMRS & ~(1 << PchgPDModeSel));
}
}
#endif
@@ -507,7 +507,7 @@ static void vErratum414(struct DCTStatStruc *pDCTstat)
static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA)
{
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
/* FIXME : as of 25.6.2010 errata 350 and 372 should apply to ((RB|BL|DA)-C[23])|(HY-D[01])|(PH-E0) but I don't find constants for all of them */
if (pDCTstatA->LogicalCPUID & (AMD_DRBH_Cx | AMD_DR_Dx)) {
vErratum372(pDCTstatA);
@@ -516,7 +516,7 @@ static void mctHookBeforeAnyTraining(struct MCTStatStruc *pMCTstat, struct DCTSt
#endif
}
-#if (CONFIG_DIMM_SUPPORT & 0x000F)==0x0005 /* AMD_FAM10_DDR3 */
+#if (CONFIG_DIMM_SUPPORT & 0x000F) == 0x0005 /* AMD_FAM10_DDR3 */
static u32 mct_AdjustSPDTimings(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA, u32 val)
{
if (pDCTstatA->LogicalCPUID & AMD_DR_Bx) {
1
0
Patch set updated for coreboot: northbridge/amdk8: Improve code formatting
by Martin Roth 21 Sep '16
by Martin Roth 21 Sep '16
21 Sep '16
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16644
-gerrit
commit 5732c5cd5b00f68386dacd05f283ee2d71e1c1ec
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 10:26:28 2016 -0600
northbridge/amdk8: Improve code formatting
Change-Id: I1c2786dfb166904ff8b19a663c5e2e8156b7aedf
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
---
src/northbridge/amd/amdk8/acpi.c | 26 ++--
src/northbridge/amd/amdk8/coherent_ht.c | 124 ++++++++---------
src/northbridge/amd/amdk8/debug.c | 10 +-
src/northbridge/amd/amdk8/early_ht.c | 4 +-
src/northbridge/amd/amdk8/exit_from_self.c | 2 +-
src/northbridge/amd/amdk8/f.h | 6 +-
src/northbridge/amd/amdk8/get_sblk_pci1234.c | 8 +-
src/northbridge/amd/amdk8/incoherent_ht.c | 72 +++++-----
src/northbridge/amd/amdk8/misc_control.c | 12 +-
src/northbridge/amd/amdk8/northbridge.c | 30 ++--
src/northbridge/amd/amdk8/raminit.c | 40 +++---
src/northbridge/amd/amdk8/raminit_f.c | 182 ++++++++++++-------------
src/northbridge/amd/amdk8/raminit_f_dqs.c | 160 +++++++++++-----------
src/northbridge/amd/amdk8/setup_resource_map.c | 8 +-
src/northbridge/amd/amdk8/util.asl | 14 +-
15 files changed, 349 insertions(+), 349 deletions(-)
diff --git a/src/northbridge/amd/amdk8/acpi.c b/src/northbridge/amd/amdk8/acpi.c
index 992a85e..906dc0b 100644
--- a/src/northbridge/amd/amdk8/acpi.c
+++ b/src/northbridge/amd/amdk8/acpi.c
@@ -101,7 +101,7 @@ static void set_srat_mem(void *gp, struct device *dev, struct resource *res)
*/
if ((basek+sizek)<1024) return;
- if (basek<1024) {
+ if (basek < 1024) {
sizek -= 1024 - basek;
basek = 1024;
}
@@ -158,29 +158,29 @@ static unsigned long acpi_fill_slit(unsigned long current)
p += 8;
#if 0
- for (i=0;i<sysconf.hc_possible_num;i++) {
- if ((sysconf.pci1234[i]&1) !=1 ) continue;
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
+ if ((sysconf.pci1234[i]&1) !=1) continue;
outer_node[(sysconf.pci1234[i] >> 4) & 0xf] = 1; // mark the outer node
}
#endif
- for (i=0;i<nodes;i++) {
- for (j=0;j<nodes; j++) {
- if (i==j) {
+ for (i = 0; i < nodes; i++) {
+ for (j = 0; j < nodes; j++) {
+ if (i == j) {
p[i*nodes+j] = 10;
} else {
#if 0
int k;
u8 latency_factor = 0;
int k_start, k_end;
- if (i<j) {
+ if (i < j) {
k_start = i;
k_end = j;
} else {
k_start = j;
k_end = i;
}
- for (k=k_start;k<=k_end; k++) {
+ for (k = k_start; k <= k_end; k++) {
if (outer_node[k]) {
latency_factor = 1;
break;
@@ -238,10 +238,10 @@ static void k8acpi_write_HT(void) {
acpigen_write_name("HCLK");
acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) {
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
acpigen_write_dword(sysconf.pci1234[i]);
}
- for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
acpigen_write_dword(0x0);
}
@@ -250,10 +250,10 @@ static void k8acpi_write_HT(void) {
acpigen_write_name("HCDN");
acpigen_write_package(HC_POSSIBLE_NUM);
- for (i=0;i<sysconf.hc_possible_num;i++) {
+ for (i = 0; i < sysconf.hc_possible_num; i++) {
acpigen_write_dword(sysconf.hcdn[i]);
}
- for (i=sysconf.hc_possible_num; i<HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
+ for (i = sysconf.hc_possible_num; i < HC_POSSIBLE_NUM; i++) { // in case we set array size to other than 8
acpigen_write_dword(0x20202020);
}
acpigen_pop_len();
@@ -268,7 +268,7 @@ static void k8acpi_write_pci_data(int dlen, const char *name, int offset) {
acpigen_write_name(name);
acpigen_write_package(dlen);
- for (i=0; i<dlen; i++) {
+ for (i = 0; i < dlen; i++) {
dword = pci_read_config32(dev, offset+i*4);
acpigen_write_dword(dword);
}
diff --git a/src/northbridge/amd/amdk8/coherent_ht.c b/src/northbridge/amd/amdk8/coherent_ht.c
index 7e33feb..887a23b 100644
--- a/src/northbridge/amd/amdk8/coherent_ht.c
+++ b/src/northbridge/amd/amdk8/coherent_ht.c
@@ -139,7 +139,7 @@ static void disable_probes(void)
printk(BIOS_SPEW, "Disabling read/write/fill probes for UP... ");
- val=pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
+ val = pci_read_config32(NODE_HT(0), HT_TRANSACTION_CONTROL);
val |= HTTC_DIS_FILL_P | HTTC_DIS_RMT_MEM_C | HTTC_DIS_P_MEM_C |
HTTC_DIS_MTS | HTTC_DIS_WR_DW_P | HTTC_DIS_WR_B_P |
HTTC_DIS_RD_DW_P | HTTC_DIS_RD_B_P;
@@ -193,7 +193,7 @@ static void enable_routing(u8 node)
/* Enable routing table */
printk(BIOS_SPEW, "Enabling routing table for node %d", node);
- val=pci_read_config32(NODE_HT(node), 0x6c);
+ val = pci_read_config32(NODE_HT(node), 0x6c);
val &= ~((1<<1)|(1<<0));
pci_write_config32(NODE_HT(node), 0x6c, val);
@@ -241,7 +241,7 @@ static void rename_temp_node(u8 node)
printk(BIOS_SPEW, "Renaming current temporary node to %d", node);
- val=pci_read_config32(NODE_HT(7), 0x60);
+ val = pci_read_config32(NODE_HT(7), 0x60);
val &= (~7); /* clear low bits. */
val |= node; /* new node */
pci_write_config32(NODE_HT(7), 0x60, val);
@@ -401,7 +401,7 @@ static void setup_row_local(u8 source, u8 row) /* source will be 7 when it is fo
uint8_t linkn;
uint32_t val;
val = 1;
- for (linkn = 0; linkn<3; linkn++) {
+ for (linkn = 0; linkn < 3; linkn++) {
uint8_t regpos;
uint32_t reg;
regpos = 0x98 + 0x20 * linkn;
@@ -423,10 +423,10 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
if (((source &1)!=(dest &1))
#if CROSS_BAR_47_56
- && ( (source<4)||(source>5) ) //(6,7) (7,6) should still be here
+ && ((source < 4)||(source > 5)) //(6,7) (7,6) should still be here
//(6,5) (7,4) should be here
#endif
- ){
+ ) {
val |= (1<<16);
} else {
/*for CROSS_BAR_47_56 47, 56, should be here too
@@ -437,7 +437,7 @@ static void setup_row_direct_x(u8 temp, u8 source, u8 dest, u8 linkn)
val |= ((val_s>>16) - (1<<(linkn+1)))<<16;
}
- fill_row(temp,dest, val );
+ fill_row(temp,dest, val);
}
#if CROSS_BAR_47_56
@@ -453,7 +453,7 @@ static void opt_broadcast_rt_group(const u8 *conn, int num)
{
int i;
- for (i=0; i<num; i+=3) {
+ for (i = 0; i < num; i+=3) {
opt_broadcast_rt(conn[i], conn[i+1],conn[i+2]);
}
}
@@ -470,7 +470,7 @@ static void opt_broadcast_rt_plus_group(const u8 *conn, int num)
{
int i;
- for (i=0; i<num; i+=3) {
+ for (i = 0; i < num; i+=3) {
opt_broadcast_rt_plus(conn[i], conn[i+1],conn[i+2]);
}
}
@@ -535,7 +535,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
#if !CROSS_BAR_47_56
u8 gateway;
u8 diff;
- if (source<dest) {
+ if (source < dest) {
gateway = source + 2;
} else {
gateway = source - 2;
@@ -552,7 +552,7 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
diff = ((source&1)!=(dest &1));
#endif
- if (diff && (val_s!=(val&0xff)) ) { /* use another connect as response*/
+ if (diff && (val_s!=(val&0xff))) { /* use another connect as response*/
val_s -= val & 0xff;
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
uint8_t byte;
@@ -562,14 +562,14 @@ static void setup_row_indirect_x(u8 temp, u8 source, u8 dest, u8 gateway, u8 dif
byte = val_s;
byte = get_linkn_last_count(byte);
if ((byte>>2)>1) { /* make sure not the corner*/
- if (source<dest) {
+ if (source < dest) {
val_s-=link_connection(temp, source-2); /* -down*/
} else {
#if CROSS_BAR_47_56
#if 0
- if (source==7) {
+ if (source == 7) {
val_s-=link_connection(temp, 6); // for 7,2 via 5
- } else if (source==6){
+ } else if (source == 6) {
val_s-=link_connection(temp, 7); // for 6,3 via 4
} else
#endif
@@ -614,10 +614,10 @@ static void setup_row_indirect_group(const u8 *conn, int num)
int i;
#if !CROSS_BAR_47_56
- for (i=0; i<num; i+=2) {
+ for (i = 0; i < num; i+=2) {
setup_row_indirect(conn[i], conn[i+1]);
#else
- for (i=0; i<num; i+=4) {
+ for (i = 0; i < num; i+=4) {
setup_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
#endif
@@ -641,10 +641,10 @@ static void setup_remote_row_indirect_group(const u8 *conn, int num)
int i;
#if !CROSS_BAR_47_56
- for (i=0; i<num; i+=2) {
+ for (i = 0; i < num; i+=2) {
setup_remote_row_indirect(conn[i], conn[i+1]);
#else
- for (i=0; i<num; i+=4) {
+ for (i = 0; i < num; i+=4) {
setup_remote_row_indirect(conn[i], conn[i+1],conn[i+2], conn[i+3]);
#endif
}
@@ -658,7 +658,7 @@ static void setup_uniprocessor(void)
printk(BIOS_SPEW, "Enabling UP settings\n");
#if CONFIG_LOGICAL_CPUS
unsigned tmp = (pci_read_config32(NODE_MC(0), 0xe8) >> 12) & 3;
- if (tmp>0) return;
+ if (tmp > 0) return;
#endif
disable_probes();
}
@@ -668,10 +668,10 @@ static int optimize_connection_group(const u8 *opt_conn, int num)
{
int needs_reset = 0;
int i;
- for (i=0; i<num; i+=2) {
+ for (i = 0; i < num; i+=2) {
needs_reset = optimize_connection(
NODE_HT(opt_conn[i]), 0x80 + link_to_register(link_connection(opt_conn[i],opt_conn[i+1])),
- NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])) );
+ NODE_HT(opt_conn[i+1]), 0x80 + link_to_register(link_connection(opt_conn[i+1],opt_conn[i])));
}
return needs_reset;
}
@@ -689,7 +689,7 @@ static unsigned setup_smp2(void)
val = get_row(0,0);
byte = (val>>16) & 0xfe;
- if (byte<0x2) { /* no coherent connection so get out.*/
+ if (byte < 0x2) { /* no coherent connection so get out.*/
nodes = 1;
return nodes;
}
@@ -717,7 +717,7 @@ static unsigned setup_smp2(void)
val = get_row(7,1);
byte = (val>>16) & 0xfe;
byte = get_linkn_last_count(byte);
- if ((byte>>2)==3) { /* Oh! we need to treat it as node2. So use another link*/
+ if ((byte>>2) == 3) { /* Oh! we need to treat it as node2. So use another link*/
val = get_row(0,0);
byte = (val>>16) & 0xfe;
#if TRY_HIGH_FIRST == 1
@@ -760,14 +760,14 @@ static unsigned setup_smp4(void)
u8 byte;
uint32_t val;
- nodes=4;
+ nodes = 4;
/* Setup and check temporary connection from Node 0 to Node 2 */
val = get_row(0,0);
byte = ((val>>16) & 0xfe) - link_connection(0,1);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have two coherent for 4p and above*/
+ if ((byte>>2) == 0) { /* We should have two coherent for 4p and above*/
nodes = 2;
return nodes;
}
@@ -841,7 +841,7 @@ static unsigned setup_smp4(void)
#if (CONFIG_MAX_PHYSICAL_CPUS > 4) || CONFIG_MAX_PHYSICAL_CPUS_4_BUT_MORE_INSTALLED
/* We need to find out which link is to node3 */
- if ((byte>>2)==2) { /* one to node3, one to node0, one to node4*/
+ if ((byte>>2) == 2) { /* one to node3, one to node0, one to node4*/
val = get_row(7,3);
if ((val>>16) == 1) { /* that link is to node4, because via node1 it has been set, recompute it*/
val = get_row(2,2);
@@ -865,7 +865,7 @@ static unsigned setup_smp4(void)
val = get_row(7,3);
byte = ((val>>16) & 0xfe) - link_connection(7,2) - link_connection(7,1);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent links on node 3 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent links on node 3 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(3,5) link=", byte);
setup_remote_row_direct(3, 5, byte);
@@ -875,7 +875,7 @@ static unsigned setup_smp4(void)
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent link on node 2 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent link on node 2 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(2,4) link=", byte);
setup_row_direct(2, 4, byte);
@@ -931,14 +931,14 @@ static unsigned setup_smp6(void)
u8 byte;
uint32_t val;
- nodes=6;
+ nodes = 6;
/* Setup and check temporary connection from Node 0 to Node 4 through 2*/
val = get_row(2,2);
byte = ((val>>16) & 0xfe) - link_connection(2,3) - link_connection(2,0);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have three coherent link on node 2 for 6p and above*/
+ if ((byte>>2) == 0) { /* We should have three coherent link on node 2 for 6p and above*/
nodes = 4;
return nodes;
}
@@ -948,7 +948,7 @@ static unsigned setup_smp6(void)
val = get_row(3,3);
byte = ((val>>16) & 0xfe) - link_connection(3,2) - link_connection(3,1);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have three coherent links on node 3 for 6p and above*/
+ if ((byte>>2) == 0) { /* We should have three coherent links on node 3 for 6p and above*/
nodes = 4;
return nodes;
}
@@ -975,7 +975,7 @@ static unsigned setup_smp6(void)
setup_row_indirect_group(conn6_1, ARRAY_SIZE(conn6_1));
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte,byte+2);
}
verify_connection(7);
@@ -1003,7 +1003,7 @@ static unsigned setup_smp6(void)
enable_routing(4);
setup_temp_row(0,1);
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
verify_connection(7);
@@ -1031,7 +1031,7 @@ static unsigned setup_smp6(void)
#if CONFIG_MAX_PHYSICAL_CPUS > 6
/* We need to find out which link is to node5 */
- if ((byte>>2)==2) { /* one to node5, one to node2, one to node6*/
+ if ((byte>>2) == 2) { /* one to node5, one to node2, one to node6*/
val = get_row(7,5);
if ((val>>16) == 1) { /* that link is to node6, because via node 3 node 5 has been set*/
val = get_row(4,4);
@@ -1054,7 +1054,7 @@ static unsigned setup_smp6(void)
val = get_row(7,5);
byte = ((val>>16) & 0xfe) - link_connection(7,4) - link_connection(7,3);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent links on node 5 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent links on node 5 for 6p and above*/
byte &= 3; /*bit [3,2] is count-2*/
print_linkn("(5,7) link=", byte);
setup_remote_row_direct(5, 7, byte);
@@ -1065,7 +1065,7 @@ static unsigned setup_smp6(void)
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==1) { /* We should have three coherent link on node 4 for 6p and above*/
+ if ((byte>>2) == 1) { /* We should have three coherent link on node 4 for 6p and above*/
byte &= 3; /* bit [3,2] is count-2*/
print_linkn("(4,6) link=", byte);
setup_row_direct(4, 6, byte);
@@ -1115,7 +1115,7 @@ static unsigned setup_smp6(void)
/* We need to do sth about reverse about setup_temp_row (0,1), (2,4), (1, 3), (3,5)
* It will be done by clear_dead_links
*/
- for (byte=0; byte<4; byte++) {
+ for (byte = 0; byte < 4; byte++) {
clear_temp_row(byte);
}
#endif
@@ -1134,7 +1134,7 @@ static unsigned setup_smp8(void)
u8 byte;
uint32_t val;
- nodes=8;
+ nodes = 8;
/* Setup and check temporary connection from Node 0 to Node 6 via 2 and 4 to 7 */
val = get_row(4,4);
@@ -1143,7 +1143,7 @@ static unsigned setup_smp8(void)
#else
byte = ((val>>16) & 0xfe) - link_connection(4,5) - link_connection(4,2);
byte = get_linkn_last_count(byte); /* Max link to 6*/
- if ((byte>>2)==0) { /* We should have two or three coherent links on node 4 for 8p*/
+ if ((byte>>2) == 0) { /* We should have two or three coherent links on node 4 for 8p*/
nodes = 6;
return nodes;
}
@@ -1170,7 +1170,7 @@ static unsigned setup_smp8(void)
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,4) - link_connection(5,3);
byte = get_linkn_last_count(byte);
- if ((byte>>2)==0) { /* We should have three coherent links on node 5 for 6p and above*/
+ if ((byte>>2) == 0) { /* We should have three coherent links on node 5 for 6p and above*/
nodes = 6;
return nodes;
}
@@ -1203,7 +1203,7 @@ static unsigned setup_smp8(void)
setup_row_indirect_group(conn8_1,ARRAY_SIZE(conn8_1));
- for (byte=0; byte<6; byte+=2) {
+ for (byte = 0; byte < 6; byte+=2) {
setup_temp_row(byte,byte+2);
}
verify_connection(7);
@@ -1241,7 +1241,7 @@ static unsigned setup_smp8(void)
setup_row_direct(5, 6, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
setup_temp_row(5,6);
@@ -1249,7 +1249,7 @@ static unsigned setup_smp8(void)
verify_connection(7);
val = get_row(7,6); // to chect it if it is node6 before renaming
- if ( (val>>16) == 1) { // it is real node 7 so swap it
+ if ((val>>16) == 1) { // it is real node 7 so swap it
/* We need to recompute link to 6 */
val = get_row(5,5);
byte = ((val>>16) & 0xfe) - link_connection(5,3);
@@ -1262,7 +1262,7 @@ static unsigned setup_smp8(void)
setup_row_direct(5, 6, byte);
#if 0
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
#endif
@@ -1282,7 +1282,7 @@ static unsigned setup_smp8(void)
#if !CROSS_BAR_47_56
setup_temp_row(0,1);
- for (byte=0; byte<6; byte+=2) {
+ for (byte = 0; byte < 6; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
@@ -1302,7 +1302,7 @@ static unsigned setup_smp8(void)
setup_row_direct(4, 7, byte);
/* Setup and check temporary connection from Node 0 to Node 7 through 2, and 4*/
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte,byte+2);
}
@@ -1327,7 +1327,7 @@ static unsigned setup_smp8(void)
setup_row_direct(5, 7, byte);
setup_temp_row(0,1); /* temp. link between nodes 0 and 1 */
- for (byte=0; byte<4; byte+=2) {
+ for (byte = 0; byte < 4; byte+=2) {
setup_temp_row(byte+1,byte+3);
}
@@ -1511,7 +1511,7 @@ static unsigned verify_mp_capabilities(unsigned nodes)
mask = 0x06; /* BigMPCap */
- for (node=0; node<nodes; node++) {
+ for (node = 0; node < nodes; node++) {
mask &= pci_read_config32(NODE_MC(node), 0xe8);
}
@@ -1525,7 +1525,7 @@ static unsigned verify_mp_capabilities(unsigned nodes)
break;
#endif
case 0x00: /* Non SMP */
- if (nodes >1 ) {
+ if (nodes >1) {
printk(BIOS_ERR, "Going back to UP\n");
return 1;
}
@@ -1542,7 +1542,7 @@ static void clear_dead_routes(unsigned nodes)
int last_row;
int node, row;
#if CONFIG_MAX_PHYSICAL_CPUS == 8
- if (nodes==8) return;/* don't touch (7,7)*/
+ if (nodes == 8) return;/* don't touch (7,7)*/
#endif
last_row = nodes;
if (nodes == 1) {
@@ -1555,9 +1555,9 @@ static void clear_dead_routes(unsigned nodes)
}
/* Update the local row */
- for ( node=0; node<nodes; node++) {
+ for (node = 0; node < nodes; node++) {
uint32_t val = 0;
- for (row =0; row<nodes; row++) {
+ for (row =0; row < nodes; row++) {
val |= get_row(node, row);
}
fill_row(node, node, (((val & 0xff) | ((val >> 8) & 0xff)) << 16) | 0x0101);
@@ -1571,7 +1571,7 @@ static unsigned verify_dualcore(unsigned nodes)
unsigned node, totalcpus, tmp;
totalcpus = 0;
- for (node=0; node<nodes; node++) {
+ for (node = 0; node < nodes; node++) {
tmp = (pci_read_config32(NODE_MC(node), 0xe8) >> 12) & 3 ;
totalcpus += (tmp + 1);
}
@@ -1626,7 +1626,7 @@ static void coherent_ht_finalize(unsigned nodes)
/* Only respond to real CPU pci configuration cycles
* and optimize the HT settings
*/
- val=pci_read_config32(dev, HT_TRANSACTION_CONTROL);
+ val = pci_read_config32(dev, HT_TRANSACTION_CONTROL);
val &= ~((HTTC_BUF_REL_PRI_MASK << HTTC_BUF_REL_PRI_SHIFT) |
(HTTC_MED_PRI_BYP_CNT_MASK << HTTC_MED_PRI_BYP_CNT_SHIFT) |
(HTTC_HI_PRI_BYP_CNT_MASK << HTTC_HI_PRI_BYP_CNT_SHIFT));
@@ -1666,14 +1666,14 @@ static int apply_cpu_errata_fixes(unsigned nodes)
if ((cmd & (3 << 0)) != 2) {
cmd &= ~(3<<0);
cmd |= (2<<0);
- pci_write_config32(dev, 0x70, cmd );
+ pci_write_config32(dev, 0x70, cmd);
needs_reset = 1;
}
cmd = pci_read_config32(dev, 0x7c);
if ((cmd & (3 << 4)) != 0) {
cmd &= ~(3<<4);
cmd |= (0<<4);
- pci_write_config32(dev, 0x7c, cmd );
+ pci_write_config32(dev, 0x7c, cmd);
needs_reset = 1;
}
/* Clock Power/Timing Low */
@@ -1694,7 +1694,7 @@ static int apply_cpu_errata_fixes(unsigned nodes)
cmd_ref = 0x04e20707; /* Registered */
cmd = pci_read_config32(dev, 0xd4);
if (cmd != cmd_ref) {
- pci_write_config32(dev, 0xd4, cmd_ref );
+ pci_write_config32(dev, 0xd4, cmd_ref);
needs_reset = 1; /* Needed? */
}
}
@@ -1765,14 +1765,14 @@ static int optimize_link_coherent_ht(void)
nodes = get_nodes();
#if CONFIG_MAX_PHYSICAL_CPUS > 1
- if (nodes>1) {
+ if (nodes > 1) {
needs_reset |= optimize_connection(
NODE_HT(0), 0x80 + link_to_register(link_connection(0,1)),
- NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)) );
+ NODE_HT(1), 0x80 + link_to_register(link_connection(1,0)));
}
#if CONFIG_MAX_PHYSICAL_CPUS > 2
- if (nodes>2) {
+ if (nodes > 2) {
/* optimize physical connections - by LYH */
static const u8 opt_conn4[] = {
0,2,
@@ -1784,7 +1784,7 @@ static int optimize_link_coherent_ht(void)
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 4
- if (nodes>4) {
+ if (nodes > 4) {
static const uint8_t opt_conn6[] ={
2, 4,
3, 5,
@@ -1797,7 +1797,7 @@ static int optimize_link_coherent_ht(void)
#endif
#if CONFIG_MAX_PHYSICAL_CPUS > 6
- if (nodes>6) {
+ if (nodes > 6) {
static const uint8_t opt_conn8[] ={
4, 6,
#if CROSS_BAR_47_56
diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c
index 18fc858..a8431f4 100644
--- a/src/northbridge/amd/amdk8/debug.c
+++ b/src/northbridge/amd/amdk8/debug.c
@@ -71,7 +71,7 @@ static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg)
int j;
printk(BIOS_DEBUG, "\n%02x:",i);
val = pci_read_config32_index_wait(dev, index_reg, i);
- for (j=0;j<4;j++) {
+ for (j = 0; j < 4; j++) {
printk(BIOS_DEBUG, " %02x", val & 0xff);
val >>= 8;
}
@@ -185,7 +185,7 @@ static void dump_smbus_registers(void)
printk(BIOS_DEBUG, "\n");
for (device = 1; device < 0x80; device++) {
int j;
- if ( smbus_read_byte(device, 0) < 0 ) continue;
+ if (smbus_read_byte(device, 0) < 0) continue;
printk(BIOS_DEBUG, "smbus: %02x", device);
for (j = 0; j < 256; j++) {
int status;
@@ -211,7 +211,7 @@ static inline void dump_io_resources(unsigned port)
int i;
udelay(2000);
printk(BIOS_DEBUG, "%04x:\n", port);
- for (i=0;i<256;i++) {
+ for (i = 0; i < 256; i++) {
uint8_t val;
if ((i & 0x0f) == 0) {
printk(BIOS_DEBUG, "%02x:", i);
@@ -229,8 +229,8 @@ static inline void dump_mem(unsigned start, unsigned end)
{
unsigned i;
printk(BIOS_DEBUG, "dump_mem:");
- for (i=start;i<end;i++) {
- if ((i & 0xf)==0) {
+ for (i = start; i < end; i++) {
+ if ((i & 0xf) == 0) {
printk(BIOS_DEBUG, "\n%08x:", i);
}
printk(BIOS_DEBUG, " %02x", (unsigned char)*((unsigned char *)i));
diff --git a/src/northbridge/amd/amdk8/early_ht.c b/src/northbridge/amd/amdk8/early_ht.c
index d07da2a..638511a 100644
--- a/src/northbridge/amd/amdk8/early_ht.c
+++ b/src/northbridge/amd/amdk8/early_ht.c
@@ -64,7 +64,7 @@ static void enumerate_ht_chain(void)
pci_devfn_t devx;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if (next_unitid>=0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f.
+ if (next_unitid >= 0x18) { // don't get mask out by k8, at this time BSP, RT is not enabled, it will response from 0x18,0--0x1f.
if (!end_used) {
next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
@@ -127,7 +127,7 @@ out:
;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if ((ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
+ if ((ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
uint16_t flags;
dev = PCI_DEV(0,real_last_unitid, 0);
flags = pci_read_config16(dev, real_last_pos + PCI_CAP_FLAGS);
diff --git a/src/northbridge/amd/amdk8/exit_from_self.c b/src/northbridge/amd/amdk8/exit_from_self.c
index 858a0c0..6da042f 100644
--- a/src/northbridge/amd/amdk8/exit_from_self.c
+++ b/src/northbridge/amd/amdk8/exit_from_self.c
@@ -144,7 +144,7 @@ void exit_from_self(int controllers, const struct mem_controller *ctrl,
dcm =
pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
} while (((dcm & DCM_MemClrStatus) ==
- 0) /* || ((dcm & DCM_DramEnabled) == 0) */ );
+ 0) /* || ((dcm & DCM_DramEnabled) == 0) */);
if (loops >= TIMEOUT_LOOPS) {
printk(BIOS_DEBUG, "timeout with with cntrl[%d]\n", i);
diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h
index ce039af..a679150 100644
--- a/src/northbridge/amd/amdk8/f.h
+++ b/src/northbridge/amd/amdk8/f.h
@@ -537,9 +537,9 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
if (sysinfo->nodes == 1) return; // in case only one CPU installed
- for (i=1; i<sysinfo->nodes; i++) {
+ for (i = 1; i < sysinfo->nodes; i++) {
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->mem_trained[i]==0x00) continue;
+ if (sysinfo->mem_trained[i]== 0x00) continue;
mask |= (1<<i);
@@ -564,7 +564,7 @@ static inline void wait_all_core0_mem_trained(struct sys_info *sysinfo)
i%=sysinfo->nodes;
}
- for (i=0; i<sysinfo->nodes; i++) {
+ for (i = 0; i < sysinfo->nodes; i++) {
printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
switch(sysinfo->mem_trained[i]) {
case 0: //don't need train
diff --git a/src/northbridge/amd/amdk8/get_sblk_pci1234.c b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
index 9cf4083..764b6d1 100644
--- a/src/northbridge/amd/amdk8/get_sblk_pci1234.c
+++ b/src/northbridge/amd/amdk8/get_sblk_pci1234.c
@@ -211,7 +211,7 @@ void get_sblk_pci1234(void)
dev = dev_find_slot(0, PCI_DEVFN(0x18, 1));
- for (j=0;j<4;j++) {
+ for (j = 0; j < 4; j++) {
uint32_t dwordx;
dwordx = pci_read_config32(dev, 0xe0 + j*4);
dwordx &=0xffff0ff1; /* keep bus num, node_id, link_num, enable bits */
@@ -225,7 +225,7 @@ void get_sblk_pci1234(void)
/* We need to find out the number of HC
* for exact match
*/
- for (i=1;i<sysconf.hc_possible_num;i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((dwordx & 0xff0) == (sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
@@ -234,7 +234,7 @@ void get_sblk_pci1234(void)
}
/* For 0xff0 match or same node */
- for (i=1;i<sysconf.hc_possible_num;i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((dwordx & 0xff0) == (dwordx & sysconf.pci1234[i] & 0xff0)) {
sysconf.pci1234[i] = dwordx;
sysconf.hcdn[i] = sysconf.hcdn_reg[j];
@@ -244,7 +244,7 @@ void get_sblk_pci1234(void)
}
}
- for (i=1;i<sysconf.hc_possible_num;i++) {
+ for (i = 1; i < sysconf.hc_possible_num; i++) {
if ((sysconf.pci1234[i] & 1) != 1) {
sysconf.pci1234[i] = 0;
sysconf.hcdn[i] = 0x20202020;
diff --git a/src/northbridge/amd/amdk8/incoherent_ht.c b/src/northbridge/amd/amdk8/incoherent_ht.c
index bc50b66..9fa0034 100644
--- a/src/northbridge/amd/amdk8/incoherent_ht.c
+++ b/src/northbridge/amd/amdk8/incoherent_ht.c
@@ -374,7 +374,7 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
if (offset_unitid) {
- if (next_unitid>= (bus ? 0x20:0x18) ) {
+ if (next_unitid >= (bus ? 0x20:0x18)) {
if (!end_used) {
next_unitid = CONFIG_HT_CHAIN_END_UNITID_BASE;
end_used = 1;
@@ -428,9 +428,9 @@ static int ht_setup_chainx(pci_devfn_t udev, uint8_t upos, uint8_t bus,
/* Remeber the location of the last device */
udev = dev;
upos = pos;
- uoffs = ( offs != PCI_HT_SLAVE0_OFFS ) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
+ uoffs = (offs != PCI_HT_SLAVE0_OFFS) ? PCI_HT_SLAVE0_OFFS : PCI_HT_SLAVE1_OFFS;
- } while (last_unitid != next_unitid );
+ } while (last_unitid != next_unitid);
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
out:
@@ -438,7 +438,7 @@ out:
end_of_chain: ;
#if CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20
- if (offset_unitid && (ht_dev_num>1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used ) {
+ if (offset_unitid && (ht_dev_num > 1) && (real_last_unitid != CONFIG_HT_CHAIN_END_UNITID_BASE) && !end_used) {
uint16_t flags;
flags = pci_read_config16(PCI_DEV(bus,real_last_unitid,0), real_last_pos + PCI_CAP_FLAGS);
flags &= ~0x1f;
@@ -448,7 +448,7 @@ end_of_chain: ;
#if CONFIG_RAMINIT_SYSINFO
// Here need to change the dev in the array
int i;
- for (i=0;i<sysinfo->link_pair_num;i++)
+ for (i = 0; i < sysinfo->link_pair_num; i++)
{
struct link_pair_st *link_pair = &sysinfo->link_pair[i];
if (link_pair->udev == PCI_DEV(bus, real_last_unitid, 0)) {
@@ -514,9 +514,9 @@ static int optimize_link_read_pointer(uint8_t node, uint8_t linkn, uint8_t linkt
link_type = dword & 0xff;
- if ( (link_type & 7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+ if ((link_type & 7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/
dword_old = dword = pci_read_config32(PCI_DEV(0,0x18+node,3), 0xdc);
- dword &= ~( 0xff<<(linkn *8) );
+ dword &= ~(0xff<<(linkn *8));
dword |= val << (linkn *8);
if (dword != dword_old) {
@@ -551,10 +551,10 @@ static int optimize_link_read_pointers_chain(uint8_t ht_c_num)
devn = offset_unit_id(i == 0) ? CONFIG_HT_CHAIN_UNITID_BASE : 1;
- reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
- if ( (reg & 0xffff) == PCI_VENDOR_ID_AMD) {
+ reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); // ? the chain dev maybe offseted
+ if ((reg & 0xffff) == PCI_VENDOR_ID_AMD) {
val = 0x25;
- } else if ( (reg & 0xffff) == PCI_VENDOR_ID_NVIDIA ) {
+ } else if ((reg & 0xffff) == PCI_VENDOR_ID_NVIDIA) {
val = 0x25;//???
} else {
continue;
@@ -581,9 +581,9 @@ static int set_ht_link_buffer_count(uint8_t node, uint8_t linkn, uint8_t linkt,
dword = pci_read_config32(dev, regpos);
link_type = dword & 0xff;
- if ( (link_type & 0x7) == linkt ) { /* Coherent Link only linkt = 3, ncoherent = 7*/
+ if ((link_type & 0x7) == linkt) { /* Coherent Link only linkt = 3, ncoherent = 7*/
regpos = 0x90 + (linkn * 0x20);
- dword = pci_read_config32(dev, regpos );
+ dword = pci_read_config32(dev, regpos);
if (dword != val) {
pci_write_config32(dev, regpos, val);
@@ -615,8 +615,8 @@ static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid,
busn = (reg & 0xff0000)>>16; //busn
for (devn = 0; devn < 0x20; devn++) {
- reg = pci_read_config32( PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
- if ( (reg & 0xffff) == vendorid ) {
+ reg = pci_read_config32(PCI_DEV(busn, devn, 0), PCI_VENDOR_ID); //1?
+ if ((reg & 0xffff) == vendorid) {
reset_needed |= set_ht_link_buffer_count(nodeid, linkn, 0x07,val);
break;
}
@@ -659,14 +659,14 @@ static int ht_setup_chains(uint8_t ht_c_num)
reg = pci_read_config32(PCI_DEV(0,0x18,1), 0xe0 + i * 4);
//We need setup 0x94, 0xb4, and 0xd4 according to the reg
- devpos = ((reg & 0xf0)>>4)+0x18; // nodeid; it will decide 0x18 or 0x19
- regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n; it will decide 0x94 or 0xb4, 0x0xd4;
+ devpos = ((reg & 0xf0)>>4)+0x18; // nodeid;it will decide 0x18 or 0x19
+ regpos = ((reg & 0xf00)>>8) * 0x20 + 0x94; // link n;it will decide 0x94 or 0xb4, 0x0xd4;
busn = (reg & 0xff0000)>>16;
- dword = pci_read_config32( PCI_DEV(0, devpos, 0), regpos) ;
+ dword = pci_read_config32(PCI_DEV(0, devpos, 0), regpos) ;
dword &= ~(0xffff<<8);
dword |= (reg & 0xffff0000)>>8;
- pci_write_config32( PCI_DEV(0, devpos,0), regpos , dword);
+ pci_write_config32(PCI_DEV(0, devpos,0), regpos , dword);
/* Make certain the HT bus is not enumerated */
ht_collapse_previous_enumeration(busn, offset_unit_id(i == 0));
@@ -712,29 +712,29 @@ static int ht_setup_chains_x(void)
/* read PCI_DEV(0,0x18,0) 0x64 bit [8:9] to find out SbLink m */
reg = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x64);
- /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn=0x3f+1 */
- print_linkn_in("SBLink=", ((reg>>8) & 3) );
+ /* update PCI_DEV(0, 0x18, 1) 0xe0 to 0x05000m03, and next_busn = 0x3f+1 */
+ print_linkn_in("SBLink=", ((reg>>8) & 3));
#if CONFIG_RAMINIT_SYSINFO
sysinfo->sblk = (reg>>8) & 3;
sysinfo->sbbusn = 0;
sysinfo->nodes = nodes;
#endif
- tempreg = 3 | ( 0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
+ tempreg = 3 | (0<<4) | (((reg>>8) & 3)<<8) | (0<<16)| (0x3f<<24);
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0, tempreg);
- next_busn=0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
+ next_busn = 0x3f+1; /* 0 will be used ht chain with SB we need to keep SB in bus0 in auto stage*/
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
- tempreg = 0 | (((reg>>8) & 0x3) << 4 )| (0x3<<12); //limit
+ tempreg = 0 | (((reg>>8) & 0x3) << 4)| (0x3<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4, tempreg);
- tempreg = 3 | ( 3<<4) | (0<<12); //base
+ tempreg = 3 | (3<<4) | (0<<12); //base
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0, tempreg);
next_io_base = 0x3+0x1;
#endif
/* clean others */
- for (ht_c_num=1;ht_c_num<4; ht_c_num++) {
+ for (ht_c_num = 1;ht_c_num < 4; ht_c_num++) {
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4, 0);
#if CONFIG_K8_ALLOCATE_IO_RANGE
@@ -744,11 +744,11 @@ static int ht_setup_chains_x(void)
#endif
}
- for (nodeid=0; nodeid<nodes; nodeid++) {
+ for (nodeid = 0; nodeid < nodes; nodeid++) {
pci_devfn_t dev;
uint8_t linkn;
dev = PCI_DEV(0, 0x18+nodeid,0);
- for (linkn = 0; linkn<3; linkn++) {
+ for (linkn = 0; linkn < 3; linkn++) {
unsigned regpos;
regpos = 0x98 + 0x20 * linkn;
reg = pci_read_config32(dev, regpos);
@@ -756,7 +756,7 @@ static int ht_setup_chains_x(void)
print_linkn_in("NC node|link=", ((nodeid & 0xf)<<4)|(linkn & 0xf));
tempreg = 3 | (nodeid <<4) | (linkn<<8);
/*compare (temp & 0xffff), with (PCI(0, 0x18, 1) 0xe0 to 0xec & 0xfffff) */
- for (ht_c_num=0;ht_c_num<4; ht_c_num++) {
+ for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if (((reg & 0xffff) == (tempreg & 0xffff)) || ((reg & 0xffff) == 0x0000)) { /*we got it*/
break;
@@ -774,7 +774,7 @@ static int ht_setup_chains_x(void)
/* io range allocation */
tempreg = nodeid | (linkn<<4) | ((next_io_base+0x3)<<12); //limit
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC4 + ht_c_num * 8, tempreg);
- tempreg = 3 /*| ( 3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
+ tempreg = 3 /*| (3<<4)*/ | (next_io_base<<12); //base :ISA and VGA ?
pci_write_config32(PCI_DEV(0, 0x18, 1), 0xC0 + ht_c_num * 8, tempreg);
next_io_base += 0x3+0x1;
#endif
@@ -783,11 +783,11 @@ static int ht_setup_chains_x(void)
}
/*update 0xe0, 0xe4, 0xe8, 0xec from PCI_DEV(0, 0x18,1) to PCI_DEV(0, 0x19,1) to PCI_DEV(0, 0x1f,1);*/
- for (nodeid = 1; nodeid<nodes; nodeid++) {
+ for (nodeid = 1; nodeid < nodes; nodeid++) {
int i;
pci_devfn_t dev;
dev = PCI_DEV(0, 0x18+nodeid,1);
- for (i = 0; i< 4; i++) {
+ for (i = 0; i < 4; i++) {
unsigned regpos;
regpos = 0xe0 + i * 4;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
@@ -796,13 +796,13 @@ static int ht_setup_chains_x(void)
#if CONFIG_K8_ALLOCATE_IO_RANGE
/* io range allocation */
- for (i = 0; i< 4; i++) {
+ for (i = 0; i < 4; i++) {
unsigned regpos;
regpos = 0xc4 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
pci_write_config32(dev, regpos, reg);
}
- for (i = 0; i< 4; i++) {
+ for (i = 0; i < 4; i++) {
unsigned regpos;
regpos = 0xc0 + i * 8;
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), regpos);
@@ -812,8 +812,8 @@ static int ht_setup_chains_x(void)
}
/* recount ht_c_num*/
- uint8_t i=0;
- for (ht_c_num=0;ht_c_num<4; ht_c_num++) {
+ uint8_t i = 0;
+ for (ht_c_num = 0;ht_c_num < 4; ht_c_num++) {
reg = pci_read_config32(PCI_DEV(0, 0x18, 1), 0xe0 + ht_c_num * 4);
if (((reg & 0xf) != 0x0)) {
i++;
@@ -841,7 +841,7 @@ static int optimize_link_incoherent_ht(struct sys_info *sysinfo)
printk(BIOS_SPEW, "entering optimize_link_incoherent_ht\n");
printk(BIOS_SPEW, "sysinfo->link_pair_num=0x%x\n", link_pair_num);
- for (i=0; i< link_pair_num; i++) {
+ for (i = 0; i < link_pair_num; i++) {
struct link_pair_st *link_pair= &sysinfo->link_pair[i];
reset_needed |= ht_optimize_link(link_pair->udev, link_pair->upos, link_pair->uoffs, link_pair->dev, link_pair->pos, link_pair->offs);
printk(BIOS_SPEW, "after ht_optimize_link for link pair %d, reset_needed=0x%x\n", i, reset_needed);
diff --git a/src/northbridge/amd/amdk8/misc_control.c b/src/northbridge/amd/amdk8/misc_control.c
index a2b4651..3cbeb04 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -120,7 +120,7 @@ static void misc_control_init(struct device *dev)
*/
cmd = pci_read_config32(dev, 0x44);
cmd |= (1<<6) | (1<<25);
- pci_write_config32(dev, 0x44, cmd );
+ pci_write_config32(dev, 0x44, cmd);
#if !CONFIG_K8_REV_F_SUPPORT
if (is_cpu_pre_c0()) {
@@ -129,11 +129,11 @@ static void misc_control_init(struct device *dev)
*/
cmd = pci_read_config32(dev, 0x80);
cmd &= ~(1<<0);
- pci_write_config32(dev, 0x80, cmd );
+ pci_write_config32(dev, 0x80, cmd);
cmd = pci_read_config32(dev, 0x84);
cmd &= ~(1<<24);
cmd &= ~(1<<8);
- pci_write_config32(dev, 0x84, cmd );
+ pci_write_config32(dev, 0x84, cmd);
/* Errata 66
* Limit the number of downstream posted requests to 1
@@ -142,14 +142,14 @@ static void misc_control_init(struct device *dev)
if ((cmd & (3 << 0)) != 2) {
cmd &= ~(3<<0);
cmd |= (2<<0);
- pci_write_config32(dev, 0x70, cmd );
+ pci_write_config32(dev, 0x70, cmd);
needs_reset = 1;
}
cmd = pci_read_config32(dev, 0x7c);
if ((cmd & (3 << 4)) != 0) {
cmd &= ~(3<<4);
cmd |= (0<<4);
- pci_write_config32(dev, 0x7c, cmd );
+ pci_write_config32(dev, 0x7c, cmd);
needs_reset = 1;
}
/* Clock Power/Timing Low */
@@ -175,7 +175,7 @@ static void misc_control_init(struct device *dev)
}
cmd = pci_read_config32(dev, 0xd4);
if (cmd != cmd_ref) {
- pci_write_config32(dev, 0xd4, cmd_ref );
+ pci_write_config32(dev, 0xd4, cmd_ref);
needs_reset = 1; /* Needed? */
}
}
diff --git a/src/northbridge/amd/amdk8/northbridge.c b/src/northbridge/amd/amdk8/northbridge.c
index d80c565..fbd4da8 100644
--- a/src/northbridge/amd/amdk8/northbridge.c
+++ b/src/northbridge/amd/amdk8/northbridge.c
@@ -42,7 +42,7 @@ struct amdk8_sysconf_t sysconf;
#define MAX_FX_DEVS 8
static device_t __f0_dev[MAX_FX_DEVS];
static device_t __f1_dev[MAX_FX_DEVS];
-static unsigned fx_devs=0;
+static unsigned fx_devs = 0;
static void get_fx_devs(void)
{
@@ -178,7 +178,7 @@ static void amdk8_scan_chain(struct bus *link)
config_busses &= 0x000fc88;
config_busses |=
(3 << 0) | /* rw enable, no device compare */
- (( nodeid & 7) << 4) |
+ ((nodeid & 7) << 4) |
((link->link_num & 3) << 8) |
((link->secondary) << 16) |
(0xff << 24);
@@ -489,8 +489,8 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d link bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
- if ((vga_pri->bus->secondary >= link->secondary ) &&
- (vga_pri->bus->secondary <= link->subordinate )
+ if ((vga_pri->bus->secondary >= link->secondary) &&
+ (vga_pri->bus->secondary <= link->subordinate)
)
#endif
break;
@@ -505,7 +505,7 @@ static void amdk8_create_vga_resource(device_t dev, unsigned nodeid)
/* allocate a temp resource for the legacy VGA buffer */
resource = new_resource(dev, IOINDEX(4, link->link_num));
- if (!resource){
+ if (!resource) {
printk(BIOS_DEBUG, "VGA: %s out of resources.\n", dev_path(dev));
return;
}
@@ -697,7 +697,7 @@ static struct hw_mem_hole_info get_hw_mem_hole_info(void)
*/
if (mem_hole.node_id==-1) {
u32 limitk_pri = 0;
- for (i=0; i<8; i++) {
+ for (i = 0; i < 8; i++) {
u32 base, limit;
unsigned base_k, limit_k;
base = f1_read_config32(0x40 + (i << 3));
@@ -738,7 +738,7 @@ static void disable_hoist_memory(unsigned long hole_startk, int node_id)
hole_sizek = (4*1024*1024) - hole_startk;
- for (i=7;i>node_id;i--) {
+ for (i = 7; i > node_id; i--) {
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
@@ -775,7 +775,7 @@ static u32 hoist_memory(unsigned long hole_startk, int node_id)
carry_over = (4*1024*1024) - hole_startk;
- for (i=7;i>node_id;i--) {
+ for (i = 7; i > node_id; i--) {
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
@@ -970,11 +970,11 @@ static void amdk8_domain_set_resources(device_t dev)
#endif
/* See if I need to split the region to accommodate pci memory space */
- if ( (basek < 4*1024*1024 ) && (limitk > mmio_basek) ) {
+ if ((basek < 4*1024*1024) && (limitk > mmio_basek)) {
if (basek <= mmio_basek) {
unsigned pre_sizek;
pre_sizek = mmio_basek - basek;
- if (pre_sizek>0) {
+ if (pre_sizek > 0) {
ram_resource(dev, (idx | i), basek, pre_sizek);
idx += 0x10;
sizek -= pre_sizek;
@@ -984,7 +984,7 @@ static void amdk8_domain_set_resources(device_t dev)
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
if (reset_memhole)
#if !CONFIG_K8_REV_F_SUPPORT
- if (!is_cpu_pre_e0() )
+ if (!is_cpu_pre_e0())
#endif
sizek += hoist_memory(mmio_basek,i);
#endif
@@ -1210,7 +1210,7 @@ static void cpu_bus_scan(device_t dev)
// ----> you can mixed single core e0 and dual core e0 at any sequence
// That is the typical case
- if (j == 0 ){
+ if (j == 0) {
#if !CONFIG_K8_REV_F_SUPPORT
e0_later_single_core = is_e0_later_in_bsp(i); // single core
#else
@@ -1222,10 +1222,10 @@ static void cpu_bus_scan(device_t dev)
if (e0_later_single_core) {
printk(BIOS_DEBUG, "\tFound Rev E or Rev F later single core\n");
- j=1;
+ j = 1;
}
- if (siblings > j ) {
+ if (siblings > j) {
}
else {
siblings = j;
@@ -1243,7 +1243,7 @@ static void cpu_bus_scan(device_t dev)
jj = siblings;
}
- for (j = 0; j <=jj; j++ ) {
+ for (j = 0; j <= jj; j++) {
u32 apic_id = i * (nb_cfg_54?(siblings+1):1) + j * (nb_cfg_54?1:8);
if (sysconf.enabled_apic_ext_id) {
if (apic_id != 0 || sysconf.lift_bsp_apicid) {
diff --git a/src/northbridge/amd/amdk8/raminit.c b/src/northbridge/amd/amdk8/raminit.c
index aab9fa7..7fbe4ec 100644
--- a/src/northbridge/amd/amdk8/raminit.c
+++ b/src/northbridge/amd/amdk8/raminit.c
@@ -645,7 +645,7 @@ static struct dimm_size spd_get_dimm_size(unsigned device)
value = spd_read_byte(device, 5); /* number of physical banks */
if (value < 0) goto hw_err;
if (value == 1) goto out;
- if ((value != 2) && (value != 4 )) {
+ if ((value != 2) && (value != 4)) {
goto val_err;
}
#if CONFIG_QRANK_DIMM_SUPPORT
@@ -760,7 +760,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map &= ~(0xf << (index * 4));
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz.rank == 4) {
- map &= ~(0xf << ( (index + 2) * 4));
+ map &= ~(0xf << ((index + 2) * 4));
}
#endif
@@ -771,7 +771,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map |= (sz.side1 - (25 + 3)) << (index *4);
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz.rank == 4) {
- map |= (sz.side1 - (25 + 3)) << ( (index + 2) * 4);
+ map |= (sz.side1 - (25 + 3)) << ((index + 2) * 4);
}
#endif
}
@@ -779,7 +779,7 @@ static void set_dimm_map(const struct mem_controller *ctrl, struct dimm_size sz,
map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << (index*4);
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz.rank == 4) {
- map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ( (index + 2) * 4);
+ map |= cs_map_aa[(sz.rows - 12) * 5 + (sz.col - 8) ] << ((index + 2) * 4);
}
#endif
}
@@ -824,7 +824,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
limit = (limit_k << 2);
limit &= 0xffff0000;
limit -= 0x00010000;
- limit |= ( 0 << 8) | (node_id << 0);
+ limit |= (0 << 8) | (node_id << 0);
base = (base_k << 2);
base &= 0xffff0000;
base |= (0 << 8) | (1<<1) | (1<<0);
@@ -940,8 +940,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
}
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
- cs_mode =( value >> ((index>>1)*4)) & 0xf;
- if (cs_mode == 0 ) continue;
+ cs_mode =(value >> ((index>>1)*4)) & 0xf;
+ if (cs_mode == 0) continue;
if (common_cs_mode == 0) {
common_cs_mode = cs_mode;
}
@@ -960,7 +960,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
}
/* Find the bits of csbase that we need to interleave on */
- if (is_cpu_pre_d0()){
+ if (is_cpu_pre_d0()) {
csbase_inc = 1 << csbase_low_shift[common_cs_mode];
if (is_dual_channel(ctrl)) {
/* Also we run out of address mask bits if we try and interleave 8 4GB dimms */
@@ -974,8 +974,8 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl)
else {
csbase_inc = 1 << csbase_low_d0_shift[common_cs_mode];
if (is_dual_channel(ctrl)) {
- if ( (bits==3) && (common_cs_mode > 8)) {
-// printk(BIOS_DEBUG, "8 cs_mode>8 chip selects cannot be interleaved\n");
+ if ((bits == 3) && (common_cs_mode > 8)) {
+// printk(BIOS_DEBUG, "8 cs_mode > 8 chip selects cannot be interleaved\n");
return 0;
}
csbase_inc <<=1;
@@ -1223,7 +1223,7 @@ static long spd_enable_2channels(const struct mem_controller *ctrl, long dimm_ma
5, /* *Physical Banks */
6, /* *Module Data Width low */
7, /* *Module Data Width high */
- 9, /* *Cycle time at highest CAS Latency CL=X */
+ 9, /* *Cycle time at highest CAS Latency CL = X */
11, /* *SDRAM Type */
13, /* *SDRAM Width */
17, /* *Logical Banks */
@@ -1390,7 +1390,7 @@ static int spd_dimm_loading_socket(const struct mem_controller *ctrl, long dimm_
/*
Following table comes directly from BKDG (unbuffered DIMM support)
- [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1=present 0=empty
+ [Y][X] Y = ch0_0, ch1_0, ch0_1, ch1_1 1 = present 0 = empty
X uses same layout but 1 means double rank 0 is single rank/empty
Following tables come from BKDG the ch{0_0,1_0,0_1,1_1} maps to
@@ -1674,7 +1674,7 @@ static struct spd_set_memclk_result spd_set_memclk(const struct mem_controller *
#if 0
/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed result in odd clock divisor, by selecting the next lowest memory speed, required only at DDR400 and higher speeds with certain DIMM loadings ---- cheating???*/
if (!is_cpu_pre_e0()) {
- if (min_cycle_time==0x50) {
+ if (min_cycle_time == 0x50) {
value |= 1<<31;
}
}
@@ -1927,7 +1927,7 @@ static int update_dimm_x4(const struct mem_controller *ctrl, const struct mem_pa
dimm = 1<<(DCL_x4DIMM_SHIFT+i);
#if CONFIG_QRANK_DIMM_SUPPORT
- if (rank==4) {
+ if (rank == 4) {
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}
#endif
@@ -2239,7 +2239,7 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
carry_over = (4*1024*1024) - hole_startk;
- for (ii=controllers - 1;ii>i;ii--) {
+ for (ii = controllers - 1; ii > i; ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
@@ -2294,7 +2294,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
* we need to decrease it.
*/
uint32_t basek_pri;
- for (i=0; i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -2315,7 +2315,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
printk(BIOS_SPEW, "Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
#endif
/* Find node number that needs the memory hole configured */
- for (i=0; i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -2480,7 +2480,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
2. check cs_base lo is 0, node 0 f2 0x40,,,,, if any one is not using lo is CS_BASE, get out
3. check if other node is the same as node 0 about f2 0x40,,,,, otherwise get out
4. if all ready enable node_interleaving in f1 0x40..... of every node
- 5. for node interleaving we need to set mem hole to every node ( need recalcute hole offset in f0 for every node)
+ 5. for node interleaving we need to set mem hole to every node (need recalcute hole offset in f0 for every node)
*/
}
@@ -2495,7 +2495,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
int i;
int j;
struct mem_controller *ctrl;
- for (i=0;i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
@@ -2505,7 +2505,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
if (spd_addr == (void *)0) continue;
- for (j=0;j<DIMM_SOCKETS;j++) {
+ for (j = 0; j < DIMM_SOCKETS; j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c
index 67f3433..4ef621c 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -222,7 +222,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
/* DRAM Control Register
* F2:0x78
- * [ 3: 0] RdPtrInit ( Read Pointer Initial Value)
+ * [ 3: 0] RdPtrInit (Read Pointer Initial Value)
* 0x03-0x00: reserved
* [ 6: 4] RdPadRcvFifoDly (Read Delay from Pad Receive FIFO)
* 000 = reserved
@@ -361,7 +361,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 01 = 3 bus clocks
* 10 = 4 bus clocks
* 11 = 5 bus clocks
- * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel A,
+ * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel A,
* BIOS should set it to reduce the power consumption)
* Bit F(1207) M2 Package S1g1 Package
* 0 N/A MA1_CLK1 N/A
@@ -400,22 +400,22 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 10 = 2 bus clocks
* 11 = 3 bus clocks
* [13:12] Twrwr (Write to Write Timing)
- * 00 = 1 bus clocks ( 0 idle cycle on the bus)
- * 01 = 2 bus clocks ( 1 idle cycle on the bus)
- * 10 = 3 bus clocks ( 2 idle cycles on the bus)
+ * 00 = 1 bus clocks (0 idle cycle on the bus)
+ * 01 = 2 bus clocks (1 idle cycle on the bus)
+ * 10 = 3 bus clocks (2 idle cycles on the bus)
* 11 = Reserved
- * [15:14] Trdrd ( Read to Read Timing)
- * 00 = 2 bus clocks ( 1 idle cycle on the bus)
- * 01 = 3 bus clocks ( 2 idle cycles on the bus)
- * 10 = 4 bus clocks ( 3 idle cycles on the bus)
- * 11 = 5 bus clocks ( 4 idle cycles on the bus)
+ * [15:14] Trdrd (Read to Read Timing)
+ * 00 = 2 bus clocks (1 idle cycle on the bus)
+ * 01 = 3 bus clocks (2 idle cycles on the bus)
+ * 10 = 4 bus clocks (3 idle cycles on the bus)
+ * 11 = 5 bus clocks (4 idle cycles on the bus)
* [17:16] Tref (Refresh Rate)
* 00 = Undefined behavior
* 01 = Reserved
* 10 = Refresh interval of 7.8 microseconds
* 11 = Refresh interval of 3.9 microseconds
* [19:18] Reserved
- * [22:20] Trfc0 ( Auto-Refresh Row Cycle Time for the Logical DIMM0,
+ * [22:20] Trfc0 (Auto-Refresh Row Cycle Time for the Logical DIMM0,
* based on DRAM density and speed)
* 000 = 75 ns (all speeds, 256Mbit)
* 001 = 105 ns (all speeds, 512Mbit)
@@ -425,11 +425,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 101 = reserved
* 110 = reserved
* 111 = reserved
- * [25:23] Trfc1 ( Auto-Refresh Row Cycle Time for the Logical DIMM1,
+ * [25:23] Trfc1 (Auto-Refresh Row Cycle Time for the Logical DIMM1,
* based on DRAM density and speed)
- * [28:26] Trfc2 ( Auto-Refresh Row Cycle Time for the Logical DIMM2,
+ * [28:26] Trfc2 (Auto-Refresh Row Cycle Time for the Logical DIMM2,
* based on DRAM density and speed)
- * [31:29] Trfc3 ( Auto-Refresh Row Cycle Time for the Logical DIMM3,
+ * [31:29] Trfc3 (Auto-Refresh Row Cycle Time for the Logical DIMM3,
* based on DRAM density and speed)
*/
PCI_ADDR(0, 0x18, 2, 0x8c), 0x000c008f, (2 << 16)|(1 << 8),
@@ -438,7 +438,7 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* [ 0: 0] InitDram (Initialize DRAM)
* 1 = write 1 cause DRAM controller to execute the DRAM
* initialization, when done it read to 0
- * [ 1: 1] ExitSelfRef ( Exit Self Refresh Command )
+ * [ 1: 1] ExitSelfRef (Exit Self Refresh Command)
* 1 = write 1 causes the DRAM controller to bring the DRAMs out
* for self refresh mode
* [ 3: 2] Reserved
@@ -448,19 +448,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 10 = 150 ohms
* 11 = 50 ohms
* [ 6: 6] Reserved
- * [ 7: 7] DramDrvWeak ( DRAM Drivers Weak Mode)
+ * [ 7: 7] DramDrvWeak (DRAM Drivers Weak Mode)
* 0 = Normal drive strength mode.
* 1 = Weak drive strength mode
* [ 8: 8] ParEn (Parity Enable)
* 1 = Enable address parity computation output, PAR,
* and enables the parity error input, ERR
* [ 9: 9] SelfRefRateEn (Faster Self Refresh Rate Enable)
- * 1 = Enable high temperature ( two times normal )
+ * 1 = Enable high temperature (two times normal)
* self refresh rate
- * [10:10] BurstLength32 ( DRAM Burst Length Set for 32 Bytes)
+ * [10:10] BurstLength32 (DRAM Burst Length Set for 32 Bytes)
* 0 = 64-byte mode
* 1 = 32-byte mode
- * [11:11] Width128 ( Width of DRAM interface)
+ * [11:11] Width128 (Width of DRAM interface)
* 0 = the controller DRAM interface is 64-bits wide
* 1 = the controller DRAM interface is 128-bits wide
* [12:12] X4Dimm (DIMM 0 is x4)
@@ -469,19 +469,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* [15:15] X4Dimm (DIMM 3 is x4)
* 0 = DIMM is not x4
* 1 = x4 DIMM present
- * [16:16] UnBuffDimm ( Unbuffered DIMMs)
+ * [16:16] UnBuffDimm (Unbuffered DIMMs)
* 0 = Buffered DIMMs
* 1 = Unbuffered DIMMs
* [18:17] Reserved
- * [19:19] DimmEccEn ( DIMM ECC Enable )
+ * [19:19] DimmEccEn (DIMM ECC Enable)
* 1 = ECC checking is being enabled for all DIMMs on the DRAM
- * controller ( Through F3 0x44[EccEn])
+ * controller (Through F3 0x44[EccEn])
* [31:20] Reserved
*/
PCI_ADDR(0, 0x18, 2, 0x90), 0xfff6004c, 0x00000010,
/* DRAM Config High Register
* F2:0x94
- * [ 0: 2] MemClkFreq ( Memory Clock Frequency)
+ * [ 0: 2] MemClkFreq (Memory Clock Frequency)
* 000 = 200MHz
* 001 = 266MHz
* 010 = 333MHz
@@ -490,25 +490,25 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* [ 3: 3] MemClkFreqVal (Memory Clock Frequency Valid)
* 1 = BIOS need to set the bit when setting up MemClkFreq to
* the proper value
- * [ 7: 4] MaxAsyncLat ( Maximum Asynchronous Latency)
+ * [ 7: 4] MaxAsyncLat (Maximum Asynchronous Latency)
* 0000 = 0 ns
* ...
* 1111 = 15 ns
* [11: 8] Reserved
- * [12:12] RDqsEn ( Read DQS Enable) This bit is only be set if x8
+ * [12:12] RDqsEn (Read DQS Enable) This bit is only be set if x8
* registered DIMMs are present in the system
* 0 = DM pins function as data mask pins
* 1 = DM pins function as read DQS pins
* [13:13] Reserved
- * [14:14] DisDramInterface ( Disable the DRAM interface ) When this bit
+ * [14:14] DisDramInterface (Disable the DRAM interface) When this bit
* is set, the DRAM controller is disabled, and interface in low power
* state
* 0 = Enabled (default)
* 1 = Disabled
- * [15:15] PowerDownEn ( Power Down Mode Enable )
+ * [15:15] PowerDownEn (Power Down Mode Enable)
* 0 = Disabled (default)
* 1 = Enabled
- * [16:16] PowerDown ( Power Down Mode )
+ * [16:16] PowerDown (Power Down Mode)
* 0 = Channel CKE Control
* 1 = Chip Select CKE Control
* [17:17] FourRankSODimm (Four Rank SO-DIMM)
@@ -526,17 +526,17 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* i.e., these signals are driven for two MEMCLK cycles
* rather than one
* [21:21] Reserved
- * [22:22] BankSwizzleMode ( Bank Swizzle Mode),
+ * [22:22] BankSwizzleMode (Bank Swizzle Mode),
* 0 = Disabled (default)
* 1 = Enabled
* [23:23] Reserved
- * [27:24] DcqBypassMax ( DRAM Controller Queue Bypass Maximum)
+ * [27:24] DcqBypassMax (DRAM Controller Queue Bypass Maximum)
* 0000 = No bypass; the oldest request is never bypassed
* 0001 = The oldest request may be bypassed no more than 1 time
* ...
* 1111 = The oldest request may be bypassed no more than 15\
* times
- * [31:28] FourActWindow ( Four Bank Activate Window) , not more than
+ * [31:28] FourActWindow (Four Bank Activate Window) , not more than
* 4 banks in a 8 bank device are activated
* 0000 = No tFAW window restriction
* 0001 = 8 MEMCLK cycles
@@ -552,11 +552,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* when set, this bit indicates that the memory clear function
* is complete. Only clear by reset. BIOS should not write or
* read the DRAM until this bit is set by hardware
- * [ 1: 1] DisableJitter ( Disable Jitter)
+ * [ 1: 1] DisableJitter (Disable Jitter)
* When set the DDR compensation circuit will not change the
* values unless the change is more than one step from the
* current value
- * [ 3: 2] RdWrQByp ( Read/Write Queue Bypass Count)
+ * [ 3: 2] RdWrQByp (Read/Write Queue Bypass Count)
* 00 = 2
* 01 = 4
* 10 = 8
@@ -565,11 +565,11 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 1 When bit enables support for mismatched DIMMs when using
* 128-bit DRAM interface, the Width128 no effect, only for
* AM2 and s1g1
- * [ 5: 5] DCC_EN ( Dynamic Idle Cycle Counter Enable)
+ * [ 5: 5] DCC_EN (Dynamic Idle Cycle Counter Enable)
* When set to 1, indicates that each entry in the page tables
* dynamically adjusts the idle cycle limit based on page
* Conflict/Page Miss (PC/PM) traffic
- * [ 8: 6] ILD_lmt ( Idle Cycle Limit)
+ * [ 8: 6] ILD_lmt (Idle Cycle Limit)
* 000 = 0 cycles
* 001 = 4 cycles
* 010 = 8 cycles
@@ -578,16 +578,16 @@ static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_in
* 101 = 64 cycles
* 110 = 128 cycles
* 111 = 256 cycles
- * [ 9: 9] DramEnabled ( DRAM Enabled)
+ * [ 9: 9] DramEnabled (DRAM Enabled)
* When Set, this bit indicates that the DRAM is enabled, this
* bit is set by hardware after DRAM initialization or on an exit
* from self refresh. The DRAM controller is initialized after the
- * hardware-controlled initialization process ( initiated by the
+ * hardware-controlled initialization process (initiated by the
* F2 0x90[DramInit]) completes or when the BIOS-controlled
* initialization process completes (F2 0x7c(EnDramInit] is
* written from 1 to 0)
* [23:10] Reserved
- * [31:24] MemClkDis ( Disable the MEMCLK outputs for DRAM channel B,
+ * [31:24] MemClkDis (Disable the MEMCLK outputs for DRAM channel B,
* BIOS should set it to reduce the power consumption)
* Bit F(1207) M2 Package S1g1 Package
* 0 N/A MA1_CLK1 N/A
@@ -785,7 +785,7 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
rank == 4 two side , and four ranks total
Some one side two ranks, because of stacked
*/
- if ((value != 1) && (value != 2) && (value != 4 )) {
+ if ((value != 1) && (value != 2) && (value != 4)) {
goto val_err;
}
sz->rank = value;
@@ -797,9 +797,9 @@ static void spd_get_dimm_size(unsigned device, struct dimm_size *sz)
if (value < 0) goto hw_err;
value &= 0xff;
value = log2(value);
- if (value <=4 ) value += 8; // add back to 1G to high
+ if (value <= 4) value += 8; // add back to 1G to high
value += (27-5); // make 128MB to the real lines
- if ( value != (sz->per_rank)) {
+ if (value != (sz->per_rank)) {
printk(BIOS_ERR, "Bad RANK Size --\n");
goto val_err;
}
@@ -836,12 +836,12 @@ static void set_dimm_size(const struct mem_controller *ctrl,
/* Make certain side1 of the dimm is at least 128MB */
if (sz->per_rank >= 27) {
- base0 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
+ base0 = (1 << ((sz->per_rank - 27) + 19)) | 1;
}
/* Make certain side2 of the dimm is at least 128MB */
if (sz->rank > 1) { // 2 ranks or 4 ranks
- base1 = (1 << ((sz->per_rank - 27 ) + 19)) | 1;
+ base1 = (1 << ((sz->per_rank - 27) + 19)) | 1;
}
/* Double the size if we are using dual channel memory */
@@ -954,7 +954,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
map &= ~(0xf << (index * 4));
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
- map &= ~(0xf << ( (index + 2) * 4));
+ map &= ~(0xf << ((index + 2) * 4));
}
#endif
@@ -965,7 +965,7 @@ static void set_dimm_cs_map(const struct mem_controller *ctrl,
map |= temp_map << (index*4);
#if CONFIG_QRANK_DIMM_SUPPORT
if (sz->rank == 4) {
- map |= temp_map << ( (index + 2) * 4);
+ map |= temp_map << ((index + 2) * 4);
}
#endif
}
@@ -1018,7 +1018,7 @@ static void route_dram_accesses(const struct mem_controller *ctrl,
limit = (limit_k << 2);
limit &= 0xffff0000;
limit -= 0x00010000;
- limit |= ( 0 << 8) | (node_id << 0);
+ limit |= (0 << 8) | (node_id << 0);
base = (base_k << 2);
base &= 0xffff0000;
base |= (0 << 8) | (1<<1) | (1<<0);
@@ -1136,7 +1136,7 @@ static unsigned long interleave_chip_selects(const struct mem_controller *ctrl,
}
value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
- cs_mode =( value >> ((index>>1)*4)) & 0xf;
+ cs_mode =(value >> ((index>>1)*4)) & 0xf;
if (common_cs_mode == 0xff) {
common_cs_mode = cs_mode;
}
@@ -1351,8 +1351,8 @@ static long spd_handle_unbuffered_dimms(const struct mem_controller *ctrl,
if (is_opteron(ctrl)) {
#if 0
- if ( registered != (meminfo->dimm_mask & ((1<<DIMM_SOCKETS)-1)) ) {
- meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS) ); //disable unbuffered dimm
+ if (registered != (meminfo->dimm_mask & ((1 << DIMM_SOCKETS)-1))) {
+ meminfo->dimm_mask &= (registered | (registered << DIMM_SOCKETS)); //disable unbuffered dimm
// die("Mixed buffered and registered dimms not supported");
}
//By yhlu for debug M2, s1g1 can do dual channel, but it use unbuffer DIMM
@@ -1647,7 +1647,7 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
/* Check for FID control support */
struct cpuid_result cpuid1;
cpuid1 = cpuid(0x80000007);
- if ( cpuid1.edx & 0x02 ) {
+ if (cpuid1.edx & 0x02) {
/* Use current FID */
unsigned fid_cur;
msr = rdmsr(0xc0010042);
@@ -1663,9 +1663,9 @@ static uint8_t get_exact_divisor(int i, uint8_t divisor)
index = fid_start>>25;
}
- if (index>12) return divisor;
+ if (index > 12) return divisor;
- if (i>3) return divisor;
+ if (i > 3) return divisor;
return dv_a[index * 4+i];
@@ -1748,7 +1748,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig
printk_raminit("\t\tvalue2: %08x\n", value);
/* Only increase the latency if we decrease the clock */
- if (value >= *min_cycle_time ) {
+ if (value >= *min_cycle_time) {
if (value < new_cycle_time) {
new_cycle_time = value;
new_latency = latency;
@@ -1763,7 +1763,7 @@ static int find_optimum_spd_latency(u32 spd_device, unsigned *min_latency, unsig
}
- if (new_latency > 6){
+ if (new_latency > 6) {
return 1;
}
@@ -2052,7 +2052,7 @@ static int update_dimm_Trfc(const struct mem_controller *ctrl, const struct mem_
static int update_dimm_TT_1_4(const struct mem_controller *ctrl, const struct mem_param *param, int i, long dimm_mask,
unsigned TT_REG,
- unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX )
+ unsigned SPD_TT, unsigned TT_SHIFT, unsigned TT_MASK, unsigned TT_BASE, unsigned TT_MIN, unsigned TT_MAX)
{
unsigned clocks, old_clocks;
uint32_t dtl;
@@ -2181,7 +2181,7 @@ static int update_dimm_Tref(const struct mem_controller *ctrl,
value = spd_read_byte(spd_device, SPD_TREF); // 0: 15.625us, 1: 3.9us 2: 7.8 us....
if (value < 0) return -1;
- if (value == 1 ) {
+ if (value == 1) {
value = 3;
} else {
value = 2;
@@ -2267,7 +2267,7 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
mask_single_rank |= 1<<i;
}
- if (meminfo->sz[i].col==10) {
+ if (meminfo->sz[i].col == 10) {
mask_page_1k |= 1<<i;
}
@@ -2278,17 +2278,17 @@ static uint32_t get_extra_dimm_mask(const struct mem_controller *ctrl,
rank = meminfo->sz[i].rank;
#endif
- if (value==4) {
+ if (value == 4) {
mask_x4 |= (1<<i);
#if CONFIG_QRANK_DIMM_SUPPORT
- if (rank==4) {
+ if (rank == 4) {
mask_x4 |= 1<<(i+2);
}
#endif
- } else if (value==16) {
+ } else if (value == 16) {
mask_x16 |= (1<<i);
#if CONFIG_QRANK_DIMM_SUPPORT
- if (rank==4) {
+ if (rank == 4) {
mask_x16 |= 1<<(i+2);
}
#endif
@@ -2340,7 +2340,7 @@ static void set_DramTerm(const struct mem_controller *ctrl,
if (param->divisor == 100) { //DDR2 800
if (meminfo->is_Width128) {
- if (count_ones(meminfo->dimm_mask & 0x0f)==2) {
+ if (count_ones(meminfo->dimm_mask & 0x0f) == 2) {
odt = 3; //50 ohms
}
}
@@ -2503,7 +2503,7 @@ static void set_max_async_latency(const struct mem_controller *ctrl, const struc
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
-#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */
static void set_SlowAccessMode(const struct mem_controller *ctrl)
{
uint32_t dch;
@@ -2524,23 +2524,23 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
{
uint32_t dword;
uint32_t dwordx;
-#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */
unsigned SlowAccessMode = 0;
#endif
-#if CONFIG_DIMM_SUPPORT==0x0104 /* DDR2 and REG */
+#if CONFIG_DIMM_SUPPORT == 0x0104 /* DDR2 and REG */
long dimm_mask = meminfo->dimm_mask & 0x0f;
/* for REG DIMM */
dword = 0x00111222;
dwordx = 0x002f0000;
switch (meminfo->memclk_set) {
case DCH_MemClkFreq_266MHz:
- if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
+ if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
dwordx = 0x002f2700;
}
break;
case DCH_MemClkFreq_333MHz:
- if ( (dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
+ if ((dimm_mask == 0x03) || (dimm_mask == 0x02) || (dimm_mask == 0x01)) {
if ((meminfo->single_rank_mask & 0x03)!=0x03) { //any double rank there?
dwordx = 0x002f2f00;
}
@@ -2553,7 +2553,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
#endif
-#if CONFIG_DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
+#if CONFIG_DIMM_SUPPORT == 0x0204 /* DDR2 and SO-DIMM, S1G1 */
dword = 0x00111222;
dwordx = 0x002F2F00;
@@ -2593,7 +2593,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
}
#endif
-#if CONFIG_DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
+#if CONFIG_DIMM_SUPPORT == 0x0004 /* DDR2 and unbuffered */
long dimm_mask = meminfo->dimm_mask & 0x0f;
/* for UNBUF DIMM */
dword = 0x00111222;
@@ -2609,7 +2609,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
if (dimm_mask == 0x03) {
SlowAccessMode = 1;
dword = 0x00111322;
- if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
+ if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) {
switch (meminfo->single_rank_mask) {
case 0x03:
dwordx = 0x00002f00; //x8 single Rank
@@ -2620,14 +2620,14 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
default:
dwordx = 0x00372f00; //x8 single Rank and double Rank mixed
}
- } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
+ } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x01) && (meminfo->single_rank_mask == 0x01)) {
dwordx = 0x00382f00; //x8 Double Rank and x16 single Rank mixed
- } else if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
+ } else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x02) && (meminfo->single_rank_mask == 0x02)) {
dwordx = 0x00382f00; //x16 single Rank and x8 double Rank mixed
}
} else {
- if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
+ if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0x00) && ((meminfo->single_rank_mask == 0x01)||(meminfo->single_rank_mask == 0x02))) { //x8 single rank
dwordx = 0x002f2f00;
} else {
dwordx = 0x002b2f00;
@@ -2639,7 +2639,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
if (dimm_mask == 0x03) {
SlowAccessMode = 1;
dword = 0x00111322;
- if ((meminfo->x4_mask == 0 ) && (meminfo->x16_mask == 0)) {
+ if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)) {
switch (meminfo->single_rank_mask) {
case 0x03:
dwordx = 0x00302220; //x8 single Rank
@@ -2676,7 +2676,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
printk_raminit("\tAddr Timing= %08x\n", dwordx);
#endif
-#if (CONFIG_DIMM_SUPPORT & 0x0100)==0x0000 /* 2T mode only used for unbuffered DIMM */
+#if (CONFIG_DIMM_SUPPORT & 0x0100) == 0x0000 /* 2T mode only used for unbuffered DIMM */
if (SlowAccessMode) {
set_SlowAccessMode(ctrl);
}
@@ -2707,7 +2707,7 @@ static void set_misc_timing(const struct mem_controller *ctrl, struct mem_info *
static void set_RDqsEn(const struct mem_controller *ctrl,
const struct mem_param *param, struct mem_info *meminfo)
{
-#if CONFIG_CPU_SOCKET_TYPE==0x10
+#if CONFIG_CPU_SOCKET_TYPE == 0x10
//only need to set for reg and x8
uint32_t dch;
@@ -2749,7 +2749,7 @@ static long spd_set_dram_timing(const struct mem_controller *ctrl,
for (i = 0; i < DIMM_SOCKETS; i++) {
int rc;
if (!(meminfo->dimm_mask & (1 << i)) &&
- !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i))) ) {
+ !(meminfo->dimm_mask & (1 << (DIMM_SOCKETS + i)))) {
continue;
}
printk_raminit("spd_set_dram_timing dimm socket: %08x\n", i);
@@ -2911,17 +2911,17 @@ static uint32_t hoist_memory(int controllers, const struct mem_controller *ctrl,
carry_over = (4*1024*1024) - hole_startk;
- for (ii=controllers - 1;ii>i;ii--) {
+ for (ii = controllers - 1; ii > i; ii--) {
base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
- limit += (carry_over << 2 );
- base += (carry_over << 2 );
+ limit += (carry_over << 2);
+ base += (carry_over << 2);
for (j = 0; j < controllers; j++) {
pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit);
- pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base );
+ pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base);
}
}
limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
@@ -2966,7 +2966,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
/* We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some */
uint32_t basek_pri;
- for (i=0; i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base;
unsigned base_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -2985,7 +2985,7 @@ static void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl)
printk_raminit("Handling memory hole at 0x%08x (adjusted)\n", hole_startk);
#endif
/* find node index that need do set hole */
- for (i=0; i < controllers; i++) {
+ for (i = 0; i < controllers; i++) {
uint32_t base, limit;
unsigned base_k, limit_k;
base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
@@ -3038,7 +3038,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
/* if no memory installed, disabled the interface */
- if (sysinfo->meminfo[i].dimm_mask==0x00){
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) {
dch |= DCH_DisDramInterface;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
@@ -3046,7 +3046,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
dch |= DCH_MemClkFreqVal;
pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
/* address timing and Output driver comp Control */
- set_misc_timing(ctrl+i, sysinfo->meminfo+i );
+ set_misc_timing(ctrl+i, sysinfo->meminfo+i);
}
}
@@ -3108,7 +3108,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
if (!sysinfo->ctrl_present[ i ])
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "Initializing memory: ");
int loops = 0;
@@ -3127,7 +3127,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
/* Wait until it is safe to touch memory */
do {
dcm = pci_read_config32(ctrl[i].f2, DRAM_CTRL_MISC);
- } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/ );
+ } while (((dcm & DCM_MemClrStatus) == 0) /* || ((dcm & DCM_DramEnabled) == 0)*/);
#if K8_REV_F_SUPPORT_F0_F1_WORKAROUND == 1
if (cpu_f0_f1[i]) {
@@ -3136,7 +3136,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
print_debug_dqs_tsc("\nbegin tsc0", i, tsc0[i].hi, tsc0[i].lo, 2);
print_debug_dqs_tsc("end tsc ", i, tsc.hi, tsc.lo, 2);
- if (tsc.lo<tsc0[i].lo) {
+ if (tsc.lo < tsc0[i].lo) {
tsc.hi--;
}
tsc.lo -= tsc0[i].lo;
@@ -3176,7 +3176,7 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl,
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00)
+ if (sysinfo->meminfo[i].dimm_mask == 0x00)
continue;
sysinfo->mem_trained[i] = 0x80; // mem need to be trained
@@ -3226,7 +3226,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
int i;
int j;
struct mem_controller *ctrl;
- for (i=0;i<controllers; i++) {
+ for (i = 0; i < controllers; i++) {
ctrl = &ctrl_a[i];
ctrl->node_id = i;
ctrl->f0 = PCI_DEV(0, 0x18+i, 0);
@@ -3236,7 +3236,7 @@ void fill_mem_ctrl(int controllers, struct mem_controller *ctrl_a,
if (spd_addr == (void *)0) continue;
- for (j=0;j<DIMM_SOCKETS;j++) {
+ for (j = 0; j < DIMM_SOCKETS; j++) {
ctrl->channel0[j] = spd_addr[(i*2+0)*DIMM_SOCKETS + j];
ctrl->channel1[j] = spd_addr[(i*2+1)*DIMM_SOCKETS + j];
}
diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c
index 9f0b8db..3a76894 100644
--- a/src/northbridge/amd/amdk8/raminit_f_dqs.c
+++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c
@@ -58,10 +58,10 @@ static void fill_mem_cs_sysinfo(unsigned nodeid, const struct mem_controller *ct
{
int i;
- sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid<<3));
+ sysinfo->mem_base[nodeid] = pci_read_config32(ctrl->f1, 0x40 + (nodeid << 3));
- for (i=0;i<8; i++) {
- sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i<<2));
+ for (i = 0; i < 8; i++) {
+ sysinfo->cs_base[nodeid*8+i] = pci_read_config32(ctrl->f2, 0x40 + (i << 2));
}
sysinfo->hole_reg[nodeid] = pci_read_config32(ctrl->f1, 0xf0);
@@ -90,9 +90,9 @@ static unsigned Get_MCTSysAddr(const struct mem_controller *ctrl, unsigned cs_id
hole_reg = sysinfo->hole_reg[nodeid];
if (hole_reg & 1) {
unsigned hole_startk;
- hole_startk = (hole_reg & (0xff<<24)) >> 10;
- if ( (dword >= (hole_startk<<2)) && (dword < ((4*1024*1024)<<2))) {
- dword += ((4*1024*1024 - hole_startk)<<2);
+ hole_startk = (hole_reg & (0xff << 24)) >> 10;
+ if ((dword >= (hole_startk << 2)) && (dword < ((4*1024*1024) << 2))) {
+ dword += ((4*1024*1024 - hole_startk) << 2);
}
}
#endif
@@ -197,12 +197,12 @@ static void WriteLNTestPattern(unsigned addr_lo, uint8_t *buf_a, unsigned line_n
static void Write1LTestPattern(unsigned addr, unsigned p, uint8_t *buf_a, uint8_t *buf_b)
{
uint8_t *buf;
- if (p==1) { buf = buf_b; }
+ if (p == 1) { buf = buf_b; }
else { buf = buf_a; }
- set_FSBASE (addr>>24);
+ set_FSBASE (addr >> 24);
- WriteLNTestPattern(addr<<8, buf, 1);
+ WriteLNTestPattern(addr << 8, buf, 1);
}
static void Read1LTestPattern(unsigned addr)
@@ -214,7 +214,7 @@ static void Read1LTestPattern(unsigned addr)
/* 1st move causes read fill (to exclusive or shared)*/
__asm__ volatile (
"movl %%fs:(%1), %0\n\t"
- :"=b"(value): "a" (addr<<8)
+ :"=b"(value): "a" (addr << 8)
);
}
@@ -243,7 +243,7 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
unsigned result = DQS_FAIL;
if (Pass == DQS_FIRST_PASS) {
- if (pattern==1) {
+ if (pattern == 1) {
test_buf = (uint32_t *)TestPattern1;
}
else {
@@ -254,9 +254,9 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
test_buf = (uint32_t *)TestPattern2;
}
- set_FSBASE(addr>>24);
+ set_FSBASE(addr >> 24);
- addr_lo = addr<<8;
+ addr_lo = addr << 8;
if (is_Width128 && (channel == 1)) {
addr_lo += 8; //second channel
@@ -285,13 +285,13 @@ static unsigned CompareTestPatternQW0(unsigned channel, unsigned addr, unsigned
print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : test_buf= ", (unsigned)test_buf, " value = ", value_test, 4);
print_debug_dqs_pair("\t\t\t\t\t\tQW0.hi : addr_lo = ", addr_lo, " value = ", value, 4);
- if (value == value_test){
+ if (value == value_test) {
result = DQS_PASS;
}
}
if (Pass == DQS_SECOND_PASS) { // second pass need to be inverted
- if (result==DQS_PASS) {
+ if (result == DQS_PASS) {
result = DQS_FAIL;
}
else {
@@ -314,7 +314,7 @@ static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly)
reg = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
- reg &= ~(DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
+ reg &= ~(DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
reg |= ((dly - DCH_MaxAsyncLat_BASE) << DCH_MaxAsyncLat_SHIFT);
pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, reg);
@@ -327,8 +327,8 @@ static void SetMaxAL_RcvrDly(const struct mem_controller *ctrl, unsigned dly)
static void SetTargetWTIO(unsigned addr)
{
msr_t msr;
- msr.hi = addr>>24;
- msr.lo = addr<<8;
+ msr.hi = addr >> 24;
+ msr.lo = addr << 8;
wrmsr(0xc0010016, msr); //IORR0 BASE
msr.hi = 0xff;
@@ -354,7 +354,7 @@ static void proc_CLFLUSH(unsigned addr)
__asm__ volatile (
/* clflush fs:[eax] */
"clflush %%fs:(%0)\n\t"
- ::"a" (addr<<8)
+ ::"a" (addr << 8)
);
}
@@ -409,7 +409,7 @@ static uint16_t get_exact_T1000(unsigned i)
/* Check for FID control support */
struct cpuid_result cpuid1;
cpuid1 = cpuid(0x80000007);
- if ( cpuid1.edx & 0x02 ) {
+ if (cpuid1.edx & 0x02) {
/* Use current FID */
unsigned fid_cur;
msr = rdmsr(0xc0010042);
@@ -425,7 +425,7 @@ static uint16_t get_exact_T1000(unsigned i)
index = fid_start>>25;
}
- if (index>12) return T1000_a[i];
+ if (index > 12) return T1000_a[i];
return TT_a[index * 4+i];
@@ -437,14 +437,14 @@ static void InitDQSPos4RcvrEn(const struct mem_controller *ctrl)
uint32_t dword;
dword = 0x00000000;
- for (i=1; i<=3; i++) {
+ for (i = 1; i <= 3; i++) {
/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x01-0x03, 0x21-0x23) to 0x00 for all bytes */
pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
}
dword = 0x2f2f2f2f;
- for (i=5; i<=7; i++) {
+ for (i = 5; i <= 7; i++) {
/* Program the DQS Write Timing Control Registers (Function 2:Offset 0x9c, index 0x05-0x07, 0x25-0x27) to 0x2f for all bytes */
pci_write_config32_index_wait(ctrl->f2, 0x98, i, dword);
pci_write_config32_index_wait(ctrl->f2, 0x98, i+0x20, dword);
@@ -554,14 +554,14 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
// SetupRcvrPattern
buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (0xfffffff0));
buf_b = buf_a + 128; //??
- if (Pass==DQS_FIRST_PASS) {
- for (i=0;i<16;i++) {
+ if (Pass == DQS_FIRST_PASS) {
+ for (i = 0; i < 16; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPattern0[i];
*((uint32_t *)(buf_b + i*4)) = TestPattern1[i];
}
}
else {
- for (i=0;i<16;i++) {
+ for (i = 0; i < 16; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPattern2[i];
*((uint32_t *)(buf_b + i*4)) = TestPattern2[i];
}
@@ -581,13 +581,13 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
channel = 1;
}
- for ( ; (channel < 2) && (!Errors); channel++)
+ for (; (channel < 2) && (!Errors); channel++)
{
print_debug_dqs("\tTrainRcvEn51: channel ",channel, 1);
/* for each rank */
/* there are four receiver pairs, loosely associated with CS */
- for ( receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
+ for (receiver = 0; (receiver < 8) && (!Errors); receiver+=2)
{
unsigned index=(receiver>>1) * 3 + 0x10;
@@ -642,7 +642,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
RcvrEnDly = dqs_rcvr_dly_a[channel * 8 + receiver];
}
- while ( RcvrEnDly < 0xaf) { // Sweep Delay value here
+ while (RcvrEnDly < 0xaf) { // Sweep Delay value here
print_debug_dqs("\t\t\tTrainRcvEn541: RcvrEnDly ", RcvrEnDly, 3);
if (RcvrEnDly & 1) {
@@ -841,7 +841,7 @@ static unsigned TrainRcvrEn(const struct mem_controller *ctrl, unsigned Pass, st
printk(BIOS_DEBUG, " CTLRMaxDelay=%02x\n", CTLRMaxDelay);
#endif
- return (CTLRMaxDelay==0xae)?1:0;
+ return (CTLRMaxDelay == 0xae)?1:0;
}
@@ -859,14 +859,14 @@ static void SetDQSDelayCSR(const struct mem_controller *ctrl, unsigned channel,
index = (bytelane>>2) + 1 + channel * 0x20 + (direction << 2);
shift = bytelane;
- while (shift>3) {
+ while (shift > 3) {
shift-=4;
}
shift <<= 3; // 8 bit
dword = pci_read_config32_index_wait(ctrl->f2, 0x98, index);
- dword &= ~(0x3f<<shift);
- dword |= (dqs_delay<<shift);
+ dword &= ~(0x3f << shift);
+ dword |= (dqs_delay << shift);
pci_write_config32_index_wait(ctrl->f2, 0x98, index, dword);
}
@@ -879,13 +879,13 @@ static void SetDQSDelayAllCSR(const struct mem_controller *ctrl, unsigned channe
dword = 0;
dqs_delay &= 0xff;
- for (i=0;i<4;i++) {
- dword |= dqs_delay<<(i*8);
+ for (i = 0; i < 4; i++) {
+ dword |= dqs_delay << (i*8);
}
index = 1 + channel * 0x20 + direction * 4;
- for (i=0; i<2; i++) {
+ for (i = 0; i < 2; i++) {
pci_write_config32_index_wait(ctrl->f2, 0x98, index + i, dword);
}
@@ -898,7 +898,7 @@ static unsigned MiddleDQS(unsigned min_d, unsigned max_d)
if (size_d & 1) { //need round up
min_d++;
}
- return ( min_d + (size_d>>1));
+ return (min_d + (size_d>>1));
}
static inline void save_dqs_delay(unsigned channel, unsigned bytelane, unsigned direction, uint8_t *dqs_delay_a, uint8_t dqs_delay)
@@ -1026,10 +1026,10 @@ static __attribute__((noinline)) void FlushDQSTestPattern_L18(unsigned addr_lo)
);
}
-static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern )
+static void FlushDQSTestPattern(unsigned addr_lo, unsigned pattern)
{
- if (pattern == 0){
+ if (pattern == 0) {
FlushDQSTestPattern_L9(addr_lo);
}
else {
@@ -1056,7 +1056,7 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign
}
bytelane = 0;
- for (i=0;i<9*64/4;i++) {
+ for (i = 0; i < 9*64/4; i++) {
__asm__ volatile (
"movl %%fs:(%1), %0\n\t"
:"=b"(value): "a" (addr_lo)
@@ -1066,9 +1066,9 @@ static unsigned CompareDQSTestPattern(unsigned channel, unsigned addr_lo, unsign
print_debug_dqs_pair("\t\t\t\t\t\ttest_buf= ", (unsigned)test_buf, " value = ", value_test, 7);
print_debug_dqs_pair("\t\t\t\t\t\ttaddr_lo = ",addr_lo, " value = ", value, 7);
- for (j=0;j<4*8;j+=8) {
+ for (j = 0; j < 4*8; j+=8) {
if (((value>>j)&0xff) != ((value_test>>j)& 0xff)) {
- bitmap &= ~(1<<bytelane);
+ bitmap &= ~(1 << bytelane);
}
bytelane++;
@@ -1116,7 +1116,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
printk(BIOS_DEBUG, "TrainDQSPos: MutualCSPassW[48] :%p\n", MutualCSPassW);
- for (DQSDelay=0; DQSDelay<48; DQSDelay++) {
+ for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) {
MutualCSPassW[DQSDelay] = 0xff; // Bitmapped status per delay setting, 0xff=All positions passing (1= PASS)
}
@@ -1135,25 +1135,25 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
if (Direction == DQS_READDIR) {
print_debug_dqs("\t\t\t\tTrainDQSPos: 13 for read so write at first", 0, 4);
- WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a);
+ WriteDQSTestPattern(TestAddr < <8, Pattern, buf_a);
}
- for (DQSDelay = 0; DQSDelay < 48; DQSDelay++ ){
+ for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 141 DQSDelay ", DQSDelay, 5);
if (MutualCSPassW[DQSDelay] == 0) continue; //skip current delay value if other chipselects have failed all 8 bytelanes
SetDQSDelayAllCSR(ctrl, channel, Direction, DQSDelay);
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 142 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
if (Direction == DQS_WRITEDIR) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 143 for write", 0, 5);
- WriteDQSTestPattern(TestAddr<<8, Pattern, buf_a);
+ WriteDQSTestPattern(TestAddr < <8, Pattern, buf_a);
}
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 144 Pattern ", Pattern, 5);
- ReadDQSTestPattern(TestAddr<<8, Pattern);
+ ReadDQSTestPattern(TestAddr << 8, Pattern);
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 145 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
- MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr<<8, Pattern, buf_a); //0: fail, 1=pass
+ MutualCSPassW[DQSDelay] &= CompareDQSTestPattern(channel, TestAddr << 8, Pattern, buf_a); //0: fail, 1=pass
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 146 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
SetTargetWTIO(TestAddr);
- FlushDQSTestPattern(TestAddr<<8, Pattern);
+ FlushDQSTestPattern(TestAddr << 8, Pattern);
ResetTargetWTIO();
}
}
@@ -1166,8 +1166,8 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
RnkDlySeqPassMax = 0;
RnkDlyFilterMax = 0;
RnkDlyFilterMin = 0;
- for (DQSDelay=0; DQSDelay<48; DQSDelay++) {
- if (MutualCSPassW[DQSDelay] & (1<<ByteLane)) {
+ for (DQSDelay = 0; DQSDelay < 48; DQSDelay++) {
+ if (MutualCSPassW[DQSDelay] & (1 << ByteLane)) {
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 321 DQSDelay ", DQSDelay, 5);
print_debug_dqs("\t\t\t\t\tTrainDQSPos: 322 MutualCSPassW ", MutualCSPassW[DQSDelay], 5);
@@ -1176,7 +1176,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
if (LastTest == DQS_FAIL) {
RnkDlySeqPassMin = DQSDelay; //start sequential run
}
- if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)){
+ if ((RnkDlySeqPassMax - RnkDlySeqPassMin)>(RnkDlyFilterMax-RnkDlyFilterMin)) {
RnkDlyFilterMin = RnkDlySeqPassMin;
RnkDlyFilterMax = RnkDlySeqPassMax;
}
@@ -1194,7 +1194,7 @@ static unsigned TrainDQSPos(const struct mem_controller *ctrl, unsigned channel,
else {
print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMax ", RnkDlyFilterMax, 4);
print_debug_dqs("\t\t\t\tTrainDQSPos: 34 RnkDlyFilterMin ", RnkDlyFilterMin, 4);
- if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW){
+ if ((RnkDlyFilterMax - RnkDlyFilterMin)< MIN_DQS_WNDW) {
Errors |= SB_SMALLDQS;
}
else {
@@ -1371,15 +1371,15 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
//SetupDqsPattern
buf_a = (uint8_t *)(((uint32_t)(&pattern_buf_x[0]) + 0x10) & (~0xf));
- if (is_Width128){
+ if (is_Width128) {
pattern = 1;
- for (i=0;i<16*18;i++) {
+ for (i = 0; i < 16*18; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPatternJD1b[i];
}
}
else {
pattern = 0;
- for (i=0; i<16*9;i++) {
+ for (i = 0; i < 16*9; i++) {
*((uint32_t *)(buf_a + i*4)) = TestPatternJD1a[i];
}
@@ -1397,7 +1397,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
channel = 1;
}
- while ( (channel<2) && (!Errors)) {
+ while ((channel < 2) && (!Errors)) {
print_debug_dqs("\tTrainDQSRdWrPos: 1 channel ",channel, 1);
for (DQSWrDelay = 0; DQSWrDelay < 48; DQSWrDelay++) {
unsigned err;
@@ -1417,7 +1417,7 @@ static unsigned TrainDQSRdWrPos(const struct mem_controller *ctrl, struct sys_in
}
channel++;
- if (!is_Width128){
+ if (!is_Width128) {
//FIXME: 64MuxMode??
channel++; // skip channel if 64-bit mode
}
@@ -1458,7 +1458,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte
DQSDelay0 = get_dqs_delay(channel, ByteLane0, Direction, dqs_delay_a);
DQSDelay1 = get_dqs_delay(channel, ByteLane1, Direction, dqs_delay_a);
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay = DQSDelay0 - DQSDelay1;
InterFactor = 0xff - InterFactor;
}
@@ -1470,7 +1470,7 @@ static unsigned CalcEccDQSPos(unsigned channel,unsigned ByteLane0, unsigned Byte
DQSDelay >>= 8; // /255
- if (DQSDelay0>DQSDelay1) {
+ if (DQSDelay0 > DQSDelay1) {
DQSDelay += DQSDelay1;
}
else {
@@ -1496,11 +1496,11 @@ static void SetEccDQSRdWrPos(const struct mem_controller *ctrl, struct sys_info
ByteLane = 8;
for (channel = 0; channel < 2; channel++) {
- for (i=0;i<2;i++) {
+ for (i = 0; i < 2; i++) {
Direction = direction[i];
lane0 = 4; lane1 = 5; ratio = 0;
dqs_delay = CalcEccDQSPos(channel, lane0, lane1, ratio, Direction, dqs_delay_a);
- print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction==DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2);
+ print_debug_dqs_pair("\t\tSetEccDQSRdWrPos: channel ", channel, Direction == DQS_READDIR? " R dqs_delay":" W dqs_delay", dqs_delay, 2);
SetDQSDelayCSR(ctrl, channel, ByteLane, Direction, dqs_delay);
save_dqs_delay(channel, ByteLane, Direction, dqs_delay_a, dqs_delay);
}
@@ -1546,7 +1546,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
uint32_t dword;
@@ -1568,7 +1568,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
print_debug_dqs_tsc("begin: tsc1", i, tsc1[i].hi, tsc1[i].lo, 2);
dword = tsc1[i].lo + tsc0[i].lo;
- if ((dword<tsc1[i].lo) || (dword<tsc0[i].lo)) {
+ if ((dword < tsc1[i].lo) || (dword < tsc0[i].lo)) {
tsc1[i].hi++;
}
tsc1[i].lo = dword;
@@ -1583,7 +1583,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
if (!cpu_f0_f1[i]) continue;
@@ -1591,7 +1591,7 @@ static void f0_svm_workaround(int controllers, const struct mem_controller *ctrl
do {
tsc = rdtsc();
- } while ((tsc1[i].hi>tsc.hi) || ((tsc1[i].hi==tsc.hi) && (tsc1[i].lo>tsc.lo)));
+ } while ((tsc1[i].hi > tsc.hi) || ((tsc1[i].hi == tsc.hi) && (tsc1[i].lo > tsc.lo)));
print_debug_dqs_tsc("end : tsc ", i, tsc.hi, tsc.lo, 2);
}
@@ -1661,8 +1661,8 @@ static unsigned int range_to_mtrr(unsigned int reg,
#if CONFIG_MEM_TRAIN_SEQ != 1
printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
- (type==MTRR_TYPE_UNCACHEABLE)?"UC":
- ((type==MTRR_TYPE_WRBACK)?"WB":"Other")
+ (type == MTRR_TYPE_UNCACHEABLE)?"UC":
+ ((type == MTRR_TYPE_WRBACK)?"WB":"Other")
);
#endif
set_var_mtrr_dqs(reg++, range_startk, sizek, type, address_bits);
@@ -1737,7 +1737,7 @@ static void clear_mtrr_dqs(unsigned tom2_k)
wrmsr(0x258, msr);
//[1M, TOM)
- for (i=0x204;i<0x210;i++) {
+ for (i = 0x204; i < 0x210; i++) {
wrmsr(i, msr);
}
@@ -1755,8 +1755,8 @@ static void set_htic_bit(unsigned i, unsigned val, unsigned bit)
{
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
- dword &= ~(1<<bit);
- dword |= ((val & 1) <<bit);
+ dword &= ~(1 << bit);
+ dword |= ((val & 1) << bit);
pci_write_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL, dword);
}
@@ -1764,7 +1764,7 @@ static unsigned get_htic_bit(unsigned i, unsigned bit)
{
uint32_t dword;
dword = pci_read_config32(PCI_DEV(0, 0x18+i, 0), HT_INIT_CONTROL);
- dword &= (1<<bit);
+ dword &= (1 << bit);
return dword;
}
@@ -1865,7 +1865,7 @@ static void dqs_restore_MC_NVRAM(unsigned int dev)
pos = dqs_load_MC_NVRAM_ch(dev, 1, pos);
/* load the maxasync lat here */
pos = s3_load_nvram_early(4, ®, pos);
- reg &= (DCH_MaxAsyncLat_MASK <<DCH_MaxAsyncLat_SHIFT);
+ reg &= (DCH_MaxAsyncLat_MASK << DCH_MaxAsyncLat_SHIFT);
reg |= pci_read_config32(dev, DRAM_CONFIG_HIGH);
pci_write_config32(dev, DRAM_CONFIG_HIGH, reg);
}
@@ -1890,7 +1890,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
fill_mem_cs_sysinfo(i, ctrl+i, sysinfo);
}
@@ -1901,7 +1901,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass1: %02x\n", i);
if (train_DqsRcvrEn(ctrl+i, 1, sysinfo)) goto out;
@@ -1919,7 +1919,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:DQSPos: %02x\n", i);
if (train_DqsPos(ctrl+i, sysinfo)) goto out;
@@ -1932,7 +1932,7 @@ static void dqs_timing(int controllers, const struct mem_controller *ctrl, struc
continue;
/* Skip everything if I don't have any memory on this controller */
- if (sysinfo->meminfo[i].dimm_mask==0x00) continue;
+ if (sysinfo->meminfo[i].dimm_mask == 0x00) continue;
printk(BIOS_DEBUG, "DQS Training:RcvrEn:Pass2: %02x\n", i);
if (train_DqsRcvrEn(ctrl+i, 2, sysinfo)) goto out;
@@ -1948,7 +1948,7 @@ out:
clear_mtrr_dqs(sysinfo->tom2_k);
- for (i=0;i<5;i++) {
+ for (i = 0; i < 5; i++) {
print_debug_dqs_tsc_x("DQS Training:tsc", i, tsc[i].hi, tsc[i].lo);
}
@@ -2004,7 +2004,7 @@ static void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
}
- if (train_DqsRcvrEn(ctrl, 2, sysinfo)){
+ if (train_DqsRcvrEn(ctrl, 2, sysinfo)) {
sysinfo->mem_trained[i]=0x83; //
goto out;
}
@@ -2021,7 +2021,7 @@ out:
#endif
if (v) {
- for (ii=0;ii<4;ii++) {
+ for (ii = 0; ii < 4; ii++) {
print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii, tsc[ii].hi, tsc[ii].lo);
}
}
diff --git a/src/northbridge/amd/amdk8/setup_resource_map.c b/src/northbridge/amd/amdk8/setup_resource_map.c
index fa03e4a..e6e79c8 100644
--- a/src/northbridge/amd/amdk8/setup_resource_map.c
+++ b/src/northbridge/amd/amdk8/setup_resource_map.c
@@ -50,9 +50,9 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
#if RES_DEBUG
printk(BIOS_DEBUG, "%04x: %02x %08x <- & %08x | %08x\n",
i>>2, register_values[i],
- register_values[i+1] + ( (register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
+ register_values[i+1] + ((register_values[i]==RES_PCI_IO) ? offset_pci_dev : 0),
register_values[i+2],
- register_values[i+3] + ( ( (register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
+ register_values[i+3] + (((register_values[i] & RES_PORT_IO_32) == RES_PORT_IO_32) ? offset_io_base : 0)
);
#endif
switch (register_values[i]) {
@@ -103,7 +103,7 @@ static void setup_resource_map_x_offset(const unsigned int *register_values, int
reg = read32(where);
reg &= register_values[i+2];
reg |= register_values[i+3];
- write32( where, reg);
+ write32(where, reg);
}
break;
#endif
@@ -174,7 +174,7 @@ static void setup_mem_resource_map(const unsigned int *register_values, int max)
reg = read32(where);
reg &= register_values[i+1];
reg |= register_values[i+2];
- write32( where, reg);
+ write32(where, reg);
#if 0
reg = read32(where);
prink(BIOS_DEBUG, " RB %08x\n", reg);
diff --git a/src/northbridge/amd/amdk8/util.asl b/src/northbridge/amd/amdk8/util.asl
index 6a9b69f..83d741e 100644
--- a/src/northbridge/amd/amdk8/util.asl
+++ b/src/northbridge/amd/amdk8/util.asl
@@ -44,9 +44,9 @@ Scope (\_SB)
Method (DADD, 2, NotSerialized)
{
- Store( Arg1, Local0)
- Store( Arg0, Local1)
- Add( ShiftLeft(Local1,16), Local0, Local0)
+ Store(Arg1, Local0)
+ Store(Arg0, Local1)
+ Add(ShiftLeft(Local1,16), Local0, Local0)
Return (Local0)
}
@@ -54,7 +54,7 @@ Scope (\_SB)
Method (GHCE, 1, NotSerialized) // check if the HC enabled
{
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if (LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ if (LEqual (And(Local1, 0x01), 0x01)) { Return (0x0F) }
Else { Return (0x00) }
}
@@ -62,7 +62,7 @@ Scope (\_SB)
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+ Store (ShiftRight(And (Local1, 0xf0), 0x04), Local0)
Return (Local0)
}
@@ -70,7 +70,7 @@ Scope (\_SB)
{
Store (0x00, Local0)
Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+ Store (ShiftRight(And (Local1, 0xf00), 0x08), Local0)
Return (Local0)
}
@@ -80,7 +80,7 @@ Scope (\_SB)
Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
- Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+ Store (And (ShiftRight(Local1, Local2), 0xff), Local0)
Return (Local0)
}
1
0
21 Sep '16
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16683
-gerrit
commit 5bab414fc5cf1dbae9cbba5b91102485d503dceb
Author: Patrick Georgi <pgeorgi(a)chromium.org>
Date: Wed Sep 21 14:08:41 2016 +0200
google/enguarde: Adapt to current tree
Some changes were made in upstream in the meantime that broke the build:
- CHROMEOS_VBNV_CMOS was renamed to VBOOT_VBNV_CMOS
- recovery_move_enabled() -> vboot_recovery_mode_enabled()
- chromeos.asl was replaced by an acpi generator
Change-Id: Icd4ed5111cce9db79e12efb0cb7e898bba725c20
Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org>
---
src/mainboard/google/enguarde/Kconfig | 2 +-
src/mainboard/google/enguarde/acpi/chromeos.asl | 32 -------------------------
src/mainboard/google/enguarde/chromeos.c | 13 +++++++++-
src/mainboard/google/enguarde/dsdt.asl | 1 -
src/mainboard/google/enguarde/mainboard.c | 2 ++
5 files changed, 15 insertions(+), 35 deletions(-)
diff --git a/src/mainboard/google/enguarde/Kconfig b/src/mainboard/google/enguarde/Kconfig
index 9a422c0..ec528a6 100644
--- a/src/mainboard/google/enguarde/Kconfig
+++ b/src/mainboard/google/enguarde/Kconfig
@@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS
select MAINBOARD_HAS_LPC_TPM
config CHROMEOS
- select CHROMEOS_VBNV_CMOS
+ select VBOOT_VBNV_CMOS
select LID_SWITCH
select EC_SOFTWARE_SYNC
select VIRTUAL_DEV_SWITCH
diff --git a/src/mainboard/google/enguarde/acpi/chromeos.asl b/src/mainboard/google/enguarde/acpi/chromeos.asl
deleted file mode 100644
index 50fc8d2..0000000
--- a/src/mainboard/google/enguarde/acpi/chromeos.asl
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: On Bay Trail we need to encode gpios within the 3 separate banks
- * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
- * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
- */
-
-Name(OIPG, Package() {
- // No physical recovery button
- Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" },
- Package () { 0x0003, 1, 0x2006, "BayTrail" },
-})
diff --git a/src/mainboard/google/enguarde/chromeos.c b/src/mainboard/google/enguarde/chromeos.c
index c8a33c4..e4f2d28 100644
--- a/src/mainboard/google/enguarde/chromeos.c
+++ b/src/mainboard/google/enguarde/chromeos.c
@@ -19,6 +19,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
#if CONFIG_EC_GOOGLE_CHROMEEC
#include "ec.h"
@@ -35,7 +36,7 @@ void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
- {-1, ACTIVE_HIGH, recovery_mode_enabled(), "recovery"},
+ {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"},
{-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
{-1, ACTIVE_HIGH, 0, "power"},
@@ -110,3 +111,13 @@ int get_write_protect_state(void)
/* WP is enabled when the pin is reading high. */
return ssus_get_gpio(WP_STATUS_PAD);
}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/enguarde/dsdt.asl b/src/mainboard/google/enguarde/dsdt.asl
index a20a197..e21b3d1 100644
--- a/src/mainboard/google/enguarde/dsdt.asl
+++ b/src/mainboard/google/enguarde/dsdt.asl
@@ -44,7 +44,6 @@ DefinitionBlock(
#include "acpi/dptf.asl"
}
- #include "acpi/chromeos.asl"
#include <vendorcode/google/chromeos/acpi/chromeos.asl>
/* Chipset specific sleep states */
diff --git a/src/mainboard/google/enguarde/mainboard.c b/src/mainboard/google/enguarde/mainboard.c
index 6b2df7a..7ca55b5 100644
--- a/src/mainboard/google/enguarde/mainboard.c
+++ b/src/mainboard/google/enguarde/mainboard.c
@@ -34,6 +34,7 @@
#include "onboard.h"
#include <soc/gpio.h>
#include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
void mainboard_suspend_resume(void)
{
@@ -154,6 +155,7 @@ static void mainboard_enable(device_t dev)
{
dev->ops->init = mainboard_init;
dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
#if CONFIG_VGA_ROM_RUN
/* Install custom int15 handler for VGA OPROM */
mainboard_interrupt_handlers(0x15, &int15_handler);
1
0
Patch set updated for coreboot: google/quawks: Upstream Asus Chromebook C300
by Patrick Georgi 21 Sep '16
by Patrick Georgi 21 Sep '16
21 Sep '16
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15443
-gerrit
commit 726e14dc53c766d4190d979002bf239e31b0055d
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu May 26 16:46:12 2016 -0500
google/quawks: Upstream Asus Chromebook C300
Migrate google/quawks (Asus Chromebook C300) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-quawks-5216.204.B
commit edb60c9 [Quawks: Update SPD data]
TEST=built and booted Linux on quawks with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: I605d0c86b613dfb9de4c671f2b253e1bbb8e80ee
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/quawks/Kconfig | 50 ++++
src/mainboard/google/quawks/Kconfig.name | 2 +
src/mainboard/google/quawks/Makefile.inc | 25 ++
src/mainboard/google/quawks/acpi/dptf.asl | 87 +++++++
src/mainboard/google/quawks/acpi/ec.asl | 20 ++
src/mainboard/google/quawks/acpi/mainboard.asl | 266 +++++++++++++++++++++
src/mainboard/google/quawks/acpi/superio.asl | 27 +++
src/mainboard/google/quawks/acpi/video.asl | 39 +++
src/mainboard/google/quawks/acpi_tables.c | 64 +++++
src/mainboard/google/quawks/board_info.txt | 3 +
src/mainboard/google/quawks/chromeos.c | 123 ++++++++++
src/mainboard/google/quawks/chromeos.fmd | 38 +++
src/mainboard/google/quawks/cmos.layout | 133 +++++++++++
src/mainboard/google/quawks/devicetree.cb | 98 ++++++++
src/mainboard/google/quawks/dsdt.asl | 53 ++++
src/mainboard/google/quawks/ec.c | 48 ++++
src/mainboard/google/quawks/ec.h | 62 +++++
src/mainboard/google/quawks/fadt.c | 46 ++++
src/mainboard/google/quawks/gpio.c | 231 ++++++++++++++++++
src/mainboard/google/quawks/irqroute.c | 18 ++
src/mainboard/google/quawks/irqroute.h | 60 +++++
src/mainboard/google/quawks/mainboard.c | 183 ++++++++++++++
src/mainboard/google/quawks/mainboard_smi.c | 121 ++++++++++
src/mainboard/google/quawks/onboard.h | 40 ++++
src/mainboard/google/quawks/romstage.c | 99 ++++++++
.../spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex | 17 ++
src/mainboard/google/quawks/spd/Makefile.inc | 49 ++++
.../spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex | 17 ++
.../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 +++
.../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 +++
.../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 +++
.../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 +++
src/mainboard/google/quawks/w25q64.c | 70 ++++++
33 files changed, 2217 insertions(+)
diff --git a/src/mainboard/google/quawks/Kconfig b/src/mainboard/google/quawks/Kconfig
new file mode 100644
index 0000000..0125b6b
--- /dev/null
+++ b/src/mainboard/google/quawks/Kconfig
@@ -0,0 +1,50 @@
+if BOARD_GOOGLE_QUAWKS
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_BAYTRAIL
+ select EC_GOOGLE_CHROMEEC
+ select ENABLE_BUILTIN_COM1
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+
+config CHROMEOS
+ select VBOOT_VBNV_CMOS
+ select LID_SWITCH
+ select EC_SOFTWARE_SYNC
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/quawks
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Quawks"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0166.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ string
+ default ""
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "QUAWKS TEST A-A 0128"
+
+endif # BOARD_GOOGLE_QUAWKS
diff --git a/src/mainboard/google/quawks/Kconfig.name b/src/mainboard/google/quawks/Kconfig.name
new file mode 100644
index 0000000..d5f9afb
--- /dev/null
+++ b/src/mainboard/google/quawks/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_QUAWKS
+ bool "Quawks"
diff --git a/src/mainboard/google/quawks/Makefile.inc b/src/mainboard/google/quawks/Makefile.inc
new file mode 100644
index 0000000..2a9475c
--- /dev/null
+++ b/src/mainboard/google/quawks/Makefile.inc
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += irqroute.c
+ramstage-y += w25q64.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/google/quawks/acpi/dptf.asl b/src/mainboard/google/quawks/acpi/dptf.asl
new file mode 100644
index 0000000..29f4d56
--- /dev/null
+++ b/src/mainboard/google/quawks/acpi/dptf.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 52
+#define DPTF_TSR0_CRITICAL 75
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 51
+#define DPTF_TSR1_CRITICAL 75
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 51
+#define DPTF_TSR2_CRITICAL 75
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6A4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x320, "mA", 0 }, /* 0.8A */
+ Package () { 0, 0, 0, 0, 16, 0x258, "mA", 0 }, /* 0.6A */
+ Package () { 0, 0, 0, 0, 8, 0x190, "mA", 0 }, /* 0.4A */
+ Package () { 0, 0, 0, 0, 0, 0x64, "mA", 0 }, /* 0.1A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, // Revision
+ Package () { // Power Limit 1
+ 0, // PowerLimitIndex, 0 for Power Limit 1
+ 1600, // PowerLimitMinimum
+ 6200, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 200 // StepSize
+ },
+ Package () { // Power Limit 2
+ 1, // PowerLimitIndex, 1 for Power Limit 2
+ 8000, // PowerLimitMinimum
+ 8000, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 1000 // StepSize
+ }
+})
+
+/* Include Baytrail DPTF */
+#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/quawks/acpi/ec.asl b/src/mainboard/google/quawks/acpi/ec.asl
new file mode 100644
index 0000000..040bbc9
--- /dev/null
+++ b/src/mainboard/google/quawks/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/quawks/ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/quawks/acpi/mainboard.asl b/src/mainboard/google/quawks/acpi/mainboard.asl
new file mode 100644
index 0000000..2c0324f
--- /dev/null
+++ b/src/mainboard/google/quawks/acpi/mainboard.asl
@@ -0,0 +1,266 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/quawks/onboard.h>
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 })
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (_UID, 1)
+ }
+
+ /* Wake device for touchpad */
+ Device (TPAD)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 1)
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Return interrupt if I2C1 is PCI mode */
+ If (LEqual (\S1EN, 0)) {
+ Return (^RBUF)
+ }
+
+ /* Return empty resource template otherwise */
+ Return (ResourceTemplate() {})
+ }
+ }
+}
+
+Scope (\_SB.I2C1)
+{
+ Device (ATPB)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad Bootloader")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x25, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ATPA)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad")
+ Name (_UID, 2)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4b, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x15, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.I2C2)
+{
+ Device (CODC)
+ {
+ /*
+ * TODO(dlaurie): Need official HID.
+ *
+ * The current HID is created from the Maxim Integrated
+ * PCI Vendor ID 193Ch and a shortened device identifier.
+ */
+ Name (_HID, "193C9890")
+ Name (_DDN, "Maxim 98090 Codec")
+ Name (_UID, 1)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x10, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C2", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_CODEC_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.I2C5)
+{
+ Device (ALSI)
+ {
+ /*
+ * TODO(dlaurie): Need official HID.
+ *
+ * The current HID is created from the Intersil PNP
+ * Vendor ID "LSD" and a shortened device identifier.
+ */
+ Name (_HID, EisaId ("LSD2918"))
+ Name (_DDN, "Intersil 29018 Ambient Light Sensor")
+ Name (_UID, 1)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x44, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C5", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_ALS_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S5EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 14 }
+
+ /* Mic Detect (index 1) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 15 }
+ })
+}
diff --git a/src/mainboard/google/quawks/acpi/superio.asl b/src/mainboard/google/quawks/acpi/superio.asl
new file mode 100644
index 0000000..f91e0a3
--- /dev/null
+++ b/src/mainboard/google/quawks/acpi/superio.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/quawks/ec.h>
+#include <mainboard/google/quawks/onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+// Override default IRQ settings
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/quawks/acpi/video.asl b/src/mainboard/google/quawks/acpi/video.asl
new file mode 100644
index 0000000..1405b04
--- /dev/null
+++ b/src/mainboard/google/quawks/acpi/video.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/quawks/acpi_tables.c b/src/mainboard/google/quawks/acpi_tables.c
new file mode 100644
index 0000000..c647c9b
--- /dev/null
+++ b/src/mainboard/google/quawks/acpi_tables.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 1;
+
+ /* Enable DPTF */
+ gnvs->dpte = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/src/mainboard/google/quawks/board_info.txt b/src/mainboard/google/quawks/board_info.txt
new file mode 100644
index 0000000..3e630d3
--- /dev/null
+++ b/src/mainboard/google/quawks/board_info.txt
@@ -0,0 +1,3 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: y
diff --git a/src/mainboard/google/quawks/chromeos.c b/src/mainboard/google/quawks/chromeos.c
new file mode 100644
index 0000000..e8f96ae
--- /dev/null
+++ b/src/mainboard/google/quawks/chromeos.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <bootmode.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#endif
+
+/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
+#define WP_STATUS_PAD 36
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif
+
+int get_lid_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+
+ return !!(ec_switches & EC_SWITCH_LID_OPEN);
+#else
+ /* Default to force open. */
+ return 1;
+#endif
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+ u32 ec_events;
+
+ /* If a switch is set, we don't need to look at events. */
+ if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
+ return 1;
+
+ /* Else check if the EC has posted the keyboard recovery event. */
+ ec_events = google_chromeec_get_events_b();
+
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+ return 0;
+#endif
+}
+
+int clear_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+#else
+ return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+ /*
+ * The vboot loader queries this function in romstage. The GPIOs have
+ * not been set up yet as that configuration is done in ramstage. The
+ * hardware defaults to an input but there is a 20K pulldown. Externally
+ * there is a 10K pullup. Disable the internal pull in romstage so that
+ * there isn't any ambiguity in the reading.
+ */
+#if defined(__PRE_RAM__)
+ ssus_disable_internal_pull(WP_STATUS_PAD);
+#endif
+
+ /* WP is enabled when the pin is reading high. */
+ return ssus_get_gpio(WP_STATUS_PAD);
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/quawks/chromeos.fmd b/src/mainboard/google/quawks/chromeos.fmd
new file mode 100644
index 0000000..113fba6
--- /dev/null
+++ b/src/mainboard/google/quawks/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0x600000 {
+ RW_SECTION_A@0x0 0xf0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0xdffc0
+ RW_FWID_A@0xeffc0 0x40
+ }
+ RW_SECTION_B@0xf0000 0xf0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0xdffc0
+ RW_FWID_B@0xeffc0 0x40
+ }
+ RW_MRC_CACHE@0x1e0000 0x10000
+ RW_ELOG@0x1f0000 0x4000
+ RW_SHARED@0x1f4000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x1f8000 0x2000
+ RW_UNUSED@0x1fa000 0x6000
+ RW_LEGACY(CBFS)@0x200000 0x200000
+ WP_RO@0x400000 0x200000 {
+ RO_VPD@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x1f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x100000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/quawks/cmos.layout b/src/mainboard/google/quawks/cmos.layout
new file mode 100644
index 0000000..b419315
--- /dev/null
+++ b/src/mainboard/google/quawks/cmos.layout
@@ -0,0 +1,133 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/google/quawks/devicetree.cb b/src/mainboard/google/quawks/devicetree.cb
new file mode 100644
index 0000000..cc5146d
--- /dev/null
+++ b/src/mainboard/google/quawks/devicetree.cb
@@ -0,0 +1,98 @@
+chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
+ # Route USB ports to XHCI
+ register "usb_route_to_xhci" = "1"
+
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+
+ # USB PHY settings
+ # TODO: These values are from Baytrail and need tuned for Quawks board
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+ # LPE audio codec settings
+ register "lpe_codec_clk_freq" = "25" # 25MHz clock
+ register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+
+ # SD Card controller
+ register "sdcard_cap_low" = "0x036864b2"
+ register "sdcard_cap_high" = "0x0"
+
+ # Enable devices in ACPI mode
+ register "lpe_acpi_mode" = "1"
+ register "lpss_acpi_mode" = "1"
+ register "scc_acpi_mode" = "1"
+
+ # Enable PIPEA as DP_C
+ register "gpu_pipea_port_select" = "2" # DP_C
+ register "gpu_pipea_power_cycle_delay" = "6" # 600ms
+ register "gpu_pipea_power_on_delay" = "5000" # 500ms
+ register "gpu_pipea_light_on_delay" = "70" # 7ms
+ register "gpu_pipea_power_off_delay" = "500" # 50ms
+ register "gpu_pipea_light_off_delay" = "2000" # 200ms
+
+ # VR PS2 control
+ register "vnn_ps2_enable" = "1"
+ register "vcc_ps2_enable" = "1"
+
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 off end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 off end # HSUART2
+ device pci 1e.5 off end # SPI
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC Bridge
+ device pci 1f.3 off end # SMBus
+ end
+end
diff --git a/src/mainboard/google/quawks/dsdt.asl b/src/mainboard/google/quawks/dsdt.asl
new file mode 100644
index 0000000..a37756f
--- /dev/null
+++ b/src/mainboard/google/quawks/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/baytrail/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+ #include <soc/intel/baytrail/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <soc/intel/baytrail/acpi/northcluster.asl>
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
+
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/baytrail/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/quawks/ec.c b/src/mainboard/google/quawks/ec.c
new file mode 100644
index 0000000..27fcb0f
--- /dev/null
+++ b/src/mainboard/google/quawks/ec.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ printk(BIOS_DEBUG, "mainboard_ec_init\n");
+ post_code(0xf0);
+
+ /* Restore SCI event mask on resume. */
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ }
+
+ /* Clear wake events, these are enabled on entry to sleep */
+ google_chromeec_set_wake_mask(0);
+
+ post_code(0xf1);
+}
diff --git a/src/mainboard/google/quawks/ec.h b/src/mainboard/google/quawks/ec.h
new file mode 100644
index 0000000..159351b
--- /dev/null
+++ b/src/mainboard/google/quawks/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+#define EC_SCI_GPI 24
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI 23
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/quawks/fadt.c b/src/mainboard/google/quawks/fadt.c
new file mode 100644
index 0000000..2434d1a
--- /dev/null
+++ b/src/mainboard/google/quawks/fadt.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/quawks/gpio.c b/src/mainboard/google/quawks/gpio.c
new file mode 100644
index 0000000..dfbc390
--- /dev/null
+++ b/src/mainboard/google/quawks/gpio.c
@@ -0,0 +1,231 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include "irqroute.h"
+
+/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */
+ GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */
+ GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */
+ GPIO_NC, /* S0_NC03 - NC */
+ GPIO_NC, /* S0_NC04 - NC */
+ GPIO_NC, /* S0_NC05 - NC */
+ GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */
+ GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */
+ GPIO_NC, /* S0_NC08 - NC */
+ GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */
+ GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */
+ GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */
+ GPIO_NC, /* S0_NC12 - NC */
+ GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */
+ GPIO_NC, /* S0_NC14 - NC */
+ GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */
+ GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */
+ GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */
+ GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */
+ GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */
+ GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */
+ GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */
+ GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */
+ GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */
+ GPIO_NC, /* S0_NC24 - NC */
+ GPIO_NC, /* S0_NC25 - NC */
+ GPIO_NC, /* S0_NC26 - NC */
+ GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */
+ GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */
+ GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */
+ GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+ GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */
+ GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+ GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */
+ GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+ GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */
+ GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */
+ GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */
+ GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */
+ GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+ GPIO_NC, /* S0-SC013 - NC */
+ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */
+ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */
+ GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */
+ GPIO_NC, /* S0-SC027 - NC */
+ GPIO_NC, /* S0-SC028 - NC */
+ GPIO_NC, /* S0-SC029 - NC */
+ GPIO_NC, /* S0-SC030 - NC */
+ GPIO_NC, /* S0-SC031 - NC */
+ GPIO_NC, /* S0-SC032 - NC */
+ GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */
+ GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */
+ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */
+ GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */
+ GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */
+ GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */
+ GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */
+ GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
+ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
+ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
+ GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */
+ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
+ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
+ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
+ GPIO_DEFAULT, /* S0-SC054 - NC */
+ GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */
+ GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+ GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */
+ GPIO_INPUT, /* S0-SC058 - SIM_DET_C */
+ GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */
+ GPIO_NC, /* S0-SC060 - NC */
+ GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */
+ GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */
+ GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */
+ GPIO_FUNC1, /* S0-SC064 - I2S_DIN */
+ GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */
+ GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */
+ GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */
+ GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */
+ GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */
+ GPIO_DIRQ, /* S0-SC070 - ALS_INT_L - INT */
+ GPIO_NC, /* S0-SC071 - NC */
+ GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */
+ GPIO_NC, /* S0-SC073 - NC */
+ GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */
+ GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */
+ GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */
+ GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */
+ GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */
+ GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */
+ GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */
+ GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */
+ GPIO_NC, /* S0-SC082 - NC */
+ GPIO_NC, /* S0-SC083 - NC */
+ GPIO_NC, /* S0-SC084 - NC */
+ GPIO_NC, /* S0-SC085 - NC */
+ GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */
+ GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */
+ GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */
+ GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */
+ GPIO_NC, /* S0-SC090 - NC */
+ GPIO_NC, /* S0-SC091 - NC */
+ GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+ GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+ GPIO_NC, /* S0-SC094 - NC */
+ GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */
+ GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */
+ GPIO_NC, /* S0-SC097 - NC */
+ GPIO_NC, /* S0-SC098 - NC */
+ GPIO_NC, /* S0-SC099 - NC */
+ GPIO_NC, /* S0-SC100 - NC */
+ GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */
+ GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */
+ GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */
+ GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */
+ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
+ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
+ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
+ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
+ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
+ GPIO_NC, /* S508 - NC */
+ GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */
+ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */
+ GPIO_FUNC0, /* S511 - SUSPWRDNACK */
+ GPIO_FUNC0, /* S512 - WIFI_SUSCLK */
+ GPIO_FUNC0, /* S513 - SLP_SX */
+ GPIO_NC, /* S514 - NC */
+ GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */
+ GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */
+ GPIO_NC, /* S517 - NC */
+ GPIO_FUNC0, /* S518 - SUS_STAT# */
+ GPIO_FUNC0, /* S519 - USB_OC0# */
+ GPIO_FUNC0, /* S520 - USB_OC1# */
+ GPIO_NC, /* S521 - NC */
+ GPIO_NC, /* S522 - XDP_GPIO_DFX0 */
+ GPIO_NC, /* S523 - XDP_GPIO_DFX1 */
+ GPIO_NC, /* S524 - XDP_GPIO_DFX2 */
+ GPIO_NC, /* S525 - XDP_GPIO_DFX3 */
+ GPIO_NC, /* S526 - XDP_GPIO_DFX4 */
+ GPIO_NC, /* S527 - XDP_GPIO_DFX5 */
+ GPIO_NC, /* S528 - XDP_GPIO_DFX6 */
+ GPIO_NC, /* S529 - XDP_GPIO_DFX7 */
+ GPIO_NC, /* S530 - XDP_GPIO_DFX8 */
+ GPIO_NC, /* S531 - NC */
+ GPIO_NC, /* S532 - NC */
+ GPIO_NC, /* S533 - NC */
+ GPIO_NC, /* S534 - NC */
+ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */
+ GPIO_NC, /* S536 - NC */
+ GPIO_INPUT, /* S537 - RAM_ID0 */
+ GPIO_INPUT, /* S538 - RAM_ID1 */
+ GPIO_INPUT, /* S539 - RAM_ID2 */
+ GPIO_NC, /* S540 - NC */
+ GPIO_NC, /* S541 - NC */
+ GPIO_NC, /* S542 - NC */
+ GPIO_NC, /* S543 - NC */
+ GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+ [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+ [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+ [ALS_IRQ_OFFSET] = ALS_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = gpncore_gpio_map,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map,
+ .core_dirq = &core_dedicated_irq,
+ .sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/google/quawks/irqroute.c b/src/mainboard/google/quawks/irqroute.c
new file mode 100644
index 0000000..db8c512
--- /dev/null
+++ b/src/mainboard/google/quawks/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/google/quawks/irqroute.h b/src/mainboard/google/quawks/irqroute.h
new file mode 100644
index 0000000..701eac3
--- /dev/null
+++ b/src/mainboard/google/quawks/irqroute.h
@@ -0,0 +1,60 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, DISABLE), \
+ PIRQ_PIC(B, DISABLE), \
+ PIRQ_PIC(C, DISABLE), \
+ PIRQ_PIC(D, DISABLE), \
+ PIRQ_PIC(E, DISABLE), \
+ PIRQ_PIC(F, DISABLE), \
+ PIRQ_PIC(G, DISABLE), \
+ PIRQ_PIC(H, DISABLE)
+
+/* CORE bank DIRQs - up to 16 supported */
+#define TPAD_IRQ_OFFSET 0
+#define TOUCH_IRQ_OFFSET 1
+#define I8042_IRQ_OFFSET 2
+#define ALS_IRQ_OFFSET 3
+/* Corresponding SCORE GPIO pins */
+#define TPAD_IRQ_GPIO 55
+#define TOUCH_IRQ_GPIO 72
+#define I8042_IRQ_GPIO 101
+#define ALS_IRQ_GPIO 70
+
+/* SUS bank DIRQs - up to 16 supported */
+#define CODEC_IRQ_OFFSET 0
+/* Corresponding SUS GPIO pins */
+#define CODEC_IRQ_GPIO 9
diff --git a/src/mainboard/google/quawks/mainboard.c b/src/mainboard/google/quawks/mainboard.c
new file mode 100644
index 0000000..adbfd96
--- /dev/null
+++ b/src/mainboard/google/quawks/mainboard.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <smbios.h>
+#include "ec.h"
+#include "onboard.h"
+#include <soc/gpio.h>
+#include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 1;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP (HDMI)
+ * bit 3 = LFP (eDP)*
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0008;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static int mainboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TOUCHSCREEN_NAME, /* name */
+ BOARD_TOUCHSCREEN_IRQ, /* instance */
+ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
+ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+static void edp_vdden_cb(void *unused)
+{
+ ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL);
diff --git a/src/mainboard/google/quawks/mainboard_smi.c b/src/mainboard/google/quawks/mainboard_smi.c
new file mode 100644
index 0000000..a3d5273
--- /dev/null
+++ b/src/mainboard/google/quawks/mainboard_smi.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+#include <soc/nvs.h>
+#include <soc/pmc.h>
+
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
+static uint8_t mainboard_smi_ec(void)
+{
+ uint8_t cmd = google_chromeec_get_event();
+ uint16_t pmbase = get_pmbase();
+ uint32_t pm1_cnt;
+
+#if CONFIG_ELOG_GSMI
+ /* Log this event */
+ if (cmd)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+ switch (cmd) {
+ case EC_HOST_EVENT_LID_CLOSED:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
+{
+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != 0);
+ }
+}
+
+void mainboard_smi_sleep(uint8_t slp_typ)
+{
+ /* Disable USB charging if required */
+ switch (slp_typ) {
+ case 3:
+ if (smm_get_gnvs()->s3u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s3u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+ /* Enable wake pin in GPE block. */
+ enable_gpe(WAKE_GPIO_EN);
+ break;
+ case 5:
+ if (smm_get_gnvs()->s5u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s5u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+ break;
+ }
+
+ /* Disable SCI and SMI events */
+ google_chromeec_set_smi_mask(0);
+ google_chromeec_set_sci_mask(0);
+
+ /* Clear pending events that may trigger immediate wake */
+ while (google_chromeec_get_event() != 0);
+}
+
+int mainboard_smi_apmc(uint8_t apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ google_chromeec_set_smi_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ google_chromeec_set_sci_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/quawks/onboard.h b/src/mainboard/google/quawks/onboard.h
new file mode 100644
index 0000000..04ed332
--- /dev/null
+++ b/src/mainboard/google/quawks/onboard.h
@@ -0,0 +1,40 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS 0
+#define BOARD_TRACKPAD_I2C_ADDR 0x4b
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS 5
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
+
+#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+#define BOARD_ALS_IRQ GPIO_S0_DED_IRQ(ALS_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/quawks/romstage.c b/src/mainboard/google/quawks/romstage.c
new file mode 100644
index 0000000..610980e
--- /dev/null
+++ b/src/mainboard/google/quawks/romstage.c
@@ -0,0 +1,99 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz
+ * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz
+ * 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz
+ * 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBR 1600MHz
+ */
+static const uint32_t dual_channel_config =
+ (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+{
+ int ram_id = 0;
+
+ /* The ram_id[2:0] pullups on quawks are too large for the default 20K
+ * pulldown on the pad. Therefore, disable the internal pull resistor to
+ * read high values correctly. */
+ ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
+ ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
+ ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
+
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+
+ printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+
+ if (ram_id >= total_spds)
+ return NULL;
+
+ /* Single channel configs */
+ if (dual_channel_config & (1 << ram_id))
+ *dual = 1;
+
+ return &spd_file_content[SPD_SIZE * ram_id];
+}
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ void *spd_content;
+ int dual_channel = 0;
+ void *spd_file;
+ size_t spd_fsize;
+
+ struct mrc_params mp = {
+ .mainboard = {
+ .dram_type = DRAM_DDR3L,
+ .dram_info_location = DRAM_INFO_SPD_MEM,
+ .weaker_odt_settings = 1,
+ },
+ };
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_fsize);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ /* Both channels are always present. */
+ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+ &dual_channel);
+ mp.mainboard.dram_data[0] = spd_content;
+ if (dual_channel)
+ mp.mainboard.dram_data[1] = spd_content;
+
+ rp->mrc_params = ∓
+ romstage_common(rp);
+}
diff --git a/src/mainboard/google/quawks/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex b/src/mainboard/google/quawks/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
new file mode 100644
index 0000000..8ced790
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/Hynix_HMT425S6CFR6A_H5TC4G63CFR.spd.hex
@@ -0,0 +1,17 @@
+# Hynix HMT425S6CFR6A-PBA
+92 13 0B 03 04 19 02 02 03 52 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 62 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 AD 01 00 00 00 00 00 00 C9 C0
+48 4D 54 34 32 35 53 36 43 46 52 36 41 2D 50 42
+20 20 4E 30 80 AD 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/quawks/spd/Makefile.inc b/src/mainboard/google/quawks/spd/Makefile.inc
new file mode 100644
index 0000000..7873bcf
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/Makefile.inc
@@ -0,0 +1,49 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 4GiB total - 2 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
+# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz
+# 0b100 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b110 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBR 1600MHz
+# 0b111 - 2GiB total - 1 x 2GiB Hynix H5TC4G63CFR-PBA 1600MHz
+SPD_SOURCES = elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += Hynix_HMT425S6CFR6A_H5TC4G63CFR
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/quawks/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex b/src/mainboard/google/quawks/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
new file mode 100644
index 0000000..eb41f0b
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
@@ -0,0 +1,17 @@
+# Elpida EDJ4216EFBG-GN-F
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
+45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
+00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/quawks/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/quawks/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
new file mode 100644
index 0000000..4bd8e0e
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 03 11 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+00 05 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 22 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 41 5f
+48 4d 54 33 31 32 53 36
+44 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/quawks/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/quawks/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000..ff4fd29
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/quawks/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/quawks/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
new file mode 100644
index 0000000..f99c92a
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 03 11 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+50 00 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 6a 15
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/quawks/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/quawks/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000..f3bcb56
--- /dev/null
+++ b/src/mainboard/google/quawks/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/quawks/w25q64.c b/src/mainboard/google/quawks/w25q64.c
new file mode 100644
index 0000000..a9ed8ac
--- /dev/null
+++ b/src/mainboard/google/quawks/w25q64.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/spi.h>
+
+/*
+ * SPI lockdown configuration W25Q64FW.
+ */
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+ (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+ (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+ .preop = SPI_OPPREFIX,
+ .optype = SPI_OPTYPE,
+ .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+ .lvscc = SPI_VSCC,
+ .uvscc = SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+ memcpy(cfg, &spi_config, sizeof(*cfg));
+
+ return 0;
+}
1
0
Patch set updated for coreboot: google/swanky: Upstream Toshiba Chromebook 2 (2014)
by Patrick Georgi 21 Sep '16
by Patrick Georgi 21 Sep '16
21 Sep '16
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15442
-gerrit
commit 81615c9af9cfaaa58cb11648f37f23e0246d5e0a
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Tue May 31 02:36:58 2016 -0500
google/swanky: Upstream Toshiba Chromebook 2 (2014)
Migrate google/swanky (Toshiba Chromebook 2 / 2014) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-swanky-5216.238.B
commit 233b2a7 [Swanky: update SPD table]
TEST=built and booted Linux on swanky with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: Ib9399b6df19b4111ee1e0ae62de793953efeb89a
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/swanky/Kconfig | 50 ++++
src/mainboard/google/swanky/Kconfig.name | 2 +
src/mainboard/google/swanky/Makefile.inc | 25 ++
src/mainboard/google/swanky/acpi/dptf.asl | 87 ++++++
src/mainboard/google/swanky/acpi/ec.asl | 20 ++
src/mainboard/google/swanky/acpi/mainboard.asl | 325 +++++++++++++++++++++
src/mainboard/google/swanky/acpi/superio.asl | 27 ++
src/mainboard/google/swanky/acpi/video.asl | 39 +++
src/mainboard/google/swanky/acpi_tables.c | 64 ++++
src/mainboard/google/swanky/board_info.txt | 3 +
src/mainboard/google/swanky/chromeos.c | 123 ++++++++
src/mainboard/google/swanky/chromeos.fmd | 38 +++
src/mainboard/google/swanky/cmos.layout | 133 +++++++++
src/mainboard/google/swanky/devicetree.cb | 101 +++++++
src/mainboard/google/swanky/dsdt.asl | 53 ++++
src/mainboard/google/swanky/ec.c | 48 +++
src/mainboard/google/swanky/ec.h | 62 ++++
src/mainboard/google/swanky/fadt.c | 46 +++
src/mainboard/google/swanky/gpio.c | 230 +++++++++++++++
src/mainboard/google/swanky/irqroute.c | 18 ++
src/mainboard/google/swanky/irqroute.h | 59 ++++
src/mainboard/google/swanky/mainboard.c | 183 ++++++++++++
src/mainboard/google/swanky/mainboard_smi.c | 121 ++++++++
src/mainboard/google/swanky/onboard.h | 36 +++
src/mainboard/google/swanky/romstage.c | 95 ++++++
src/mainboard/google/swanky/spd/Makefile.inc | 41 +++
.../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 ++
.../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 17 ++
src/mainboard/google/swanky/w25q64.c | 70 +++++
29 files changed, 2148 insertions(+)
diff --git a/src/mainboard/google/swanky/Kconfig b/src/mainboard/google/swanky/Kconfig
new file mode 100644
index 0000000..53e45ad
--- /dev/null
+++ b/src/mainboard/google/swanky/Kconfig
@@ -0,0 +1,50 @@
+if BOARD_GOOGLE_SWANKY
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_BAYTRAIL
+ select EC_GOOGLE_CHROMEEC
+ select ENABLE_BUILTIN_COM1
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+
+config CHROMEOS
+ select VBOOT_VBNV_CMOS
+ select LID_SWITCH
+ select EC_SOFTWARE_SYNC
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/swanky
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Swanky"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0f31.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ string
+ default ""
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "SWANKY TEST A-A 0128"
+
+endif # BOARD_GOOGLE_SWANKY
diff --git a/src/mainboard/google/swanky/Kconfig.name b/src/mainboard/google/swanky/Kconfig.name
new file mode 100644
index 0000000..900bab5
--- /dev/null
+++ b/src/mainboard/google/swanky/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_SWANKY
+ bool "Swanky"
diff --git a/src/mainboard/google/swanky/Makefile.inc b/src/mainboard/google/swanky/Makefile.inc
new file mode 100644
index 0000000..2a9475c
--- /dev/null
+++ b/src/mainboard/google/swanky/Makefile.inc
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += irqroute.c
+ramstage-y += w25q64.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/google/swanky/acpi/dptf.asl b/src/mainboard/google/swanky/acpi/dptf.asl
new file mode 100644
index 0000000..cf82fa6
--- /dev/null
+++ b/src/mainboard/google/swanky/acpi/dptf.asl
@@ -0,0 +1,87 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Internal"
+#define DPTF_TSR0_PASSIVE 48
+#define DPTF_TSR0_CRITICAL 70
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top"
+#define DPTF_TSR1_PASSIVE 60
+#define DPTF_TSR1_CRITICAL 70
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 55
+#define DPTF_TSR2_CRITICAL 70
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x6a4, "mA", 0 }, /* 1.7A (MAX) */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, // Revision
+ Package () { // Power Limit 1
+ 0, // PowerLimitIndex, 0 for Power Limit 1
+ 1600, // PowerLimitMinimum
+ 6200, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 200 // StepSize
+ },
+ Package () { // Power Limit 2
+ 1, // PowerLimitIndex, 1 for Power Limit 2
+ 8000, // PowerLimitMinimum
+ 8000, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 1000 // StepSize
+ }
+})
+
+/* Include Baytrail DPTF */
+#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/swanky/acpi/ec.asl b/src/mainboard/google/swanky/acpi/ec.asl
new file mode 100644
index 0000000..2d76142
--- /dev/null
+++ b/src/mainboard/google/swanky/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/swanky/ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/swanky/acpi/mainboard.asl b/src/mainboard/google/swanky/acpi/mainboard.asl
new file mode 100644
index 0000000..9546931
--- /dev/null
+++ b/src/mainboard/google/swanky/acpi/mainboard.asl
@@ -0,0 +1,325 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/swanky/onboard.h>
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (_UID, 1)
+ }
+
+ /* Wake device for touchpad */
+ Device (TPAD)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 1)
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Return interrupt if I2C1 is PCI mode */
+ If (LEqual (\S1EN, 0)) {
+ Return (^RBUF)
+ }
+
+ /* Return empty resource template otherwise */
+ Return (ResourceTemplate() {})
+ }
+ }
+
+ /* Wake device for touchscreen */
+ Device (TSCR)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 2)
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Return interrupt if I2C6 is PCI mode */
+ If (LEqual (\S6EN, 0)) {
+ Return (^RBUF)
+ }
+
+ /* Return empty resource template otherwise */
+ Return (ResourceTemplate() {})
+ }
+ }
+}
+
+Scope (\_SB.I2C1)
+{
+ Device (ATPB)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad Bootloader")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x25, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ATPA)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad")
+ Name (_UID, 2)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4b, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x15, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.I2C2)
+{
+ Device (CODC)
+ {
+ /*
+ * TODO(dlaurie): Need official HID.
+ *
+ * The current HID is created from the Maxim Integrated
+ * PCI Vendor ID 193Ch and a shortened device identifier.
+ */
+ Name (_HID, "193C9890")
+ Name (_DDN, "Maxim 98090 Codec")
+ Name (_UID, 1)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x10, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C2", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_CODEC_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.I2C6)
+{
+ Device (ATSB)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen Bootloader")
+ Name (_UID, 4)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x26, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ATSA)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen")
+ Name (_UID, 5)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4a, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 14 }
+
+ /* Mic Detect (index 1) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 15 }
+ })
+}
diff --git a/src/mainboard/google/swanky/acpi/superio.asl b/src/mainboard/google/swanky/acpi/superio.asl
new file mode 100644
index 0000000..4ca2fc8
--- /dev/null
+++ b/src/mainboard/google/swanky/acpi/superio.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/swanky/ec.h>
+#include <mainboard/google/swanky/onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+// Override default IRQ settings
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/swanky/acpi/video.asl b/src/mainboard/google/swanky/acpi/video.asl
new file mode 100644
index 0000000..1405b04
--- /dev/null
+++ b/src/mainboard/google/swanky/acpi/video.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/swanky/acpi_tables.c b/src/mainboard/google/swanky/acpi_tables.c
new file mode 100644
index 0000000..c647c9b
--- /dev/null
+++ b/src/mainboard/google/swanky/acpi_tables.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 1;
+
+ /* Enable DPTF */
+ gnvs->dpte = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/src/mainboard/google/swanky/board_info.txt b/src/mainboard/google/swanky/board_info.txt
new file mode 100644
index 0000000..3e630d3
--- /dev/null
+++ b/src/mainboard/google/swanky/board_info.txt
@@ -0,0 +1,3 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: y
diff --git a/src/mainboard/google/swanky/chromeos.c b/src/mainboard/google/swanky/chromeos.c
new file mode 100644
index 0000000..e8f96ae
--- /dev/null
+++ b/src/mainboard/google/swanky/chromeos.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <bootmode.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#endif
+
+/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
+#define WP_STATUS_PAD 36
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif
+
+int get_lid_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+
+ return !!(ec_switches & EC_SWITCH_LID_OPEN);
+#else
+ /* Default to force open. */
+ return 1;
+#endif
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+ u32 ec_events;
+
+ /* If a switch is set, we don't need to look at events. */
+ if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
+ return 1;
+
+ /* Else check if the EC has posted the keyboard recovery event. */
+ ec_events = google_chromeec_get_events_b();
+
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+ return 0;
+#endif
+}
+
+int clear_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+#else
+ return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+ /*
+ * The vboot loader queries this function in romstage. The GPIOs have
+ * not been set up yet as that configuration is done in ramstage. The
+ * hardware defaults to an input but there is a 20K pulldown. Externally
+ * there is a 10K pullup. Disable the internal pull in romstage so that
+ * there isn't any ambiguity in the reading.
+ */
+#if defined(__PRE_RAM__)
+ ssus_disable_internal_pull(WP_STATUS_PAD);
+#endif
+
+ /* WP is enabled when the pin is reading high. */
+ return ssus_get_gpio(WP_STATUS_PAD);
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/swanky/chromeos.fmd b/src/mainboard/google/swanky/chromeos.fmd
new file mode 100644
index 0000000..113fba6
--- /dev/null
+++ b/src/mainboard/google/swanky/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0x600000 {
+ RW_SECTION_A@0x0 0xf0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0xdffc0
+ RW_FWID_A@0xeffc0 0x40
+ }
+ RW_SECTION_B@0xf0000 0xf0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0xdffc0
+ RW_FWID_B@0xeffc0 0x40
+ }
+ RW_MRC_CACHE@0x1e0000 0x10000
+ RW_ELOG@0x1f0000 0x4000
+ RW_SHARED@0x1f4000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x1f8000 0x2000
+ RW_UNUSED@0x1fa000 0x6000
+ RW_LEGACY(CBFS)@0x200000 0x200000
+ WP_RO@0x400000 0x200000 {
+ RO_VPD@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x1f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x100000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/swanky/cmos.layout b/src/mainboard/google/swanky/cmos.layout
new file mode 100644
index 0000000..b419315
--- /dev/null
+++ b/src/mainboard/google/swanky/cmos.layout
@@ -0,0 +1,133 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/google/swanky/devicetree.cb b/src/mainboard/google/swanky/devicetree.cb
new file mode 100644
index 0000000..5e78a10
--- /dev/null
+++ b/src/mainboard/google/swanky/devicetree.cb
@@ -0,0 +1,101 @@
+chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
+ # Route USB ports to XHCI
+ register "usb_route_to_xhci" = "1"
+
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+
+ # USB PHY settings
+ # TODO: These values are from Baytrail and need tuned for Swanky board
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+ # LPE audio codec settings
+ register "lpe_codec_clk_freq" = "25" # 25MHz clock
+ register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+
+ # SD Card controller
+ register "sdcard_cap_low" = "0x036864b2"
+ register "sdcard_cap_high" = "0x0"
+
+ # Enable devices in ACPI mode
+ register "lpe_acpi_mode" = "1"
+ register "lpss_acpi_mode" = "1"
+ register "scc_acpi_mode" = "1"
+
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+
+ # Enable PIPEA as DP_C
+ register "gpu_pipea_port_select" = "2" # DP_C
+ register "gpu_pipea_power_cycle_delay" = "6" # 600ms
+ register "gpu_pipea_power_on_delay" = "5000" # 500ms
+ register "gpu_pipea_light_on_delay" = "70" # 7ms
+ register "gpu_pipea_power_off_delay" = "500" # 50ms
+ register "gpu_pipea_light_off_delay" = "2000" # 200ms
+
+ # VR PS2 control
+ register "vnn_ps2_enable" = "1"
+ register "vcc_ps2_enable" = "1"
+
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 off end # HSUART2
+ device pci 1e.5 off end # SPI
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC Bridge
+ device pci 1f.3 off end # SMBus
+ end
+end
diff --git a/src/mainboard/google/swanky/dsdt.asl b/src/mainboard/google/swanky/dsdt.asl
new file mode 100644
index 0000000..a37756f
--- /dev/null
+++ b/src/mainboard/google/swanky/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/baytrail/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+ #include <soc/intel/baytrail/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <soc/intel/baytrail/acpi/northcluster.asl>
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
+
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/baytrail/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/swanky/ec.c b/src/mainboard/google/swanky/ec.c
new file mode 100644
index 0000000..27fcb0f
--- /dev/null
+++ b/src/mainboard/google/swanky/ec.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ printk(BIOS_DEBUG, "mainboard_ec_init\n");
+ post_code(0xf0);
+
+ /* Restore SCI event mask on resume. */
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ }
+
+ /* Clear wake events, these are enabled on entry to sleep */
+ google_chromeec_set_wake_mask(0);
+
+ post_code(0xf1);
+}
diff --git a/src/mainboard/google/swanky/ec.h b/src/mainboard/google/swanky/ec.h
new file mode 100644
index 0000000..159351b
--- /dev/null
+++ b/src/mainboard/google/swanky/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+#define EC_SCI_GPI 24
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI 23
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/swanky/fadt.c b/src/mainboard/google/swanky/fadt.c
new file mode 100644
index 0000000..2434d1a
--- /dev/null
+++ b/src/mainboard/google/swanky/fadt.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/swanky/gpio.c b/src/mainboard/google/swanky/gpio.c
new file mode 100644
index 0000000..f999da2
--- /dev/null
+++ b/src/mainboard/google/swanky/gpio.c
@@ -0,0 +1,230 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include "irqroute.h"
+
+/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */
+ GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */
+ GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */
+ GPIO_NC, /* S0_NC03 - NC */
+ GPIO_NC, /* S0_NC04 - NC */
+ GPIO_NC, /* S0_NC05 - NC */
+ GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */
+ GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */
+ GPIO_NC, /* S0_NC08 - NC */
+ GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */
+ GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */
+ GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */
+ GPIO_NC, /* S0_NC12 - NC */
+ GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */
+ GPIO_NC, /* S0_NC14 - NC */
+ GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */
+ GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */
+ GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */
+ GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */
+ GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */
+ GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */
+ GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */
+ GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */
+ GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */
+ GPIO_NC, /* S0_NC24 - NC */
+ GPIO_NC, /* S0_NC25 - NC */
+ GPIO_NC, /* S0_NC26 - NC */
+ GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */
+ GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */
+ GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */
+ GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+ GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */
+ GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+ GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */
+ GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+ GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */
+ GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */
+ GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */
+ GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */
+ GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+ GPIO_NC, /* S0-SC013 - NC */
+ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */
+ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */
+ GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */
+ GPIO_NC, /* S0-SC027 - NC */
+ GPIO_NC, /* S0-SC028 - NC */
+ GPIO_NC, /* S0-SC029 - NC */
+ GPIO_NC, /* S0-SC030 - NC */
+ GPIO_NC, /* S0-SC031 - NC */
+ GPIO_NC, /* S0-SC032 - NC */
+ GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */
+ GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */
+ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */
+ GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */
+ GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */
+ GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */
+ GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */
+ GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
+ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
+ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
+ GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */
+ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
+ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
+ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
+ GPIO_DEFAULT, /* S0-SC054 - NC */
+ GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */
+ GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+ GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */
+ GPIO_INPUT, /* S0-SC058 - SIM_DET_C */
+ GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */
+ GPIO_NC, /* S0-SC060 - NC */
+ GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */
+ GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */
+ GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */
+ GPIO_FUNC1, /* S0-SC064 - I2S_DIN */
+ GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */
+ GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */
+ GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */
+ GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */
+ GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */
+ GPIO_NC, /* S0-SC070 - ALS_INT_L - INT(NC) */
+ GPIO_NC, /* S0-SC071 - NC */
+ GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */
+ GPIO_NC, /* S0-SC073 - NC */
+ GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */
+ GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */
+ GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */
+ GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */
+ GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */
+ GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */
+ GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */
+ GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */
+ GPIO_NC, /* S0-SC082 - NC */
+ GPIO_NC, /* S0-SC083 - NC */
+ GPIO_NC, /* S0-SC084 - NC */
+ GPIO_NC, /* S0-SC085 - NC */
+ GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */
+ GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */
+ GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */
+ GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */
+ GPIO_NC, /* S0-SC090 - NC */
+ GPIO_NC, /* S0-SC091 - NC */
+ GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+ GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+ GPIO_NC, /* S0-SC094 - NC */
+ GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */
+ GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */
+ GPIO_NC, /* S0-SC097 - NC */
+ GPIO_NC, /* S0-SC098 - NC */
+ GPIO_NC, /* S0-SC099 - NC */
+ GPIO_NC, /* S0-SC100 - NC */
+ GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */
+ GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */
+ GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */
+ GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */
+ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
+ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
+ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
+ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
+ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
+ GPIO_NC, /* S508 - NC */
+ GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */
+ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */
+ GPIO_FUNC0, /* S511 - SUSPWRDNACK */
+ GPIO_FUNC0, /* S512 - WIFI_SUSCLK */
+ GPIO_FUNC0, /* S513 - SLP_SX */
+ GPIO_NC, /* S514 - NC */
+ GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */
+ GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */
+ GPIO_NC, /* S517 - NC */
+ GPIO_FUNC0, /* S518 - SUS_STAT# */
+ GPIO_FUNC0, /* S519 - USB_OC0# */
+ GPIO_FUNC0, /* S520 - USB_OC1# */
+ GPIO_NC, /* S521 - NC */
+ GPIO_NC, /* S522 - XDP_GPIO_DFX0 */
+ GPIO_NC, /* S523 - XDP_GPIO_DFX1 */
+ GPIO_NC, /* S524 - XDP_GPIO_DFX2 */
+ GPIO_NC, /* S525 - XDP_GPIO_DFX3 */
+ GPIO_NC, /* S526 - XDP_GPIO_DFX4 */
+ GPIO_NC, /* S527 - XDP_GPIO_DFX5 */
+ GPIO_NC, /* S528 - XDP_GPIO_DFX6 */
+ GPIO_NC, /* S529 - XDP_GPIO_DFX7 */
+ GPIO_NC, /* S530 - XDP_GPIO_DFX8 */
+ GPIO_NC, /* S531 - NC */
+ GPIO_NC, /* S532 - NC */
+ GPIO_NC, /* S533 - NC */
+ GPIO_NC, /* S534 - NC */
+ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */
+ GPIO_NC, /* S536 - NC */
+ GPIO_INPUT, /* S537 - RAM_ID0 */
+ GPIO_INPUT, /* S538 - RAM_ID1 */
+ GPIO_INPUT, /* S539 - RAM_ID2 */
+ GPIO_NC, /* S540 - NC */
+ GPIO_INPUT, /* S541 - PANEL_ID */
+ GPIO_NC, /* S542 - NC */
+ GPIO_NC, /* S543 - NC */
+ GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+ [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+ [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = gpncore_gpio_map,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map,
+ .core_dirq = &core_dedicated_irq,
+ .sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/google/swanky/irqroute.c b/src/mainboard/google/swanky/irqroute.c
new file mode 100644
index 0000000..db8c512
--- /dev/null
+++ b/src/mainboard/google/swanky/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/google/swanky/irqroute.h b/src/mainboard/google/swanky/irqroute.h
new file mode 100644
index 0000000..6e91946
--- /dev/null
+++ b/src/mainboard/google/swanky/irqroute.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, DISABLE), \
+ PIRQ_PIC(B, DISABLE), \
+ PIRQ_PIC(C, DISABLE), \
+ PIRQ_PIC(D, DISABLE), \
+ PIRQ_PIC(E, DISABLE), \
+ PIRQ_PIC(F, DISABLE), \
+ PIRQ_PIC(G, DISABLE), \
+ PIRQ_PIC(H, DISABLE)
+
+/* CORE bank DIRQs - up to 16 supported */
+#define TPAD_IRQ_OFFSET 0
+#define TOUCH_IRQ_OFFSET 1
+#define I8042_IRQ_OFFSET 2
+
+/* Corresponding SCORE GPIO pins */
+#define TPAD_IRQ_GPIO 55
+#define TOUCH_IRQ_GPIO 72
+#define I8042_IRQ_GPIO 101
+
+/* SUS bank DIRQs - up to 16 supported */
+#define CODEC_IRQ_OFFSET 0
+/* Corresponding SUS GPIO pins */
+#define CODEC_IRQ_GPIO 9
diff --git a/src/mainboard/google/swanky/mainboard.c b/src/mainboard/google/swanky/mainboard.c
new file mode 100644
index 0000000..adbfd96
--- /dev/null
+++ b/src/mainboard/google/swanky/mainboard.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2011 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <smbios.h>
+#include "ec.h"
+#include "onboard.h"
+#include <soc/gpio.h>
+#include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 1;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP (HDMI)
+ * bit 3 = LFP (eDP)*
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0008;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static int mainboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TOUCHSCREEN_NAME, /* name */
+ BOARD_TOUCHSCREEN_IRQ, /* instance */
+ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
+ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+static void edp_vdden_cb(void *unused)
+{
+ ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL);
diff --git a/src/mainboard/google/swanky/mainboard_smi.c b/src/mainboard/google/swanky/mainboard_smi.c
new file mode 100644
index 0000000..a3d5273
--- /dev/null
+++ b/src/mainboard/google/swanky/mainboard_smi.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+#include <soc/nvs.h>
+#include <soc/pmc.h>
+
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
+static uint8_t mainboard_smi_ec(void)
+{
+ uint8_t cmd = google_chromeec_get_event();
+ uint16_t pmbase = get_pmbase();
+ uint32_t pm1_cnt;
+
+#if CONFIG_ELOG_GSMI
+ /* Log this event */
+ if (cmd)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+ switch (cmd) {
+ case EC_HOST_EVENT_LID_CLOSED:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
+{
+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != 0);
+ }
+}
+
+void mainboard_smi_sleep(uint8_t slp_typ)
+{
+ /* Disable USB charging if required */
+ switch (slp_typ) {
+ case 3:
+ if (smm_get_gnvs()->s3u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s3u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+ /* Enable wake pin in GPE block. */
+ enable_gpe(WAKE_GPIO_EN);
+ break;
+ case 5:
+ if (smm_get_gnvs()->s5u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s5u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+ break;
+ }
+
+ /* Disable SCI and SMI events */
+ google_chromeec_set_smi_mask(0);
+ google_chromeec_set_sci_mask(0);
+
+ /* Clear pending events that may trigger immediate wake */
+ while (google_chromeec_get_event() != 0);
+}
+
+int mainboard_smi_apmc(uint8_t apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ google_chromeec_set_smi_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ google_chromeec_set_sci_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/swanky/onboard.h b/src/mainboard/google/swanky/onboard.h
new file mode 100644
index 0000000..7b55cd4
--- /dev/null
+++ b/src/mainboard/google/swanky/onboard.h
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS 0
+#define BOARD_TRACKPAD_I2C_ADDR 0x4b
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS 5
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
+
+#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/swanky/romstage.c b/src/mainboard/google/swanky/romstage.c
new file mode 100644
index 0000000..b398c92
--- /dev/null
+++ b/src/mainboard/google/swanky/romstage.c
@@ -0,0 +1,95 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ */
+static const uint32_t dual_channel_config =
+ (1 << 2) | (1 << 3);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+
+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+{
+ int ram_id = 0;
+
+ /* The ram_id[2:0] pullups on Swanky are too large for the default 20K
+ * pulldown on the pad. Therefore, disable the internal pull resistor to
+ * read high values correctly. */
+ ssus_disable_internal_pull(GPIO_SSUS_37_PAD);
+ ssus_disable_internal_pull(GPIO_SSUS_38_PAD);
+ ssus_disable_internal_pull(GPIO_SSUS_39_PAD);
+
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+
+ printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+
+ if (ram_id >= total_spds)
+ return NULL;
+
+ /* Single channel configs */
+ if (dual_channel_config & (1 << ram_id))
+ *dual = 1;
+
+ return &spd_file_content[SPD_SIZE * ram_id];
+}
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ void *spd_content;
+ int dual_channel = 0;
+ void *spd_file;
+ size_t spd_fsize;
+
+ struct mrc_params mp = {
+ .mainboard = {
+ .dram_type = DRAM_DDR3L,
+ .dram_info_location = DRAM_INFO_SPD_MEM,
+ .weaker_odt_settings = 1,
+ },
+ };
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_fsize);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ /* Both channels are always present. */
+ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+ &dual_channel);
+ mp.mainboard.dram_data[0] = spd_content;
+ if (dual_channel)
+ mp.mainboard.dram_data[1] = spd_content;
+
+ rp->mrc_params = ∓
+ romstage_common(rp);
+}
diff --git a/src/mainboard/google/swanky/spd/Makefile.inc b/src/mainboard/google/swanky/spd/Makefile.inc
new file mode 100644
index 0000000..0158ba2
--- /dev/null
+++ b/src/mainboard/google/swanky/spd/Makefile.inc
@@ -0,0 +1,41 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b000 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b001 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b010 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b011 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+SPD_SOURCES = samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/swanky/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/swanky/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000..ff4fd29
--- /dev/null
+++ b/src/mainboard/google/swanky/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/swanky/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/swanky/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 0000000..ac9a0e0
--- /dev/null
+++ b/src/mainboard/google/swanky/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646Q-HYK0
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/swanky/w25q64.c b/src/mainboard/google/swanky/w25q64.c
new file mode 100644
index 0000000..a9ed8ac
--- /dev/null
+++ b/src/mainboard/google/swanky/w25q64.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/spi.h>
+
+/*
+ * SPI lockdown configuration W25Q64FW.
+ */
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+ (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+ (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+ .preop = SPI_OPPREFIX,
+ .optype = SPI_OPTYPE,
+ .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+ .lvscc = SPI_VSCC,
+ .uvscc = SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+ memcpy(cfg, &spi_config, sizeof(*cfg));
+
+ return 0;
+}
1
0
Patch set updated for coreboot: google/glimmer: Upstream Lenovo Thinkpad 11e Chromebook
by Patrick Georgi 21 Sep '16
by Patrick Georgi 21 Sep '16
21 Sep '16
Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15445
-gerrit
commit e6e0f718fa4109a42ec3464c47230cfc76a6614e
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Fri Jun 3 10:53:57 2016 -0500
google/glimmer: Upstream Lenovo Thinkpad 11e Chromebook
Migrate google/glimmer (Lenovo Thinkpad 11e Chromebook) from Chromium tree to
upstream, using google/rambi as a reference.
original source:
branch firmware-glimmer-5216.198.B
commit fae0770 [baytrail: add code for supporting dual channel 2x ddr ...]
TEST=built and booted Linux on glimmer with full functionality
blobs required for working image:
VGA BIOS (vgabios.bin)
firmware descriptor (ifd.bin)
Intel ME firmware (me.bin)
MRC (mrc.elf)
external reference code (refcode.elf)
Change-Id: Ic13bd5826a7a83bc30c51b48bfce736445ba07ea
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/glimmer/Kconfig | 50 ++++
src/mainboard/google/glimmer/Kconfig.name | 2 +
src/mainboard/google/glimmer/Makefile.inc | 25 ++
src/mainboard/google/glimmer/acpi/dptf.asl | 88 ++++++
src/mainboard/google/glimmer/acpi/ec.asl | 20 ++
src/mainboard/google/glimmer/acpi/mainboard.asl | 326 +++++++++++++++++++++
src/mainboard/google/glimmer/acpi/superio.asl | 27 ++
src/mainboard/google/glimmer/acpi/video.asl | 39 +++
src/mainboard/google/glimmer/acpi_tables.c | 64 ++++
src/mainboard/google/glimmer/board_info.txt | 3 +
src/mainboard/google/glimmer/chromeos.c | 123 ++++++++
src/mainboard/google/glimmer/chromeos.fmd | 38 +++
src/mainboard/google/glimmer/cmos.layout | 133 +++++++++
src/mainboard/google/glimmer/devicetree.cb | 98 +++++++
src/mainboard/google/glimmer/dsdt.asl | 53 ++++
src/mainboard/google/glimmer/ec.c | 48 +++
src/mainboard/google/glimmer/ec.h | 62 ++++
src/mainboard/google/glimmer/fadt.c | 46 +++
src/mainboard/google/glimmer/gpio.c | 232 +++++++++++++++
src/mainboard/google/glimmer/irqroute.c | 18 ++
src/mainboard/google/glimmer/irqroute.h | 59 ++++
src/mainboard/google/glimmer/mainboard.c | 183 ++++++++++++
src/mainboard/google/glimmer/mainboard_smi.c | 121 ++++++++
src/mainboard/google/glimmer/onboard.h | 39 +++
src/mainboard/google/glimmer/romstage.c | 115 ++++++++
src/mainboard/google/glimmer/spd/Makefile.inc | 55 ++++
.../spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex | 16 +
.../spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex | 32 ++
.../spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex | 32 ++
.../spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex | 32 ++
.../spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex | 32 ++
.../spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex | 17 ++
.../spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex | 17 ++
src/mainboard/google/glimmer/w25q64.c | 70 +++++
34 files changed, 2315 insertions(+)
diff --git a/src/mainboard/google/glimmer/Kconfig b/src/mainboard/google/glimmer/Kconfig
new file mode 100644
index 0000000..28a8af0
--- /dev/null
+++ b/src/mainboard/google/glimmer/Kconfig
@@ -0,0 +1,50 @@
+if BOARD_GOOGLE_GLIMMER
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_BAYTRAIL
+ select EC_GOOGLE_CHROMEEC
+ select ENABLE_BUILTIN_COM1
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select HAVE_ACPI_RESUME
+ select MAINBOARD_HAS_CHROMEOS
+ select MAINBOARD_HAS_LPC_TPM
+
+config CHROMEOS
+ select VBOOT_VBNV_CMOS
+ select LID_SWITCH
+ select EC_SOFTWARE_SYNC
+ select VIRTUAL_DEV_SWITCH
+
+config MAINBOARD_DIR
+ string
+ default google/glimmer
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Glimmer"
+
+config VGA_BIOS_FILE
+ string
+ default "pci8086,0f31.rom"
+
+config HAVE_IFD_BIN
+ bool
+ default n
+
+config HAVE_ME_BIN
+ bool
+ default n
+
+config EC_GOOGLE_CHROMEEC_BOARDNAME
+ string
+ default ""
+
+config GBB_HWID
+ string
+ depends on CHROMEOS
+ default "GLIMMER TEST A-A 0128"
+
+endif # BOARD_GOOGLE_GLIMMER
diff --git a/src/mainboard/google/glimmer/Kconfig.name b/src/mainboard/google/glimmer/Kconfig.name
new file mode 100644
index 0000000..67d0b20
--- /dev/null
+++ b/src/mainboard/google/glimmer/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_GOOGLE_GLIMMER
+ bool "Glimmer"
diff --git a/src/mainboard/google/glimmer/Makefile.inc b/src/mainboard/google/glimmer/Makefile.inc
new file mode 100644
index 0000000..da7053a
--- /dev/null
+++ b/src/mainboard/google/glimmer/Makefile.inc
@@ -0,0 +1,25 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += gpio.c
+ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
+ramstage-y += irqroute.c
+ramstage-y += w25q64.c
+
+smm-$(CONFIG_HAVE_SMI_HANDLER) += mainboard_smi.c
diff --git a/src/mainboard/google/glimmer/acpi/dptf.asl b/src/mainboard/google/glimmer/acpi/dptf.asl
new file mode 100644
index 0000000..8a15b08
--- /dev/null
+++ b/src/mainboard/google/glimmer/acpi/dptf.asl
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define DPTF_CPU_PASSIVE 80
+#define DPTF_CPU_CRITICAL 90
+
+#define DPTF_TSR0_SENSOR_ID 1
+#define DPTF_TSR0_SENSOR_NAME "TMP432_Power_Bottom"
+#define DPTF_TSR0_PASSIVE 75
+#define DPTF_TSR0_CRITICAL 80
+
+#define DPTF_TSR1_SENSOR_ID 2
+#define DPTF_TSR1_SENSOR_NAME "TMP432_RAM_bottom"
+#define DPTF_TSR1_PASSIVE 75
+#define DPTF_TSR1_CRITICAL 80
+
+#define DPTF_TSR2_SENSOR_ID 3
+#define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom"
+#define DPTF_TSR2_PASSIVE 75
+#define DPTF_TSR2_CRITICAL 80
+
+#define DPTF_ENABLE_CHARGER
+
+/* Charger performance states, board-specific values from charger and EC */
+Name (CHPS, Package () {
+ Package () { 0, 0, 0, 0, 255, 0x8ca, "mA", 0 }, /* 2.25A (MAX) */
+ Package () { 0, 0, 0, 0, 32, 0x7d0, "mA", 0 }, /* 2.0A */
+ Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */
+ Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */
+ Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */
+ Package () { 0, 0, 0, 0, 0, 0x080, "mA", 0 }, /* 0.128A */
+})
+
+/* Mainboard specific _PDL is 1GHz */
+Name (MPDL, 8)
+
+Name (DTRT, Package () {
+ /* CPU Throttle Effect on CPU */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TCPU, 100, 50, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 0 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 },
+
+#ifdef DPTF_ENABLE_CHARGER
+ /* Charger Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 },
+#endif
+
+ /* CPU Effect on Temp Sensor 1 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 },
+
+ /* CPU Effect on Temp Sensor 2 */
+ Package () { \_SB.DPTF.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 },
+})
+
+Name (MPPC, Package ()
+{
+ 0x2, // Revision
+ Package () { // Power Limit 1
+ 0, // PowerLimitIndex, 0 for Power Limit 1
+ 1600, // PowerLimitMinimum
+ 6200, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 200 // StepSize
+ },
+ Package () { // Power Limit 2
+ 1, // PowerLimitIndex, 1 for Power Limit 2
+ 8000, // PowerLimitMinimum
+ 8000, // PowerLimitMaximum
+ 1000, // TimeWindowMinimum
+ 1000, // TimeWindowMaximum
+ 1000 // StepSize
+ }
+})
+
+/* Include Baytrail DPTF */
+#include <soc/intel/baytrail/acpi/dptf/dptf.asl>
diff --git a/src/mainboard/google/glimmer/acpi/ec.asl b/src/mainboard/google/glimmer/acpi/ec.asl
new file mode 100644
index 0000000..4b9c27c
--- /dev/null
+++ b/src/mainboard/google/glimmer/acpi/ec.asl
@@ -0,0 +1,20 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/glimmer/ec.h>
+
+/* ACPI code for EC functions */
+#include <ec/google/chromeec/acpi/ec.asl>
diff --git a/src/mainboard/google/glimmer/acpi/mainboard.asl b/src/mainboard/google/glimmer/acpi/mainboard.asl
new file mode 100644
index 0000000..a7a8b8e
--- /dev/null
+++ b/src/mainboard/google/glimmer/acpi/mainboard.asl
@@ -0,0 +1,326 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <mainboard/google/glimmer/onboard.h>
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name (_HID, EisaId ("PNP0C0D"))
+ Name (_PRW, Package() { BOARD_PCH_WAKE_GPIO, 0x5 })
+ Method (_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+ }
+
+ Device (PWRB)
+ {
+ Name (_HID, EisaId ("PNP0C0C"))
+ Name (_UID, 1)
+ }
+
+ /* Wake device for touchpad */
+ Device (TPAD)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 1)
+ Name (_PRW, Package() { BOARD_TRACKPAD_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Return interrupt if I2C1 is PCI mode */
+ If (LEqual (\S1EN, 0)) {
+ Return (^RBUF)
+ }
+
+ /* Return empty resource template otherwise */
+ Return (ResourceTemplate() {})
+ }
+ }
+
+ /* Wake device for touchscreen */
+ Device (TSCR)
+ {
+ Name (_HID, EisaId ("PNP0C0E"))
+ Name (_UID, 2)
+ Name (_PRW, Package() { BOARD_TOUCHSCREEN_WAKE_GPIO, 0x3 })
+
+ Name (RBUF, ResourceTemplate()
+ {
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_CRS)
+ {
+ /* Return interrupt if I2C6 is PCI mode */
+ If (LEqual (\S6EN, 0)) {
+ Return (^RBUF)
+ }
+
+ /* Return empty resource template otherwise */
+ Return (ResourceTemplate() {})
+ }
+ }
+}
+
+Scope (\_SB.I2C1)
+{
+ Device (ATPB)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad Bootloader")
+ Name (_UID, 1)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x25, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ATPA)
+ {
+ Name (_HID, "ATML0000")
+ Name (_DDN, "Atmel Touchpad")
+ Name (_UID, 2)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4b, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ETPA)
+ {
+ Name (_HID, "ELAN0000")
+ Name (_DDN, "Elan Touchpad")
+ Name (_UID, 3)
+ Name (ISTP, 1) /* Touchpad */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x15, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C1", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TRACKPAD_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S1EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.I2C2)
+{
+ Device (CODC)
+ {
+ /*
+ * TODO(dlaurie): Need official HID.
+ *
+ * The current HID is created from the Maxim Integrated
+ * PCI Vendor ID 193Ch and a shortened device identifier.
+ */
+ Name (_HID, "193C9890")
+ Name (_DDN, "Maxim 98090 Codec")
+ Name (_UID, 1)
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x10, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C2", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_CODEC_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S2EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+ }
+}
+
+Scope (\_SB.I2C6)
+{
+ Device (ATSB)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen Bootloader")
+ Name (_UID, 4)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x26, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+
+ Device (ATSA)
+ {
+ Name (_HID, "ATML0001")
+ Name (_DDN, "Atmel Touchscreen")
+ Name (_UID, 5)
+ Name (ISTP, 0) /* TouchScreen */
+
+ Name (_CRS, ResourceTemplate()
+ {
+ I2cSerialBus (
+ 0x4a, // SlaveAddress
+ ControllerInitiated, // SlaveMode
+ 400000, // ConnectionSpeed
+ AddressingMode7Bit, // AddressingMode
+ "\\_SB.I2C6", // ResourceSource
+ )
+ Interrupt (ResourceConsumer, Edge, ActiveLow)
+ {
+ BOARD_TOUCHSCREEN_IRQ
+ }
+ })
+
+ Method (_STA)
+ {
+ If (LEqual (\S6EN, 1)) {
+ Return (0xF)
+ } Else {
+ Return (0x0)
+ }
+ }
+
+ /* Allow device to power off in S0 */
+ Name (_S0W, 4)
+ }
+}
+
+Scope (\_SB.LPEA)
+{
+ Name (GBUF, ResourceTemplate ()
+ {
+ /* Jack Detect (index 0) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 14 }
+
+ /* Mic Detect (index 1) */
+ GpioInt (Edge, ActiveHigh, Exclusive, PullNone,,
+ "\\_SB.GPSC") { 15 }
+ })
+}
diff --git a/src/mainboard/google/glimmer/acpi/superio.asl b/src/mainboard/google/glimmer/acpi/superio.asl
new file mode 100644
index 0000000..c5ad8ac
--- /dev/null
+++ b/src/mainboard/google/glimmer/acpi/superio.asl
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/* mainboard configuration */
+#include <mainboard/google/glimmer/ec.h>
+#include <mainboard/google/glimmer/onboard.h>
+
+#define SIO_EC_MEMMAP_ENABLE // EC Memory Map Resources
+#define SIO_EC_HOST_ENABLE // EC Host Interface Resources
+#define SIO_EC_ENABLE_PS2K // Enable PS/2 Keyboard
+// Override default IRQ settings
+#define SIO_EC_PS2K_IRQ Interrupt(ResourceConsumer, Edge, ActiveLow) {BOARD_I8042_IRQ}
+
+/* ACPI code for EC SuperIO functions */
+#include <ec/google/chromeec/acpi/superio.asl>
diff --git a/src/mainboard/google/glimmer/acpi/video.asl b/src/mainboard/google/glimmer/acpi/video.asl
new file mode 100644
index 0000000..1405b04
--- /dev/null
+++ b/src/mainboard/google/glimmer/acpi/video.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+// Brightness write
+Method (BRTW, 1, Serialized)
+{
+ // TODO
+}
+
+// Hot Key Display Switch
+Method (HKDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Lid Switch Display Switch
+Method (LSDS, 1, Serialized)
+{
+ // TODO
+}
+
+// Brightness Notification
+Method(BRTN,1,Serialized)
+{
+ // TODO (no displays defined yet)
+}
+
diff --git a/src/mainboard/google/glimmer/acpi_tables.c b/src/mainboard/google/glimmer/acpi_tables.c
new file mode 100644
index 0000000..4eaf103
--- /dev/null
+++ b/src/mainboard/google/glimmer/acpi_tables.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <cbmem.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/ioapic.h>
+#include <arch/acpigen.h>
+#include <arch/smp/mpspec.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/msr.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(global_nvs_t *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+
+ /* TPM Present */
+ gnvs->tpmp = 1;
+
+ /* Enable DPTF */
+ gnvs->dpte = 1;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
diff --git a/src/mainboard/google/glimmer/board_info.txt b/src/mainboard/google/glimmer/board_info.txt
new file mode 100644
index 0000000..3e630d3
--- /dev/null
+++ b/src/mainboard/google/glimmer/board_info.txt
@@ -0,0 +1,3 @@
+Category: laptop
+ROM protocol: SPI
+Flashrom support: y
diff --git a/src/mainboard/google/glimmer/chromeos.c b/src/mainboard/google/glimmer/chromeos.c
new file mode 100644
index 0000000..e4f2d28
--- /dev/null
+++ b/src/mainboard/google/glimmer/chromeos.c
@@ -0,0 +1,123 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <bootmode.h>
+#include <arch/io.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+#if CONFIG_EC_GOOGLE_CHROMEEC
+#include "ec.h"
+#include <ec/google/chromeec/ec.h>
+#endif
+
+/* The WP status pin lives on GPIO_SSUS_6 which is pad 36 in the SUS well. */
+#define WP_STATUS_PAD 36
+
+#ifndef __PRE_RAM__
+#include <boot/coreboot_tables.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+ {-1, ACTIVE_HIGH, vboot_recovery_mode_enabled(), "recovery"},
+ {-1, ACTIVE_HIGH, get_developer_mode_switch(), "developer"},
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+#endif
+
+int get_lid_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+
+ return !!(ec_switches & EC_SWITCH_LID_OPEN);
+#else
+ /* Default to force open. */
+ return 1;
+#endif
+}
+
+int get_developer_mode_switch(void)
+{
+ return 0;
+}
+
+int get_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ u8 ec_switches = inb(EC_LPC_ADDR_MEMMAP + EC_MEMMAP_SWITCHES);
+ u32 ec_events;
+
+ /* If a switch is set, we don't need to look at events. */
+ if (ec_switches & (EC_SWITCH_DEDICATED_RECOVERY))
+ return 1;
+
+ /* Else check if the EC has posted the keyboard recovery event. */
+ ec_events = google_chromeec_get_events_b();
+
+ return !!(ec_events &
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
+#else
+ return 0;
+#endif
+}
+
+int clear_recovery_mode_switch(void)
+{
+#if CONFIG_EC_GOOGLE_CHROMEEC
+ const uint32_t kb_rec_mask =
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY);
+ /* Unconditionally clear the EC recovery request. */
+ return google_chromeec_clear_events_b(kb_rec_mask);
+#else
+ return 0;
+#endif
+}
+
+int get_write_protect_state(void)
+{
+ /*
+ * The vboot loader queries this function in romstage. The GPIOs have
+ * not been set up yet as that configuration is done in ramstage. The
+ * hardware defaults to an input but there is a 20K pulldown. Externally
+ * there is a 10K pullup. Disable the internal pull in romstage so that
+ * there isn't any ambiguity in the reading.
+ */
+#if defined(__PRE_RAM__)
+ ssus_disable_internal_pull(WP_STATUS_PAD);
+#endif
+
+ /* WP is enabled when the pin is reading high. */
+ return ssus_get_gpio(WP_STATUS_PAD);
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}
diff --git a/src/mainboard/google/glimmer/chromeos.fmd b/src/mainboard/google/glimmer/chromeos.fmd
new file mode 100644
index 0000000..113fba6
--- /dev/null
+++ b/src/mainboard/google/glimmer/chromeos.fmd
@@ -0,0 +1,38 @@
+FLASH@0xff800000 0x800000 {
+ SI_ALL@0x0 0x200000 {
+ SI_DESC@0x0 0x1000
+ SI_ME@0x1000 0x1ff000
+ }
+ SI_BIOS@0x200000 0x600000 {
+ RW_SECTION_A@0x0 0xf0000 {
+ VBLOCK_A@0x0 0x10000
+ FW_MAIN_A(CBFS)@0x10000 0xdffc0
+ RW_FWID_A@0xeffc0 0x40
+ }
+ RW_SECTION_B@0xf0000 0xf0000 {
+ VBLOCK_B@0x0 0x10000
+ FW_MAIN_B(CBFS)@0x10000 0xdffc0
+ RW_FWID_B@0xeffc0 0x40
+ }
+ RW_MRC_CACHE@0x1e0000 0x10000
+ RW_ELOG@0x1f0000 0x4000
+ RW_SHARED@0x1f4000 0x4000 {
+ SHARED_DATA@0x0 0x2000
+ VBLOCK_DEV@0x2000 0x2000
+ }
+ RW_VPD@0x1f8000 0x2000
+ RW_UNUSED@0x1fa000 0x6000
+ RW_LEGACY(CBFS)@0x200000 0x200000
+ WP_RO@0x400000 0x200000 {
+ RO_VPD@0x0 0x4000
+ RO_UNUSED@0x4000 0xc000
+ RO_SECTION@0x10000 0x1f0000 {
+ FMAP@0x0 0x800
+ RO_FRID@0x800 0x40
+ RO_FRID_PAD@0x840 0x7c0
+ GBB@0x1000 0xef000
+ COREBOOT(CBFS)@0xf0000 0x100000
+ }
+ }
+ }
+}
diff --git a/src/mainboard/google/glimmer/cmos.layout b/src/mainboard/google/glimmer/cmos.layout
new file mode 100644
index 0000000..b419315
--- /dev/null
+++ b/src/mainboard/google/glimmer/cmos.layout
@@ -0,0 +1,133 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+#411 5 r 0 unused
+
+# coreboot config options: bootloader
+#Used by ChromeOS:
+416 128 r 0 vbnv
+#544 440 r 0 unused
+
+# SandyBridge MRC Scrambler Seed values
+896 32 r 0 mrc_scrambler_seed
+928 32 r 0 mrc_scrambler_seed_s3
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 415 984
diff --git a/src/mainboard/google/glimmer/devicetree.cb b/src/mainboard/google/glimmer/devicetree.cb
new file mode 100644
index 0000000..bf01cd9
--- /dev/null
+++ b/src/mainboard/google/glimmer/devicetree.cb
@@ -0,0 +1,98 @@
+chip soc/intel/baytrail
+
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ register "ide_legacy_combined" = "0x0"
+
+ # Route USB ports to XHCI
+ register "usb_route_to_xhci" = "1"
+
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+
+ # USB PHY settings
+ # TODO: These values are from Baytrail and need tuned for Glimmer board
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+
+ # LPE audio codec settings
+ register "lpe_codec_clk_freq" = "25" # 25MHz clock
+ register "lpe_codec_clk_num" = "0" # PMC_PLT_CLK[0]
+
+ # SD Card controller
+ register "sdcard_cap_low" = "0x036864b2"
+ register "sdcard_cap_high" = "0x0"
+
+ # Enable devices in ACPI mode
+ register "lpe_acpi_mode" = "1"
+ register "lpss_acpi_mode" = "1"
+ register "scc_acpi_mode" = "1"
+
+ # Enable PIPEA as DP_C
+ register "gpu_pipea_port_select" = "2" # DP_C
+ register "gpu_pipea_power_cycle_delay" = "6" # 600ms
+ register "gpu_pipea_power_on_delay" = "5000" # 500ms
+ register "gpu_pipea_light_on_delay" = "70" # 7ms
+ register "gpu_pipea_power_off_delay" = "500" # 50ms
+ register "gpu_pipea_light_off_delay" = "2000" # 200ms
+
+ # VR PS2 control
+ register "vnn_ps2_enable" = "1"
+ register "vcc_ps2_enable" = "1"
+
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+ device domain 0 on
+ device pci 00.0 on end # SoC router
+ device pci 02.0 on end # GFX
+ device pci 11.0 off end # SDIO
+ device pci 12.0 on end # SD
+ device pci 13.0 on end # SATA
+ device pci 14.0 on end # XHCI
+ device pci 15.0 on end # LPE
+ device pci 17.0 on end # MMC
+ device pci 18.0 on end # SIO_DMA1
+ device pci 18.1 on end # I2C1
+ device pci 18.2 on end # I2C2
+ device pci 18.3 off end # I2C3
+ device pci 18.4 off end # I2C4
+ device pci 18.5 on end # I2C5
+ device pci 18.6 on end # I2C6
+ device pci 18.7 off end # I2C7
+ device pci 1a.0 on end # TXE
+ device pci 1b.0 on end # HDA
+ device pci 1c.0 on end # PCIE_PORT1
+ device pci 1c.1 on end # PCIE_PORT2
+ device pci 1c.2 off end # PCIE_PORT3
+ device pci 1c.3 off end # PCIE_PORT4
+ device pci 1d.0 on end # EHCI
+ device pci 1e.0 on end # SIO_DMA2
+ device pci 1e.1 off end # PWM1
+ device pci 1e.2 off end # PWM2
+ device pci 1e.3 off end # HSUART1
+ device pci 1e.4 off end # HSUART2
+ device pci 1e.5 off end # SPI
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ # We only have one init function that
+ # we need to call to initialize the
+ # keyboard part of the EC.
+ device pnp ff.1 on # dummy address
+ end
+ end
+ end # LPC Bridge
+ device pci 1f.3 off end # SMBus
+ end
+end
diff --git a/src/mainboard/google/glimmer/dsdt.asl b/src/mainboard/google/glimmer/dsdt.asl
new file mode 100644
index 0000000..e21b3d1
--- /dev/null
+++ b/src/mainboard/google/glimmer/dsdt.asl
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define ENABLE_TPM
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x05, // DSDT revision: ACPI v5.0
+ "COREv4", // OEM id
+ "COREBOOT", // OEM table id
+ 0x20110725 // OEM revision
+)
+{
+ // Some generic macros
+ #include <soc/intel/baytrail/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+
+ #include <soc/intel/baytrail/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ //#include <soc/intel/baytrail/acpi/northcluster.asl>
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ }
+
+ /* Dynamic Platform Thermal Framework */
+ #include "acpi/dptf.asl"
+ }
+
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ /* Chipset specific sleep states */
+ #include <soc/intel/baytrail/acpi/sleepstates.asl>
+
+ #include "acpi/mainboard.asl"
+}
diff --git a/src/mainboard/google/glimmer/ec.c b/src/mainboard/google/glimmer/ec.c
new file mode 100644
index 0000000..33c8d24
--- /dev/null
+++ b/src/mainboard/google/glimmer/ec.c
@@ -0,0 +1,48 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <types.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+void mainboard_ec_init(void)
+{
+ printk(BIOS_DEBUG, "mainboard_ec_init\n");
+ post_code(0xf0);
+
+ /* Restore SCI event mask on resume. */
+ if (acpi_is_wakeup_s3()) {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S3_WAKE_EVENTS);
+
+ /* Disable SMI and wake events */
+ google_chromeec_set_smi_mask(0);
+
+ /* Clear pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ } else {
+ google_chromeec_log_events(MAINBOARD_EC_LOG_EVENTS |
+ MAINBOARD_EC_S5_WAKE_EVENTS);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ }
+
+ /* Clear wake events, these are enabled on entry to sleep */
+ google_chromeec_set_wake_mask(0);
+
+ post_code(0xf1);
+}
diff --git a/src/mainboard/google/glimmer/ec.h b/src/mainboard/google/glimmer/ec.h
new file mode 100644
index 0000000..19f6090
--- /dev/null
+++ b/src/mainboard/google/glimmer/ec.h
@@ -0,0 +1,62 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_EC_H
+#define MAINBOARD_EC_H
+
+#include <ec/google/chromeec/ec_commands.h>
+
+/* GPIO_S0_000 is EC_SCI#, but it is bit 24 in GPE_STS */
+#define EC_SCI_GPI 24
+/* GPIO_S5_07 is EC_SMI#, but it is bit 23 in GPE_STS and ALT_GPIO_SMI. */
+#define EC_SMI_GPI 23
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_OVERLOAD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_CHARGER))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid or power button or key press */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN))
+
+#ifndef __ACPI__
+extern void mainboard_ec_init(void);
+#endif
+
+#endif
diff --git a/src/mainboard/google/glimmer/fadt.c b/src/mainboard/google/glimmer/fadt.c
new file mode 100644
index 0000000..2434d1a
--- /dev/null
+++ b/src/mainboard/google/glimmer/fadt.c
@@ -0,0 +1,46 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/acpi.h>
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = sizeof(acpi_fadt_t);
+ header->revision = 3;
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+ header->asl_compiler_revision = 1;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->model = 1;
+ fadt->preferred_pm_profile = PM_MOBILE;
+
+ fadt->x_firmware_ctl_l = (unsigned long)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (unsigned long)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ acpi_fill_in_fadt(fadt);
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
diff --git a/src/mainboard/google/glimmer/gpio.c b/src/mainboard/google/glimmer/gpio.c
new file mode 100644
index 0000000..582b385
--- /dev/null
+++ b/src/mainboard/google/glimmer/gpio.c
@@ -0,0 +1,232 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include "irqroute.h"
+
+/* TODO(SHAWNN): Modify gpios labeled 'INT' for interrupt handling */
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_FUNC2, /* S0_NC00 - INT_HDMI_HPD - INT */
+ GPIO_FUNC2, /* S0_NC01 - HDMI_DDCDATA_SW */
+ GPIO_FUNC2, /* S0_NC02 - HDMI_DDCCLK_SW */
+ GPIO_NC, /* S0_NC03 - NC */
+ GPIO_NC, /* S0_NC04 - NC */
+ GPIO_NC, /* S0_NC05 - NC */
+ GPIO_FUNC2, /* S0_NC06 - EDP_HPD_L */
+ GPIO_INPUT, /* S0_NC07 - DDI1_DDCDATA - STRAP */
+ GPIO_NC, /* S0_NC08 - NC */
+ GPIO_OUT_HIGH, /* S0_NC09 - SOC_DISP_ON_C */
+ GPIO_FUNC2, /* S0_NC10 - SOC_EDP_BLON_C */
+ GPIO_FUNC2, /* S0_NC11 - SOC_DPST_PWM_C */
+ GPIO_NC, /* S0_NC12 - NC */
+ GPIO_INPUT, /* S0_NC13 - GPIO_NC13 - STRAP */
+ GPIO_NC, /* S0_NC14 - NC */
+ GPIO_DEFAULT, /* S0_NC15 - XDP_GPIO_S0_NC15 */
+ GPIO_DEFAULT, /* S0_NC16 - XDP_GPIO_S0_NC16 */
+ GPIO_DEFAULT, /* S0_NC17 - XDP_GPIO_S0_NC17 */
+ GPIO_DEFAULT, /* S0_NC18 - XDP_GPIO_S0_NC18 */
+ GPIO_DEFAULT, /* S0_NC19 - XDP_GPIO_S0_NC19 */
+ GPIO_DEFAULT, /* S0_NC20 - XDP_GPIO_S0_NC20 */
+ GPIO_DEFAULT, /* S0_NC21 - XDP_GPIO_S0_NC21 */
+ GPIO_DEFAULT, /* S0_NC22 - XDP_GPIO_S0_NC22 */
+ GPIO_DEFAULT, /* S0_NC23 - XDP_GPIO_S0_NC23 */
+ GPIO_NC, /* S0_NC24 - NC */
+ GPIO_NC, /* S0_NC25 - NC */
+ GPIO_NC, /* S0_NC26 - NC */
+ GPIO_END
+};
+
+/* SCORE GPIOs */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_ACPI_SCI, /* S0_SC000 - SOC_KBC_SCI - INT */
+ GPIO_FUNC2, /* S0_SC001 - SATA_DEVSLP_C */
+ GPIO_NC, /* S0-SC002 - SATA_LED_R_N (NC/PU) */
+ GPIO_FUNC1, /* S0-SC003 - PCIE_CLKREQ_IMAGE# */
+ GPIO_FUNC1, /* S0-SC004 - PCIE_CLKREQ_WLAN# */
+ GPIO_NC, /* S0-SC005 - PCIE_CLKREQ_LAN# (NC) */
+ GPIO_NC, /* S0-SC006 - PCIE_CLKREQ3# (NC) */
+ GPIO_FUNC(2, PULL_DISABLE, 10K), /* S0-SC007 - SD3_WP external pull */
+ GPIO_NC, /* S0-SC008 - ACZ_RST# (NC) */
+ GPIO_NC, /* S0-SC009 - ACZ_SYNC (NC) */
+ GPIO_NC, /* S0-SC010 - ACZ_BCLK (NC) */
+ GPIO_NC, /* S0-SC011 - ACZ_STDOUT (NC) */
+ GPIO_NC, /* S0-SC012 - PCH_AZ_CODEC_SDIN0 (NC) */
+ GPIO_NC, /* S0-SC013 - NC */
+ GPIO_INPUT, /* S0-SC014 - DET_TRIGGER - INT */
+ GPIO_INPUT, /* S0-SC015 - AJACK_MICPRES_L - INT */
+ GPIO_FUNC(3, PULL_DOWN, 20K), /* S0-SC016 - MMC1_45_CLK */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC017 - MMC1_45_D[0] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC018 - MMC1_45_D[1] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC019 - MMC1_45_D[2] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC020 - MMC1_45_D[3] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC021 - MMC1_45_D[4] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC022 - MMC1_45_D[5] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC023 - MMC1_45_D[6] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC024 - MMC1_45_D[7] */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC025 - MMC1_45_CMD */
+ GPIO_FUNC(3, PULL_UP, 20K), /* S0-SC026 - MMC1_45_RST */
+ GPIO_NC, /* S0-SC027 - NC */
+ GPIO_NC, /* S0-SC028 - NC */
+ GPIO_NC, /* S0-SC029 - NC */
+ GPIO_NC, /* S0-SC030 - NC */
+ GPIO_NC, /* S0-SC031 - NC */
+ GPIO_NC, /* S0-SC032 - NC */
+ GPIO_FUNC(1, PULL_DOWN, 20K), /* S0-SC033 - SD3_CLK */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC034 - SD3_D0 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC035 - SD3_D1 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC036 - SD3_D2 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC037 - SD3_D3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC038 - SD3_CD# */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC039 - SD3_CMD */
+ GPIO_NC, /* S0-SC040 - SDMMC3_1P8_EN - TP3 */
+ GPIO_FUNC(1, PULL_UP, 20K), /* S0-SC041 - SDIO3_PWR_EN# */
+ GPIO_FUNC1, /* S0-SC042 - LPC_LAD0 */
+ GPIO_FUNC1, /* S0-SC043 - LPC-LAD1 */
+ GPIO_FUNC1, /* S0-SC044 - LPC_LAD2 */
+ GPIO_FUNC1, /* S0-SC045 - LPC_LAD3 */
+ GPIO_FUNC1, /* S0-SC046 - LPC_LFRAME# */
+ GPIO_FUNC1, /* S0-SC047 - PCLK_TPM */
+ GPIO_FUNC1, /* S0-SC048 - CLK_PCI_EC */
+ GPIO_FUNC1, /* S0-SC049 - LPC_CLKRUN_L */
+ GPIO_NC, /* S0-SC050 - IRQ_SERIRQ */
+ GPIO_NC, /* S0-SC051 - SMB_SOC_DATA (XDP) */
+ GPIO_NC, /* S0-SC052 - SMB_SOC_CLK (XDP) */
+ GPIO_NC, /* S0-SC053 - SMB_SOC_ALERTB (NC) */
+ GPIO_DEFAULT, /* S0-SC054 - NC */
+ GPIO_DIRQ, /* S0-SC055 - TRACKPAD_INT_DX */
+ GPIO_INPUT, /* S0-SC056 - GPIO_S0_SC_56 - STRAP */
+ GPIO_FUNC1, /* S0-SC057 - PCH_UART_TXD */
+ GPIO_INPUT, /* S0-SC058 - SIM_DET_C */
+ GPIO_INPUT_LEGACY, /* S0-SC059 - EC_IN_RW_C */
+ GPIO_NC, /* S0-SC060 - NC */
+ GPIO_FUNC1, /* S0-SC061 - SOC_UART_RX */
+ GPIO_FUNC1, /* S0-SC062 - I2S_BCLK */
+ GPIO_FUNC1, /* S0-SC063 - I2S_LRCLK */
+ GPIO_FUNC1, /* S0-SC064 - I2S_DIN */
+ GPIO_FUNC1, /* S0-SC065 - I2S_DOUT */
+ GPIO_FUNC1, /* S0-SC066 - SIO_SPI_CS# */
+ GPIO_FUNC1, /* S0-SC067 - SIO_SPI_MISO */
+ GPIO_FUNC1, /* S0-SC068 - SIO_SPI_MOSI */
+ GPIO_FUNC1, /* S0-SC069 - SIO_SPI_CLK */
+ GPIO_NC, /* S0-SC070 - ALS_INT_L - INT (NC) */
+ GPIO_NC, /* S0-SC071 - NC */
+ GPIO_DIRQ, /* S0-SC072 - TOUCH_INT_L_DX */
+ GPIO_NC, /* S0-SC073 - NC */
+ GPIO_NC, /* S0-SC074 - SIO_UART2_RXD (NC) */
+ GPIO_NC, /* S0-SC075 - SIO_UART2_TXD (NC) */
+ GPIO_INPUT, /* S0-SC076 - BIOS_STRAP - STRAP */
+ GPIO_INPUT, /* S0-SC077 - SOC_OVERRIDE - STRAP */
+ GPIO_FUNC1, /* S0-SC078 - I2C_0_SDA */
+ GPIO_FUNC1, /* S0-SC079 - I2C_0_SCL */
+ GPIO_FUNC1, /* S0-SC080 - I2C_1_SDA */
+ GPIO_FUNC1, /* S0-SC081 - I2C_1_SCL */
+ GPIO_NC, /* S0-SC082 - NC */
+ GPIO_NC, /* S0-SC083 - NC */
+ GPIO_NC, /* S0-SC084 - NC */
+ GPIO_NC, /* S0-SC085 - NC */
+ GPIO_FUNC1, /* S0-SC086 - I2C_4_SDA */
+ GPIO_FUNC1, /* S0-SC087 - I2C_4_SCL */
+ GPIO_FUNC1, /* S0-SC088 - I2C_5_SDA */
+ GPIO_FUNC1, /* S0-SC089 - I2C_5_SCL */
+ GPIO_NC, /* S0-SC090 - NC */
+ GPIO_NC, /* S0-SC091 - NC */
+ GPIO_NC, /* S0-SC092 - I2C_NGFF_SDA (NC/PU) */
+ GPIO_NC, /* S0-SC093 - I2C_NGFF_SCL (NC/PU) */
+ GPIO_NC, /* S0-SC094 - NC */
+ GPIO_NC, /* S0-SC095 - SIO_PWM1 (NC) */
+ GPIO_FUNC1, /* S0-SC096 - I2S_MCLK */
+ GPIO_NC, /* S0-SC097 - NC */
+ GPIO_NC, /* S0-SC098 - NC */
+ GPIO_NC, /* S0-SC099 - NC */
+ GPIO_NC, /* S0-SC100 - NC */
+ GPIO_DIRQ, /* S0-SC101 - KBD_IRQ# */
+ GPIO_END
+};
+
+/* SSUS GPIOs */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_ACPI_WAKE, /* S500 - PCH_WAKE# */
+ GPIO_ACPI_WAKE, /* S501 - TRACKPAD_INT# - INT */
+ GPIO_ACPI_WAKE, /* S502 - TOUCH_INT# - INT */
+ GPIO_FUNC6, /* S503 - LTE_WAKE_L# - INT */
+ GPIO_NC, /* S504 - SOC_JTAG2_TDO (NC/PU) */
+ GPIO_FUNC1, /* S505 - SUS_CLK_WLAN (NC) */
+ GPIO_INPUT_PU, /* S506 - PCH_SPI_WP */
+ GPIO_ACPI_SMI, /* S507 - SOC_KBC_SMI - INT */
+ GPIO_NC, /* S508 - NC */
+ GPIO_DIRQ, /* S509 - MUX_AUD_INT1# */
+ GPIO_OUT_HIGH, /* S510 - WIFI_DISABLE_L */
+ GPIO_FUNC0, /* S511 - SUSPWRDNACK */
+ GPIO_FUNC0, /* S512 - WIFI_SUSCLK */
+ GPIO_FUNC0, /* S513 - SLP_SX */
+ GPIO_NC, /* S514 - NC */
+ GPIO_FUNC0, /* S515 - WLAN_WAKE_L - INT */
+ GPIO_FUNC0, /* S516 - PCH_PWRBTN_L */
+ GPIO_NC, /* S517 - NC */
+ GPIO_FUNC0, /* S518 - SUS_STAT# */
+ GPIO_FUNC0, /* S519 - USB_OC0# */
+ GPIO_FUNC0, /* S520 - USB_OC1# */
+ GPIO_NC, /* S521 - NC */
+ GPIO_NC, /* S522 - XDP_GPIO_DFX0 */
+ GPIO_NC, /* S523 - XDP_GPIO_DFX1 */
+ GPIO_NC, /* S524 - XDP_GPIO_DFX2 */
+ GPIO_NC, /* S525 - XDP_GPIO_DFX3 */
+ GPIO_NC, /* S526 - XDP_GPIO_DFX4 */
+ GPIO_NC, /* S527 - XDP_GPIO_DFX5 */
+ GPIO_NC, /* S528 - XDP_GPIO_DFX6 */
+ GPIO_NC, /* S529 - XDP_GPIO_DFX7 */
+ GPIO_NC, /* S530 - XDP_GPIO_DFX8 */
+ GPIO_NC, /* S531 - NC */
+ GPIO_NC, /* S532 - NC */
+ GPIO_NC, /* S533 - NC */
+ GPIO_NC, /* S534 - NC */
+ GPIO_OUT_HIGH, /* S535 - LTE_DISABLE_L */
+ GPIO_NC, /* S536 - NC */
+ GPIO_INPUT, /* S537 - RAM_ID0 */
+ GPIO_INPUT, /* S538 - RAM_ID1 */
+ GPIO_INPUT, /* S539 - RAM_ID2 */
+ /* TODO(shawnn): Change to normal input once our old boards
+ * are no longer in use. */
+ GPIO_FUNC(0, PULL_DOWN, 20K), /* S540 - RAM_ID3 */
+ GPIO_NC, /* S541 - NC */
+ GPIO_NC, /* S542 - NC */
+ GPIO_NC, /* S543 - NC */
+ GPIO_END
+};
+
+static const u8 core_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [TPAD_IRQ_OFFSET] = TPAD_IRQ_GPIO,
+ [TOUCH_IRQ_OFFSET] = TOUCH_IRQ_GPIO,
+ [I8042_IRQ_OFFSET] = I8042_IRQ_GPIO,
+};
+
+static const u8 sus_dedicated_irq[GPIO_MAX_DIRQS] = {
+ [CODEC_IRQ_OFFSET] = CODEC_IRQ_GPIO,
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = gpncore_gpio_map,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map,
+ .core_dirq = &core_dedicated_irq,
+ .sus_dirq = &sus_dedicated_irq,
+};
+
+struct soc_gpio_config* mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/google/glimmer/irqroute.c b/src/mainboard/google/glimmer/irqroute.c
new file mode 100644
index 0000000..f2bb352
--- /dev/null
+++ b/src/mainboard/google/glimmer/irqroute.c
@@ -0,0 +1,18 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/google/glimmer/irqroute.h b/src/mainboard/google/glimmer/irqroute.h
new file mode 100644
index 0000000..18bc296
--- /dev/null
+++ b/src/mainboard/google/glimmer/irqroute.h
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+#include <soc/pmc.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, C, D, E, F), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, C, D, E), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, DISABLE), \
+ PIRQ_PIC(B, DISABLE), \
+ PIRQ_PIC(C, DISABLE), \
+ PIRQ_PIC(D, DISABLE), \
+ PIRQ_PIC(E, DISABLE), \
+ PIRQ_PIC(F, DISABLE), \
+ PIRQ_PIC(G, DISABLE), \
+ PIRQ_PIC(H, DISABLE)
+
+/* CORE bank DIRQs - up to 16 supported */
+#define TPAD_IRQ_OFFSET 0
+#define TOUCH_IRQ_OFFSET 1
+#define I8042_IRQ_OFFSET 2
+
+/* Corresponding SCORE GPIO pins */
+#define TPAD_IRQ_GPIO 55
+#define TOUCH_IRQ_GPIO 72
+#define I8042_IRQ_GPIO 101
+
+/* SUS bank DIRQs - up to 16 supported */
+#define CODEC_IRQ_OFFSET 0
+/* Corresponding SUS GPIO pins */
+#define CODEC_IRQ_GPIO 9
diff --git a/src/mainboard/google/glimmer/mainboard.c b/src/mainboard/google/glimmer/mainboard.c
new file mode 100644
index 0000000..cd3a3c1
--- /dev/null
+++ b/src/mainboard/google/glimmer/mainboard.c
@@ -0,0 +1,183 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#if CONFIG_VGA_ROM_RUN
+#include <x86emu/x86emu.h>
+#endif
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include <smbios.h>
+#include "ec.h"
+#include "onboard.h"
+#include <soc/gpio.h>
+#include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void mainboard_suspend_resume(void)
+{
+}
+
+#if CONFIG_VGA_ROM_RUN
+static int int15_handler(void)
+{
+ int res = 1;
+
+ printk(BIOS_DEBUG, "%s: AX=%04x BX=%04x CX=%04x DX=%04x\n",
+ __func__, X86_AX, X86_BX, X86_CX, X86_DX);
+
+ switch (X86_AX) {
+ case 0x5f34:
+ /*
+ * Set Panel Fitting Hook:
+ * bit 2 = Graphics Stretching
+ * bit 1 = Text Stretching
+ * bit 0 = Centering (do not set with bit1 or bit2)
+ * 0 = video bios default
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0001;
+ res = 1;
+ break;
+ case 0x5f35:
+ /*
+ * Boot Display Device Hook:
+ * bit 0 = CRT
+ * bit 1 = TV
+ * bit 2 = EFP (HDMI)
+ * bit 3 = LFP (eDP)*
+ * bit 4 = CRT2
+ * bit 5 = TV2
+ * bit 6 = EFP2
+ * bit 7 = LFP2
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0008;
+ res = 1;
+ break;
+ case 0x5f51:
+ /*
+ * Hook to select active LFP configuration:
+ * 00h = No LVDS, VBIOS does not enable LVDS
+ * 01h = Int-LVDS, LFP driven by integrated LVDS decoder
+ * 02h = SVDO-LVDS, LFP driven by SVDO decoder
+ * 03h = eDP, LFP Driven by Int-DisplayPort encoder
+ */
+ X86_AX = 0x005f;
+ X86_CX = 0x0003;
+ res = 1;
+ break;
+ case 0x5f70:
+ switch ((X86_CX >> 8) & 0xff) {
+ case 0:
+ /* Get Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 1:
+ /* Set Mux */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ case 2:
+ /* Get SG/Non-SG mode */
+ X86_AX = 0x005f;
+ X86_CX = 0x0000;
+ res = 1;
+ break;
+ default:
+ /* Interrupt was not handled */
+ printk(BIOS_DEBUG,
+ "Unknown INT15 5f70 function: 0x%02x\n",
+ ((X86_CX >> 8) & 0xff));
+ break;
+ }
+ break;
+
+ default:
+ printk(BIOS_DEBUG, "Unknown INT15 function %04x!\n", X86_AX);
+ break;
+ }
+ return res;
+}
+#endif
+
+static void mainboard_init(device_t dev)
+{
+ mainboard_ec_init();
+}
+
+static int mainboard_smbios_data(device_t dev, int *handle,
+ unsigned long *current)
+{
+ int len = 0;
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TRACKPAD_NAME, /* name */
+ BOARD_TRACKPAD_IRQ, /* instance */
+ BOARD_TRACKPAD_I2C_BUS, /* segment */
+ BOARD_TRACKPAD_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ len += smbios_write_type41(
+ current, handle,
+ BOARD_TOUCHSCREEN_NAME, /* name */
+ BOARD_TOUCHSCREEN_IRQ, /* instance */
+ BOARD_TOUCHSCREEN_I2C_BUS, /* segment */
+ BOARD_TOUCHSCREEN_I2C_ADDR, /* bus */
+ 0, /* device */
+ 0); /* function */
+
+ return len;
+}
+
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+ dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+#if CONFIG_VGA_ROM_RUN
+ /* Install custom int15 handler for VGA OPROM */
+ mainboard_interrupt_handlers(0x15, &int15_handler);
+#endif
+}
+
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
+
+static void edp_vdden_cb(void *unused)
+{
+ ncore_select_func(SOC_DDI1_VDDEN_PAD, PAD_FUNC2);
+}
+
+BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL);
diff --git a/src/mainboard/google/glimmer/mainboard_smi.c b/src/mainboard/google/glimmer/mainboard_smi.c
new file mode 100644
index 0000000..a3d5273
--- /dev/null
+++ b/src/mainboard/google/glimmer/mainboard_smi.c
@@ -0,0 +1,121 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <console/console.h>
+#include <cpu/x86/smm.h>
+#include <elog.h>
+
+#include <ec/google/chromeec/ec.h>
+#include "ec.h"
+
+#include <soc/nvs.h>
+#include <soc/pmc.h>
+
+/* The wake gpio is SUS_GPIO[0]. */
+#define WAKE_GPIO_EN SUS_GPIO_EN0
+
+static uint8_t mainboard_smi_ec(void)
+{
+ uint8_t cmd = google_chromeec_get_event();
+ uint16_t pmbase = get_pmbase();
+ uint32_t pm1_cnt;
+
+#if CONFIG_ELOG_GSMI
+ /* Log this event */
+ if (cmd)
+ elog_add_event_byte(ELOG_TYPE_EC_EVENT, cmd);
+#endif
+
+ switch (cmd) {
+ case EC_HOST_EVENT_LID_CLOSED:
+ printk(BIOS_DEBUG, "LID CLOSED, SHUTDOWN\n");
+
+ /* Go to S5 */
+ pm1_cnt = inl(pmbase + PM1_CNT);
+ pm1_cnt |= SLP_EN | (SLP_TYP_S5 << SLP_TYP_SHIFT);
+ outl(pm1_cnt, pmbase + PM1_CNT);
+ break;
+ }
+
+ return cmd;
+}
+
+/* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
+ * this includes the enable bits in the lower 16 bits. */
+void mainboard_smi_gpi(uint32_t alt_gpio_smi)
+{
+ if (alt_gpio_smi & (1 << EC_SMI_GPI)) {
+ /* Process all pending events */
+ while (mainboard_smi_ec() != 0);
+ }
+}
+
+void mainboard_smi_sleep(uint8_t slp_typ)
+{
+ /* Disable USB charging if required */
+ switch (slp_typ) {
+ case 3:
+ if (smm_get_gnvs()->s3u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s3u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S3_WAKE_EVENTS);
+ /* Enable wake pin in GPE block. */
+ enable_gpe(WAKE_GPIO_EN);
+ break;
+ case 5:
+ if (smm_get_gnvs()->s5u0 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 0, USB_CHARGE_MODE_DISABLED);
+ if (smm_get_gnvs()->s5u1 == 0)
+ google_chromeec_set_usb_charge_mode(
+ 1, USB_CHARGE_MODE_DISABLED);
+
+ /* Enable wake events */
+ google_chromeec_set_wake_mask(MAINBOARD_EC_S5_WAKE_EVENTS);
+ break;
+ }
+
+ /* Disable SCI and SMI events */
+ google_chromeec_set_smi_mask(0);
+ google_chromeec_set_sci_mask(0);
+
+ /* Clear pending events that may trigger immediate wake */
+ while (google_chromeec_get_event() != 0);
+}
+
+int mainboard_smi_apmc(uint8_t apmc)
+{
+ switch (apmc) {
+ case APM_CNT_ACPI_ENABLE:
+ google_chromeec_set_smi_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_sci_mask(MAINBOARD_EC_SCI_EVENTS);
+ break;
+ case APM_CNT_ACPI_DISABLE:
+ google_chromeec_set_sci_mask(0);
+ /* Clear all pending events */
+ while (google_chromeec_get_event() != 0);
+ google_chromeec_set_smi_mask(MAINBOARD_EC_SMI_EVENTS);
+ break;
+ }
+ return 0;
+}
diff --git a/src/mainboard/google/glimmer/onboard.h b/src/mainboard/google/glimmer/onboard.h
new file mode 100644
index 0000000..c8649f3
--- /dev/null
+++ b/src/mainboard/google/glimmer/onboard.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef ONBOARD_H
+#define ONBOARD_H
+
+#include "irqroute.h"
+
+/* PCH wake signal from EC. */
+#define BOARD_PCH_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(0)
+
+#define BOARD_TRACKPAD_NAME "trackpad"
+#define BOARD_TRACKPAD_IRQ GPIO_S0_DED_IRQ(TPAD_IRQ_OFFSET)
+#define BOARD_TRACKPAD_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(1)
+#define BOARD_TRACKPAD_I2C_BUS 0
+#define BOARD_TRACKPAD_I2C_ADDR 0x4b
+
+#define BOARD_TOUCHSCREEN_NAME "touchscreen"
+#define BOARD_TOUCHSCREEN_IRQ GPIO_S0_DED_IRQ(TOUCH_IRQ_OFFSET)
+#define BOARD_TOUCHSCREEN_WAKE_GPIO ACPI_ENABLE_WAKE_SUS_GPIO(2)
+#define BOARD_TOUCHSCREEN_I2C_BUS 5
+#define BOARD_TOUCHSCREEN_I2C_ADDR 0x4a /* TODO(shawnn): Check this */
+
+#define BOARD_I8042_IRQ GPIO_S0_DED_IRQ(I8042_IRQ_OFFSET)
+#define BOARD_CODEC_IRQ GPIO_S5_DED_IRQ(CODEC_IRQ_OFFSET)
+
+#endif
diff --git a/src/mainboard/google/glimmer/romstage.c b/src/mainboard/google/glimmer/romstage.c
new file mode 100644
index 0000000..99fd9b8
--- /dev/null
+++ b/src/mainboard/google/glimmer/romstage.c
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/gpio.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+/*
+ * RAM_ID[2:0] are on GPIO_SSUS[39:37]
+ * 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+ * 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
+ * 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
+ * 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+ * 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ * 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+ * 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+ * 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+ */
+static const uint32_t dual_channel_config =
+ (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3) |
+ (1 << 4) | (1 << 6) | (1 << 7);
+
+#define SPD_SIZE 256
+#define GPIO_SSUS_37_PAD 57
+#define GPIO_SSUS_38_PAD 50
+#define GPIO_SSUS_39_PAD 58
+#define GPIO_SSUS_40_PAD 52
+
+static inline void set_internal_pull(int pad, int mask)
+{
+ const int pull_mask = ~(0xf << 7);
+ write32(ssus_pconf0(pad),
+ (read32(ssus_pconf0(pad)) & pull_mask) | mask);
+}
+
+static void *get_spd_pointer(char *spd_file_content, int total_spds, int *dual)
+{
+ int ram_id = 0;
+
+ /* The ram_id[2:0] pullups on glimmer are too large for the default 20K
+ * pulldown on the pad. Therefore, disable the internal pull resistor to
+ * read high values correctly. */
+ set_internal_pull(GPIO_SSUS_37_PAD, PAD_PULL_DISABLE);
+ set_internal_pull(GPIO_SSUS_38_PAD, PAD_PULL_DISABLE);
+ set_internal_pull(GPIO_SSUS_39_PAD, PAD_PULL_DISABLE);
+ /* TODO(shawnn): Disable the PD once our old boards are no longer in
+ * use. */
+ set_internal_pull(GPIO_SSUS_40_PAD, PAD_PULL_DOWN | PAD_PU_20K);
+
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_37_PAD) << 0);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_38_PAD) << 1);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_39_PAD) << 2);
+ ram_id |= (ssus_get_gpio(GPIO_SSUS_40_PAD) << 3);
+
+ printk(BIOS_DEBUG, "ram_id=%d, total_spds: %d\n", ram_id, total_spds);
+
+ if (ram_id >= total_spds)
+ return NULL;
+
+ /* Single channel configs */
+ if (dual_channel_config & (1 << ram_id))
+ *dual = 1;
+
+ return &spd_file_content[SPD_SIZE * ram_id];
+}
+
+void mainboard_romstage_entry(struct romstage_params *rp)
+{
+ void *spd_content;
+ int dual_channel = 0;
+ void *spd_file;
+ size_t spd_fsize;
+
+ struct mrc_params mp = {
+ .mainboard = {
+ .dram_type = DRAM_DDR3L,
+ .dram_info_location = DRAM_INFO_SPD_MEM,
+ .weaker_odt_settings = 1,
+ },
+ };
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
+ &spd_fsize);
+ if (!spd_file)
+ die("SPD data not found.");
+
+ /* Both channels are always present. */
+ spd_content = get_spd_pointer(spd_file, spd_fsize / SPD_SIZE,
+ &dual_channel);
+ mp.mainboard.dram_data[0] = spd_content;
+ if (dual_channel)
+ mp.mainboard.dram_data[1] = spd_content;
+
+ rp->mrc_params = ∓
+ romstage_common(rp);
+}
diff --git a/src/mainboard/google/glimmer/spd/Makefile.inc b/src/mainboard/google/glimmer/spd/Makefile.inc
new file mode 100644
index 0000000..341f6d3
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/Makefile.inc
@@ -0,0 +1,55 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Google Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+SPD_BIN = $(obj)/spd.bin
+
+# Order matters for SPD sources. The following indicies
+# define the SPD data to use.
+# 0b0000 - 4GiB total - 2 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b0001 - 4GiB total - 2 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b0010 - 2GiB total - 2 x 1GiB Micron MT41K128M16JT-125:K 1600MHz
+# 0b0011 - 2GiB total - 2 x 1GiB Hynix H5TC2G63FFR-PBA 1600MHz
+# 0b0100 - 2GiB total - 2 x 1GiB Samsung K4B2G1646Q-BYK0 1600MHz
+# 0b0101 - 2GiB total - 1 x 2GiB Hynix H5TC4G63AFR-PBA 1600MHz
+# 0b0110 - 4GiB total - 2 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+# 0b0111 - 4GiB total - 2 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b1000 - 2GiB total - 1 x 2GiB Micron MT41K256M16HA-125:E 1600MHz
+# 0b1001 - 2GiB total - 1 x 2GiB Elpida EDJ4216EFBG-GNL-F 1600MHz
+# 0b1010 - 2GiB total - 1 x 2GiB Samsung K4B4G1646Q-HYK0 1600MHz
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += micron_1GiB_dimm_MT41K128M16JT-125
+SPD_SOURCES += hynix_1GiB_dimm_H5TC2G63FFR-PBA
+SPD_SOURCES += samsung_1GiB_dimm_K4B2G1646Q-BYK0
+SPD_SOURCES += hynix_2GiB_dimm_H5TC4G63AFR-PBA
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125
+SPD_SOURCES += elpida_2GiB_dimm_EDJ4216EFBG-GNL-F
+SPD_SOURCES += samsung_2GiB_dimm_K4B4G1646Q-HYK0
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd rom data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/google/glimmer/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex b/src/mainboard/google/glimmer/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
new file mode 100644
index 0000000..6e3eab3
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/elpida_2GiB_dimm_EDJ4216EFBG-GNL-F.spd.hex
@@ -0,0 +1,16 @@
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 81
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 02 FE 00 00 00 00 00 00 00 A1 CE
+45 44 4A 34 32 31 36 45 46 42 47 2D 47 4E 2D 46
+00 00 00 00 02 FE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
+FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
diff --git a/src/mainboard/google/glimmer/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex b/src/mainboard/google/glimmer/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
new file mode 100644
index 0000000..4bd8e0e
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/hynix_1GiB_dimm_H5TC2G63FFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 03 11 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+00 05 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 22 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 41 5f
+48 4d 54 33 31 32 53 36
+44 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/glimmer/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex b/src/mainboard/google/glimmer/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
new file mode 100644
index 0000000..ff4fd29
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/hynix_2GiB_dimm_H5TC4G63AFR-PBA.spd.hex
@@ -0,0 +1,32 @@
+92 12 0b 03 04 19 02 02
+03 52 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 81
+20 08 3c 3c 01 40 83 01
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 11 62 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 ad 01
+00 00 00 00 00 00 ff ab
+48 4d 54 34 32 35 53 36
+41 46 52 36 41 2d 50 42
+20 20 4e 30 80 ad 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/glimmer/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex b/src/mainboard/google/glimmer/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
new file mode 100644
index 0000000..f99c92a
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/micron_1GiB_dimm_MT41K128M16JT-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 03 11 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+50 00 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 6a 15
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/glimmer/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/google/glimmer/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000..f3bcb56
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/mainboard/google/glimmer/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex b/src/mainboard/google/glimmer/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex
new file mode 100644
index 0000000..96cf568
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/samsung_1GiB_dimm_K4B2G1646Q-BYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B2G1646Q-BYK0
+92 12 0B 03 03 11 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 00 05 3C 3C 01 40 83 01
+00 00 00 00 00 00 00 00 00 88 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 11 20 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 00 00
+4b 34 42 32 47 31 36 34 36 51 2d 42 59 4b 30 20
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glimmer/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex b/src/mainboard/google/glimmer/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
new file mode 100644
index 0000000..ac9a0e0
--- /dev/null
+++ b/src/mainboard/google/glimmer/spd/samsung_2GiB_dimm_K4B4G1646Q-HYK0.spd.hex
@@ -0,0 +1,17 @@
+# Samsung K4B4G1646Q-HYK0
+92 12 0B 03 04 19 02 02 03 11 01 08 0A 00 FE 00
+69 78 69 3C 69 11 18 81 20 08 3C 3C 01 40 83 05
+00 00 00 00 00 00 00 00 88 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 80 CE 01 00 00 00 00 00 00 6C F9
+4D 34 37 31 42 35 36 37 34 51 48 30 2D 59 4B 30
+20 20 00 00 80 CE 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/google/glimmer/w25q64.c b/src/mainboard/google/glimmer/w25q64.c
new file mode 100644
index 0000000..a9ed8ac
--- /dev/null
+++ b/src/mainboard/google/glimmer/w25q64.c
@@ -0,0 +1,70 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <soc/spi.h>
+
+/*
+ * SPI lockdown configuration W25Q64FW.
+ */
+#define SPI_OPMENU_0 0x01 /* WRSR: Write Status Register */
+#define SPI_OPTYPE_0 0x01 /* Write, no address */
+
+#define SPI_OPMENU_1 0x02 /* BYPR: Byte Program */
+#define SPI_OPTYPE_1 0x03 /* Write, address required */
+
+#define SPI_OPMENU_2 0x03 /* READ: Read Data */
+#define SPI_OPTYPE_2 0x02 /* Read, address required */
+
+#define SPI_OPMENU_3 0x05 /* RDSR: Read Status Register */
+#define SPI_OPTYPE_3 0x00 /* Read, no address */
+
+#define SPI_OPMENU_4 0x20 /* SE20: Sector Erase 0x20 */
+#define SPI_OPTYPE_4 0x03 /* Write, address required */
+
+#define SPI_OPMENU_5 0x9f /* RDID: Read ID */
+#define SPI_OPTYPE_5 0x00 /* Read, no address */
+
+#define SPI_OPMENU_6 0xd8 /* BED8: Block Erase 0xd8 */
+#define SPI_OPTYPE_6 0x03 /* Write, address required */
+
+#define SPI_OPMENU_7 0x0b /* FAST: Fast Read */
+#define SPI_OPTYPE_7 0x02 /* Read, address required */
+
+#define SPI_OPPREFIX ((0x50 << 8) | 0x06) /* EWSR and WREN */
+#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
+ (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
+ (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
+ (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
+#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
+ (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
+#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
+ (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
+#define SPI_VSCC (WG_64_BYTE | EO(0x20) | BES_4_KB)
+
+static const struct spi_config spi_config = {
+ .preop = SPI_OPPREFIX,
+ .optype = SPI_OPTYPE,
+ .opmenu = { SPI_OPMENU_LOWER, SPI_OPMENU_UPPER },
+ .lvscc = SPI_VSCC,
+ .uvscc = SPI_VSCC,
+};
+
+int mainboard_get_spi_config(struct spi_config *cfg)
+{
+ memcpy(cfg, &spi_config, sizeof(*cfg));
+
+ return 0;
+}
1
0