the following patch was just integrated into master:
commit 3727a8d909c0323eaf21076fd5e327757911ca10
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 19 16:37:46 2016 -0700
drivers/i2c/tpm/cr50: Reduce max buffer size
Reduce the static buffer size from the generic default 1260
down to 64 to match the max FIFO size for the cr50 hardware
and reduce the footprint of the driver.
BUG=chrome-os-partner:53336
Change-Id: I6f9f71d501b60299edad4b16cc553a85391a1866
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16664
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16664 for details.
-gerrit
the following patch was just integrated into master:
commit 2ea13c8699dc27a7a0ed2874c20508a6a59a201f
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Mon Sep 19 16:04:39 2016 -0700
drivers/i2c/tpm: Split cr50 driver from main driver
Originally I thought it would be cleaner to keep this code in one
place, but as things continue to diverge it ends up being easier
to split this into its own driver. This way the different drivers
in coreboot, depthcharge, and the kernel, can all be standalone
and if one is changed it is easier to modify the others.
This change splits out the cr50 driver and brings along the basic
elements from the existing driver with no real change in
functionality. The following commits will modify the code to make
it consistent so it can all be shared with depthcharge and the
linux kernel drivers.
BUG=chrome-os-partner:53336
Change-Id: I3b62b680773d23cc5a7d2217b9754c6c28bccfa7
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16663
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16663 for details.
-gerrit
the following patch was just integrated into master:
commit dca223cb38ab73744f490eb5b4cc6c7c2598f2c3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Wed Sep 14 16:27:04 2016 -0700
drivers/i2c/tpm: Move common variables to header
Move the common enums and variables to tpm.h so it can be
used by multiple drivers.
BUG=chrome-os-partner:53336
Change-Id: Ie749f13562be753293448fee2c2d643797bf8049
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16662
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/16662 for details.
-gerrit
the following patch was just integrated into master:
commit 8ea06512e69f5f5378316021e106732f6c89fbd2
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Sep 19 13:58:01 2016 -0600
Makefiles: update cbfs types from bare numbers to values
These values are found in util/cbfstool/cbfs.h.
Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16646
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16646 for details.
-gerrit
伊藤雄一 (yui.corebt(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15930
-gerrit
commit 6e5cc12b1e8a22d901613b0626635d95ab03e90b
Author: Yuichi Ito <yui.corebt(a)gmail.com>
Date: Tue Aug 2 08:51:59 2016 +0300
mainboard/elmex: Add new board pcm205401
pcm205401 is CPU board equipped with T40R of AMD. We used SeaBIOS and
Windows Embedded Standard 7 to test pcm205401.
In comparison to pcm205400, only VGA PCI ID is changed and board
identifier strings in SMBIOS / DMI.
Change-Id: I6c7e90db84f13ffbf9e629f2b92649895a466155
Signed-off-by: Yuichi Ito <yui.corebt(a)gmail.com>
---
src/mainboard/elmex/pcm205400/Kconfig | 14 +++++++++-----
src/mainboard/elmex/pcm205401/Kconfig | 26 ++++++++++++++++++++++++++
src/mainboard/elmex/pcm205401/Kconfig.name | 2 ++
src/mainboard/elmex/pcm205401/board_info.txt | 5 +++++
4 files changed, 42 insertions(+), 5 deletions(-)
diff --git a/src/mainboard/elmex/pcm205400/Kconfig b/src/mainboard/elmex/pcm205400/Kconfig
index 61667ec..a901301 100644
--- a/src/mainboard/elmex/pcm205400/Kconfig
+++ b/src/mainboard/elmex/pcm205400/Kconfig
@@ -19,6 +19,14 @@ config MAINBOARD_PART_NUMBER
string
default "pcm205400"
+config VGA_BIOS_ID
+ string
+ default "1002,9806" # FUSION_G_T56N
+
+endif # BOARD_ELMEX_PCM205400
+
+if BOARD_ELMEX_PCM205400 || BOARD_ELMEX_PCM205401
+
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_AGESA_FAMILY14
@@ -61,12 +69,8 @@ config VGA_BIOS
bool
default n
-config VGA_BIOS_ID
- string
- default "1002,9806" # FUSION_G_T56N
-
config SB800_AHCI_ROM
bool
default n
-endif # BOARD_ELMEX_PCM205400
+endif # BOARD_ELMEX_PCM205400 | BOARD_ELMEX_PCM205401
diff --git a/src/mainboard/elmex/pcm205401/Kconfig b/src/mainboard/elmex/pcm205401/Kconfig
new file mode 100644
index 0000000..a9bbe6e
--- /dev/null
+++ b/src/mainboard/elmex/pcm205401/Kconfig
@@ -0,0 +1,26 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2011 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+if BOARD_ELMEX_PCM205401
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "pcm205401"
+
+config VGA_BIOS_ID
+ string
+ default "1002,9804" # FUSION_G_T40R
+
+endif # BOARD_ELMEX_PCM205401
diff --git a/src/mainboard/elmex/pcm205401/Kconfig.name b/src/mainboard/elmex/pcm205401/Kconfig.name
new file mode 100644
index 0000000..f70b215
--- /dev/null
+++ b/src/mainboard/elmex/pcm205401/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ELMEX_PCM205401
+ bool "pcm205401"
diff --git a/src/mainboard/elmex/pcm205401/board_info.txt b/src/mainboard/elmex/pcm205401/board_info.txt
new file mode 100644
index 0000000..4d51c8f
--- /dev/null
+++ b/src/mainboard/elmex/pcm205401/board_info.txt
@@ -0,0 +1,5 @@
+Board name: PCM205401
+Category: sbc
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit a68bdb8fe08347c3991b2e1daa6d55d270dbed11
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 57 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++
2 files changed, 60 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..182dd42
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH,
+ 0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store (PMC_BAR0, IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store (PMC_SRAM_BASE_0, SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..11c27ea 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,9 @@
#include "xhci.asl"
+/* PMC IPC */
+#include "pmc_ipc.asl"
+
/* LPC */
#include "lpc.asl"