the following patch was just integrated into master:
commit 386f084f976bfe80c34676ec80e09f44ee02b746
Author: Shunqian Zheng <zhengsq(a)rock-chips.com>
Date: Sat Sep 3 08:29:20 2016 +0800
gru/kevin: Decrease voltage for little cpu 1.5G to 1.15v
In kernel side we set 1.1v for 1.5G, even for coreboot RO,
a higher voltage could be safer, 1.2v now seems too high.
BRANCH=none
BUG=chrome-os-partner:56948
TEST=bootup
Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab
Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df
Original-Signed-off-by: Shunqian Zheng <zhengsq(a)rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/380896
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16583
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16583 for details.
-gerrit
the following patch was just integrated into master:
commit 03cd118025e0f7aab139254e07f9d1dca3c242e5
Author: Simon Glass <sjg(a)chromium.org>
Date: Sat Aug 27 15:10:30 2016 -0600
rockchip: spi: Improve SPI read efficiency
The SPI driver is quite slow at reading data. For example, with a 24MHz
clock on gru it achieves a read speed of only 13.9Mbps.
We can correct this by reading the status registers once, then reading as
many bytes as are available before checking the status registers again. It
seems likely that a status register read requires synchronizing with the
SPI FIFO clock domain, which takes a while.
BUG=chrome-os-partner:56556
BRANCH=none
TEST=run on gru and see the speed increase from 13.920 Mbps to 24.712 Mbps
Change-Id: I24aed0c9c6c5445634c4e056922afaee4e9a7b33
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 49c2fc20d7d7d703763e9b0a6f68313a349a84b9
Original-Change-Id: I42745f01f0fe069f6ae26d866004d36bb257e6b2
Original-Signed-off-by: Simon Glass <sjg(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376945
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16582 for details.
-gerrit
the following patch was just integrated into master:
commit 2b7a6019f26aaaa1d01a2a69adfbf58cde919679
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Fri Aug 26 17:03:34 2016 -0700
Veyron: Increase bit-per-pixel to 32
This enhances gradation of some icons on vboot screens.
BUG=chrome-os-partner:56056
BRANCH=none
TEST=Booted Jerry
Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166
Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376884
Reviewed-on: https://review.coreboot.org/16581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16581 for details.
-gerrit
the following patch was just integrated into master:
commit f52288f9350324602552481bd3647e11a97f99c6
Author: Julius Werner <jwerner(a)chromium.org>
Date: Thu Sep 1 11:50:18 2016 -0700
google/gru: Fix up PWM regulator ranges
We did yet another small adjustment to the PWM regulator ranges for
Kevin rev6... this patch reflects that in code. Also rewrite code and
descriptions to indicate that these new ranges are not just for Kevin,
but also planned to be used on Gru rev2 and any future Gru derivatives
(which as I understand it is the plan, right?).
BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted my rev5, for whatever that's worth...
Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9
Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/379921
Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16580
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16580 for details.
-gerrit
the following patch was just integrated into master:
commit dd6ab34d5b6207a2e06591debbe5b46647e27bf6
Author: Daisuke Nojiri <dnojiri(a)chromium.org>
Date: Fri Aug 26 17:03:09 2016 -0700
Gru: Increase bit-per-pixel to 32
This enhances gradation of some icons on vboot screens.
BUG=chrome-os-partner:56056
BRANCH=none
TEST=Booted kevin-tpm2
Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c
Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4
Original-Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376883
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16579
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16579 for details.
-gerrit
the following patch was just integrated into master:
commit b6bf1ddb91ccb6241827792afead6ac3fce79eb5
Author: Julius Werner <jwerner(a)chromium.org>
Date: Wed Aug 24 19:38:05 2016 -0700
gru: Add watchdog reset support
This patch adds support to reboot the whole board after a hardware
watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to
Veyron.
From my tests it looks like both SRAM and PMUSRAM get preserved across
warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that
makes it easier to deal with in coreboot (PMUSRAM is currently not
mapped as cached, so we don't need to worry about flushing the results
back before reboot).
BRANCH=None
BUG=chrome-os-partner:56600
TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30
seconds. Confirm that system reboots correctly without entering recovery
and we get a HW watchdog event in the eventlog.
Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098
Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3
Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/375562
Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16578
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16578 for details.
-gerrit
the following patch was just integrated into master:
commit aa1d314ac2febafc5243266b420ff57b280621c5
Author: Randall Spangler <rspangler(a)chromium.org>
Date: Fri Aug 26 16:01:16 2016 -0700
vboot/vbnv_flash: Binary search to find last used entry
This improves the previous linear search to O(log n). No change in
storage format.
BUG=chromium:640656
BRANCH=none
TEST=Manual
(test empty)
flashrom -i RW_NVRAM -e
Reboot; device should boot normally.
(start using records)
crossystem kern_nv=0xaab0
crossystem recovery_request=1 && reboot
Device should go into recovery mode with reason 1
Reboot again; it should boot normally.
crossystem kern_nv (should still contain 0xaab0)
Repeat steps several times with request=2, 3, etc.
flashrom -i RW_NVRAM -r nvdata
Modify nvdata to copy the first record across all valid
records
flashrom -i RW_NVRAM -w nvdata
Reboot; device should boot normally.
Change-Id: Ieb97563ab92bd1d18a4f6a9e1d20157efe311fb4
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: db9bb2d3927ad57270d7acfd42cf0652102993b1
Original-Change-Id: I1eb5fd9fa6b2ae56833f024bcd3c250147bcc7a1
Original-Signed-off-by: Randall Spangler <rspangler(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376928
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16577
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16577 for details.
-gerrit
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16362
-gerrit
commit f3ef3ca0fc62d36a5ebf6531bbcd35489be5177f
Author: Martin Roth <martinroth(a)google.com>
Date: Tue Aug 30 09:39:48 2016 -0600
Makefile.inc: lint: Update to run lint-server scripts
- Add junit-amend command so that junit.xml doesn't get overwritten
- Add lint-server as a valid option
- Call lint with lint-server --junit-amend from what-jenkins-does
- Add final newlines check as lint-server script
Change-Id: I7e4156844b8c60790e03a0e43564610bb0c8f386
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
Makefile.inc | 1 +
util/lint/lint | 8 ++++++--
util/lint/lint-server-015-final-newlines | 17 +++++++++++++++++
3 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/Makefile.inc b/Makefile.inc
index 40e8942..a34c727 100644
--- a/Makefile.inc
+++ b/Makefile.inc
@@ -1047,6 +1047,7 @@ JENKINS_PAYLOAD?=none
CPUS?=4
what-jenkins-does:
util/lint/lint lint-stable --junit
+ util/lint/lint lint-server --junit-amend
util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD) -x -X $(top)/abuild-chromeos.xml
util/abuild/abuild -B -J $(if $(JENKINS_NOCCACHE),,-y) -c $(CPUS) -z -p $(JENKINS_PAYLOAD)
(cd payloads/libpayload; unset COREBOOT_BUILD_DIR; $(MAKE) $(if $(JENKINS_NOCCACHE),,CONFIG_LP_CCACHE=y) V=$(V) Q=$(Q) junit.xml)
diff --git a/util/lint/lint b/util/lint/lint
index 826685d..db24c7d 100755
--- a/util/lint/lint
+++ b/util/lint/lint
@@ -14,7 +14,7 @@
#set -x # uncomment for debug
usage () {
- printf "Usage: %s <lint|lint-stable> [--junit]\n" "$0"
+ printf "Usage: %s <lint|lint-stable|lint-server> [--junit]\n" "$0"
}
#write to the junit xml file if --junit was specified
@@ -25,7 +25,8 @@ junit_write () {
}
#verify the first command line parameter
-if [ -z "$1" ] || [ "$1" != "lint" ] && [ "$1" != "lint-stable" ]; then
+if [ -z "$1" ] || [ "$1" != "lint" ] && [ "$1" != "lint-stable" ] && \
+ [ "$1" != "lint-server" ]; then
usage
exit 1
fi
@@ -40,6 +41,9 @@ if [ "$2" = "--junit" ]; then
JUNIT=1
echo '<?xml version="1.0" encoding="utf-8"?>' > "$XMLFILE"
junit_write '<testsuite>'
+elif [ "$2" = "--junit-amend" ]; then
+ JUNIT=1
+ junit_write '<testsuite>'
else
JUNIT=0
fi
diff --git a/util/lint/lint-server-015-final-newlines b/util/lint/lint-server-015-final-newlines
new file mode 100755
index 0000000..c3f66c0
--- /dev/null
+++ b/util/lint/lint-server-015-final-newlines
@@ -0,0 +1,17 @@
+#!/bin/sh
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2016 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# DESCR: Check that files end with a single newline
+
+lint-015-final-newlines
Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16360
-gerrit
commit 288ad2b5ab42963b91e5e4df4053c786172ef560
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Aug 29 15:49:02 2016 -0600
util/lint: add stable checkpatch for jenkins
The checkpatch script takes a while to run, so don't add it to the
lint-stable checks which run pre-commit.
Change-Id: I907176c21c057564495b75133ba10b0761c9fe7b
Signed-off-by: Martin Roth <martinroth(a)google.com>
---
util/lint/lint-server-007-checkpatch | 44 ++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)
diff --git a/util/lint/lint-server-007-checkpatch b/util/lint/lint-server-007-checkpatch
new file mode 100755
index 0000000..5fbed01
--- /dev/null
+++ b/util/lint/lint-server-007-checkpatch
@@ -0,0 +1,44 @@
+#!/bin/sh
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2016 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+#
+# DESCR: Run checkpatch on directories that are known good
+
+# Top level
+util/lint/lint-007-checkpatch "src/acpi"
+
+#src/cpu
+util/lint/lint-007-checkpatch "src/cpu/armltd src/cpu/qemu-power8 \
+src/cpu/qemu-x86"
+
+#src/drivers
+util/lint/lint-007-checkpatch "src/drivers/dec src/drivers/gic \
+src/drivers/ti"
+
+#src/ec
+util/lint/lint-007-checkpatch "src/ec/purism"
+
+#src/include
+util/lint/lint-007-checkpatch "src/include/boot src/include/superio \
+src/include/sys"
+
+#src/mainboard
+util/lint/lint-007-checkpatch "src/mainboard/adlink src/mainboard/linutop \
+src/mainboard/purism src/mainboard/ti"
+
+# src/soc
+util/lint/lint-007-checkpatch "src/soc/rdc"
+
+# src/superio
+util/lint/lint-007-checkpatch "src/superio/acpi src/superio/common"
the following patch was just integrated into master:
commit 57bfbb0508e81c338696539f051ce04f4ba5393d
Author: Martin Roth <martinroth(a)google.com>
Date: Mon Aug 29 15:32:10 2016 -0600
checkpatch.pl: ignore '#define asmlinkage'
checkpatch warns that the asmlinkage storage class should be at the
beginning of the declaration when we define it to be an empty value.
Change-Id: I12292d5b42bf6da9130bb969ebe00fca8efcf049
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16358
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16358 for details.
-gerrit