Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit ffd1f8720dcca4df50c543a36341ef4a0751f4fe
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 58 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 3 ++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..2dc5323
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH,
+ 0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store (PMC_BAR0, IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store (MCH_BASE_ADDR+MAILBOX_DATA, MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store (MCH_BASE_ADDR+MAILBOX_INTF, MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store (PMC_SRAM_BASE_0, SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..11c27ea 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,9 @@
#include "xhci.asl"
+/* PMC IPC */
+#include "pmc_ipc.asl"
+
/* LPC */
#include "lpc.asl"
Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16649
-gerrit
commit 9c2ca329440a40d02437876a75f91fd163953355
Author: Zhao, Lijian <lijian.zhao(a)intel.com>
Date: Tue Sep 6 18:48:19 2016 -0700
soc/intel/apollolake: Add pmc_ipc device support
Dedicate pmc_ipc DSDT entry is required for pmc_ipc kernel driver.The
ACPI mode entry include resources for PMC_IPC, SRAM, ACPI IO and
Punit Mailbox.
BRANCH=None
BUG=chrome-os-partner:57364
TEST=Boot up into OS successully and check with dmesg to see the
driver had been loadded success without errors.
Change-Id: I3f60999ab90962c4ea0a444812e4a7dcce1da5b6
Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com>
---
src/soc/intel/apollolake/acpi/pmc_ipc.asl | 56 +++++++++++++++++++++++++++
src/soc/intel/apollolake/acpi/southbridge.asl | 5 +++
2 files changed, 61 insertions(+)
diff --git a/src/soc/intel/apollolake/acpi/pmc_ipc.asl b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
new file mode 100644
index 0000000..44838bc
--- /dev/null
+++ b/src/soc/intel/apollolake/acpi/pmc_ipc.asl
@@ -0,0 +1,56 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/iomap.h>
+
+#define MAILBOX_DATA 0x7080
+#define MAILBOX_INTF 0x7084
+#define PMIO_LENGTH 0x80
+
+Device (IPC1)
+{
+ Name (_ADR, 0x0) //ACPI MODE as P2SB got hidden in OS
+ Name (_HID, "INT34D2")
+ Name (_CID, "INT34D2")
+ Name (_DDN, "Intel(R) IPC1 Controller")
+ Name (RBUF, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x0,0x2000,IBAR)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MDAT)
+ Memory32Fixed (ReadWrite, 0x0,0x4,MINF)
+ IO (Decode16, ACPI_PMIO_BASE, ACPI_PMIO_BASE+PMIO_LENGTH, 0x04, PMIO_LENGTH)
+ Memory32Fixed (ReadWrite, 0x0,0x2000,SBAR)
+ Interrupt (ResourceConsumer, Level, ActiveLow, Exclusive, , , )
+ {
+ PMC_INT
+ }
+ })
+ Method (_CRS, 0x0, NotSerialized)
+ {
+ CreateDwordField (^RBUF, ^IBAR._BAS, IBAS)
+ Store(PMC_BAR0,IBAS)
+
+ CreateDwordField (^RBUF, ^MDAT._BAS, MDBA)
+ Store(MCH_BASE_ADDR+MAILBOX_DATA,MDBA)
+ CreateDwordField (^RBUF, ^MINF._BAS, MIBA)
+ Store(MCH_BASE_ADDR+MAILBOX_INTF,MIBA)
+
+ CreateDwordField (^RBUF, ^SBAR._BAS, SBAS)
+ Store(PMC_SRAM_BASE_0,SBAS)
+
+ Return (^RBUF)
+ }
+}
diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl
index d7ced0f..f31a086 100644
--- a/src/soc/intel/apollolake/acpi/southbridge.asl
+++ b/src/soc/intel/apollolake/acpi/southbridge.asl
@@ -31,6 +31,11 @@
#include "xhci.asl"
+#if IS_ENABLED(CONFIG_INTEL_PMC_IPC)
+ /* PMC IPC */
+ #include "pmc_ipc.asl"
+#endif
+
/* LPC */
#include "lpc.asl"
the following patch was just integrated into master:
commit 2ab981b87eacd1e2baf29b514b220e5de61af681
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Aug 31 16:43:49 2016 -0600
buildgcc: Update to acpica version 20160831
Change-Id: I3e3973e1c47505718cf73435156104ab73680441
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16387
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16387 for details.
-gerrit
the following patch was just integrated into master:
commit 03b9ecb2cf9c9fea8c9e849b6ebd5860a842329d
Author: Martin Roth <martinroth(a)google.com>
Date: Sat Sep 10 15:02:11 2016 -0600
Makefile.inc: Add aliases for submodule updates to gitconfig target
Updating submodules seem to give people headaches, so this adds a pair
of git aliases to update them.
'git sup' updates the submodules to the latest versions, but leaves any
locally modified files.
'git sup-destroy' will remove the current submodules and re-initialize
them. This deletes any local changes.
Change-Id: Id62a30d88b3b6d285b3f00555d7609509aa1561f
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/16573
Tested-by: build bot (Jenkins)
Reviewed-by: Omar Pakker
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16573 for details.
-gerrit
the following patch was just integrated into master:
commit a5aad2ed68690d748c650f69a2e39f91a7b02608
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 09:47:16 2016 -0600
src/mainboard/lenovo-winent: Add space around operators
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/16641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16641 for details.
-gerrit
the following patch was just integrated into master:
commit 531b87ac4e8038aedf9c44c29fe2c1fc31adb346
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Mon Sep 19 09:46:33 2016 -0600
src/mainboard/getac - kontron: Add space around operators
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16640 for details.
-gerrit
the following patch was just integrated into master:
commit 78c63860a61c4562e78a35c5d5457085acf27670
Author: Simon Glass <sjg(a)chromium.org>
Date: Sun Sep 4 16:37:04 2016 -0600
selfboot: Move the usable-RAM check into a function
In preparation for making this check optional, move it into its own
function. load_self_segments() is already long and we don't want to make
it longer.
BUG=chrome-os-partner:56314
BRANCH=none
TEST=boot on gru and see that BL31 loads and runs correctly
Change-Id: If48d2bf485a23f21c5599670e77a7b8b098f1a88
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 2381e02efa2033857ac06acbc4f0c0dd08de1080
Original-Change-Id: I005e5e4d9b2136605bdd95e9060655df7a8238cb
Original-Signed-off-by: Simon Glass <sjg(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/381092
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: https://review.coreboot.org/16585
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
See https://review.coreboot.org/16585 for details.
-gerrit
the following patch was just integrated into master:
commit 17c2b94ac1d1926f66c66fd4a00bdb044247b090
Author: Simon Glass <sjg(a)chromium.org>
Date: Sat Aug 27 12:02:09 2016 -0600
arm_tf: Fix code style nits and comments
Tidy up a few things which look incorrect in this file.
BUG=chrome-os-partner:56314
BRANCH=none
TEST=build for gru
Signed-off-by: Martin Roth <martinroth(a)chromium.org>
Original-Commit-Id: 434e9ceb5fce69b28de577cdc3541a439871f5ed
Original-Change-Id: Ida7a62ced953107c8e1723003bcb470c81de4c2f
Original-Signed-off-by: Simon Glass <sjg(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/376848
Original-Commit-Ready: Simon Glass <sjg(a)google.com>
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: If8c283fe8513e6120de2fd52eab539096a4e0c9b
Reviewed-on: https://review.coreboot.org/16584
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/16584 for details.
-gerrit