coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: rockchip: spi: Add support for 16-bit APB reads
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16712 -gerrit commit 91cdcba9bed9d54ff6652c76741a40197b3fbcb0 Author: Simon Glass <sjg(a)chromium.org> Date: Mon Sep 5 11:10:26 2016 -0600 rockchip: spi: Add support for 16-bit APB reads With a SPI clock above about 24MHz the APB cannot keep up when doing individual byte transfers. Adjust the driver to use 16-bit reads when it can, to remove this bottleneck. Any transaction which involves writing bytes still uses 8-bit transfers, to simplify the code. These are the transfers that are not time-critical since they tend to be small. The case that really matters is reading from SPI flash. In general we can use 16-bit reads anytime we are transferring an even number of bytes. If the code detects an odd number of bytes, it tries to perform the operation in two steps: once in 16-bit mode with an even number of bytes, and once in 8-bit mode for the final byte. This allow us to use 16-bit reads even if asked to transfer (for example) 0xf423 bytes. The limit on in_now and out_now is adjusted to 0xfffe to avoid an extra transfer when transferring ~>=64KB. CQ-DEPEND=CL:383232 BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. I tested (with extra debugging) that the 16-bit case is being picked when it should be. Change-Id: If5effae9a84e4de06537fd594bedf7f01d6a9c88 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ec250b4931c7d99cc014e32ab597fca948299d08 Original-Change-Id: Idc5b7e5d82cdbdc1e8fe8b2d6da819edf2d5570c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381312 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/spi.c | 53 ++++++++++++++++++++++++++++++++----------- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 7dcaaad..57e9ca1 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -149,9 +149,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) /* First Bit Mode */ ctrlr0 |= (SPI_FBM_MSB << SPI_FBM_OFFSET); - /* Byte and Halfword Transform */ - ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); - /* Frame Format */ ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); @@ -220,7 +217,7 @@ static void set_transfer_mode(struct rockchip_spi *regs, } /* returns 0 to indicate success, <0 otherwise */ -static int do_xfer(struct rockchip_spi *regs, const void *dout, +static int do_xfer(struct rockchip_spi *regs, bool use_16bit, const void *dout, unsigned int *bytes_out, void *din, unsigned int *bytes_in) { uint8_t *in_buf = din; @@ -251,12 +248,23 @@ static int do_xfer(struct rockchip_spi *regs, const void *dout, * sychronizing with the SPI clock which is pretty slow. */ if (*bytes_in && !(sr & SR_RF_EMPT)) { - int todo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK; - - *bytes_in -= todo; - xferred = todo; - while (todo-- > 0) - *in_buf++ = read32(&regs->rxdr) & 0xff; + int fifo = read32(&regs->rxflr) & RXFLR_LEVEL_MASK; + int val; + + if (use_16bit) + xferred = fifo * 2; + else + xferred = fifo; + *bytes_in -= xferred; + while (fifo-- > 0) { + val = read32(&regs->rxdr); + if (use_16bit) { + *in_buf++ = val & 0xff; + *in_buf++ = (val >> 8) & 0xff; + } else { + *in_buf++ = val & 0xff; + } + } } min_xfer -= xferred; @@ -290,12 +298,31 @@ int spi_xfer(struct spi_slave *slave, const void *dout, * seems to work fine. */ while (bytes_out || bytes_in) { - unsigned int in_now = MIN(bytes_in, 0xffff); - unsigned int out_now = MIN(bytes_out, 0xffff); + unsigned int in_now = MIN(bytes_in, 0xfffe); + unsigned int out_now = MIN(bytes_out, 0xfffe); unsigned int in_rem, out_rem; + unsigned int mask; + bool use_16bit; rockchip_spi_enable_chip(regs, 0); + /* + * Use 16-bit transfers for higher-speed reads. If we are + * transferring an odd number of bytes, try to make it even. + */ + use_16bit = false; + if (bytes_out == 0) { + if ((in_now & 1) && in_now > 1) + in_now--; + if (!(in_now & 1)) + use_16bit = true; + } + mask = SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET; + if (use_16bit) + clrbits_le32(&regs->ctrlr0, mask); + else + setbits_le32(&regs->ctrlr0, mask); + /* Enable/disable transmitter and receiver as needed to * avoid sending or reading spurious bits. */ set_transfer_mode(regs, bytes_out, bytes_in); @@ -307,7 +334,7 @@ int spi_xfer(struct spi_slave *slave, const void *dout, in_rem = in_now; out_rem = out_now; - ret = do_xfer(regs, dout, &out_rem, din, &in_rem); + ret = do_xfer(regs, use_16bit, dout, &out_rem, din, &in_rem); if (ret < 0) break;

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New patch to review for coreboot: google/gru: Ensure correct pull resistors for special-function pins
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16711 -gerrit commit 948c1dea30808d9d9e27057e4e217baf7dc5e5af Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 2 11:25:56 2016 -0700 google/gru: Ensure correct pull resistors for special-function pins Several of the special function pins we're using in firmware have a pre-assigned pull-up or pull-down on power-on reset. We don't want those to interfere with any of the signaling we're trying to do on those pins, so this patch disables them. Also do some house-cleaning to group the bootblock code better, and change the setup code for all SPI and I2C buses to first initialize the controller and then mux the pins... I assume this might be a little safer (in case the controller peripheral has some pins in a weird state before it gets fully initialized, we don't want to mux it through too early). BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560 Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382532 --- src/mainboard/google/gru/bootblock.c | 71 +++++++++++++++++++++++--------- src/mainboard/google/gru/mainboard.c | 37 ++++++++++------- src/mainboard/google/gru/pwm_regulator.c | 5 +++ 3 files changed, 78 insertions(+), 35 deletions(-) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index c630b2d..d76ec8b 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -63,42 +63,73 @@ void bootblock_mainboard_early_init(void) #endif } -static void speed_up_boot_cpu(void) +static void configure_spi_flash(void) { - pwm_regulator_configure(PWM_REGULATOR_LIT, 1150); + gpio_input(GPIO(1, A, 7)); /* SPI1_MISO remove pull-up */ + gpio_input(GPIO(1, B, 0)); /* SPI1_MOSI remove pull-up */ + gpio_input(GPIO(1, B, 1)); /* SPI1_CLK remove pull-up */ + gpio_input(GPIO(1, B, 2)); /* SPI1_CS remove pull-up */ - udelay(200); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33*MHz); + rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5); - rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); + write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); + write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); } -void bootblock_mainboard_init(void) +static void configure_ec(void) { - speed_up_boot_cpu(); - - if (rkclk_was_watchdog_reset()) - reboot_from_watchdog(); + gpio_input(GPIO(2, C, 4)); /* SPI5_MISO remove pull-up */ + gpio_input(GPIO(2, C, 5)); /* SPI5_MOSI remove pull-up */ + gpio_input(GPIO(2, C, 6)); /* SPI5_CLK remove pull-up */ + gpio_input_pullup(GPIO(2, C, 7)); /* SPI5_CS confirm pull-up */ - /* Set pinmux and configure spi flashrom. */ - write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); - write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); - rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33000*KHz); - rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5); + rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750); - /* Set pinmux and configure EC SPI. */ write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5); - rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 3093750); +} +static void configure_tpm(void) +{ if (IS_ENABLED(CONFIG_GRU_HAS_TPM2)) { - /* Set pinmux and configure TPM SPI, which is not very fast. */ - write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0); + gpio_input(GPIO(3, A, 4)); /* SPI0_MISO remove pull-up */ + gpio_input(GPIO(3, A, 5)); /* SPI0_MOSI remove pull-up */ + gpio_input(GPIO(3, A, 6)); /* SPI0_CLK remove pull-up */ + gpio_input_pullup(GPIO(3, A, 7)); /* SPI0_CS confirm */ + rockchip_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, 1500*KHz); + + write32(&rk3399_grf->iomux_spi0, IOMUX_SPI0); } else { - /* Set pinmux and configure TPM I2C */ + gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull-up */ + gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull-up */ + + i2c_init(0, 400*KHz); + write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); - i2c_init(0, 400*KHz); } +} + +static void speed_up_boot_cpu(void) +{ + pwm_regulator_configure(PWM_REGULATOR_LIT, 1150); + + udelay(200); + + rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); +} + +void bootblock_mainboard_init(void) +{ + speed_up_boot_cpu(); + + if (rkclk_was_watchdog_reset()) + reboot_from_watchdog(); + + configure_spi_flash(); + configure_ec(); + configure_tpm(); setup_chromeos_gpios(); } diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index a2b74ba..8359ca4 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -94,19 +94,13 @@ static void configure_sdmmc(void) gpio_output(GPIO(2, D, 4), 0); /* Keep the max voltage */ - /* - * The SD card on this board is connected to port SDMMC0, which is - * multiplexed with GPIO4B pins 0..5. - * - * Disable all pullups on these pins. For pullup configuration - * register layout stacks banks 2 through 4 together, hence [2] means - * group 4, [1] means bank B. This register is described on page 342 - * of section 1 of the TRM. - * - * Each GPIO pin's pull config takes two bits, writing zero to the - * field disables pull ups/downs, as described on page 342 of rk3399 - * TRM Version 0.3 Part 1. - */ + gpio_input(GPIO(4, B, 0)); /* SDMMC0_D0 remove pull-up */ + gpio_input(GPIO(4, B, 1)); /* SDMMC0_D1 remove pull-up */ + gpio_input(GPIO(4, B, 2)); /* SDMMC0_D2 remove pull-up */ + gpio_input(GPIO(4, B, 3)); /* SDMMC0_D3 remove pull-up */ + gpio_input(GPIO(4, B, 4)); /* SDMMC0_CLK remove pull-down */ + gpio_input(GPIO(4, B, 5)); /* SDMMC0_CMD remove pull-up */ + write32(&rk3399_grf->gpio2_p[2][1], RK_CLRSETBITS(0xfff, 0)); /* @@ -132,6 +126,16 @@ static void configure_sdmmc(void) static void configure_codec(void) { + gpio_input(GPIO(3, D, 0)); /* I2S0_SCLK remove pull-up */ + gpio_input(GPIO(3, D, 1)); /* I2S0_RX remove pull-up */ + gpio_input(GPIO(3, D, 2)); /* I2S0_TX remove pull-up */ + gpio_input(GPIO(3, D, 3)); /* I2S0_SDI0 remove pull-up */ + gpio_input(GPIO(3, D, 4)); /* I2S0_SDI1 remove pull-up */ + /* GPIO3_D5 (I2S0_SDI2SDO2) not connected */ + gpio_input(GPIO(3, D, 6)); /* I2S0_SDO1 remove pull-up */ + gpio_input(GPIO(3, D, 7)); /* I2S0_SDO0 remove pull-up */ + gpio_input(GPIO(4, A, 0)); /* I2S0_MCLK remove pull-up */ + write32(&rk3399_grf->iomux_i2s0, IOMUX_I2S0); write32(&rk3399_grf->iomux_i2sclk, IOMUX_I2SCLK); @@ -206,10 +210,13 @@ static void enable_backlight_booster(void) */ udelay(1000); - /* Select pinmux for i2c0, which is the display backlight booster. */ + gpio_input(GPIO(1, B, 7)); /* I2C0_SDA remove pull_up */ + gpio_input(GPIO(1, C, 0)); /* I2C0_SCL remove pull_up */ + + i2c_init(0, 100*KHz); + write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); - i2c_init(0, 100*KHz); for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) { i2c_buf[0] = i2c_writes[i].reg; diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index d6d2eec..a81480a 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -17,6 +17,7 @@ #include <assert.h> #include <boardid.h> #include <console/console.h> +#include <gpio.h> #include <soc/grf.h> #include <soc/pwm.h> @@ -68,15 +69,19 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) switch (pwm) { case PWM_REGULATOR_GPU: + gpio_input(GPIO(4, C, 2)); /* PWM0 remove pull-down */ write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); break; case PWM_REGULATOR_BIG: + gpio_input(GPIO(4, C, 6)); /* PWM1 remove pull-down */ write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); break; case PWM_REGULATOR_LIT: + gpio_input(GPIO(1, C, 3)); /* PWM2 remove pull-down */ write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); break; case PWM_REGULATOR_CENTERLOG: + gpio_input(GPIO(0, A, 6)); /* PWM3 remove pull-down */ write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); break; }

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New patch to review for coreboot: rockchip: Remove pulls for gpio_output(), clean up code
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16710 -gerrit commit a541c8dd874588247b828a6235d2768de0a9f447 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Sep 1 22:55:58 2016 -0700 rockchip: Remove pulls for gpio_output(), clean up code Output GPIOs should never have a pull-up or pull-down resistor attached since they're actively driven. Since some GPIOs get initialized with a pull at power-on reset, we should explicitly overwrite that setting. Most other platforms do this on gpio_output, but Rockchip hadn't yet. Also, shuffle some code around to make things cleaner and allow for easier code reuse. BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I1425d074ea1e90f4484e1e84a8002b057192c5f7 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: df5b236bfd58b172435043c1cb792b917a4ec4ab Original-Change-Id: I044266d71ef8bd0518316ff72d829d1ca1e30f35 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382531 Original-Reviewed-by: Simon Glass <sjg(a)google.com> --- src/soc/rockchip/common/gpio.c | 21 +++++++++++++++------ src/soc/rockchip/common/include/soc/gpio.h | 15 ++++++++++----- src/soc/rockchip/rk3288/gpio.c | 2 +- src/soc/rockchip/rk3399/gpio.c | 8 ++++---- 4 files changed, 30 insertions(+), 16 deletions(-) diff --git a/src/soc/rockchip/common/gpio.c b/src/soc/rockchip/common/gpio.c index 6ea38d4..1ff0bc9 100644 --- a/src/soc/rockchip/common/gpio.c +++ b/src/soc/rockchip/common/gpio.c @@ -21,10 +21,15 @@ #include <soc/soc.h> #include <stdlib.h> -static void __gpio_input(gpio_t gpio, u32 pull) +static void gpio_set_dir(gpio_t gpio, enum gpio_dir dir) +{ + clrsetbits_le32(&gpio_port[gpio.port]->swporta_ddr, + 1 << gpio.num, dir << gpio.num); +} + +static void gpio_set_pull(gpio_t gpio, enum gpio_pull pull) { u32 pull_val = gpio_get_pull_val(gpio, pull); - clrbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); if (is_pmu_gpio(gpio)) clrsetbits_le32(gpio_grf_reg(gpio), 3 << (gpio.idx * 2), pull_val << (gpio.idx * 2)); @@ -35,17 +40,20 @@ static void __gpio_input(gpio_t gpio, u32 pull) void gpio_input(gpio_t gpio) { - __gpio_input(gpio, PULLNONE); + gpio_set_pull(gpio, GPIO_PULLNONE); + gpio_set_dir(gpio, GPIO_INPUT); } void gpio_input_pulldown(gpio_t gpio) { - __gpio_input(gpio, PULLDOWN); + gpio_set_pull(gpio, GPIO_PULLDOWN); + gpio_set_dir(gpio, GPIO_INPUT); } void gpio_input_pullup(gpio_t gpio) { - __gpio_input(gpio, PULLUP); + gpio_set_pull(gpio, GPIO_PULLUP); + gpio_set_dir(gpio, GPIO_INPUT); } int gpio_get(gpio_t gpio) @@ -55,7 +63,8 @@ int gpio_get(gpio_t gpio) void gpio_output(gpio_t gpio, int value) { - setbits_le32(&gpio_port[gpio.port]->swporta_ddr, 1 << gpio.num); clrsetbits_le32(&gpio_port[gpio.port]->swporta_dr, 1 << gpio.num, !!value << gpio.num); + gpio_set_dir(gpio, GPIO_OUTPUT); + gpio_set_pull(gpio, GPIO_PULLNONE); } diff --git a/src/soc/rockchip/common/include/soc/gpio.h b/src/soc/rockchip/common/include/soc/gpio.h index 2c72435..a888635 100644 --- a/src/soc/rockchip/common/include/soc/gpio.h +++ b/src/soc/rockchip/common/include/soc/gpio.h @@ -73,13 +73,18 @@ int is_pmu_gpio(gpio_t gpio); /* Return the io addr of gpio register */ void *gpio_grf_reg(gpio_t gpio); -enum { - PULLNONE = 0, - PULLUP, - PULLDOWN +enum gpio_pull { + GPIO_PULLNONE = 0, + GPIO_PULLUP = 1, + GPIO_PULLDOWN = 2, +}; + +enum gpio_dir { + GPIO_INPUT = 0, + GPIO_OUTPUT = 1, }; /* The gpio pull bias setting may be different between SoCs */ -u32 gpio_get_pull_val(gpio_t gpio, u32 pull); +u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull); #endif diff --git a/src/soc/rockchip/rk3288/gpio.c b/src/soc/rockchip/rk3288/gpio.c index c610408..41056f8 100644 --- a/src/soc/rockchip/rk3288/gpio.c +++ b/src/soc/rockchip/rk3288/gpio.c @@ -51,7 +51,7 @@ void *gpio_grf_reg(gpio_t gpio) return &rk3288_grf->gpio1_p[(gpio.port - 1)][gpio.bank]; } -u32 gpio_get_pull_val(gpio_t gpio, u32 pull) +u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull) { /* use the default gpio pull bias setting defined in soc/gpio.h */ return pull; diff --git a/src/soc/rockchip/rk3399/gpio.c b/src/soc/rockchip/rk3399/gpio.c index a0cf059..3316027 100644 --- a/src/soc/rockchip/rk3399/gpio.c +++ b/src/soc/rockchip/rk3399/gpio.c @@ -56,7 +56,7 @@ enum { PULLUP_1V8 = 3, }; -u32 gpio_get_pull_val(gpio_t gpio, u32 pull) +u32 gpio_get_pull_val(gpio_t gpio, enum gpio_pull pull) { /* The default pull bias setting defined in soc/gpio.h */ u32 pull_val = pull; @@ -67,13 +67,13 @@ u32 gpio_get_pull_val(gpio_t gpio, u32 pull) if (IS_GPIO_BANK(gpio, 0, A) || IS_GPIO_BANK(gpio, 0, B) || IS_GPIO_BANK(gpio, 2, C) || IS_GPIO_BANK(gpio, 2, D)) { switch (pull) { - case PULLUP: + case GPIO_PULLUP: pull_val = PULLUP_1V8; break; - case PULLDOWN: + case GPIO_PULLDOWN: pull_val = PULLDOWN_1V8; break; - default: + case GPIO_PULLNONE: pull_val = PULLNONE_1V8; } }

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New patch to review for coreboot: rockchip: rk3399: lower down kevin board sdram frequency to 800MHz
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16709 -gerrit commit 6e8d30fb995c10d5e5b1353be69d9c529a7f2506 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 8 11:16:26 2016 -0700 rockchip: rk3399: lower down kevin board sdram frequency to 800MHz we found some board not stable when sdram run 933Mhz, before we fix it, we need to lower down the sdram frequency to 800MHz. In this patch we modify the DQS delay from 0x280 to 0x260, extend the DQS window. BRANCH=None BUG=chrome-os-partner:56940 TEST=Booted Kevin. Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382724 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Tested-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/mainboard/google/gru/sdram_configs.c | 4 +-- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 40 +++++++++++----------- 2 files changed, 21 insertions(+), 23 deletions(-) diff --git a/src/mainboard/google/gru/sdram_configs.c b/src/mainboard/google/gru/sdram_configs.c index 2ececdf..1235eff 100644 --- a/src/mainboard/google/gru/sdram_configs.c +++ b/src/mainboard/google/gru/sdram_configs.c @@ -56,10 +56,8 @@ static enum dram_speeds get_sdram_index(void) return dram_200MHz; case 3: return dram_666MHz_NO_ODT; - case 4: - return dram_800MHz; default: - return dram_933MHz; + return dram_800MHz; } if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 3a937bf..034e9d8 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -660,11 +660,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_56_DATA */ 0x00000000, /* DENALI_PHY_57_DATA */ 0x00000000, /* DENALI_PHY_58_DATA */ - 0x02800280, /* DENALI_PHY_59_DATA */ - 0x02800280, /* DENALI_PHY_60_DATA */ - 0x02800280, /* DENALI_PHY_61_DATA */ - 0x02800280, /* DENALI_PHY_62_DATA */ - 0x00000280, /* DENALI_PHY_63_DATA */ + 0x02600260, /* DENALI_PHY_59_DATA */ + 0x02600260, /* DENALI_PHY_60_DATA */ + 0x02600260, /* DENALI_PHY_61_DATA */ + 0x02600260, /* DENALI_PHY_62_DATA */ + 0x00000260, /* DENALI_PHY_63_DATA */ 0x00000000, /* DENALI_PHY_64_DATA */ 0x00000000, /* DENALI_PHY_65_DATA */ 0x00000000, /* DENALI_PHY_66_DATA */ @@ -788,11 +788,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_184_DATA */ 0x00000000, /* DENALI_PHY_185_DATA */ 0x00000000, /* DENALI_PHY_186_DATA */ - 0x02800280, /* DENALI_PHY_187_DATA */ - 0x02800280, /* DENALI_PHY_188_DATA */ - 0x02800280, /* DENALI_PHY_189_DATA */ - 0x02800280, /* DENALI_PHY_190_DATA */ - 0x00000280, /* DENALI_PHY_191_DATA */ + 0x02600260, /* DENALI_PHY_187_DATA */ + 0x02600260, /* DENALI_PHY_188_DATA */ + 0x02600260, /* DENALI_PHY_189_DATA */ + 0x02600260, /* DENALI_PHY_190_DATA */ + 0x00000260, /* DENALI_PHY_191_DATA */ 0x00000000, /* DENALI_PHY_192_DATA */ 0x00000000, /* DENALI_PHY_193_DATA */ 0x00000000, /* DENALI_PHY_194_DATA */ @@ -916,11 +916,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_312_DATA */ 0x00000000, /* DENALI_PHY_313_DATA */ 0x00000000, /* DENALI_PHY_314_DATA */ - 0x02800280, /* DENALI_PHY_315_DATA */ - 0x02800280, /* DENALI_PHY_316_DATA */ - 0x02800280, /* DENALI_PHY_317_DATA */ - 0x02800280, /* DENALI_PHY_318_DATA */ - 0x00000280, /* DENALI_PHY_319_DATA */ + 0x02600260, /* DENALI_PHY_315_DATA */ + 0x02600260, /* DENALI_PHY_316_DATA */ + 0x02600260, /* DENALI_PHY_317_DATA */ + 0x02600260, /* DENALI_PHY_318_DATA */ + 0x00000260, /* DENALI_PHY_319_DATA */ 0x00000000, /* DENALI_PHY_320_DATA */ 0x00000000, /* DENALI_PHY_321_DATA */ 0x00000000, /* DENALI_PHY_322_DATA */ @@ -1044,11 +1044,11 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PHY_440_DATA */ 0x00000000, /* DENALI_PHY_441_DATA */ 0x00000000, /* DENALI_PHY_442_DATA */ - 0x02800280, /* DENALI_PHY_443_DATA */ - 0x02800280, /* DENALI_PHY_444_DATA */ - 0x02800280, /* DENALI_PHY_445_DATA */ - 0x02800280, /* DENALI_PHY_446_DATA */ - 0x00000280, /* DENALI_PHY_447_DATA */ + 0x02600260, /* DENALI_PHY_443_DATA */ + 0x02600260, /* DENALI_PHY_444_DATA */ + 0x02600260, /* DENALI_PHY_445_DATA */ + 0x02600260, /* DENALI_PHY_446_DATA */ + 0x00000260, /* DENALI_PHY_447_DATA */ 0x00000000, /* DENALI_PHY_448_DATA */ 0x00000000, /* DENALI_PHY_449_DATA */ 0x00000000, /* DENALI_PHY_450_DATA */

1 0

New patch to review for coreboot: gru: Increase SPI speed to 33MHz
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16708 -gerrit commit 0f027f52bd50d0fe63b56bf514dd0feaf47ab6e7 Author: Simon Glass <sjg(a)chromium.org> Date: Sun Sep 4 18:56:46 2016 -0600 gru: Increase SPI speed to 33MHz Increase the SPI bus speed to speed up boot time. The maximum supported speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed, given the clock parents. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. Total time spent on reading from SPI reduces from 185ms to 141ms. Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381313 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/bootblock.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 6598dfe..c630b2d 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -82,7 +82,8 @@ void bootblock_mainboard_init(void) /* Set pinmux and configure spi flashrom. */ write32(&rk3399_pmugrf->spi1_rxd, IOMUX_SPI1_RX); write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX); - rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 24750*KHz); + rockchip_spi_init(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 33000*KHz); + rockchip_spi_set_sample_delay(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 5); /* Set pinmux and configure EC SPI. */ write32(&rk3399_grf->iomux_spi5, IOMUX_SPI5);

1 0

New patch to review for coreboot: rockchip: spi: Set rxd sample delay when using high speed
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16707 -gerrit commit 84f89cdb8cdec9c43010ec72e60d900e88732960 Author: Simon Glass <sjg(a)chromium.org> Date: Mon Sep 5 11:04:50 2016 -0600 rockchip: spi: Set rxd sample delay when using high speed At higher SPI bus speeds the SPI RX value is not available in time for sampling at the normal time. Add a delay to ensure that we read the correct data. The value of 40ns is chosen arbitrarily. In my testing I can use a sample delay of 1 even at 24MHz. But since it is not necessary, I have left that case alone. It kicks in at 25MHz and up. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see no change at current speed Change-Id: I3ef335d9a532eaef1e76034bd02e185acf11176a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e9b620c47fc3e39211487507fadb8657afdebee7 Original-Change-Id: I65d66d752cbbbee4d02f475de23a52069a0e9782 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381311 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/include/soc/spi.h | 3 +++ src/soc/rockchip/common/spi.c | 18 ++++++++++++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/common/include/soc/spi.h b/src/soc/rockchip/common/include/soc/spi.h index dcaa471..0e1847c 100644 --- a/src/soc/rockchip/common/include/soc/spi.h +++ b/src/soc/rockchip/common/include/soc/spi.h @@ -199,4 +199,7 @@ check_member(rockchip_spi, rxdr, 0x800); void rockchip_spi_init(unsigned int bus, unsigned int speed_hz); +/* Set the receive sample delay in nanoseconds */ +void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns); + #endif /* ! __COREBOOT_SRC_SOC_ROCKCHIP_COMMON_INCLUDE_SOC_SPI_H */ diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index f35f915..7dcaaad 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -32,7 +32,7 @@ struct rockchip_spi_slave { }; #define SPI_TIMEOUT_US 1000 -#define SPI_SRCCLK_HZ (99*MHz) +#define SPI_SRCCLK_HZ (198*MHz) #define SPI_FIFO_DEPTH 32 static struct rockchip_spi_slave rockchip_spi_slaves[] = { @@ -152,9 +152,6 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) /* Byte and Halfword Transform */ ctrlr0 |= (SPI_APB_8BIT << SPI_HALF_WORLD_TX_OFFSET); - /* Rxd Sample Delay */ - ctrlr0 |= (0 << SPI_RXDSD_OFFSET); - /* Frame Format */ ctrlr0 |= (SPI_FRF_SPI << SPI_FRF_OFFSET); @@ -165,6 +162,19 @@ void rockchip_spi_init(unsigned int bus, unsigned int speed_hz) write32(&regs->rxftlr, SPI_FIFO_DEPTH / 2 - 1); } +void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) +{ + assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); + struct rockchip_spi *regs = rockchip_spi_slaves[bus].regs; + unsigned int rsd; + + /* Rxd Sample Delay */ + rsd = DIV_ROUND_CLOSEST(delay_ns * (SPI_SRCCLK_HZ >> 8), 1*GHz >> 8); + assert(rsd >= 0 && rsd <= 3); + clrsetbits_le32(&regs->ctrlr0, SPI_RXDSD_MASK << SPI_RXDSD_OFFSET, + rsd << SPI_RXDSD_OFFSET); +} + int spi_claim_bus(struct spi_slave *slave) { spi_cs_activate(slave);

1 0

New patch to review for coreboot: arm64: Use 'payload' format for ATF instead of 'stage'
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16706 -gerrit commit 5461404295d6283e607dd9f4073d3fe511115d73 Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 12:18:38 2016 -0600 arm64: Use 'payload' format for ATF instead of 'stage' Switch the BL31 (ARM Trusted Firmware) format to payload so that it can have multiple independent segments. This also requires disabling the region check since SRAM is currently faulted by that check. This has been tested with Rockchip's pending change: https://chromium-review.googlesource.com/#/c/368592/3 with the patch mentioned on the bug at #13. BUG=chrome-os-partner:56314 BRANCH=none TEST=boot on gru and see that BL31 loads and runs. Im not sure if it is correct though: CBFS: Locating 'fallback/payload' CBFS: Found @ offset 1b440 size 15a75 Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x18104800 memsize 0x117fbe0 srcaddr 0x100038 filesize 0x15a3d Loading segment from ROM address 0x000000000010001c Entry Point 0x0000000018104800 Loading Segment: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000018104800 memsz: 0x000000000117fbe0 filesz: 0x0000000000015a3d using LZMA [ 0x18104800, 18137d90, 0x192843e0) <- 00100038 Clearing Segment: addr: 0x0000000018137d90 memsz: 0x000000000114c650 dest 0000000018104800, end 00000000192843e0, bouncebuffer ffffffffffffffff Loaded segments BS: BS_PAYLOAD_LOAD times (us): entry 0 run 125150 exit 1 Jumping to boot code at 0000000018104800(00000000f7eda000) CPU0: stack: 00000000ff8ec000 - 00000000ff8f0000, lowest used address 00000000ff8ef3d0, stack used: 3120 bytes CBFS: 'VBOOT' located CBFS at [402000:44cc00) CBFS: Locating 'fallback/bl31' CBFS: Found @ offset 10ec0 size 8d0c Loading segment from ROM address 0x0000000000100000 code (compression=1) New segment dstaddr 0x10000 memsize 0x40000 srcaddr 0x100054 filesize 0x8192 Loading segment from ROM address 0x000000000010001c code (compression=1) New segment dstaddr 0xff8d4000 memsize 0x1f50 srcaddr 0x1081e6 filesize 0xb26 Loading segment from ROM address 0x0000000000100038 Entry Point 0x0000000000010000 Loading Segment: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x0000000000010000 memsz: 0x0000000000040000 filesz: 0x0000000000008192 using LZMA [ 0x00010000, 00035708, 0x00050000) <- 00100054 Clearing Segment: addr: 0x0000000000035708 memsz: 0x000000000001a8f8 dest 0000000000010000, end 0000000000050000, bouncebuffer ffffffffffffffff Loading Segment: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 lb: [0x0000000000300000, 0x0000000000320558) Post relocation: addr: 0x00000000ff8d4000 memsz: 0x0000000000001f50 filesz: 0x0000000000000b26 using LZMA [ 0xff8d4000, ff8d5f50, 0xff8d5f50) <- 001081e6 dest 00000000ff8d4000, end 00000000ff8d5f50, bouncebuffer ffffffffffffffff Loaded segments INFO: plat_rockchip_pmusram_prepare pmu: code d2bfe625,d2bfe625,80 INFO: plat_rockchip_pmusram_prepare pmu: code 0xff8d4000,0x50000,3364 INFO: plat_rockchip_pmusram_prepare: data 0xff8d4d28,0xff8d4d24,4648 NOTICE: BL31: v1.2(debug): NOTICE: BL31: Built : Sun Sep 4 22:36:16 UTC 2016 INFO: GICv3 with legacy support detected. ARM GICV3 driver initialized in EL3 INFO: plat_rockchip_pmu_init(1189): pd status 3e INFO: BL31: Initializing runtime services INFO: BL31: Preparing for EL3 exit to normal world INFO: Entry point address = 0x18104800 INFO: SPSR = 0x8 Change-Id: Ie2484d122a603f1c7b7082a1de3f240aa6e6d540 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 8c1d75bff6e810a39776048ad9049ec0a9c5d94e Original-Change-Id: I2d60e5762f8377e43835558f76a3928156acb26c Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376849 Original-Commit-Ready: Simon Glass <sjg(a)google.com> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/arch/arm64/Makefile.inc | 2 +- src/arch/arm64/arm_tf.c | 5 ++--- src/include/program_loading.h | 10 ++++++++-- src/lib/prog_loaders.c | 2 +- src/lib/selfboot.c | 24 ++++++++++++++---------- 5 files changed, 26 insertions(+), 17 deletions(-) diff --git a/src/arch/arm64/Makefile.inc b/src/arch/arm64/Makefile.inc index ece35a6..6e3f080 100644 --- a/src/arch/arm64/Makefile.inc +++ b/src/arch/arm64/Makefile.inc @@ -178,7 +178,7 @@ $(BL31): $(obj)/build.h BL31_CBFS := $(CONFIG_CBFS_PREFIX)/bl31 $(BL31_CBFS)-file := $(BL31) -$(BL31_CBFS)-type := stage +$(BL31_CBFS)-type := payload $(BL31_CBFS)-compression := $(CBFS_COMPRESS_FLAG) cbfs-files-y += $(BL31_CBFS) diff --git a/src/arch/arm64/arm_tf.c b/src/arch/arm64/arm_tf.c index 1ec87c4..e976e34 100644 --- a/src/arch/arm64/arm_tf.c +++ b/src/arch/arm64/arm_tf.c @@ -50,11 +50,10 @@ void arm_tf_run_bl31(u64 payload_entry, u64 payload_arg0, u64 payload_spsr) if (prog_locate(&bl31)) die("BL31 not found"); - if (cbfs_prog_stage_load(&bl31)) + bl31_entry = selfload(&bl31, false); + if (!bl31_entry) die("BL31 load failed"); - bl31_entry = prog_entry(&bl31); - SET_PARAM_HEAD(&bl31_params, PARAM_BL31, VERSION_1, 0); if (IS_ENABLED(CONFIG_ARM64_USE_SECURE_OS)) { diff --git a/src/include/program_loading.h b/src/include/program_loading.h index e265b18..3958fda 100644 --- a/src/include/program_loading.h +++ b/src/include/program_loading.h @@ -189,7 +189,13 @@ void payload_run(void); /* Mirror the payload to be loaded. */ void mirror_payload(struct prog *payload); -/* Defined in src/lib/selfboot.c */ -void *selfload(struct prog *payload); +/* + * Set check_regions to true to check that the payload targets usable memory. + * With this flag set, if it does not, the load will fail and this function + * will return NULL. + * + * Defined in src/lib/selfboot.c + */ +void *selfload(struct prog *payload, bool check_regions); #endif /* PROGRAM_LOADING_H */ diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index ecbc679..c0dcd60 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -161,7 +161,7 @@ void payload_load(void) mirror_payload(payload); /* Pass cbtables to payload if architecture desires it. */ - prog_set_entry(payload, selfload(payload), + prog_set_entry(payload, selfload(payload, true), cbmem_find(CBMEM_ID_CBTABLE)); out: diff --git a/src/lib/selfboot.c b/src/lib/selfboot.c index 1ce7f94..162a034 100644 --- a/src/lib/selfboot.c +++ b/src/lib/selfboot.c @@ -88,7 +88,8 @@ static void get_bounce_buffer(unsigned long req_size) /* When the ramstage is relocatable there is no need for a bounce * buffer. All payloads should not overlap the ramstage. */ - if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)) { + if (IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) || + !arch_supports_bounce_buffer()) { bounce_buffer = ~0UL; bounce_size = 0; return; @@ -357,15 +358,16 @@ static int payload_targets_usable_ram(struct segment *head) return 1; } -static int load_self_segments( - struct segment *head, - struct prog *payload) +static int load_self_segments(struct segment *head, struct prog *payload, + bool check_regions) { struct segment *ptr; unsigned long bounce_high = lb_end; - if (!payload_targets_usable_ram(head)) - return 0; + if (check_regions) { + if (!payload_targets_usable_ram(head)) + return 0; + } for(ptr = head->next; ptr != head; ptr = ptr->next) { /* @@ -373,8 +375,10 @@ static int load_self_segments( * allocated so that there aren't conflicts with the actual * payload. */ - bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, - LB_MEM_UNUSABLE); + if (check_regions) { + bootmem_add_range(ptr->s_dstaddr, ptr->s_memsz, + LB_MEM_UNUSABLE); + } if (!overlaps_coreboot(ptr)) continue; @@ -486,7 +490,7 @@ static int load_self_segments( return 1; } -void *selfload(struct prog *payload) +void *selfload(struct prog *payload, bool check_regions) { uintptr_t entry = 0; struct segment head; @@ -502,7 +506,7 @@ void *selfload(struct prog *payload) goto out; /* Load the segments */ - if (!load_self_segments(&head, payload)) + if (!load_self_segments(&head, payload, check_regions)) goto out; printk(BIOS_SPEW, "Loaded segments\n");

1 0

New patch to review for coreboot: Add DIV_ROUND_CLOSEST
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16705 -gerrit commit 6c0ac553762dca0c1412d6a75785bd96a0b09661 Author: Simon Glass <sjg(a)chromium.org> Date: Wed Sep 7 16:01:55 2016 -0600 Add DIV_ROUND_CLOSEST Bring in this useful function from Linux 4.7. BUG=chrome-os-partner:56556 BRANCH=none TEST=build on gru Change-Id: I1577309e3e9ddea794e7e77354d50e582b70a43c Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 99f22182c2be0a6d02204b40f8f792f36d31c745 Original-Change-Id: I37617e35b4784d6cdc51e6910aa91f566caf971d Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382320 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/include/stdlib.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/include/stdlib.h b/src/include/stdlib.h index d6e7faf..6200f1c 100644 --- a/src/include/stdlib.h +++ b/src/include/stdlib.h @@ -16,6 +16,22 @@ static inline unsigned long div_round_up(unsigned int n, unsigned int d) { return (n + d - 1) / d; } + +/* + * Divide positive or negative dividend by positive divisor and round + * to closest integer. Result is undefined for negative divisors and + * for negative dividends if the divisor variable type is unsigned. + */ +#define DIV_ROUND_CLOSEST(x, divisor)( \ +{ \ + typeof(x) __x = x; \ + typeof(divisor) __d = divisor; \ + (((typeof(x))-1) > 0 || \ + ((typeof(divisor))-1) > 0 || (__x) > 0) ? \ + (((__x) + ((__d) / 2)) / (__d)) : \ + (((__x) - ((__d) / 2)) / (__d)); \ +} \ +) #endif

1 0

New patch to review for coreboot: rockchip: Correct and standardize clock divisor range assertions
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16704 -gerrit commit fc44cf4fe8eee3675a3d6ace09783d2a93a2365c Author: Julius Werner <jwerner(a)chromium.org> Date: Tue Sep 6 14:09:16 2016 -0700 rockchip: Correct and standardize clock divisor range assertions Some of the asserts for valid clock divisor ranges were off by one. This patch corrects them and writes them all in a consistent way. BRANCH=None BUG=None TEST=Booted Kevin. Change-Id: I81749408a40822100797f1734f3b88987d12d8d5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: e09cdfde26700496aaa1fc41489f63a355e8a89d Original-Change-Id: I429edb99e2d5ff2302d9750e6569b3d21f5686fa Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381574 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> --- src/soc/rockchip/rk3288/clock.c | 20 ++++++++++---------- src/soc/rockchip/rk3399/clock.c | 32 ++++++++++++++++---------------- 2 files changed, 26 insertions(+), 26 deletions(-) diff --git a/src/soc/rockchip/rk3288/clock.c b/src/soc/rockchip/rk3288/clock.c index bb5b846..74151e8 100644 --- a/src/soc/rockchip/rk3288/clock.c +++ b/src/soc/rockchip/rk3288/clock.c @@ -272,14 +272,14 @@ void rkclk_init(void) * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PD_BUS_ACLK_HZ - 1; - assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PD_BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PD_BUS_ACLK_HZ / PD_BUS_HCLK_HZ - 1; assert((hclk_div + 1) * PD_BUS_HCLK_HZ == - PD_BUS_ACLK_HZ && (hclk_div < 0x4) && (hclk_div != 0x2)); + PD_BUS_ACLK_HZ && (hclk_div <= 0x3) && (hclk_div != 0x2)); pclk_div = PD_BUS_ACLK_HZ / PD_BUS_PCLK_HZ - 1; assert((pclk_div + 1) * PD_BUS_PCLK_HZ == - PD_BUS_ACLK_HZ && pclk_div < 0x7); + PD_BUS_ACLK_HZ && pclk_div <= 0x7); write32(&cru_ptr->cru_clksel_con[1], RK_SETBITS(PD_BUS_SEL_GPLL) | RK_CLRSETBITS(PD_BUS_PCLK_DIV_MSK, @@ -295,15 +295,15 @@ void rkclk_init(void) * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; - assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = log2(PERI_ACLK_HZ / PERI_HCLK_HZ); assert((1 << hclk_div) * PERI_HCLK_HZ == - PERI_ACLK_HZ && (hclk_div < 0x4)); + PERI_ACLK_HZ && (hclk_div <= 0x2)); pclk_div = log2(PERI_ACLK_HZ / PERI_PCLK_HZ); assert((1 << pclk_div) * PERI_PCLK_HZ == - PERI_ACLK_HZ && (pclk_div < 0x4)); + PERI_ACLK_HZ && (pclk_div <= 0x3)); write32(&cru_ptr->cru_clksel_con[10], RK_SETBITS(PERI_SEL_GPLL) | RK_CLRSETBITS(PERI_PCLK_DIV_MSK, @@ -429,7 +429,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) { int src_clk_div = GPLL_HZ / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == GPLL_HZ)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == GPLL_HZ)); switch (bus) { /*select gpll as spi src clk, and set div*/ case 0: @@ -487,7 +487,7 @@ void rkclk_configure_crypto(unsigned int hz) { u32 div = PD_BUS_ACLK_HZ / hz; - assert((div - 1 < 4) && (div * hz == PD_BUS_ACLK_HZ)); + assert((div - 1 <= 3) && (div * hz == PD_BUS_ACLK_HZ)); assert(hz <= 150*MHz); /* Suggested max in TRM. */ write32(&cru_ptr->cru_clksel_con[26], RK_CLRSETBITS(0x3 << 6, (div - 1) << 6)); @@ -499,7 +499,7 @@ void rkclk_configure_tsadc(unsigned int hz) u32 src_clk = 32 * KHz; /* tsadc source clock is 32KHz*/ div = src_clk / hz; - assert((div - 1 < 64) && (div * hz == 32 * KHz)); + assert((div - 1 <= 63) && (div * hz == 32 * KHz)); write32(&cru_ptr->cru_clksel_con[2], RK_CLRSETBITS(0x3f << 0, (div - 1) << 0)); } @@ -604,7 +604,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) /* vop aclk source clk: cpll */ div = CPLL_HZ / aclk_hz; - assert((div - 1 < 64) && (div * aclk_hz == CPLL_HZ)); + assert((div - 1 <= 63) && (div * aclk_hz == CPLL_HZ)); switch (vop_id) { case 0: diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index c695ac0..e45ec0a 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -402,7 +402,7 @@ void rkclk_init(void) /* configure pmu pclk */ pclk_div = PPLL_HZ / PMU_PCLK_HZ - 1; - assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div < 0x1f); + assert((pclk_div + 1) * PMU_PCLK_HZ == PPLL_HZ && pclk_div <= 0x1f); write32(&pmucru_ptr->pmucru_clksel[0], RK_CLRSETBITS(PMU_PCLK_DIV_CON_MASK << PMU_PCLK_DIV_CON_SHIFT, pclk_div << PMU_PCLK_DIV_CON_SHIFT)); @@ -420,15 +420,15 @@ void rkclk_init(void) /* configure perihp aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1; - assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1; assert((hclk_div + 1) * PERIHP_HCLK_HZ == - PERIHP_ACLK_HZ && (hclk_div < 0x4)); + PERIHP_ACLK_HZ && (hclk_div <= 0x3)); pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1; assert((pclk_div + 1) * PERIHP_PCLK_HZ == - PERIHP_ACLK_HZ && (pclk_div < 0x7)); + PERIHP_ACLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[14], RK_CLRSETBITS(PCLK_PERIHP_DIV_CON_MASK << @@ -447,15 +447,15 @@ void rkclk_init(void) /* configure perilp0 aclk, hclk, pclk */ aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1; - assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1; assert((hclk_div + 1) * PERILP0_HCLK_HZ == - PERILP0_ACLK_HZ && (hclk_div < 0x4)); + PERILP0_ACLK_HZ && (hclk_div <= 0x3)); pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1; assert((pclk_div + 1) * PERILP0_PCLK_HZ == - PERILP0_ACLK_HZ && (pclk_div < 0x7)); + PERILP0_ACLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[23], RK_CLRSETBITS(PCLK_PERILP0_DIV_CON_MASK << @@ -475,11 +475,11 @@ void rkclk_init(void) /* perilp1 hclk select gpll as source */ hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1; assert((hclk_div + 1) * PERILP1_HCLK_HZ == - GPLL_HZ && (hclk_div < 0x1f)); + GPLL_HZ && (hclk_div <= 0x1f)); pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; assert((pclk_div + 1) * PERILP1_PCLK_HZ == - PERILP1_HCLK_HZ && (pclk_div < 0x7)); + PERILP1_HCLK_HZ && (pclk_div <= 0x7)); write32(&cru_ptr->clksel_con[25], RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << @@ -589,7 +589,7 @@ void rkclk_configure_spi(unsigned int bus, unsigned int hz) /* spi3 src clock from ppll, while spi0,1,2,4,5 src clock from gpll */ pll = (bus == 3) ? PPLL_HZ : GPLL_HZ; src_clk_div = pll / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); switch (bus) { case 0: @@ -645,7 +645,7 @@ static void rkclk_configure_i2c(unsigned int bus, unsigned int hz) /* i2c0,4,8 src clock from ppll, i2c1,2,3,5,6,7 src clock from gpll*/ pll = (bus == 0 || bus == 4 || bus == 8) ? PPLL_HZ : GPLL_HZ; src_clk_div = pll / hz; - assert((src_clk_div - 1 < 127) && (src_clk_div * hz == pll)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * hz == pll)); switch (bus) { case 0: @@ -748,7 +748,7 @@ void rkclk_configure_saradc(unsigned int hz) /* saradc src clk from 24MHz */ src_clk_div = 24 * MHz / hz; - assert((src_clk_div - 1 < 255) && (src_clk_div * hz == 24 * MHz)); + assert((src_clk_div - 1 <= 255) && (src_clk_div * hz == 24 * MHz)); write32(&cru_ptr->clksel_con[26], RK_CLRSETBITS(CLK_SARADC_DIV_CON_MASK << @@ -764,7 +764,7 @@ void rkclk_configure_vop_aclk(u32 vop_id, u32 aclk_hz) /* vop aclk source clk: cpll */ div = CPLL_HZ / aclk_hz; - assert((div - 1 < 32) && (div * aclk_hz == CPLL_HZ)); + assert((div - 1 <= 31) && (div * aclk_hz == CPLL_HZ)); write32(reg_addr, RK_CLRSETBITS( ACLK_VOP_PLL_SEL_MASK << ACLK_VOP_PLL_SEL_SHIFT | @@ -802,7 +802,7 @@ void rkclk_configure_tsadc(unsigned int hz) /* use 24M as src clock */ src_clk_div = OSC_HZ / hz; - assert((src_clk_div - 1 < 1024) && (src_clk_div * hz == OSC_HZ)); + assert((src_clk_div - 1 <= 1023) && (src_clk_div * hz == OSC_HZ)); write32(&cru_ptr->clksel_con[27], RK_CLRSETBITS( CLK_TSADC_DIV_CON_MASK << CLK_TSADC_DIV_CON_SHIFT | @@ -819,7 +819,7 @@ void rkclk_configure_emmc(void) /* Select aclk_emmc source from GPLL */ src_clk_div = GPLL_HZ / aclk_emmc; - assert((src_clk_div - 1 < 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); + assert((src_clk_div - 1 <= 31) && (src_clk_div * aclk_emmc == GPLL_HZ)); write32(&cru_ptr->clksel_con[21], RK_CLRSETBITS(ACLK_EMMC_PLL_SEL_MASK << @@ -831,7 +831,7 @@ void rkclk_configure_emmc(void) /* Select clk_emmc source from GPLL too */ src_clk_div = GPLL_HZ / clk_emmc; - assert((src_clk_div - 1 < 127) && (src_clk_div * clk_emmc == GPLL_HZ)); + assert((src_clk_div - 1 <= 127) && (src_clk_div * clk_emmc == GPLL_HZ)); write32(&cru_ptr->clksel_con[22], RK_CLRSETBITS(CLK_EMMC_PLL_MASK << CLK_EMMC_PLL_SHIFT |

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New patch to review for coreboot: rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16703 -gerrit commit 6a6885a069c63bff1cde5939809de8cf1efcf410 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Sep 2 23:48:10 2016 -0700 rockchip/rk3399: Fix rkclk_init() to actually use PERILP1_PCLK_HZ This patch fixes a typo in the clock initialization code that caused the PERILP1_PCLK_HZ constant to be ignored and the clock to always run at the same speed as its parent (PERILP1_HCLK_HZ). Since we've done all our previous tests and validation with this bug, we should probably increase the value of the constant (that had not actually been used) to the value that we had been incorrectly using instead (which also makes effective SPI read times faster). BRANCH=None BUG=chrome-os-partner:56556 TEST=Booted Kevin. Change-Id: Ibeb08f5fe5e984a74e3f57e60c62d4bfb644b6ca Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 06e605a5fcb9bdf13a3d301112380633b892fd4e Original-Change-Id: Icb5e079f53eb22b0dbf0ea4d1c2ff08688e3fa8e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381031 Original-Reviewed-by: Simon Glass <sjg(a)chromium.org> --- src/soc/rockchip/rk3399/clock.c | 6 +++--- src/soc/rockchip/rk3399/include/soc/clock.h | 2 +- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 291a70c..c695ac0 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -477,9 +477,9 @@ void rkclk_init(void) assert((hclk_div + 1) * PERILP1_HCLK_HZ == GPLL_HZ && (hclk_div < 0x1f)); - pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1; - assert((pclk_div + 1) * PERILP1_HCLK_HZ == - PERILP1_HCLK_HZ && (hclk_div < 0x7)); + pclk_div = PERILP1_HCLK_HZ / PERILP1_PCLK_HZ - 1; + assert((pclk_div + 1) * PERILP1_PCLK_HZ == + PERILP1_HCLK_HZ && (pclk_div < 0x7)); write32(&cru_ptr->clksel_con[25], RK_CLRSETBITS(PCLK_PERILP1_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 9d57e46..5926051 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -92,7 +92,7 @@ static struct rk3399_cru_reg * const cru_ptr = (void *)CRU_BASE; #define PERILP0_PCLK_HZ (49500*KHz) #define PERILP1_HCLK_HZ (99000*KHz) -#define PERILP1_PCLK_HZ (49500*KHz) +#define PERILP1_PCLK_HZ (99000*KHz) #define PWM_CLOCK_HZ PMU_PCLK_HZ

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coreboot-gerrit September 2016