coreboot-gerrit September 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16702 -gerrit commit c6910fcb5ed6715d6b5eb0227eebd639e0f3d7d6 Author: Julius Werner <jwerner(a)chromium.org> Date: Thu Aug 25 22:37:38 2016 -0700 rockchip/rk3399: Remove CONFIG_ARM64_A53_ERRATUM_843419 As far as I know, the Cortex-A53 cores in RK3399 are of a newer revision that is not affected by ARM erratum 843419. If it was, the workaround would also need to be enabled in libpayload and Chrome OS userspace, which it currently isn't. I assume this was just incorrectly copied over from another SoC and we can safely remove it. BRANCH=None BUG=chrome-os-partner:56700 TEST=Booted Kevin. Change-Id: I5b1534c954a6d985499b481738723cabbdc07253 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 4891cc866583532ee3dcb1a5ad5b81670eb0743d Original-Change-Id: Iadb57428f8727ce0e563204723644e2c79e3007c Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376363 Original-Commit-Queue: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/soc/rockchip/rk3399/Kconfig | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/Kconfig b/src/soc/rockchip/rk3399/Kconfig index 1eaa870..b4017c8 100644 --- a/src/soc/rockchip/rk3399/Kconfig +++ b/src/soc/rockchip/rk3399/Kconfig @@ -5,7 +5,6 @@ config SOC_ROCKCHIP_RK3399 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 - select ARM64_A53_ERRATUM_843419 select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select DRIVERS_UART_8250MEM_32

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New patch to review for coreboot: spi: Add a way to show SPI transfer speed for reads
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16701 -gerrit commit d56777a29a2c6f6096a74ff98943b71fe3bf1d42 Author: Simon Glass <sjg(a)chromium.org> Date: Sat Aug 27 15:03:02 2016 -0600 spi: Add a way to show SPI transfer speed for reads SPI read speed directly impacts boot time and we do quite a lot of reading. Add a way to easily find out the speed of SPI flash reads within coreboot. Write speed is less important since there are very few writes and they are small. BUG=chrome-os-partner:56556 BRANCH=none TEST=run on gru with SPI_SPEED_DEBUG set to 1. See the output messages: read SPI 627d4 7d73: 18455 us, 1740 KB/s, 13.920 Mbps Change-Id: Id3814bd2b7bd045cdfcc67eb1fabc861bf9ed3b2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 82cb93f6be47efce3b0a3843bab89d2381baef89 Original-Change-Id: Iec66f5b8e3ad62f14d836a538dc7801e4ca669e7 Original-Signed-off-by: Simon Glass <sjg(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376944 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/drivers/spi/cbfs_spi.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/drivers/spi/cbfs_spi.c b/src/drivers/spi/cbfs_spi.c index 1895b9d..e76a665 100644 --- a/src/drivers/spi/cbfs_spi.c +++ b/src/drivers/spi/cbfs_spi.c @@ -23,14 +23,44 @@ #include <spi_flash.h> #include <symbols.h> #include <cbmem.h> +#include <timer.h> static struct spi_flash *spi_flash_info; +/* + * Set this to 1 to debug SPI speed, 0 to disable it + * The format is: + * + * read SPI 62854 7db7: 10416 us, 3089 KB/s, 24.712 Mbps + * + * The important number is the last one. It should roughyly match your SPI + * clock. If it doesn't, your driver might need a little tuning. + */ +#define SPI_SPEED_DEBUG 0 + static ssize_t spi_readat(const struct region_device *rd, void *b, size_t offset, size_t size) { + struct stopwatch sw; + bool show = SPI_SPEED_DEBUG && size >= 4*KiB; + + if (show) + stopwatch_init(&sw); if (spi_flash_info->read(spi_flash_info, offset, size, b)) return -1; + if (show) { + long usecs; + + usecs = stopwatch_duration_usecs(&sw); + u64 speed; /* KiB/s */ + int bps; /* Bits per second */ + + speed = (u64)size * 1000 / usecs; + bps = speed * 8; + + printk(BIOS_DEBUG, "read SPI %#zx %#zx: %ld us, %lld KB/s, %d.%03d Mbps\n", + offset, size, usecs, speed, bps / 1000, bps % 1000); + } return size; }

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New patch to review for coreboot: google/gru: Init the PWM pinmux after setting up the PWM
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16700 -gerrit commit 455e4f4b068970b0512191d62a054fab5031b666 Author: Douglas Anderson <dianders(a)chromium.org> Date: Tue Sep 6 13:51:03 2016 -0700 google/gru: Init the PWM pinmux after setting up the PWM If we setup the PWM _after_ the pinmux then there's a period of time when we're driving the PWM incorrectly. Let's setup the regulator and _then_ configure the pinmux. This fixes no known bugs, but it is more correct and probably makes the signals look better at bootup. BRANCH=None BUG=None TEST=scope Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1 Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1 Original-Signed-off-by: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381592 Original-Reviewed-by: Simon Glass <sjg(a)google.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/pwm_regulator.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/src/mainboard/google/gru/pwm_regulator.c b/src/mainboard/google/gru/pwm_regulator.c index d0cdf43..d6d2eec 100644 --- a/src/mainboard/google/gru/pwm_regulator.c +++ b/src/mainboard/google/gru/pwm_regulator.c @@ -44,21 +44,6 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) int duty_ns, voltage_max, voltage_min; int voltage = millivolt * 10; /* for higer calculation accuracy */ - switch (pwm) { - case PWM_REGULATOR_GPU: - write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); - break; - case PWM_REGULATOR_BIG: - write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); - break; - case PWM_REGULATOR_LIT: - write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); - break; - case PWM_REGULATOR_CENTERLOG: - write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); - break; - } - voltage_min = PWM_DESIGN_VOLTAGE_MIN; voltage_max = PWM_DESIGN_VOLTAGE_MAX; if (!(IS_ENABLED(CONFIG_BOARD_GOOGLE_KEVIN) && board_id() < 6) && @@ -80,4 +65,19 @@ void pwm_regulator_configure(enum pwm_regulator pwm, int millivolt) / (voltage_max - voltage_min); pwm_init(pwm, PWM_PERIOD, duty_ns); + + switch (pwm) { + case PWM_REGULATOR_GPU: + write32(&rk3399_grf->iomux_pwm_0, IOMUX_PWM_0); + break; + case PWM_REGULATOR_BIG: + write32(&rk3399_grf->iomux_pwm_1, IOMUX_PWM_1); + break; + case PWM_REGULATOR_LIT: + write32(&rk3399_pmugrf->iomux_pwm_2, IOMUX_PWM_2); + break; + case PWM_REGULATOR_CENTERLOG: + write32(&rk3399_pmugrf->iomux_pwm_3a, IOMUX_PWM_3_A); + break; + } }

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New patch to review for coreboot: google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16699 -gerrit commit bd532adebecdd5b65a007d0e5a45d35630614891 Author: Jeffy Chen <jeffy.chen(a)rock-chips.com> Date: Fri Sep 2 18:16:33 2016 +0800 google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configuration Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan(a)chromium.org> Original-Tested-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Alexandru Stan <amstan(a)chromium.org> Original-Reviewed-by: Jonathan Dixon <joth(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron_rialto/sdram_configs.c | 2 +- .../sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc | 77 ++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/veyron_rialto/sdram_configs.c b/src/mainboard/google/veyron_rialto/sdram_configs.c index 42fa582..0e260c3 100644 --- a/src/mainboard/google/veyron_rialto/sdram_configs.c +++ b/src/mainboard/google/veyron_rialto/sdram_configs.c @@ -22,7 +22,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-K4E8E304EE-1GB.inc" /* ram_code = 0000 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0001 */ +#include "sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc"/* ram_code = 0001 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-unused.inc" /* ram_code = 0100 */ diff --git a/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc new file mode 100644 index 0000000..df3bb2a --- /dev/null +++ b/src/mainboard/google/veyron_rialto/sdram_inf/sdram-lpddr3-K4E6E304EB-2GB-1CH.inc @@ -0,0 +1,77 @@ +{ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x0, + .col = 0x0, + .bk = 0x0, + .bw = 0x0, + .dbw = 0x0, + .row_3_4 = 0x0, + .cs0_row = 0x0, + .cs1_row = 0x0 + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 1, + .stride = 22, + .odt = 0 +},

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New patch to review for coreboot: rockchip/rk3399: Move big CPU cluster initialization into ramstage
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16698 -gerrit commit 46b1a459de4cdd3089d3cd0b6feffc2e107fb7c8 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 29 15:07:58 2016 -0700 rockchip/rk3399: Move big CPU cluster initialization into ramstage This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders(a)chromium.org> --- src/mainboard/google/gru/bootblock.c | 2 +- src/soc/rockchip/rk3399/clock.c | 39 ++++++++++++++++------------- src/soc/rockchip/rk3399/include/soc/clock.h | 7 +++++- src/soc/rockchip/rk3399/soc.c | 4 +++ 4 files changed, 33 insertions(+), 19 deletions(-) diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c index 2214a5c..6598dfe 100644 --- a/src/mainboard/google/gru/bootblock.c +++ b/src/mainboard/google/gru/bootblock.c @@ -69,7 +69,7 @@ static void speed_up_boot_cpu(void) udelay(200); - rkclk_configure_cpu(APLL_1512_MHZ, false); + rkclk_configure_cpu(APLL_1512_MHZ, CPU_CLUSTER_LITTLE); } void bootblock_mainboard_init(void) diff --git a/src/soc/rockchip/rk3399/clock.c b/src/soc/rockchip/rk3399/clock.c index 3eeda38..291a70c 100644 --- a/src/soc/rockchip/rk3399/clock.c +++ b/src/soc/rockchip/rk3399/clock.c @@ -494,26 +494,31 @@ void rkclk_init(void) HCLK_PERILP1_PLL_SEL_SHIFT)); } -void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big) +void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster) { - u32 aclkm_div; - u32 pclk_dbg_div; - u32 atclk_div; - u32 apll_l_hz; - int con_base = is_big ? 2 : 0; - int parent = is_big ? CLK_CORE_PLL_SEL_ABPLL : CLK_CORE_PLL_SEL_ALPLL; - u32 *pll_con = is_big ? &cru_ptr->apll_b_con[0] : - &cru_ptr->apll_l_con[0]; - - apll_l_hz = apll_cfgs[apll_freq]->freq; - - rkclk_set_pll(pll_con, apll_cfgs[apll_freq]); - - aclkm_div = div_round_up(apll_l_hz, ACLKM_CORE_HZ) - 1; + u32 aclkm_div, atclk_div, pclk_dbg_div, apll_hz; + int con_base, parent; + u32 *pll_con; + + switch (cluster) { + case CPU_CLUSTER_LITTLE: + con_base = 0; + parent = CLK_CORE_PLL_SEL_ALPLL; + pll_con = &cru_ptr->apll_l_con[0]; + break; + case CPU_CLUSTER_BIG: + con_base = 2; + parent = CLK_CORE_PLL_SEL_ABPLL; + pll_con = &cru_ptr->apll_b_con[0]; + break; + } - pclk_dbg_div = div_round_up(apll_l_hz, PCLK_DBG_HZ) - 1; + apll_hz = apll_cfgs[freq]->freq; + rkclk_set_pll(pll_con, apll_cfgs[freq]); - atclk_div = div_round_up(apll_l_hz, ATCLK_CORE_HZ) - 1; + aclkm_div = div_round_up(apll_hz, ACLKM_CORE_HZ) - 1; + pclk_dbg_div = div_round_up(apll_hz, PCLK_DBG_HZ) - 1; + atclk_div = div_round_up(apll_hz, ATCLK_CORE_HZ) - 1; write32(&cru_ptr->clksel_con[con_base], RK_CLRSETBITS(ACLKM_CORE_DIV_CON_MASK << diff --git a/src/soc/rockchip/rk3399/include/soc/clock.h b/src/soc/rockchip/rk3399/include/soc/clock.h index 53f16ac..9d57e46 100644 --- a/src/soc/rockchip/rk3399/include/soc/clock.h +++ b/src/soc/rockchip/rk3399/include/soc/clock.h @@ -101,9 +101,14 @@ enum apll_frequencies { APLL_600_MHZ, }; +enum cpu_cluster { + CPU_CLUSTER_LITTLE, + CPU_CLUSTER_BIG, +}; + void rkclk_init(void); int rkclk_configure_vop_dclk(u32 vop_id, u32 dclk_hz); -void rkclk_configure_cpu(enum apll_frequencies apll_freq, bool is_big); +void rkclk_configure_cpu(enum apll_frequencies freq, enum cpu_cluster cluster); void rkclk_configure_ddr(unsigned int hz); void rkclk_configure_emmc(void); void rkclk_configure_i2s(unsigned int hz); diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 1adf3f6..12c757f 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -18,6 +18,7 @@ #include <cpu/cpu.h> #include <device/device.h> #include <soc/addressmap.h> +#include <soc/clock.h> #include <soc/display.h> #include <stddef.h> #include <stdlib.h> @@ -42,6 +43,9 @@ static void soc_init(device_t dev) _framebuffer_size); else printk(BIOS_INFO, "Display initialization disabled.\n"); + + /* We don't need big CPUs, but bring them up as a courtesy to Linux. */ + rkclk_configure_cpu(APLL_600_MHZ, CPU_CLUSTER_BIG); } static struct device_operations soc_ops = {

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New patch to review for coreboot: i2c/ww_ring: LED changes for Gale EVT3
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16697 -gerrit commit 828dcdbec13bb44363e716e847e2571a2f58f708 Author: Suresh Rajashekara <sureshraj(a)google.com> Date: Mon Aug 15 16:18:11 2016 -0700 i2c/ww_ring: LED changes for Gale EVT3 Gale EVT3 has only one LED controller (earlier we had 2). Removing the support for the second controller and also the corresponding microcode. The color values used are the same as onHub (Arkham to be specific). BUG=b:30890905 TEST=Move the device to different states manually by appropriate actions (like dev mode, rec mode etc) and observe the differnet colors. BRANCH=None Change-Id: I853035610ea7ea7c8d29c30d2de13c9e2e786b2b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 593905d2d69daa7482318aa5f5c5cd7cf984043e Original-Change-Id: If8f22abd605faac6f6215ef600041740ce15ea0c Original-Signed-off-by: Suresh Rajashekara <sureshraj(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/370821 Original-Commit-Ready: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Tested-by: Suresh Rajashekara <sureshraj(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/drivers/i2c/ww_ring/ww_ring_programs.c | 232 ++++++----------------------- src/drivers/i2c/ww_ring/ww_ring_programs.h | 2 +- 2 files changed, 49 insertions(+), 185 deletions(-) diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.c b/src/drivers/i2c/ww_ring/ww_ring_programs.c index a35998c..5b0c8a8 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.c +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.c @@ -46,36 +46,36 @@ * Solid LED display, the arguments of the set_pwm commands set intensity and * color of the display: -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 1 + set_pwm 0 end .segment program2 mux_map_addr row_green - set_pwm 1 + set_pwm 0 end .segment program3 mux_map_addr row_blue - set_pwm 1 + set_pwm 0 end */ /* RGB set to 000000, resulting in all LEDs off. */ static const uint8_t solid_000000_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 0, 0xC0, 0x00, 0x9F, 0x81, 0x40, 0, 0xC0, 0x00, 0x9F, 0x82, 0x40, 0, 0xC0, 0x00 }; /* Rgb set to 128, resulting in a brightish white color. */ static const uint8_t solid_808080_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9F, 0x80, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9F, 0x80, 0x40, 128, 0xC0, 0x00, 0x9F, 0x81, 0x40, 128, 0xC0, 0x00, 0x9F, 0x82, 0x40, 128, 0xC0, 0x00 }; @@ -100,20 +100,10 @@ static const TiLp55231Program solid_000000_program = { * The three internal engines seem to be competing for resources and get out * of sync in seconds if left running asynchronously. * - * When there are two separate controllers, with three engine each, they all - * run away from each other in no time, resulting in some completely chaotic - * LED behavior. - * * When solid patterns are deployed with instanteneous color intensity * changes, all three LEDs can be controlled by one engine in sequential * accesses. But the controllers still neeed to be synchronized. * - * The first controller is loaded and started first, but it sits waiting for - * the trigger from the second controller to actually start the cycle. Once - * both controllers start running, the first controller is the master, sending - * sych triggers to the second one each time the LED is supposed to be turned - * on or off. - * * The maximum timer duration of lp55231 is .48 seconds. To achieve longer * blinking intervals the loops delays are deployed. Only the first controller * intervals need to be changed, as the second one is in lockstep with the @@ -126,29 +116,26 @@ static const TiLp55231Program solid_000000_program = { */ /* * blink_solid1.src -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b +row_red: dw 0000000000000001b +row_green: dw 0000000000000010b +row_blue: dw 0000000000000100b .segment program1 ld ra, 2 # LED on duration - ld rb, 10 # LED off duration + ld rb, 2 # LED off duration mux_map_addr row_red - trigger w{e} loop: - trigger s{e} - ld rc, 98 ; red intensity + ld rc, 180 ; red intensity set_pwm rc mux_map_addr row_green - ld rc, 0 ; green intensity + ld rc, 80 ; green intensity set_pwm rc mux_map_addr row_blue - ld rc, 234 ; blue intensity + ld rc, 0 ; blue intensity set_pwm rc wait1: wait 0.1 branch ra, wait1 - trigger s{e} set_pwm 0 mux_map_addr row_green set_pwm 0 @@ -158,203 +145,82 @@ wait2: wait 0.1 branch rb, wait2 branch 0, loop - -.segment program2 - end - -.segment program3 - end*/ -/* - * blink_solid2.src - -row_red: dw 0000000001001001b -row_green: dw 0000000010010010b -row_blue: dw 0000000100100100b - -.segment program1 - ld ra, 98 - ld rb, 0 - ld rc, 234 - trigger s{e} - mux_map_addr row_red -loop: - trigger w{e} - set_pwm ra ; red intensity - mux_map_addr row_green - set_pwm rb ; green intensity - mux_map_addr row_blue - set_pwm rc ; blue intensity -wait1: - wait 0.1 - branch 1, wait1 - trigger w{e} - set_pwm 0 - mux_map_addr row_green - set_pwm 0 - mux_map_addr row_red - set_pwm 0 -wait2: - wait 0.1 - branch 1, wait2 - branch 0, loop - .segment program2 end - .segment program3 end */ static const uint8_t blink_wipeout1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 80, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, -}; - -static const uint8_t blink_wipeout2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 80, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 180, 0x84, 0x62, + 0x9f, 0x81, 0x98, 80, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_wipeout1_program = { blink_wipeout1_text, sizeof(blink_wipeout1_text), 0, - { 3, 27, 28, } -}; -static const TiLp55231Program blink_wipeout2_program = { - blink_wipeout2_text, - sizeof(blink_wipeout2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; static const uint8_t blink_recovery1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 0x02, - 0x94, 0x02, 0x9f, 0x80, 0xf0, 0x00, 0xe0, 0x40, - 0x98, 255, 0x84, 0x62, 0x9f, 0x81, 0x98, 24, - 0x84, 0x62, 0x9f, 0x82, 0x98, 0, 0x84, 0x62, - 0x4c, 0x00, 0x86, 0x34, 0xe0, 0x40, 0x40, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, 0x40, 0x00, - 0x4c, 0x00, 0x86, 0x55, 0xa0, 0x04, 0xc0, 0x00, - 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x90, 0x02, + 0x94, 0x02, 0x9f, 0x80, 0x98, 255, 0x84, 0x62, + 0x9f, 0x81, 0x98, 50, 0x84, 0x62, 0x9f, 0x82, + 0x98, 0, 0x84, 0x62, 0x4c, 0x00, 0x86, 0x2c, + 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, 0x9f, 0x80, + 0x40, 0x00, 0x4c, 0x00, 0x86, 0x49, 0xa0, 0x03, + 0xc0, 0x00, 0xc0, 0x00, 0x00, }; static const TiLp55231Program blink_recovery1_program = { blink_recovery1_text, sizeof(blink_recovery1_text), 0, - { 3, 27, 28, } -}; -static const uint8_t blink_recovery2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x90, 255, - 0x94, 24, 0x98, 0, 0xe0, 0x40, 0x9f, 0x80, - 0xf0, 0x00, 0x84, 0x60, 0x9f, 0x81, 0x84, 0x61, - 0x9f, 0x82, 0x84, 0x62, 0x4c, 0x00, 0xa0, 0x8b, - 0xf0, 0x00, 0x40, 0x00, 0x9f, 0x81, 0x40, 0x00, - 0x9f, 0x80, 0x40, 0x00, 0x4c, 0x00, 0xa0, 0x93, - 0xa0, 0x05, 0xc0, 0x00, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program blink_recovery2_program = { - blink_recovery2_text, - sizeof(blink_recovery2_text), - 0, - { 3, 26, 26, } + { 3, 24, 25, } }; /* * fade_in1.src * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b + row_red: dw 0000000000000001b + row_green: dw 0000000000000010b + row_blue: dw 0000000000000100b .segment program1 mux_map_addr row_red - set_pwm 0h - trigger w{e} + set_pwm 1h trigger s{2|3} end - .segment program2 mux_map_addr row_green set_pwm 0h - trigger w{1} - ramp 2, 87 + ramp 2, 50 end - .segment program3 mux_map_addr row_blue set_pwm 0h loop3: trigger w{1} - ramp 2, 155 - end -*/ -/* - * fade_in2.src - * - row_red: dw 0000000001001001b - row_green: dw 0000000010010010b - row_blue: dw 0000000100100100b - - .segment program1 - mux_map_addr row_red - set_pwm 0h - trigger s{e} - trigger s{2|3} - end - - .segment program2 - mux_map_addr row_green - set_pwm 0h - - trigger w{1} - ramp 2, 87 - end - -.segment program3 - mux_map_addr row_blue - set_pwm 0h - loop3: trigger w{1} - ramp 2, 155 + ramp 2, 255 end */ static const uint8_t fade_in1_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xf0, 0x00, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, + 0x00, 0x01, 0x00, 0x02, 0x00, 0x04, 0x9f, 0x80, + 0x40, 0x01, 0xe0, 0x0c, 0xc0, 0x00, 0x9f, 0x81, + 0x40, 0x00, 0xe0, 0x80, 0x46, 0x32, 0xc0, 0x00, + 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, 0x20, 0xff, + 0xc0, 0x00, 0x00, }; static const TiLp55231Program fade_in1_program = { fade_in1_text, sizeof(fade_in1_text), 0, - { 3, 8, 13, } -}; - -static const uint8_t fade_in2_text[] = { - 0x00, 0x49, 0x00, 0x92, 0x01, 0x24, 0x9f, 0x80, - 0x40, 0x00, 0xe0, 0x40, 0xe0, 0x0c, 0xc0, 0x00, - 0x9f, 0x81, 0x40, 0x00, 0xe0, 0x80, 0x42, 0x57, - 0xc0, 0x00, 0x9f, 0x82, 0x40, 0x00, 0xe0, 0x80, - 0x34, 0x9b, 0xc0, 0x00, 0x00, -}; -static const TiLp55231Program fade_in2_program = { - fade_in2_text, - sizeof(fade_in2_text), - 0, - { 3, 8, 13, } + { 3, 7, 12, } }; const WwRingStateProg wwr_state_programs[] = { @@ -362,12 +228,10 @@ const WwRingStateProg wwr_state_programs[] = { * for test purposes the blank screen program is set to blinking, will * be changed soon. */ - {WWR_ALL_OFF, {&solid_000000_program, &solid_000000_program} }, - {WWR_RECOVERY_PUSHED, {&solid_808080_program, &solid_808080_program} }, - {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program, - &blink_wipeout2_program} }, - {WWR_RECOVERY_REQUEST, {&blink_recovery1_program, - &blink_recovery2_program} }, - {WWR_NORMAL_BOOT, {&fade_in1_program, &fade_in2_program} }, + {WWR_ALL_OFF, {&solid_000000_program} }, + {WWR_RECOVERY_PUSHED, {&solid_808080_program} }, + {WWR_WIPEOUT_REQUEST, {&blink_wipeout1_program} }, + {WWR_RECOVERY_REQUEST, {&blink_recovery1_program} }, + {WWR_NORMAL_BOOT, {&fade_in1_program} }, {}, /* Empty record to mark the end of the table. */ }; diff --git a/src/drivers/i2c/ww_ring/ww_ring_programs.h b/src/drivers/i2c/ww_ring/ww_ring_programs.h index 9f4b928..5fb8ebf 100644 --- a/src/drivers/i2c/ww_ring/ww_ring_programs.h +++ b/src/drivers/i2c/ww_ring/ww_ring_programs.h @@ -36,7 +36,7 @@ #define LP55231_NUM_OF_ENGINES 3 /* Number of lp55321 controllers on the ring */ -#define WW_RING_NUM_LED_CONTROLLERS 2 +#define WW_RING_NUM_LED_CONTROLLERS 1 /* * Structure to describe an lp55231 program: pointer to the text of the

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New patch to review for coreboot: mainboard/intel/amenia: Enable software sync in coreboot
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16696 -gerrit commit 791a110f76c836b2111609f4f9861fb0da9f851a Author: li feng <li1.feng(a)intel.com> Date: Thu Apr 21 17:33:32 2016 -0700 mainboard/intel/amenia: Enable software sync in coreboot Software sync in depthcharge should be enabled as well. BUG=none BRANCH=none TEST=On Amenia TR1.2, observed software sync after boot up, and checked with console command sysinfo. Change-Id: I7bd9a4934bec8e4fafbcdeb4c69313d83522063b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 2ef1dd668e6b7c7f9739b13d525ea2d2bb7ae7a1 Original-Change-Id: Ia807ca8881747ec80adfaa48ef832835784159bf Original-Signed-off-by: li feng <li1.feng(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/355221 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/intel/amenia/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index 5d50d7b..455d136 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS config CHROMEOS select LID_SWITCH +config CHROMEOS + select EC_SOFTWARE_SYNC + config MAINBOARD_DIR string default intel/amenia

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New patch to review for coreboot: util/scripts: add gerrit-rebase script
by Patrick Georgi 22 Sep '16

22 Sep '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16695 -gerrit commit af1bb41fb0e2f018d9a27b8990377dd86e6503a4 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Thu Sep 22 12:46:45 2016 +0200 util/scripts: add gerrit-rebase script gerrit-rebase is a gerrit-context aware rebase script. Given a source and a target branch (that need to have a common ancestor), it prepares a rebase todo list that applies all commits from source that aren't already found on target. It matches commits using Reviewed-on lines in the commit message that are added by gerrit when submitting commits using the "cherry-pick" strategy. This has been shown to be the best preserved meta data to work from in existing data (Change-Id was mangled in all kinds of ways). Change-Id: I9618c1b66ebc1fb7ed006efbc1665fb08386e1a5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- util/scripts/gerrit-rebase | 61 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/util/scripts/gerrit-rebase b/util/scripts/gerrit-rebase new file mode 100755 index 0000000..002c499 --- /dev/null +++ b/util/scripts/gerrit-rebase @@ -0,0 +1,61 @@ +#!/bin/bash +# $0 from-branch to-branch +# applies all commits that from-branch has over to-branch, +# based on a common ancestor and gerrit meta-data +from=$1 +to=$2 + +# match string: this is the git commit line that is used to +# identify commits that were already copied over. +# +# Must not contain spaces except for leading and trailing. +# +# The first pick was Change-Id, but it was lost too often, +# so go for Reviewed-on instead. It's also unique because it +# contains the gerrit instance's host name and the change's number +# on that system. +match_string='^ [-A-Za-z]*[Rr]eviewed-on: ' + +# fetch common ancestor +common_base=$(git merge-base ${from} ${to} 2>/dev/null) + +if [ -z "${common_base}" ]; then + echo \"${from}\" or \"${to}\" is not a valid branch name. + exit 1 +fi + +# collect matches that are present on the target side +to_matches="$(git log ${common_base}..${to} | \ + grep "${match_string}" | \ + cut -d: -f2-)" + +# start rebase process, but fail immediately by enforcing an invalid todo +GIT_SEQUENCE_EDITOR="echo foo >" \ + git rebase -i --onto ${to} ${from} ${to} 2>/dev/null + +# write new rebase todo +# the appended "commit" line triggers handling of the last log entry +commit="" +(git log --reverse ${common_base}..${from} | \ + grep -E "(^commit [0-9a-f]{40}\$|${match_string})"; \ + echo "commit") | \ +while read key value; do + if [ "${key}" = "commit" ]; then + if [ -n "${commit}" ]; then + git log -n 1 --pretty="pick %h %s" ${commit} + fi + commit="${value}" + else + # if value was already found on the "to" side, skip this + # commit + if [[ ${to_matches} == *"${value}"* ]]; then + commit="" + fi + fi +done | GIT_SEQUENCE_EDITOR="cat >" git rebase --edit-todo + +# allow user to edit todo +git rebase --edit-todo + +# start processing todo to mimick git rebase -i behavior +git rebase --continue

1 0

New patch to review for coreboot: soc/intel/apollolake: Initialize processor count in GNVS
by Duncan Laurie 22 Sep '16

22 Sep '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16693 -gerrit commit ece9a07e4fe0917c9a5f56eaf86f4abbd03c61bc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed Sep 21 18:30:44 2016 -0700 soc/intel/apollolake: Initialize processor count in GNVS Initialize the PCNT variable in GNVS so it is available to ACPI code that expects to know the number of CPUs. Change-Id: I7a6e003ac94218061bf98e8883ed2c62d856af8d Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/apollolake/acpi.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 5718d7e..ba22aee 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -168,6 +168,9 @@ static void acpi_create_gnvs(struct global_nvs_t *gnvs) /* Set unknown wake source */ gnvs->pm1i = ~0ULL; + /* CPU core count */ + gnvs->pcnt = dev_count_cpu(); + if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return;

1 0

Patch set updated for coreboot: libpayload: mvmap2315: Introduce timer driver
by hakim giydan 22 Sep '16

22 Sep '16

hakim giydan (hgiydan(a)marvell.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16692 -gerrit commit 2f29d61103a1c6fcbbc3e2308135a0d182be8aaf Author: Hakim Giydan <hgiydan(a)marvell.com> Date: Wed Sep 21 15:50:39 2016 -0700 libpayload: mvmap2315: Introduce timer driver Testing: booted successfully. Change-Id: I4a50c9fb7aec929ea29a3cf2eec3e424e3629c92 Signed-off-by: Hakim Giydan <hgiydan(a)marvell.com> --- payloads/libpayload/drivers/Makefile.inc | 1 + payloads/libpayload/drivers/timer/Kconfig | 13 ++++++++ payloads/libpayload/drivers/timer/mvmap2315.c | 44 +++++++++++++++++++++++++++ 3 files changed, 58 insertions(+) diff --git a/payloads/libpayload/drivers/Makefile.inc b/payloads/libpayload/drivers/Makefile.inc index 75f08f2..899c5d2 100644 --- a/payloads/libpayload/drivers/Makefile.inc +++ b/payloads/libpayload/drivers/Makefile.inc @@ -57,6 +57,7 @@ libc-$(CONFIG_LP_TIMER_BG4CD) += timer/bg4cd.c libc-$(CONFIG_LP_TIMER_IMG_PISTACHIO) += timer/img_pistachio.c libc-$(CONFIG_LP_TIMER_CYGNUS) += timer/cygnus.c libc-$(CONFIG_LP_TIMER_ARMADA38X) += timer/armada38x.c +libc-$(CONFIG_LP_TIMER_MVMAP2315) += timer/mvmap2315.c # Video console drivers libc-$(CONFIG_LP_VIDEO_CONSOLE) += video/video.c diff --git a/payloads/libpayload/drivers/timer/Kconfig b/payloads/libpayload/drivers/timer/Kconfig index 0b981b0..b3ab6ec 100644 --- a/payloads/libpayload/drivers/timer/Kconfig +++ b/payloads/libpayload/drivers/timer/Kconfig @@ -61,6 +61,9 @@ config TIMER_IMG_PISTACHIO config TIMER_MTK bool "Timer for MediaTek MT8173" +config TIMER_MVMAP2315 + bool "Timer for Marvell MVMAP2315" + endchoice config TIMER_MCT_HZ @@ -108,6 +111,16 @@ config ARMADA38X_TIMER_REG default 0xF1020314 depends on TIMER_ARMADA38X +config MVMAP2315_TIMER_FREQ + int "Hardware timer frequency" + depends on TIMER_MVMAP2315 + default 1000000 + +config MVMAP2315_TIMER_REG + hex "Timer register address" + depends on TIMER_MVMAP2315 + default 0xE1020004 + config IPROC_PERIPH_GLB_TIM_REG_BASE hex "Cygnus timer base address" depends on TIMER_CYGNUS diff --git a/payloads/libpayload/drivers/timer/mvmap2315.c b/payloads/libpayload/drivers/timer/mvmap2315.c new file mode 100644 index 0000000..5b1f813 --- /dev/null +++ b/payloads/libpayload/drivers/timer/mvmap2315.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marvell Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS + * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) + * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. + */ + +#include <assert.h> +#include <libpayload.h> + +static u32 *reg = (void *)CONFIG_LP_MVMAP2315_TIMER_REG; + +uint64_t timer_hz(void) +{ + return CONFIG_LP_MVMAP2315_TIMER_FREQ; +} + +uint64_t timer_raw_value(void) +{ + /* invert count to change from down to up count */ + return ~readl(reg); +}

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coreboot-gerrit September 2016