coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: Gale board: Move TPM setup function to verstage.c
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 1bfcc843ff18653fc42fff06c22869406ff52677 Author: Kan Yan <kyan(a)google.com> Date: Mon May 9 19:03:17 2016 -0700 Gale board: Move TPM setup function to verstage.c TPM should be only be reset once in verstage. BUG=chrome-os-partner:51096 TEST=Depthcharge no longer shows TPM error. BRANCH=None Original-Signed-off-by: Kan Yan <kyan(a)google.com> Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3 Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9 Original-Reviewed-on: https://chromium-review.googlesource.com/343537 Original-Commit-Ready: Kan Yan <kyan(a)google.com> Original-Tested-by: Kan Yan <kyan(a)google.com> Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14845 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> See https://review.coreboot.org/14845 for details. -gerrit

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Patch set updated for coreboot: rockchip: rk3399: initialize display for eDP
by Martin Roth 02 Jun '16

02 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14857 -gerrit commit 35e3a0a6d228ffb29f147e39666fa02e86028409 Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Wed May 4 16:21:36 2016 +0800 rockchip: rk3399: initialize display for eDP This patch add functions to init display. To setup display, initialize the eDP and read EDID, basing on which we then set the clock for VOP, and finally enable VOP and backlight. For a mainboard, it should set the vop_id, vop_mode and framebuffer_bits_per_pixel in devicetree.cb. For VOP_MODE_AUTO_DETECT, it will try eDP first and then HDMI(which is not supported yet). EDIT: Updated Makefile to only build in new files if MAINBOARD_DO_NATIVE_VGA_INIT is enabled. All of these platforms should have it enabled, so this shouldn't make any difference except now, before the platform code is in place. BRANCH=none BUG=chrome-os-partner:51537 TEST=test with the other patch Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Commit-Id: c1020cc806775629f4d5dc57bd805a9a12169386 Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342336 Original-Commit-Ready: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/soc/rockchip/rk3399/Makefile.inc | 3 + src/soc/rockchip/rk3399/chip.h | 32 ++++++ src/soc/rockchip/rk3399/display.c | 122 +++++++++++++++++++++++ src/soc/rockchip/rk3399/include/soc/addressmap.h | 5 + src/soc/rockchip/rk3399/include/soc/display.h | 25 +++++ src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 + src/soc/rockchip/rk3399/soc.c | 8 ++ 7 files changed, 196 insertions(+) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 68f346c..8abafe3 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -55,6 +55,8 @@ ramstage-y += sdram.c ramstage-y += ../common/spi.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c ramstage-y += clock.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c ramstage-y += emmc.c ramstage-y += ../common/gpio.c ramstage-y += gpio.c @@ -62,6 +64,7 @@ ramstage-y += ../common/i2c.c ramstage-y += saradc.c ramstage-y += soc.c ramstage-y += timer.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c BL31_MAKEARGS += PLAT=rk3399 ################################################################################ diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h new file mode 100644 index 0000000..46baa8c --- /dev/null +++ b/src/soc/rockchip/rk3399/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_CHIP_H__ +#define __SOC_ROCKCHIP_RK3399_CHIP_H__ + +#include <soc/gpio.h> +#include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */ + +struct soc_rockchip_rk3399_config { + u32 vop_id; + gpio_t lcd_bl_pwm_gpio; + gpio_t lcd_bl_en_gpio; + u32 bl_power_on_udelay; + u32 bl_pwm_to_enable_udelay; + u32 framebuffer_bits_per_pixel; + u32 vop_mode; +}; + +#endif /* __SOC_ROCKCHIP_RK3399_CHIP_H__ */ diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c new file mode 100644 index 0000000..25389b0 --- /dev/null +++ b/src/soc/rockchip/rk3399/display.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <arch/mmu.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <delay.h> +#include <edid.h> +#include <gpio.h> +#include <stdlib.h> +#include <stddef.h> +#include <string.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/display.h> +#include <soc/edp.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/mmu_operations.h> +#include <soc/soc.h> +#include <soc/vop.h> + +#include "chip.h" + +void rk_display_init(device_t dev, uintptr_t lcdbase, + unsigned long fb_size) +{ + struct edid edid; + uint32_t val; + struct soc_rockchip_rk3399_config *conf = dev->chip_info; + uintptr_t lower = ALIGN_DOWN(lcdbase, MiB); + uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + enum vop_modes detected_mode = VOP_MODE_UNKNOWN; + + printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase)); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ + dcache_clean_invalidate_by_mva((void *)lower, upper - lower); + mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM); + + switch (conf->vop_mode) { + case VOP_MODE_NONE: + return; + case VOP_MODE_AUTO_DETECT: + /* try EDP first, then HDMI */ + case VOP_MODE_EDP: + printk(BIOS_DEBUG, "Attempting to setup EDP display.\n"); + rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + + /* select edp signal from vop0(big) or vop1(little) */ + val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) : + RK_CLRBITS(1 << 5); + write32(&rk3399_grf->soc_con20, val); + + /* select edp clk from SoC interal 24M crystal, otherwise, + * it will source from edp's 24M clock(that depends on + * edp vendor, could be unstable) + */ + write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); + + rk_edp_init(); + + if (rk_edp_get_edid(&edid) == 0) { + detected_mode = VOP_MODE_EDP; + break; + } + printk(BIOS_WARNING, "Cannot get EDID from EDP.\n"); + if (conf->vop_mode == VOP_MODE_EDP) + return; + /* fall thru */ + case VOP_MODE_HDMI: + printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n"); + return; + default: + printk(BIOS_WARNING, "Cannot read any edid info, aborting.\n"); + return; + } + + if (rkclk_configure_vop_dclk(conf->vop_id, + edid.mode.pixel_clock * KHz)) { + printk(BIOS_WARNING, "config vop err\n"); + return; + } + + edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; + edid.bytes_per_line = + edid.mode.ha * conf->framebuffer_bits_per_pixel / 8; + edid.x_resolution = edid.mode.ha; + edid.y_resolution = edid.mode.va; + rkvop_mode_set(conf->vop_id, &edid, detected_mode); + + rkvop_enable(conf->vop_id, lcdbase, &edid); + + switch (detected_mode) { + case VOP_MODE_HDMI: + /* should not be here before HDMI supported */ + return; + case VOP_MODE_EDP: + default: + if (rk_edp_enable()) { + printk(BIOS_WARNING, "edp enable err\n"); + return; + } + mainboard_power_on_backlight(); + break; + } + + set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); +} diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index 28cbd7a..6d494fd 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -59,6 +59,11 @@ #define TSADC_BASE 0xff260000 #define SARADC_BASE 0xff100000 #define RK_PWM_BASE 0xff420000 +#define EDP_BASE 0xff970000 + +#define VOP_BIG_BASE 0xff900000 /* corresponsed to vop_id 0 */ +#define VOP_LIT_BASE 0xff8f0000 /* corresponsed to vop_id 1 */ + #define DDRC0_BASE_ADDR 0xffa80000 #define SERVER_MSCH0_BASE_ADDR 0xffa84000 diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h new file mode 100644 index 0000000..7ccde56 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_DISPLAY_H__ +#define __SOC_ROCKCHIP_RK3399_DISPLAY_H__ + +#define REF_CLK_24M (0x1 << 0) + +void rk_display_init(device_t dev, uintptr_t lcdbase, + unsigned long fb_size); +void mainboard_power_on_backlight(void); + +#endif diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index edb246d..ac16394 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,6 +22,7 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) + FRAMEBUFFER(0x10200000, 8M) SRAM_START(0xFF8C0000) BOOTBLOCK(0xFF8C2004, 32K - 4) diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 5b6ddb2b..826abc2 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -13,10 +13,12 @@ * GNU General Public License for more details. */ +#include <bootmode.h> #include <console/console.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/addressmap.h> +#include <soc/display.h> #include <stddef.h> #include <stdlib.h> #include <string.h> @@ -34,6 +36,12 @@ static void soc_init(device_t dev) * arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h */ mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB)); + + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) + rk_display_init(dev, (uintptr_t)_framebuffer, + _framebuffer_size); + else + printk(BIOS_INFO, "Skipping display init.\n"); } static struct device_operations soc_ops = {

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Patch merged into coreboot/master: mb/lenovo/T4xx: enable PEG device
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 830fdc77cb6ab5333a82833db2fc47725c1b508f Author: Patrick Rudolph <siro(a)das-labor.org> Date: Thu Apr 21 07:15:14 2016 +0200 mb/lenovo/T4xx: enable PEG device Enable the PEG device in devicetree to expose the device if any. This is already default behaviour for T5xx series. Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> See https://review.coreboot.org/14448 for details. -gerrit

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Patch merged into coreboot/master: drivers/lenovo: Add hybrid graphics driver
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 5919ba42ed0ce5b1b13717514698444232c6036c Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/12896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> See https://review.coreboot.org/12896 for details. -gerrit

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Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Martin Roth 01 Jun '16

01 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit fbae0950a2f790f5bc1385a78a0c9911a0228fdd Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 ++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 125 ++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t400/cmos.default | 1 + src/mainboard/lenovo/t400/cmos.layout | 3 + src/mainboard/lenovo/t420/cmos.default | 1 + src/mainboard/lenovo/t420/cmos.layout | 5 +- src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t420s/cmos.default | 1 + src/mainboard/lenovo/t420s/cmos.layout | 5 +- src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t520/cmos.default | 1 + src/mainboard/lenovo/t520/cmos.layout | 5 +- src/mainboard/lenovo/t530/Kconfig | 1 + src/mainboard/lenovo/t530/cmos.default | 1 + src/mainboard/lenovo/t530/cmos.layout | 6 +- src/southbridge/intel/i82801ix/Kconfig | 1 + 18 files changed, 169 insertions(+), 4 deletions(-) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..9b46646 --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,125 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <option.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * Nvidia is calling this functionality "muxed Optimus". + * Some devices, like T430s, only support "muxless Optimus" where the + * Intel GPU is always connected to the panel. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +#define HYBRID_GRAPHICS_INTEGRATED 0 +#define HYBRID_GRAPHICS_DISCRETE 1 + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to integrated GPU.\n"); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; + + printk(BIOS_DEBUG, "Hybrid graphics: Disabled PEG10.\n"); +} + +/* Called before VGA enable bits are set and only if dGPU + * is present. Enable/disable VGA devices here. */ +static void hybrid_graphics_enable_peg(struct device *dev) +{ + u8 hybrid_graphics_mode; + + hybrid_graphics_mode = HYBRID_GRAPHICS_INTEGRATED; + get_option(&hybrid_graphics_mode, "hybrid_graphics_mode"); + + if (hybrid_graphics_mode == HYBRID_GRAPHICS_DISCRETE) { + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Hybrid graphics: Switching panel to discrete GPU.\n"); + dev->enabled = 1; + + /* Disable IGD */ + dev = dev_find_slot(0, PCI_DEVFN(2, 0)); + if (dev && dev->ops->disable) + dev->ops->disable(dev); + dev->enabled = 0; + + printk(BIOS_DEBUG, "Hybrid graphics: Disabled IGD.\n"); + } else + hybrid_graphics_disable_peg(dev); +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index d74a813..a444bf8 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t400/cmos.default b/src/mainboard/lenovo/t400/cmos.default index ac9f96d..98ce970 100644 --- a/src/mainboard/lenovo/t400/cmos.default +++ b/src/mainboard/lenovo/t400/cmos.default @@ -13,3 +13,4 @@ sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable sata_mode=AHCI +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 0c12458..b0131f6 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -78,6 +78,7 @@ entries # coreboot config options: northbridge 941 3 e 11 gfx_uma_size +944 2 e 12 hybrid_graphics_mode # coreboot config options: EC 952 8 h 0 volume @@ -132,6 +133,8 @@ enumerations 11 3 128M 11 5 96M 11 6 160M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420/cmos.default b/src/mainboard/lenovo/t420/cmos.default index 1b8e212..3a82c97 100644 --- a/src/mainboard/lenovo/t420/cmos.default +++ b/src/mainboard/lenovo/t420/cmos.default @@ -14,3 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index bf0f195..58a4abe 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume @@ -135,6 +136,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index 935e659..feacb51 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t420s/cmos.default b/src/mainboard/lenovo/t420s/cmos.default index 1b8e212..3a82c97 100644 --- a/src/mainboard/lenovo/t420s/cmos.default +++ b/src/mainboard/lenovo/t420s/cmos.default @@ -14,3 +14,4 @@ fn_ctrl_swap=Disable sticky_fn=Disable trackpoint=Enable hyper_threading=Enable +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 4362840..3521849 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume @@ -135,6 +136,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index c70581a..ee5dd81 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_IVYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/cmos.default b/src/mainboard/lenovo/t520/cmos.default index 00e8863..ad7dcf5 100644 --- a/src/mainboard/lenovo/t520/cmos.default +++ b/src/mainboard/lenovo/t520/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 2cf3629..044c310 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values @@ -134,6 +135,8 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index c1d0625..085711b 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/cmos.default b/src/mainboard/lenovo/t530/cmos.default index 00e8863..ad7dcf5 100644 --- a/src/mainboard/lenovo/t530/cmos.default +++ b/src/mainboard/lenovo/t530/cmos.default @@ -15,3 +15,4 @@ sticky_fn=Disable trackpoint=Enable hyper_threading=Enable backlight=Both +hybrid_graphics_mode=Integrated Only \ No newline at end of file diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index e21c197..0e28bdd 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -77,7 +77,8 @@ entries # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused +435 2 e 12 hybrid_graphics_mode +#437 3 r 0 unused 440 8 h 0 volume @@ -135,6 +136,9 @@ enumerations 11 4 160M 11 5 192M 11 6 224M +12 0 Integrated Only +12 1 Discrete Only + # ----------------------------------------------------------------- checksums diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 2822774..b3e5069 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS + select SOUTHBRIDGE_INTEL_COMMON_GPIO if SOUTHBRIDGE_INTEL_I82801IX

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Patch merged into coreboot/master: Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 14d1a93e444b91311eeed2a25953bf6c0779cdcb Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Dec 28 13:21:43 2015 +0100 Revert "mainboard/lenovo/t400: Add initial hybrid graphics support" This reverts commit 59597ead1f26d4c18997bda81b2ec33e52973b80. Will be replaced by lenovo common hybrid driver. Change-Id: I994114734fa931926c34ed04305cddfbeb429b62 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/12895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> See https://review.coreboot.org/12895 for details. -gerrit

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Patch set updated for coreboot: apollolake/amenia: Adding NHLA and NHLL
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit f5f1b9602db9ccec432e7ad28b0d82b1b66198e1 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 apollolake/amenia: Adding NHLA and NHLL Add address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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Patch merged into coreboot/master: nau8825: Add driver for I2C codec
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 7522dc3c072b9ef09363afd6a699cdb0564f9865 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue May 10 20:20:16 2016 -0700 nau8825: Add driver for I2C codec The Nuvoton NAU8825 audio codec is an I2C device that has a number of tunable parameters that can be provided to the kernel device driver for basic configuration and optimal operation. The configuration options are exposed to devicetree as registers and then presented as Device Properties via ACPI to the operation system. This sample configuration in devicetree: device pci 19.2 on chip drivers/i2c/nau8825 register "irq" = "IRQ_LEVEL_LOW(GPP_F10_IRQ)" register "jkdet_enable" = "1" register "sar_threshold_num" = "2" register "sar_threshold[0]" = "0x0c" register "sar_threshold[1]" = "0x1c" device i2c 1a on end end end Will generate the following code in the SSDT, trimmed for this commit message as there are more properties that can be configured: Scope (\_SB.PCI0.I2C4) { Name (_HID, "10508825") Name (_UID, Zero) Name (_DDN, "Nuvoton NAU8825 Codec") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x1A, ControllerInitiated, 0x61A80, AddressingMode7Bit, "\_SB.PCI0.I2C4", 0, ResourceConsumer) Interrupt (ResourceConsumer, Level, ActiveLow) { 0x3A } }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bff4aa301"), Package () { Package () { "nuvoton,jkdet-enable", 1 }, Package () { "nuvoton,sar-threshold-num", 2 }, Package () { "nuvoton,sar-threshold", Package () { 0x0c, 0x1c } } } }) } Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I480d72daf5ac3dded9b1cbb5fbc737b9dfde3834 Reviewed-on: https://review.coreboot.org/15015 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15015 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phase
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 16f3d3d35f4fb7b70fd45399ad52ba3129719133 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Apr 29 14:40:40 2016 -0700 intel/fsp2.0: Add END_OF_FIRMWARE in enum fsp_notify_phase Change-Id: Ib39e828c6e3145957ecc2dacc1f72de793165514 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/15020 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15020 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake: remove _RMV and _DSW methods from xhci.asl
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 85e3c77226e1b95c6878d238b60ec144293de91b Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 25 11:12:43 2016 -0700 soc/apollolake: remove _RMV and _DSW methods from xhci.asl Change-Id: Ic314656f34fda10e58e55bdefeb0a1f0c6ab5ae2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/14966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/14966 for details. -gerrit

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coreboot-gerrit June 2016