coreboot-gerrit June 2016

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Patch set updated for coreboot: generic: Add a Maxim 98357A codec driver
by Duncan Laurie 02 Jun '16

02 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15017 -gerrit commit cc24c90c546daa81d8e60607df19d17180ec9483 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 11:27:47 2016 -0700 generic: Add a Maxim 98357A codec driver The Maxim Integrated 98357A codec is an I2S slave device that has no control channel for configuration and instead provides a GPIO that is used for channel selection and power down. This means it does not fit into a bus hierarchy easily and is instead represented as a generic device and found with a static bus scan using the devicetree. This driver provides configuration options for passing the "sdmode" GPIO descriptor as well as a second option for "sdmode delay" which can configure the timing of the sdmode toggling in relation to the I2S channel output. In addition an GPIO can be provided to indicate to the driver whether this device is present or not. This can be used for board designs that may have different codec possibilities that are selected by HW strap. Sample usage for this device driver: device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)" register "sdmode_delay" = "100" device generic 0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.HDAS) { Device (MAXM) { Name (_HID, "MX98357A") Name (_UID, Zero) Name (_DDN, "Maxim Integrated 98357A Amplifier") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 } Package () { "maxim,sdmode-delay", 100 } Package () { "sdmode-delay", 100 } } }) } } Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/generic/max98357a/Kconfig | 2 + src/drivers/generic/max98357a/Makefile.inc | 1 + src/drivers/generic/max98357a/chip.h | 13 ++++ src/drivers/generic/max98357a/max98357a.c | 109 +++++++++++++++++++++++++++++ 4 files changed, 125 insertions(+) diff --git a/src/drivers/generic/max98357a/Kconfig b/src/drivers/generic/max98357a/Kconfig new file mode 100644 index 0000000..a7104f1 --- /dev/null +++ b/src/drivers/generic/max98357a/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_MAX98357A + bool diff --git a/src/drivers/generic/max98357a/Makefile.inc b/src/drivers/generic/max98357a/Makefile.inc new file mode 100644 index 0000000..529e24a --- /dev/null +++ b/src/drivers/generic/max98357a/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_MAX98357A) += max98357a.c diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h new file mode 100644 index 0000000..0abd616 --- /dev/null +++ b/src/drivers/generic/max98357a/chip.h @@ -0,0 +1,13 @@ +#include <arch/acpi_device.h> + +struct drivers_generic_max98357a_config { + /* SDMODE GPIO */ + struct acpi_gpio sdmode_gpio; + + /* SDMODE Delay */ + unsigned sdmode_delay; + + /* GPIO used to indicate if this device is present */ + unsigned device_present_gpio; + unsigned device_present_gpio_invert; +}; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c new file mode 100644 index 0000000..331df4c --- /dev/null +++ b/src/drivers/generic/max98357a/max98357a.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define MAX98357A_ACPI_NAME "MAXM" +#define MAX98357A_ACPI_HID "MX98357A" + +static void max98357a_fill_ssdt(struct device *dev) +{ + struct drivers_generic_max98357a_config *config = dev->chip_info; + const char *path = acpi_device_path(dev); + + if (!dev->enabled || !path) + return; + + /* Device */ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_gpio(&config->sdmode_gpio); + acpigen_write_resourcetemplate_footer(); + + /* _DSD for devicetree properties */ + acpi_dp_write_header(); + /* This points to the first pin in the first gpio entry in _CRS */ + acpi_dp_write_gpio("maxim,sdmode-gpio", path, 0, 0, 0); + /* This is the correctly formatted Device Property name */ + acpi_dp_write_integer("maxim,sdmode-delay", config->sdmode_delay); + /* This is used by the chromium kernel but is not upstream */ + acpi_dp_write_integer("sdmode-delay", config->sdmode_delay); + acpi_dp_write_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s\n", path, dev->chip_ops->name); +} + +static const char *max98357a_acpi_name(struct device *dev) +{ + return MAX98357A_ACPI_NAME; +} +#endif + +static struct device_operations max98357a_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &max98357a_acpi_name, + .acpi_fill_ssdt_generator = &max98357a_fill_ssdt, +#endif +}; + +static void max98357a_enable(struct device *dev) +{ + struct drivers_generic_max98357a_config *config = dev->chip_info; + + /* Check if device is present by reading GPIO */ + if (config->device_present_gpio) { + int present = gpio_get(config->device_present_gpio); + present ^= config->device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + + dev->ops = &max98357a_ops; +} + +struct chip_operations drivers_generic_max98357a_ops = { + CHIP_NAME("Maxim Integrated 98357A Amplifier") + .enable_dev = &max98357a_enable +};

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Patch set updated for coreboot: i2c: Add a generic i2c driver
by Duncan Laurie 02 Jun '16

02 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15016 -gerrit commit 6acd74329393b77224c08ca0a668ec9ce99676a0 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 09:50:59 2016 -0700 i2c: Add a generic i2c driver This adds a generic I2C driver that can be described in the devicetree and used to generate ACPI objects in the SSDT based on the information provided in the config registers. The I2C bus can be configured and the device can provide an interrupt and wake capability to the OS. A configuration option allows for a GPIO to be provided that will be checked to determine if the device is preset on the board before including it in the generated SSDT. The driver is generic enough to be used for basic I2C devices that do not have special configuration needs such as touchpads, touchscreens, sensors, some audio codec/amplifiers, etc. Sample usage for a touchpad device: device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = "ELAN Touchpad" register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.I2C1) { Device (D015) { Name (_HID, "ELAN0000") Name (_UID, 0) Name (_S0W, 4) Name (_PRW, Package () { 5, 3 }) Method (_STA) { Return (0x0f) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit, "\\_S.PCI0.I2C1", 0, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 } }) } } Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/generic/Kconfig | 2 + src/drivers/i2c/generic/Makefile.inc | 1 + src/drivers/i2c/generic/chip.h | 16 +++++ src/drivers/i2c/generic/generic.c | 124 +++++++++++++++++++++++++++++++++++ 4 files changed, 143 insertions(+) diff --git a/src/drivers/i2c/generic/Kconfig b/src/drivers/i2c/generic/Kconfig new file mode 100644 index 0000000..a4c0104 --- /dev/null +++ b/src/drivers/i2c/generic/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_GENERIC + bool diff --git a/src/drivers/i2c/generic/Makefile.inc b/src/drivers/i2c/generic/Makefile.inc new file mode 100644 index 0000000..86cbc7b --- /dev/null +++ b/src/drivers/i2c/generic/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_GENERIC) += generic.c diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h new file mode 100644 index 0000000..84657d5 --- /dev/null +++ b/src/drivers/i2c/generic/chip.h @@ -0,0 +1,16 @@ +#include <arch/acpi_device.h> +#include <device/i2c.h> + +struct drivers_i2c_generic_config { + const char *hid; /* ACPI _HID (required) */ + const char *name; /* ACPI Device Name */ + const char *desc; /* Device Description */ + unsigned uid; /* ACPI _UID */ + enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ + unsigned wake; /* Wake GPE */ + struct acpi_irq irq; /* Interrupt */ + + /* GPIO used to indicate if this device is present */ + unsigned device_present_gpio; + unsigned device_present_gpio_invert; +}; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c new file mode 100644 index 0000000..1c10b0e --- /dev/null +++ b/src/drivers/i2c/generic/generic.c @@ -0,0 +1,124 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void i2c_generic_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_generic_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + + if (!dev->enabled || !scope) + return; + + if (!config->hid) { + printk(BIOS_ERR, "%s: ERROR: HID required\n", dev_path(dev)); + return; + } + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", config->hid); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpi_device_write_interrupt(&config->irq); + acpigen_write_resourcetemplate_footer(); + + /* Wake capabilities */ + if (config->wake) { + acpigen_write_name_integer("_S0W", 4); + acpigen_write_PRW(config->wake, 3); + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +/* Use name specified in config or build one from I2C address */ +static const char *i2c_generic_acpi_name(struct device *dev) +{ + struct drivers_i2c_generic_config *config = dev->chip_info; + static char name[5]; + + if (config->name) + return name; + + snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); + name[4] = '\0'; + return name; +} +#endif + +static struct device_operations i2c_generic_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_generic_acpi_name, + .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, +#endif +}; + +static void i2c_generic_enable(struct device *dev) +{ + struct drivers_i2c_generic_config *config = dev->chip_info; + + /* Check if device is present by reading GPIO */ + if (config->device_present_gpio) { + int present = gpio_get(config->device_present_gpio); + present ^= config->device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + + dev->ops = &i2c_generic_ops; +} + +struct chip_operations drivers_i2c_generic_ops = { + CHIP_NAME("I2C Device") + .enable_dev = &i2c_generic_enable +};

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Patch set updated for coreboot: drivers/intel/wifi: Add support for generating SSDT table
by Duncan Laurie 02 Jun '16

02 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15019 -gerrit commit 1c527f51bb147cd7de54ebb3390a1083ef53465e Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 14:05:07 2016 -0700 drivers/intel/wifi: Add support for generating SSDT table Intel WiFi devices that support wake-on-wifi need to declare a Power Resource for this wake pin. Typically this has been done with a static declaration in the DSDT for each mainboard. By adding it to the existing intel/wifi driver it can be done based on a configuration register in the devicetree. Additionally the WiFi regulatory domain can be set in the SSDT directly instead of needing to use NVS to pass the value to the DSDT. Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that are found on Chromebooks, and clean up a long line and some comment formatting. This was tested by booting on an HP Chromebook 13 device and comparing that the output in the SSDT matches what used to be in the DSDT. The WRDD value is read from VPD, if present, not from devicetree.cb. Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but the wifi device is not described in devicetree.cb is tested to ensure it still generates the AML but does not include the _PRW wake pin. Example: devicetree.cb: device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end VPD: "region"="us" SSDT.dsl: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) Name (_DDN, "Intel WiFi") Name (_ADR, 0x00000000) Name (_PRW, Package () { 16, 3 }) Name (WRDD, Package () { Zero, Package () { 0x00000007, 0x00004150 } }) } } Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/intel/wifi/chip.h | 3 ++ src/drivers/intel/wifi/wifi.c | 106 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 96 insertions(+), 13 deletions(-) diff --git a/src/drivers/intel/wifi/chip.h b/src/drivers/intel/wifi/chip.h new file mode 100644 index 0000000..117d39c --- /dev/null +++ b/src/drivers/intel/wifi/chip.h @@ -0,0 +1,3 @@ +struct drivers_intel_wifi_config { + unsigned wake; /* Wake pin for ACPI _PRW */ +}; diff --git a/src/drivers/intel/wifi/wifi.c b/src/drivers/intel/wifi/wifi.c index 5ae5498..5661bf4 100644 --- a/src/drivers/intel/wifi/wifi.c +++ b/src/drivers/intel/wifi/wifi.c @@ -14,12 +14,16 @@ * GNU General Public License for more details. */ +#include <arch/acpi_device.h> +#include <arch/acpigen.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> #include <device/pci_ids.h> #include <smbios.h> #include <string.h> +#include <wrdd.h> +#include "chip.h" static int smbios_write_wifi(struct device *dev, int *handle, unsigned long *current) @@ -32,15 +36,17 @@ static int smbios_write_wifi(struct device *dev, int *handle, char eos[2]; } __attribute__((packed)); - struct smbios_type_intel_wifi *t = (struct smbios_type_intel_wifi *)*current; + struct smbios_type_intel_wifi *t = + (struct smbios_type_intel_wifi *)*current; int len = sizeof(struct smbios_type_intel_wifi); memset(t, 0, sizeof(struct smbios_type_intel_wifi)); t->type = 0x85; t->length = len - 2; t->handle = *handle; - /* Intel wifi driver expects this string to be in the table 0x85 - with PCI IDs enumerated below. + /* + * Intel wifi driver expects this string to be in the table 0x85 + * with PCI IDs enumerated below. */ t->str = smbios_add_string(t->eos, "KHOIHGIUCCHHII"); @@ -50,30 +56,104 @@ static int smbios_write_wifi(struct device *dev, int *handle, return len; } +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) +static void intel_wifi_fill_ssdt(struct device *dev) +{ + struct drivers_intel_wifi_config *config = dev->chip_info; + const char *path = acpi_device_path(dev->bus->dev); + u32 address; + + if (!path) + return; + + /* Device */ + acpigen_write_scope(path); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + + /* Address */ + address = PCI_SLOT(dev->path.pci.devfn) & 0xffff; + address <<= 16; + address |= PCI_FUNC(dev->path.pci.devfn) & 0xffff; + acpigen_write_name_dword("_ADR", address); + + /* Wake capabilities */ + if (config && config->wake) + acpigen_write_PRW(config->wake, 3); + + /* Fill regulatory domain structure */ + if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) { + /* + * Name ("WRDD", Package () { + * WRDD_REVISION, // Revision + * Package () { + * WRDD_DOMAIN_TYPE_WIFI, // Domain Type, 7:WiFi + * wifi_regulatory_domain() // Country Identifier + * } + * }) + */ + acpigen_write_name("WRDD"); + acpigen_write_package(2); + acpigen_write_integer(WRDD_REVISION); + acpigen_write_package(2); + acpigen_write_dword(WRDD_DOMAIN_TYPE_WIFI); + acpigen_write_dword(wifi_regulatory_domain()); + acpigen_pop_len(); + acpigen_pop_len(); + } + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s.%s: %s %s\n", path, acpi_device_name(dev), + dev->chip_ops->name, dev_path(dev)); +} + +static const char *intel_wifi_acpi_name(struct device *dev) +{ + return "WIFI"; +} +#endif + static struct pci_operations pci_ops = { .set_subsystem = pci_dev_set_subsystem, }; struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = pci_dev_init, - .scan_bus = 0, - .enable = 0, - .get_smbios_data = smbios_write_wifi, - .ops_pci = &pci_ops, + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .get_smbios_data = smbios_write_wifi, + .ops_pci = &pci_ops, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &intel_wifi_acpi_name, + .acpi_fill_ssdt_generator = &intel_wifi_fill_ssdt, +#endif }; - static const unsigned short pci_device_ids[] = { 0x0084, 0x0085, 0x0089, 0x008b, 0x008e, 0x0090, 0x0886, 0x0888, 0x0891, 0x0893, 0x0895, 0x088f, 0x4236, 0x4237, 0x4238, 0x4239, 0x423b, 0x423d, - 0 }; + 0x08b1, 0x08b2, /* Wilkins Peak 2 */ + 0x095a, 0x095b, /* Stone Peak 2 */ + 0 +}; static const struct pci_driver pch_intel_wifi __pci_driver = { .ops = &device_ops, .vendor = PCI_VENDOR_ID_INTEL, .devices = pci_device_ids, }; + +static void intel_wifi_enable(struct device *dev) +{ + dev->ops = &device_ops; +} + +struct chip_operations drivers_intel_wifi_ops = { + CHIP_NAME("Intel WiFi") + .enable_dev = &intel_wifi_enable +};

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Patch set updated for coreboot: wrdd: Export WRDD info in the header
by Duncan Laurie 02 Jun '16

02 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15018 -gerrit commit 6540fc4a4e6b2fc76245aa2aa33e6f060b8b001b Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 13:52:43 2016 -0700 wrdd: Export WRDD info in the header Export the WRDD spec revision and WiFi domain type in the header file so it can be used to generate ACPI tables by wifi drivers. Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/include/wrdd.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/include/wrdd.h b/src/include/wrdd.h index 97fa5dc..0ede015 100644 --- a/src/include/wrdd.h +++ b/src/include/wrdd.h @@ -18,6 +18,12 @@ #include <stdint.h> +/* WRDD Spec Revision */ +#define WRDD_REVISION 0x0 + +/* Domain type */ +#define WRDD_DOMAIN_TYPE_WIFI 0x7 + /* Default regulatory domain ID */ #define WRDD_DEFAULT_REGULATORY_DOMAIN 0x4150 /* INDONESIA regulatory domain ID */

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 02 Jun '16

02 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit 4bc66cafb96b137f4c055fd65a7ba2c9ae52a705 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 ++++ src/mainboard/intel/amenia/dsdt.asl | 14 ++++-- src/mainboard/intel/amenia/mainboard.c | 87 +++++++++++++++++++++++++++++++++- 3 files changed, 102 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..07d01e6 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -24,18 +24,22 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..5a01c11 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,13 @@ */ #include <device/device.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +94,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -100,7 +104,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */ PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */ - /* Configure eMMC pins for proper pull UP/DN */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */ PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */ @@ -129,7 +132,44 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +static const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; +static struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) @@ -138,6 +178,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), &headset_tdm_cfg, + AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, + AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

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New patch to review for coreboot: intel/apollolake: Clear TSEG reg early in bootblock
by Furquan Shaikh 02 Jun '16

02 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15049 -gerrit commit 16485c5a60e1592aaf8a383ed064ecd83220db69 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 15:09:21 2016 -0700 intel/apollolake: Clear TSEG reg early in bootblock TSEG register comes out of reset with a non-zero default value. This causes issues when cbmem_top returns non-zero value based on TSEG read before DRAM is initialized. Thus, clear TSEG reg early in bootblock to avoid unwanted side-effects. Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index b8d6f22..68ce7ab 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -60,6 +60,12 @@ void asmlinkage bootblock_c_entry(uint32_t tsc_hi, uint32_t tsc_lo) /* Set PCI Express BAR */ pci_io_write_config32(dev, PCIEXBAR, CONFIG_MMCONF_BASE_ADDRESS | 1); + /* + * Clear TSEG register - TSEG register comes out of reset with a + * non-zero default value. Clear this register to ensure that there are + * no surprises in CBMEM handling. + */ + pci_write_config32(dev, TSEG, 0); dev = P2SB_DEV; /* BAR and MMIO enable for IOSF, so that GPIOs can be configured */

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Patch set updated for coreboot: cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP
by Furquan Shaikh 02 Jun '16

02 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15045 -gerrit commit bb9bc4398420b06fca1102e547dbef7a80b6193c Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:53:18 2016 -0700 cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP Modern platforms like Apollolake do not use XIP for early stages. In such cases, cbfs_prog_stage_load should check for NO_XIP_EARLY_STAGES instead of relying on ARCH_X86 to decide if a stage is XIP. Change-Id: I1729ce82b5f678ce8c37256090fcf353cc22b1ec Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/Kconfig | 3 +-- src/lib/cbfs.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..6e6e944 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -204,8 +204,7 @@ config NO_XIP_EARLY_STAGES default n if ARCH_X86 default y help - Identify if --xip parameter needs to be passed into cbfstool for early - stages. + Identify if early stages are eXecute-In-Place(XIP). config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 764a6f7..aa652c2 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -192,7 +192,7 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ - if (ENV_VERSTAGE && IS_ENABLED(CONFIG_ARCH_X86) && + if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED)) { void *mapping = rdev_mmap(fh, foffset, fsize); rdev_munmap(fh, mapping);

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Patch set updated for coreboot: google/reef: Select UART_FOR_CONSOLE for reef
by Furquan Shaikh 02 Jun '16

02 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15044 -gerrit commit 973346ca925d3e46736a45e0e790404af066e14f Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 31 23:38:26 2016 -0700 google/reef: Select UART_FOR_CONSOLE for reef Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5d8ded6..c1ccc5c 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,4 +50,8 @@ config MAX_CPUS int default 8 +config UART_FOR_CONSOLE + int + default 2 + endif # BOARD_GOOGLE_REEF

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Patch set updated for coreboot: intel/apollolake: Add car.c to verstage
by Furquan Shaikh 02 Jun '16

02 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15046 -gerrit commit 240cb710a01e14d0a7a37c1a1bf539c77c6ce871 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:55:43 2016 -0700 intel/apollolake: Add car.c to verstage Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 29636e1..9e4e160 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -59,6 +59,7 @@ postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +verstage-y += car.c verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c

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Patch set updated for coreboot: rockchip: gru: enable eDP display
by Martin Roth 02 Jun '16

02 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14858 -gerrit commit caacfed4a34c6b49376539f70b87652aa2b6fff1 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Mar 31 18:44:13 2016 +0800 rockchip: gru: enable eDP display This patch enable eDP display by, o. set HPD pinmux, backligh, vdd for eDP o. set vop mode o. enable VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=the dev screen shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq(a)rock-chips.com> --- src/mainboard/google/gru/Kconfig | 2 ++ src/mainboard/google/gru/devicetree.cb | 3 ++ src/mainboard/google/gru/mainboard.c | 58 +++++++++++++++++++++++++++++++ src/soc/rockchip/rk3399/include/soc/grf.h | 2 ++ 4 files changed, 65 insertions(+) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index b0ea9ff..48ae698 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -24,7 +24,9 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET + select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_NATIVE_VGA_INIT select SOC_ROCKCHIP_RK3399 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index b349888..be1d466 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -15,4 +15,7 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end + register "vop_id" = "0" + register "vop_mode" = "VOP_MODE_EDP" + register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 6824cbf..0ccedd3 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -15,11 +15,15 @@ */ #include <boardid.h> +#include <delay.h> #include <device/device.h> +#include <device/i2c.h> #include <gpio.h> #include <soc/clock.h> +#include <soc/display.h> #include <soc/emmc.h> #include <soc/grf.h> +#include <soc/i2c.h> static void configure_emmc(void) { @@ -86,10 +90,64 @@ static void configure_sdmmc(void) write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC); } +static void configure_display(void) +{ + /* set pinmux for edp HPD*/ + gpio_input_pulldown(GPIO(4, C, 7)); + write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); + + gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */ +} + static void mainboard_init(device_t dev) { configure_sdmmc(); configure_emmc(); + configure_display(); +} + +static void enable_backlight_booster(void) +{ + const struct { + uint8_t reg; + uint8_t value; + } i2c_writes[] = { + {1, 0x84}, + {1, 0x85}, + {0, 0x26} + }; + int i; + const int booster_i2c_port = 0; + uint8_t i2c_buf[2]; + struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c, + .buf = i2c_buf, .len = sizeof(i2c_buf) + }; + + /* + * This function is called on Gru right after BL_EN is asserted. It + * takes time for the switcher chip to come online, let's wait a bit + * to let the voltage settle, so that the chip can be accessed. + */ + udelay(1000); + + /* Select pinmux for i2c0, which is the display backlight booster. */ + write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); + write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); + i2c_init(0, 100*KHz); + + for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) { + i2c_buf[0] = i2c_writes[i].reg; + i2c_buf[1] = i2c_writes[i].value; + i2c_transfer(booster_i2c_port, &i2c_command, 1); + } +} + +void mainboard_power_on_backlight(void) +{ + gpio_output(GPIO(1, C, 1), 1); /* BL_EN */ + + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) + enable_backlight_booster(); } static void mainboard_enable(device_t dev) diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index df1fb03..241c97f 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -140,6 +140,7 @@ struct rk3399_grf_regs { u32 iomux_pwm_1; u32 iomux_uart2b; u32 iomux_uart2c; + u32 iomux_edp_hotplug; u32 gpio4c_iomux; }; u32 gpio4d_iomux; @@ -346,4 +347,5 @@ static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE; #define IOMUX_PWM_3_A RK_SETBITS(1 << 12) #define IOMUX_PWM_3_B RK_SETBITS(1 << 12) #define IOMUX_TSADC_INT RK_CLRSETBITS(3 << 12, 1 << 12) +#define IOMUX_EDP_HOTPLUG RK_CLRSETBITS(3 << 14, 2 << 14) #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */

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coreboot-gerrit June 2016