coreboot-gerrit June 2016

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New patch to review for coreboot: mainboard/intel/galileo: Set board version
by Leroy P Leahy 01 Jun '16

01 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15041 -gerrit commit da034c0725cc6674c4cf5b69fec63d5c6818e990 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 31 08:32:21 2016 -0700 mainboard/intel/galileo: Set board version Return the correct board version in SMBIOS. TEST=Build and run on Galileo Gen2 Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Makefile.inc | 1 + src/mainboard/intel/galileo/ramstage.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/src/mainboard/intel/galileo/Makefile.inc b/src/mainboard/intel/galileo/Makefile.inc index 83fb0db..449392c 100644 --- a/src/mainboard/intel/galileo/Makefile.inc +++ b/src/mainboard/intel/galileo/Makefile.inc @@ -21,4 +21,5 @@ romstage-y += gpio.c romstage-y += reg_access.c ramstage-y += gpio.c +ramstage-y += ramstage.c ramstage-y += reg_access.c diff --git a/src/mainboard/intel/galileo/ramstage.c b/src/mainboard/intel/galileo/ramstage.c new file mode 100644 index 0000000..2a8ade7 --- /dev/null +++ b/src/mainboard/intel/galileo/ramstage.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> + +/* Set the board version */ +const char *smbios_mainboard_version(void) +{ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + return "Gen 2"; + return "1.0"; +}

1 0

Patch set updated for coreboot: Add Board Checklist Support
by Leroy P Leahy 01 Jun '16

01 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15011 -gerrit commit 2dbce7217a6b8a89f9b161e1881331d75b983440 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 26 17:12:17 2016 -0700 Add Board Checklist Support Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Makefile.inc | 182 +++++++++++++++++++++ src/Kconfig | 8 + src/drivers/intel/fsp1_1/Kconfig | 4 + .../fsp/fsp1_1/checklist/bootblock_complete.dat | 77 +++++++++ .../fsp/fsp1_1/checklist/ramstage_complete.dat | 53 ++++++ .../fsp/fsp1_1/checklist/ramstage_optional.dat | 46 ++++++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 54 ++++++ .../fsp/fsp1_1/checklist/romstage_optional.dat | 34 ++++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 35 ++++ .../fsp/fsp1_1/checklist/verstage_optional.dat | 22 +++ 10 files changed, 515 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 574f2fe..2d2405e 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -559,6 +559,188 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug mv $@.tmp $@ ########################################################################### +# Build the board implementation checklist +########################################################################### + +%.symbols: %.elf + echo $@ + # + # All symbols in the image + # + nm $< | sed -r 's/^.{11}//' > $@ + +%.weak: %.elf + echo $@ + # + # Weak symbols in the image + # + nm $< | fgrep " W " | sed -r 's/^.{11}//' > $@ + +%.expected: %.elf + echo $@ + # + # Expected symbols in the image + # + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ ! -e $(*D)/verstage.elf ]; \ + then \ + if [ "$(*F)" = "romstage" ]; \ + then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat >> $@.tmp; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + sort -u $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +%.optional: %.elf + echo $@ + # + # Optional symbols in the image + # + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ ! -e $(*D)/verstage.elf ]; \ + then \ + if [ "$(*F)" = "romstage" ]; \ + then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + sort -u $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +%.done: %.symbols %.expected %.weak %.optional + echo $@ + # + # Expected Symbols Optional Weak Done Type + # no yes no d/c yes Don't display + # yes no no no no Required - not implemented + # yes no yes no no Optional - not implemented + # yes yes yes yes no Optional - not implemented + # yes yes no no yes Required - implemented + # yes yes yes no yes Required - implemented + # + # Implemented routines are in the symbol table and are not weak + # + comm -12 $(*D)/$(*F).expected $(*D)/$(*F).symbols | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).weak | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +%.optional2: %.optional %.done + echo $@ + # + # Remove any routines that are implemented + # + comm -23 $^ | sed "s/^[ \t]*//" > $@ + +%.tbd: %.expected %.done %.optional2 + echo $@ + # + # Remove any implemented or optional routines + # + comm -23 $(*D)/$(*F).expected $(*D)/$(*F).done | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).optional2 | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +# Count the lines in the done file +done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') + +# Count the lines in the optional file +optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional2 | sed 's/ .*//') + +# Count the lines in the expected file +expected_lines = $$(wc -l $(*D)/$(basename $(*F)).expected | sed 's/ .*//') + +# Compute the percentage done by routine count +percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lines)))) + +# Build the implementation table for each stage +%.html: %.optional2 %.done %.expected %.tbd + # + # Done table rows are in green + # + sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp + # + # Optional table rows are in yellow + # + sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional2 >> $@.tmp + # + # TBD table rows are in red + # + if [ -s $(*D)/$(basename $(*F)).tbd ]; \ + then \ + sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).tbd >> $@.tmp; \ + fi + # + # Add the table row termination + # + sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp + # + # Sort the table into alphabetical order + # + sort -t ">" -k4 $@.tmp > $@.tmp2 + # + # Build the table + # + echo "<table border=1>" > $@ + echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ + echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ + cat $@.tmp2 >> $@ + echo "</table>" >> $@ + echo "<br>" >> $@ + rm $@.tmp $@.tmp2 + +html_table_files = $(objcbfs)/romstage.html $(objcbfs)/ramstage.html +list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) +current_date = $$(date +"%Y/%m/%d") + +# Build the web page from the implementation tables +$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) + # + # Add the header to the web page + # + echo "<html>" > $@ + echo "<head>" >> $@ + echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ + echo "</title>" >> $@ + echo "<body>" >> $@ + echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status: $(current_date)</h1>" >> $@ + # + # Add the tables to the web page + # + for table in $(list_of_html_files); do \ + cat $$table >> $@; \ + done + # + # Add the trailer to the web page + # + echo "</body>" >> $@ + echo "</html>" >> $@ + +Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ + fi + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; \ + then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ + fi + cp $< $@ + +# Only build the checklist for boards under development +ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) +ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) +INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +else +INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +endif +endif + +########################################################################### # Build the final rom image ########################################################################### diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..2b9a136 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1175,3 +1175,11 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + +config MAKE_CHECKLIST_PUBLIC + bool + default n diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..86f6c7b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" +config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat new file mode 100644 index 0000000..8a4325f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -0,0 +1,77 @@ +arch_segment_loaded +backup_top_of_ram +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +mrc_cache_get_current +mrc_cache_stash_data +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +raminit +ramstage_cache_invalid +report_memory_config +save_chromeos_gpios +setup_stack_and_mtrrs +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_ram_init +soc_after_silicon_init +soc_display_memory_init_params +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_memory_init_params +soc_pre_ram_init +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000..64f8584 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,53 @@ +acpi_create_serialio_ssdt +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000..6608583 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,46 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000..e6bef6c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,54 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_fill_spd_data +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +migrate_power_state +mrc_cache_get_current_with_version +mrc_cache_stash_data_with_version +platform_prog_run +platform_segment_loaded +print_fsp_info +raminit +ramstage_cache_invalid +report_memory_config +romstage_common +save_chromeos_gpios +set_max_freq +setup_stack_and_mtrrs +smm_region +smm_region_size +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000..2634566 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,34 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000..2124f0f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,35 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +gpio_acpi_path +init_timer +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000..f589eaa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,22 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init

1 0

Patch set updated for coreboot: Documentation/Intel/Board: Add Galileo checklist
by Leroy P Leahy 01 Jun '16

01 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15012 -gerrit commit 3b4e426d9c521efe20e5557e3c4b78d90954584d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 17:09:09 2016 -0700 Documentation/Intel/Board: Add Galileo checklist Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/Galileo_checklist.html | 130 +++++++++++++++++++++++ Documentation/Intel/Board/galileo.html | 1 + 2 files changed, 131 insertions(+) diff --git a/Documentation/Intel/Board/Galileo_checklist.html b/Documentation/Intel/Board/Galileo_checklist.html new file mode 100644 index 0000000..3c33bb4 --- /dev/null +++ b/Documentation/Intel/Board/Galileo_checklist.html @@ -0,0 +1,130 @@ +<html> +<head> +<title>Galileo Implementation Status</title> +</title> +<body> +<h1>Galileo Implementation Status: 2016/05/31</h1> +<table border=1> +<tr><th colspan=2>romstage: 65% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>car_mainboard_post_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_mainboard_pre_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_post_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>car_soc_pre_console_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>fill_power_state</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_check_ec_image</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_fill_spd_data</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mainboard_memory_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>mainboard_romstage_entry</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_save_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>migrate_power_state</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_get_current_with_version</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>mrc_cache_stash_data_with_version</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>print_fsp_info</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>raminit</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>ramstage_cache_invalid</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>report_memory_config</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>romstage_common</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>set_max_freq</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>setup_stack_and_mtrrs</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>smm_region_size</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_after_ram_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_memory_init_params</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_display_mtrrs</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_get_variable_mtrr_count</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_memory_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_pre_ram_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>timestamp_get</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vboot_platform_prepare_reboot</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>verstage_mainboard_init</td></tr> +</table> +<br> +<table border=1> +<tr><th colspan=2>ramstage: 55% Done</th></tr> +<tr><th>Type</th><th>Routine</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>acpi_create_serialio_ssdt</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>arch_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>backup_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>boot_device_init</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>cbfs_master_header_locator</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cbmem_fail_resume</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>clear_recovery_mode_switch</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>cpu_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>fw_cfg_acpi_tables</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_sw_write_protect_state</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>get_top_of_ram</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>gpio_acpi_path</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>init_timer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>lb_board</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>lb_framebuffer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_add_dimm_info</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_io_trap_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_post</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_silicon_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_apmc</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_gpi</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_smi_sleep</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mainboard_suspend_resume</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>map_oprom_vendev</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>mirror_payload</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>northbridge_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>nvm_mmio_to_flash_offset</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_prog_run</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>platform_segment_loaded</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>save_chromeos_gpios</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_bios_version</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_manufacturer</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_product_name</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_serial_number</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smbios_mainboard_set_uuid</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>smbios_mainboard_version</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>smm_disable_busmaster</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_after_silicon_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_display_silicon_init_params</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>soc_fill_acpi_wake</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>soc_silicon_init_params</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>soc_skip_ucode_update</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>southbridge_smi_handler</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_add</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>stage_cache_load_stage</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_get</td></tr> +<tr bgcolor=#ffc0c0><td>Required</td><td>timestamp_tick_freq_mhz</td></tr> +<tr bgcolor=#c0ffc0><td>Required</td><td>tsc_freq_mhz</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_extend</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_finalize</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>vb2ex_hwcrypto_digest_init</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>wifi_regulatory_domain</td></tr> +<tr bgcolor=#ffffc0><td>Optional</td><td>write_smp_table</td></tr> +</table> +<br> +</body> +</html> diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index 3639419..cdc8fda 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -17,6 +17,7 @@ <li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li> <li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li> <li><a target="_blank" href="board.html">Board</a> support</li> + <li><a target="_blank" href="Galileo_checklist.html">Implementation Checklist</a></li> </ul> </td> </tr>

1 0

Patch set updated for coreboot: mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST
by Leroy P Leahy 01 Jun '16

01 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15004 -gerrit commit 0fe1b2631fa5753eca08a7926f58aa1b3d96fc42 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat May 28 14:34:44 2016 -0700 mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC and Galileo board. TEST=Build and run on Galileo Gen2. Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/galileo/Kconfig b/src/mainboard/intel/galileo/Kconfig index 96f1a8f..b0c69e4 100644 --- a/src/mainboard/intel/galileo/Kconfig +++ b/src/mainboard/intel/galileo/Kconfig @@ -18,6 +18,7 @@ if BOARD_INTEL_GALILEO config BOARD_SPECIFIC_OPTIONS def_bool y select BOARD_ROMSIZE_KB_8192 + select CREATE_BOARD_CHECKLIST select ENABLE_BUILTIN_HSUART1 select HAVE_ACPI_TABLES select SOC_INTEL_QUARK

1 0

New patch to review for coreboot: soc/intel/apollolake: Include nvh.h in acpi.h
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15040 -gerrit commit 549212648f72cc82f34dd756f3765b7c5fa8aa77 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue May 31 18:18:22 2016 -0700 soc/intel/apollolake: Include nvh.h in acpi.h Defines structure global_nvs_t. Change-Id: I0b3863445473e3d5ec84beb6fac7b7934c70b133 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/include/soc/acpi.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index ba3b8fc..b1eceec 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_ACPI_H_ #include <arch/acpi.h> +#include <soc/nvs.h> unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp);

1 0

Patch set updated for coreboot: apollolake: Add ACPI device for audio controller
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15026 -gerrit commit b9ade7edbf3da88205bf6b1987ddcc27c03c9a4f Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue Mar 8 17:33:29 2016 -0800 apollolake: Add ACPI device for audio controller Add the audio controller device to ACPI and define the _DSM handler to return the address of the NHLT table, if set in NVS. Change-Id: I619dbfb562b94255e42a3e5d5a3926c28b14db3e Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/pch.asl | 23 ++++++++ src/soc/intel/apollolake/acpi/pch_hda.asl | 89 +++++++++++++++++++++++++++++++ 2 files changed, 112 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/pch.asl b/src/soc/intel/apollolake/acpi/pch.asl new file mode 100644 index 0000000..8bcbfd7 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch.asl @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* PCH HDA */ +#include "pch_hda.asl" diff --git a/src/soc/intel/apollolake/acpi/pch_hda.asl b/src/soc/intel/apollolake/acpi/pch_hda.asl new file mode 100644 index 0000000..ac027e6 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/pch_hda.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +/* Audio Controller - Device 14, Function 0 */ + +Device (HDAS) +{ + Name (_ADR, 0x000E0000) + Name (_DDN, "Audio Controller") + Name (UUID, ToUUID ("A69F886E-6CEB-4594-A41F-7B5DCE24C553")) + + /* Device is D3 wake capable */ + Name (_S0W, 3) + + /* NHLT Table Address populated from GNVS values */ + Name (NBUF, ResourceTemplate () { + QWordMemory (ResourceConsumer, PosDecode, MinFixed, + MaxFixed, NonCacheable, ReadOnly, + 0, 0, 0, 0, 1,,, NHLT, AddressRangeACPI) + }) + + /* + * Device Specific Method + * Arg0 - UUID + * Arg1 - Revision + * Arg2 - Function Index + */ + Method (_DSM, 4) + { + If (LEqual (Arg0, ^UUID)) { + /* + * Function 0: Function Support Query + * Returns a bitmask of functions supported. + */ + If (LEqual (Arg2, Zero)) { + /* + * NHLT Query only supported for revision 1 and + * if NHLT address and length are set in NVS. + */ + If (LAnd (LEqual (Arg1, One), + LAnd (LNotEqual (NHLA, Zero), + LNotEqual (NHLL, Zero)))) { + Return (Buffer (One) { 0x03 }) + } Else { + Return (Buffer (One) { 0x01 }) + } + } + + /* + * Function 1: Query NHLT memory address used by + * Intel Offload Engine Driver to discover any non-HDA + * devices that are supported by the DSP. + * + * Returns a pointer to NHLT table in memory. + */ + If (LEqual (Arg2, One)) { + CreateQWordField (NBUF, ^NHLT._MIN, NBAS) + CreateQWordField (NBUF, ^NHLT._MAX, NMAS) + CreateQWordField (NBUF, ^NHLT._LEN, NLEN) + + Store (NHLA, NBAS) + Store (NHLA, NMAS) + Store (NHLL, NLEN) + + Return (NBUF) + } + } + + Return (Buffer (One) { 0x00 }) + } +} +

1 0

Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit f67cca6198c16642af613f55086c5a792d7b83fa Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 +++ src/mainboard/intel/amenia/dsdt.asl | 1 + src/mainboard/intel/amenia/mainboard.c | 90 +++++++++++++++++++++++++++++++++- 3 files changed, 98 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..1be4a9f 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -29,6 +29,7 @@ DefinitionBlock( { #include <soc/intel/apollolake/acpi/northbridge.asl> #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch.asl } } /* Mainboard Specific devices */ diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..40a65ff 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,14 @@ */ #include <device/device.h> +#include <pc80/keyboard.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +95,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -114,6 +119,9 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_165, UP_20K, DEEP, NF1), /* EMMC0_CMD */ PAD_CFG_NF(GPIO_182, DN_20K, DEEP, NF1), /* EMMC_RCLK */ + PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF1), /* DDI0_HPD */ + PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF1), /* DDI1_HPD */ + PAD_CFG_NF(GPIO_203, NATIVE, DEEP, NF1), /* USB2_OC0_3p3_N */ PAD_CFG_NF(GPIO_204, NATIVE, DEEP, NF1), /* USB2_OC2_N */ @@ -129,15 +137,95 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; + +struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) { gpio_configure_pads(amenia_gpios, ARRAY_SIZE(amenia_gpios)); mainboard_ec_init(); + pc_keyboard_init(NO_AUX_DEVICE); +} + +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), &headset_tdm_cfg, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

1 0

Patch set updated for coreboot: apollolake/amenia: Adding NHLA and NHLL
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 16fb715fe00705f635661ff91ae68c9d25619b10 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 apollolake/amenia: Adding NHLA and NHLL Address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/dsdt.asl | 3 +++ src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 3 files changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 1be4a9f..95ca98b 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -24,6 +24,9 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

1 0

Patch set updated for coreboot: soc/intel/apollolake: Increase heap size to 64 KiB
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15038 -gerrit commit ab7f19fd44fb39205607cf43058c1839cb054adf Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Wed Apr 20 15:30:16 2016 -0700 soc/intel/apollolake: Increase heap size to 64 KiB We run out of heap space (current default is 16 KiB) when NHLT blobs are loaded. Change-Id: I5d4872178d6e8700da89bf93e8d48cf46c4cd85b Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index d6c5ffc..0b9c05a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -160,4 +160,8 @@ config LBP2_FILE_NAME help Name of file to store in the logical boot partition 2 region. +config HEAP_SIZE + hex + default 0x10000 + endif

1 0

Patch set updated for coreboot: drivers/intel/audio: Add common NHLT audio for Intel platforms
by Saurabh Satija 01 Jun '16

01 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15023 -gerrit commit dc432beb0fde7f24f92801c91139a1fcc61c9c73 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 15:53:41 2016 -0700 drivers/intel/audio: Add common NHLT audio for Intel platforms The use of a NHLT table is required to make audio work on the intel SoCs employing the internal DSP. The table describes the audo endpoints (render vs capture) along with their supported formats. These formats are not only dependent on the audio peripheral but also hardware interfaces. As such each format has an associated blob of DSP settings to make the peripheral work. Lastly, each of these settings are provided by Intel and need to be generated for each device's hardware connection plus mode/format it supports. This patch does not include the dsp setting blobs. Change-Id: I3c75d3537288c47d29e8949ca253ea8c5c1a387d Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/drivers/intel/audio/Kconfig | 48 +++++++++++++ src/drivers/intel/audio/Makefile.inc | 43 +++++++++++ src/drivers/intel/audio/dmic.c | 53 ++++++++++++++ src/drivers/intel/audio/headset.c | 60 ++++++++++++++++ src/drivers/intel/audio/include/drivers/audio.h | 59 +++++++++++++++ src/drivers/intel/audio/nhlt.c | 95 +++++++++++++++++++++++++ src/drivers/intel/audio/speaker.c | 40 +++++++++++ 7 files changed, 398 insertions(+) diff --git a/src/drivers/intel/audio/Kconfig b/src/drivers/intel/audio/Kconfig new file mode 100644 index 0000000..fdc494c --- /dev/null +++ b/src/drivers/intel/audio/Kconfig @@ -0,0 +1,48 @@ +config USE_COMMON_AUDIO + bool + default n + help + Build support for drivers audio code, common to intel + platforms that use NHLT. + +config AUDIO_DMIC_2CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 16B DMIC array. + +config AUDIO_DMIC_2CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 2 channel 32B DMIC array. + +config AUDIO_DMIC_4CH_16B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 16B DMIC array. + +config AUDIO_DMIC_4CH_32B + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for 4 channel 32B DMIC array. + +config AUDIO_HEADSET + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for headset codec. + +config AUDIO_SPEAKER + bool + depends on USE_COMMON_AUDIO + default n + help + Include DSP firmware settings for speaker amplifier. diff --git a/src/drivers/intel/audio/Makefile.inc b/src/drivers/intel/audio/Makefile.inc new file mode 100644 index 0000000..6bea190 --- /dev/null +++ b/src/drivers/intel/audio/Makefile.inc @@ -0,0 +1,43 @@ +ifeq ($(CONFIG_USE_COMMON_AUDIO),y) +ramstage-y += nhlt.c +ramstage-y += dmic.c +ramstage-y += headset.c +ramstage-y += speaker.c + +# DSP firmware settings files. +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/apollolake/nhlt-blobs +DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin +DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin +DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin +DMIC_4CH_48KHZ_32B = dmic-4ch-48khz-32b.bin + +HEADSET = headset-2ch-48khz-24b.bin + +SPEAKER_RENDER = max98357-render-2ch-48khz-24b.bin + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_16B) += $(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) +$(DMIC_2CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_2CH_32B) += $(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_32B) +$(DMIC_2CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_16B) += $(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_16B) +$(DMIC_4CH_48KHZ_16B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_DMIC_4CH_32B) += $(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-file := $(NHLT_BLOB_PATH)/$(DMIC_4CH_48KHZ_32B) +$(DMIC_4CH_48KHZ_32B)-type := raw + +cbfs-files-$(CONFIG_AUDIO_HEADSET) += $(HEADSET) +$(HEADSET)-file := $(NHLT_BLOB_PATH)/$(HEADSET) +$(HEADSET)-type := raw + +cbfs-files-$(CONFIG_AUDIO_SPEAKER) += $(SPEAKER_RENDER) +$(SPEAKER_RENDER)-file := $(NHLT_BLOB_PATH)/$(SPEAKER_RENDER) +$(SPEAKER_RENDER)-type := raw +endif + +CPPFLAGS_common += -I$(src)/drivers/intel/audio/include diff --git a/src/drivers/intel/audio/dmic.c b/src/drivers/intel/audio/dmic.c new file mode 100644 index 0000000..fe11d51 --- /dev/null +++ b/src/drivers/intel/audio/dmic.c @@ -0,0 +1,53 @@ + /* + * This file is part of the coreboot project. + * + * Copyright 2016 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <string.h> + +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_cfg, int fmt_size, int num_channels) +{ + struct nhlt_endpoint *endp; + struct nhlt_dmic_array_config mic_config; + const struct nhlt_format_config *formats; + + if (num_channels != 2 && num_channels != 4) + return -1; + + endp = nhlt_soc_add_endpoint(nhlt, AUDIO_LINK_DMIC, AUDIO_DEV_DMIC, + NHLT_DIR_CAPTURE); + + if (endp == NULL) + return -1; + + memset(&mic_config, 0, sizeof(mic_config)); + mic_config.tdm_config.config_type = NHLT_TDM_MIC_ARRAY; + + formats = dmic_ch_cfg; + + switch (num_channels) { + case 2: + mic_config.array_type = NHLT_MIC_ARRAY_2CH_SMALL; + break; + case 4: + mic_config.array_type = NHLT_MIC_ARRAY_4CH_L_SHAPED; + break; + } + + if (nhlt_endpoint_append_config(endp, &mic_config, sizeof(mic_config))) + return -1; + + return nhlt_endpoint_add_formats(endp, formats, fmt_size); +} + diff --git a/src/drivers/intel/audio/headset.c b/src/drivers/intel/audio/headset.c new file mode 100644 index 0000000..68acee2 --- /dev/null +++ b/src/drivers/intel/audio/headset.c @@ -0,0 +1,60 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> +#include <console/console.h> + +/* The same DSP firmwware settings are used for both the capture and + * render endpoints. */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + /* The headphone codec has headphones and a mic. Both the capture and + * render endpoints occupy the same virtual slot. */ + const void *fmt_cfg = headset_cfg; + size_t fmt_sz = fmt_size; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + /* Capture Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_CAPTURE); + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, fmt_cfg, fmt_sz)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +} diff --git a/src/drivers/intel/audio/include/drivers/audio.h b/src/drivers/intel/audio/include/drivers/audio.h new file mode 100644 index 0000000..caf1edc --- /dev/null +++ b/src/drivers/intel/audio/include/drivers/audio.h @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _DRIVERS_AUDIO_H_ +#define _DRIVERS_AUDIO_H_ + +#include <nhlt.h> + +/* + * Skylake NHLT device and hardware link types. These values are to be used + * with nhlt_soc_add_endpoint(). + */ + +enum { + AUDIO_LINK_SSP0, + AUDIO_LINK_SSP1, + AUDIO_LINK_SSP2, /* Only Bluetooth supported on SSP2. */ + AUDIO_LINK_SSP3, + AUDIO_LINK_SSP4, + AUDIO_LINK_SSP5, + AUDIO_LINK_DMIC, +}; + +enum { + AUDIO_DEV_I2S, + AUDIO_DEV_DMIC, + AUDIO_DEV_BT, +}; + +/* + * Add a dmic array composed of the provided number of channels. + * Returns 0 on success, < 0 on error. + */ +int nhlt_soc_add_dmic_array(struct nhlt *nhlt, const struct nhlt_format_config *dmic_ch_config, int cfg_size, int num_channels); + +/* + * Add headset codec on provided SSP link. Return 0 on succes, < 0 on error. + */ +int nhlt_soc_add_headset(struct nhlt *nhlt, const struct nhlt_format_config *headset_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +/* + * Add speaker amplifier in stereo configuration on provide SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int cfg_size, struct nhlt_tdm_config *tdm_config, int hwlink); + +#endif diff --git a/src/drivers/intel/audio/nhlt.c b/src/drivers/intel/audio/nhlt.c new file mode 100644 index 0000000..0f8e6e1 --- /dev/null +++ b/src/drivers/intel/audio/nhlt.c @@ -0,0 +1,95 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <soc/acpi.h> +#include <drivers/audio.h> + +#define NHLT_VID 0x8086 +#define NHLT_DID_DMIC 0xae20 +#define NHLT_DID_BT 0xae30 +#define NHLT_DID_SSP 0xae34 + +struct nhlt_endpoint *nhlt_soc_add_endpoint(struct nhlt *nhlt, int soc_hwintf, + int soc_devtype, int dir) +{ + int nhlt_link_type; + int nhlt_dev_type; + uint16_t did; + struct nhlt_endpoint *endp; + + /* Check link type and device type. */ + switch (soc_hwintf) { + case AUDIO_LINK_SSP0: + case AUDIO_LINK_SSP1: + case AUDIO_LINK_SSP5: + case AUDIO_LINK_SSP2: + nhlt_link_type = NHLT_LINK_SSP; + break; + case AUDIO_LINK_DMIC: + /* Only DMIC devices on DMIC links. */ + if (soc_devtype != AUDIO_DEV_DMIC) + return NULL; + nhlt_link_type = NHLT_LINK_PDM; + break; + default: + return NULL; + } + + switch (soc_devtype) { + case AUDIO_DEV_I2S: + nhlt_dev_type = NHLT_SSP_DEV_I2S; + did = NHLT_DID_SSP; + break; + case AUDIO_DEV_DMIC: + nhlt_dev_type = NHLT_PDM_DEV; + did = NHLT_DID_DMIC; + break; + case AUDIO_DEV_BT: + nhlt_dev_type = NHLT_SSP_DEV_BT; + did = NHLT_DID_BT; + break; + default: + return NULL; + } + + endp = nhlt_add_endpoint(nhlt, nhlt_link_type, nhlt_dev_type, dir, + NHLT_VID, did); + + if (endp == NULL) + return NULL; + + /* Virtual bus id of SSP links are the hardware port ids proper. */ + if (nhlt_link_type == NHLT_LINK_SSP) + endp->virtual_bus_id = soc_hwintf; + + return endp; +} + +uintptr_t nhlt_soc_serialize(struct nhlt *nhlt, uintptr_t acpi_addr) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs == NULL) + return acpi_addr; + + /* Update NHLT GNVS Data */ + gnvs->nhla = (uintptr_t)acpi_addr; + gnvs->nhll = nhlt_current_size(nhlt); + + return nhlt_serialize(nhlt, acpi_addr); +} diff --git a/src/drivers/intel/audio/speaker.c b/src/drivers/intel/audio/speaker.c new file mode 100644 index 0000000..63dba66 --- /dev/null +++ b/src/drivers/intel/audio/speaker.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2015 Google, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <drivers/audio.h> + +int nhlt_soc_add_speaker(struct nhlt *nhlt, const struct nhlt_format_config *speaker_cfg, int fmt_size, struct nhlt_tdm_config *tdm_config, int hwlink) +{ + struct nhlt_endpoint *endp; + + /* Render Endpoint */ + endp = nhlt_soc_add_endpoint(nhlt, hwlink, AUDIO_DEV_I2S, + NHLT_DIR_RENDER); + + if (endp == NULL) + return -1; + + if(tdm_config != NULL){ + if (nhlt_endpoint_append_config(endp, &tdm_config, 1)) + return -1; + } + + if (nhlt_endpoint_add_formats(endp, speaker_cfg, fmt_size)) + return -1; + + nhlt_next_instance(nhlt, NHLT_LINK_SSP); + + return 0; +}

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coreboot-gerrit June 2016