coreboot-gerrit June 2016

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Patch merged into coreboot/master: intel/apollolake: Add support to enable google ChromeEC
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit d6463dd42c0b5688601ce6de5e7cff16926df297 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed May 25 11:34:43 2016 -0700 intel/apollolake: Add support to enable google ChromeEC ChromeEC is needed for EC controlled features to work properly. This patch adds neccessary support in soc/intel so that mainboard asl files can include the ChromeEC e.g. PNOT method and LPCB and also the nvs fields. BUG = 53096 TEST = This patch is needed by the mainboard specific ASL change to include src/ec/google/chromeec/acpi/ec.asl Change-Id: Icecc437df05cd3efb41579317a353fd22526e0c9 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> Reviewed-on: https://review.coreboot.org/14967 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14967 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: add support for IFWI region
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 7043bf353af14b5a11f18875e6e41ceac56ebfa7 Author: Furquan Shaikh <furquan(a)google.com> Date: Sat May 28 12:57:05 2016 -0700 soc/intel/apollolake: add support for IFWI region On apollolake, the boot media layout is different in that the traditional "BIOS" region contains another data structure with the boot assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware to name a few. This region is referred to as the IFWI. Add support for writing the IFWI to a specified FMAP region to accommodate such platforms. Change-Id: Ia61f12a77893c3dd3256a9bd4e0f5eca0065de26 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/14999 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14999 for details. -gerrit

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Patch merged into coreboot/master: Makefile: Add ifwitool to list of tools to be built
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 3ac9d4cbb0354dedb95c44fcd656a23071dfc326 Author: Furquan Shaikh <furquan(a)google.com> Date: Mon May 30 23:03:58 2016 -0700 Makefile: Add ifwitool to list of tools to be built Add ifwitool to list of tools to be built so that it can be used by the build system. Change-Id: Ifcfbfd87ad9b7ba3ea11cfbcf40894f3e0dae694 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15013 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15013 for details. -gerrit

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Patch merged into coreboot/master: ifwitool: Fix syntax issues with ifwitool
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 55d2e5398b79c4f4c63caee39a9fb740fab7ae52 Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 31 11:02:47 2016 -0700 ifwitool: Fix syntax issues with ifwitool Change-Id: Ie7a12a39116ee08f5e24c81c97695201169a63f7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15022 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15022 for details. -gerrit

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Patch set updated for coreboot: soc/intel/common: Add _OSC method
by Hannah Williams 01 Jun '16

01 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15021 -gerrit commit aeb3b8b17466e3d694a282693ab406c15479d240 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 18 13:45:20 2016 -0700 soc/intel/common: Add _OSC method Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/acpi/osc.asl | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/src/soc/intel/common/acpi/osc.asl b/src/soc/intel/common/acpi/osc.asl new file mode 100644 index 0000000..1891ac0 --- /dev/null +++ b/src/soc/intel/common/acpi/osc.asl @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0) { + + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +}

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New patch to review for coreboot: soc/apollolake/pmc: Store the ACPI bar during set_resources stage
by Alexandru Gagniuc 01 Jun '16

01 Jun '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15048 -gerrit commit 92e0586977552eda55b527d586f5bfb2f6a49f7f Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed May 18 14:41:48 2016 -0700 soc/apollolake/pmc: Store the ACPI bar during set_resources stage Because the resource for the ACPI BAR is fixed, pci_dev_set_resources does not store it to the device. This means we need to do part of the dance to get the ACPI IO region to work after coreboot. Of course, this BAR can be destroyed later by the OS probing it, but at least we try to get it working out of coreboot. Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/pmc.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/pmc.c b/src/soc/intel/apollolake/pmc.c index 8cf9843..c88e14c 100644 --- a/src/soc/intel/apollolake/pmc.c +++ b/src/soc/intel/apollolake/pmc.c @@ -38,9 +38,29 @@ static void read_resources(device_t dev) res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; } +/* + * Part 2: + * Resources are assigned, and no other device was given an IO resource to + * overlap with our ACPI BAR. But because the resource is FIXED, + * pci_dev_set_resources() will not store it for us. We need to do that + * explicitly. + */ +static void set_resources(device_t dev) +{ + struct resource *res; + + pci_dev_set_resources(dev); + + res = find_resource(dev, PCI_BASE_ADDRESS_4); + pci_write_config32(dev, res->index, res->base); + dev->command |= PCI_COMMAND_IO; + res->flags |= IORESOURCE_STORED; + report_resource_stored(dev, res, " ACPI BAR"); +} + static const struct device_operations device_ops = { .read_resources = read_resources, - .set_resources = pci_dev_set_resources, + .set_resources = set_resources, .enable_resources = pci_dev_enable_resources, };

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Patch merged into coreboot/master: mainboard/google/reef: Add IFWI region to chromeos.fmd
by gerrit＠coreboot.org 01 Jun '16

01 Jun '16

the following patch was just integrated into master: commit 989842c972bcadb7772ca519c155e3ebab0a9252 Author: Furquan Shaikh <furquan(a)google.com> Date: Sun May 29 20:24:37 2016 -0700 mainboard/google/reef: Add IFWI region to chromeos.fmd IFWI region holds different components required for booting including CSE firmware, PMC firmware, CPU microcode as well as the bootblock. Add section for IFWI in chromeos.fmd Change-Id: Ic97980ff222ad7cbd7a2970417b79150256a7a16 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15000 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15000 for details. -gerrit

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Patch set updated for coreboot: cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP
by Furquan Shaikh 01 Jun '16

01 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15045 -gerrit commit 03409c9b7ff1f11d5d2fac1fb6a134d12cca2a87 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:53:18 2016 -0700 cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP Modern platforms like Apollolake do not use XIP for early stages. In such cases, cbfs_prog_stage_load should check for NO_XIP_EARLY_STAGES instead of relying on ARCH_X86 to decide if a stage is XIP. Change-Id: I1729ce82b5f678ce8c37256090fcf353cc22b1ec Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/Kconfig | 3 +-- src/lib/cbfs.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..6e6e944 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -204,8 +204,7 @@ config NO_XIP_EARLY_STAGES default n if ARCH_X86 default y help - Identify if --xip parameter needs to be passed into cbfstool for early - stages. + Identify if early stages are eXecute-In-Place(XIP). config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 764a6f7..aa652c2 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -192,7 +192,7 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ - if (ENV_VERSTAGE && IS_ENABLED(CONFIG_ARCH_X86) && + if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED)) { void *mapping = rdev_mmap(fh, foffset, fsize); rdev_munmap(fh, mapping);

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Patch set updated for coreboot: google/reef: Select UART_FOR_CONSOLE for reef
by Furquan Shaikh 01 Jun '16

01 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15044 -gerrit commit 9c319d50519eae26afac9da95fff0ed0fcba958b Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 31 23:38:26 2016 -0700 google/reef: Select UART_FOR_CONSOLE for reef Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5d8ded6..c1ccc5c 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -50,4 +50,8 @@ config MAX_CPUS int default 8 +config UART_FOR_CONSOLE + int + default 2 + endif # BOARD_GOOGLE_REEF

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Patch set updated for coreboot: intel/apollolake: Add car.c to verstage
by Furquan Shaikh 01 Jun '16

01 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15046 -gerrit commit 1a35e63e45383f69fbb093c60f617a75d7180b4b Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:55:43 2016 -0700 intel/apollolake: Add car.c to verstage Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 29636e1..9e4e160 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -59,6 +59,7 @@ postcar-y += mmap_boot.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +verstage-y += car.c verstage-y += memmap.c verstage-y += mmap_boot.c verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c

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coreboot-gerrit June 2016