coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

1 participants
1491 discussions

New patch to review for coreboot: intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()
by Ben Gardner 01 Jun '16

01 Jun '16

Ben Gardner (gardner.ben(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15047 -gerrit commit cc49754bba4b7757d833a45a9373fa2012eafc2c Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Jun 1 09:25:28 2016 -0500 intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init() i2c_init() leaves the I2C device enabled. Combined with the default interrupt mask (0x8ff) and the fact that the interrupt line is shared, this leads to an interrupt storm in the OS until a proper I2C driver is loaded. This change clears the interrupt mask to prevent the interrupt storm. Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> --- src/soc/intel/fsp_baytrail/i2c.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/fsp_baytrail/i2c.c b/src/soc/intel/fsp_baytrail/i2c.c index eb83180..4565ba4 100644 --- a/src/soc/intel/fsp_baytrail/i2c.c +++ b/src/soc/intel/fsp_baytrail/i2c.c @@ -141,6 +141,8 @@ int i2c_init(unsigned bus) /* For 400 kHz, the counter value is 0x7d */ write32(base_ptr + I2C_FS_SCL_HCNT, 0x7d); write32(base_ptr + I2C_FS_SCL_LCNT, 0x7d); + /* no interrupts in BIOS */ + write32(base_ptr + I2C_INTR_MASK, 0); /* Enable the I2C controller for operation */ write32(base_ptr + I2C_ENABLE, 0x1);

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Patch set updated for coreboot: SMBIOS: Implement SKU field
by Kyösti Mälkki 01 Jun '16

01 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14996 -gerrit commit 497db51aa9e5ec5f33ef157c0d4e3abb8395a251 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 30 16:52:31 2016 +0300 SMBIOS: Implement SKU field Leave it for the platform to fill in the string. Change-Id: I7b4fe585f8d1efc8c9743f0d8b38de1f98124aab Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/smbios.c | 6 ++++++ src/include/smbios.h | 1 + 2 files changed, 7 insertions(+) diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 7c5497e..7b6dda1 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -340,6 +340,11 @@ void __attribute__((weak)) smbios_mainboard_set_uuid(u8 *uuid) } #endif +const char *__attribute__((weak)) smbios_mainboard_sku(void) +{ + return ""; +} + #ifdef CONFIG_MAINBOARD_FAMILY const char *smbios_mainboard_family(void) { @@ -359,6 +364,7 @@ static int smbios_write_type1(unsigned long *current, int handle) t->manufacturer = smbios_add_string(t->eos, smbios_mainboard_manufacturer()); t->product_name = smbios_add_string(t->eos, smbios_mainboard_product_name()); t->serial_number = smbios_add_string(t->eos, smbios_mainboard_serial_number()); + t->sku = smbios_add_string(t->eos, smbios_mainboard_sku()); t->version = smbios_add_string(t->eos, smbios_mainboard_version()); #ifdef CONFIG_MAINBOARD_FAMILY t->family = smbios_add_string(t->eos, smbios_mainboard_family()); diff --git a/src/include/smbios.h b/src/include/smbios.h index 004bcc6..0400262 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -35,6 +35,7 @@ const char *smbios_mainboard_serial_number(void); const char *smbios_mainboard_version(void); void smbios_mainboard_set_uuid(u8 *uuid); const char *smbios_mainboard_bios_version(void); +const char *smbios_mainboard_sku(void); u8 smbios_mainboard_enclosure_type(void); #ifdef CONFIG_MAINBOARD_FAMILY const char *smbios_mainboard_family(void);

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Patch set updated for coreboot: pcengines/apu1: Add SMBIOS SKU field
by Kyösti Mälkki 01 Jun '16

01 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14997 -gerrit commit e4dc3c36b619fde01ffac16e09adebeb3efed6d9 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 30 16:56:11 2016 +0300 pcengines/apu1: Add SMBIOS SKU field Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/mainboard.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 2ebdc75..96b2020 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -260,6 +260,22 @@ static void usb_oc_setup(void) pci_write_config32(dev, 0x58, 0x011f0); } +/* + * We will stuff the memory size into the smbios sku location. + */ +const char *smbios_mainboard_sku(void) +{ + static char sku[5]; + if (sku[0] != 0) + return sku; + + if (!get_spd_offset()) + snprintf(sku, sizeof(sku), "2 GB"); + else + snprintf(sku, sizeof(sku), "4 GB"); + return sku; +} + static void mainboard_final(void *chip_info) { u32 mmio_base;

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Patch set updated for coreboot: pcengines/apu1: Add RS485 configuration
by Kyösti Mälkki 01 Jun '16

01 Jun '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14998 -gerrit commit 904b664a6f311a1c7b91dce58bffb201ea13b7bb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 13 15:01:15 2015 +0300 pcengines/apu1: Add RS485 configuration In RS485 mode #RTS line acts as a transceiver direction control. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/pcengines/apu1/Kconfig | 6 ++++++ src/mainboard/pcengines/apu1/mainboard.c | 23 +++++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index e9aab8c..3099d14 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -95,6 +95,9 @@ config APU1_PINMUX_UART_C endchoice +config UART_C_RS485 + bool "UART C drives RTS# in RS485 mode" if APU1_PINMUX_UART_C + choice prompt "J19 pins 11-20" default APU1_PINMUX_OFF_D @@ -110,4 +113,7 @@ config APU1_PINMUX_UART_D endchoice +config UART_D_RS485 + bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu1/mainboard.c b/src/mainboard/pcengines/apu1/mainboard.c index 96b2020..055cd58 100644 --- a/src/mainboard/pcengines/apu1/mainboard.c +++ b/src/mainboard/pcengines/apu1/mainboard.c @@ -158,6 +158,28 @@ static void config_gpio_mux(void) gpio->enabled = CONFIG_APU1_PINMUX_GPIO1; } +static void pnp_raw_resource(struct device *dev, u8 reg, u8 val) +{ + struct resource *res; + res = new_resource(dev, reg); + res->base = val; + res->size = 0; + res->flags |= IORESOURCE_IRQ | IORESOURCE_ASSIGNED; +} + +static void config_addon_uart(void) +{ + struct device *uart; + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP3); + if (uart && uart->enabled && CONFIG_UART_C_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); + + uart = dev_find_slot_pnp(SIO_PORT, NCT5104D_SP4); + if (uart && uart->enabled && CONFIG_UART_D_RS485) + pnp_raw_resource(uart, 0xf2, 0x12); +} + /** * TODO * SB CIMx callback @@ -182,6 +204,7 @@ static void mainboard_enable(device_t dev) printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); config_gpio_mux(); + config_addon_uart(); /* Power off unused clock pins of GPP PCIe devices */ u8 *misc_mem_clk_cntrl = (u8 *)(ACPI_MMIO_BASE + MISC_BASE);

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Patch set updated for coreboot: lenovo/t420: correct the eSATA port
by Iru Cai 01 Jun '16

01 Jun '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14632 -gerrit commit 007ba382c795c62302beb7df0803b5ddebe90e94 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri May 6 23:05:28 2016 +0800 lenovo/t420: correct the eSATA port The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU model and a dGPU model. Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/mainboard/lenovo/t420/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/t420/devicetree.cb b/src/mainboard/lenovo/t420/devicetree.cb index 8041e5b..f549d4c 100644 --- a/src/mainboard/lenovo/t420/devicetree.cb +++ b/src/mainboard/lenovo/t420/devicetree.cb @@ -54,8 +54,8 @@ chip northbridge/intel/sandybridge register "gpi1_routing" = "2" register "gpi13_routing" = "2" - # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 4 (dock) & 5 (eSATA) - register "sata_port_map" = "0x37" + # Enable SATA ports 0 (HDD bay) & 1 (ODD bay) & 2 (mSATA) & 3 (eSATA) & 4 (dock) + register "sata_port_map" = "0x1f" # Set max SATA speed to 6.0 Gb/s register "sata_interface_speed_support" = "0x3"

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New patch to review for coreboot: intel/apollolake: Add car.c to verstage
by Furquan Shaikh 01 Jun '16

01 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15046 -gerrit commit cbc3b7d39ee89ca35da2c70578c71540e5bc6ab5 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:55:43 2016 -0700 intel/apollolake: Add car.c to verstage Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/soc/intel/apollolake/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 29636e1..c26cd07 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -18,6 +18,8 @@ bootblock-y += mmap_boot.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +verstage-y += car.c + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c

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New patch to review for coreboot: cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP
by Furquan Shaikh 01 Jun '16

01 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15045 -gerrit commit bbb37c86194bcb4004146a2e013d5ce3a86733e9 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:53:18 2016 -0700 cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP Modern platforms like Apollolake do not use XIP for early stages. In such cases, cbfs_prog_stage_load should check for NO_XIP_EARLY_STAGES instead of relying on ARCH_X86 to decide if a stage is XIP. Change-Id: I1729ce82b5f678ce8c37256090fcf353cc22b1ec Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/Kconfig | 3 +-- src/lib/cbfs.c | 2 +- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..6e6e944 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -204,8 +204,7 @@ config NO_XIP_EARLY_STAGES default n if ARCH_X86 default y help - Identify if --xip parameter needs to be passed into cbfstool for early - stages. + Identify if early stages are eXecute-In-Place(XIP). config EARLY_CBMEM_INIT def_bool !LATE_CBMEM_INIT diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 764a6f7..aa652c2 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -192,7 +192,7 @@ int cbfs_prog_stage_load(struct prog *pstage) /* Hacky way to not load programs over read only media. The stages * that would hit this path initialize themselves. */ - if (ENV_VERSTAGE && IS_ENABLED(CONFIG_ARCH_X86) && + if (ENV_VERSTAGE && !IS_ENABLED(CONFIG_NO_XIP_EARLY_STAGES) && IS_ENABLED(CONFIG_SPI_FLASH_MEMORY_MAPPED)) { void *mapping = rdev_mmap(fh, foffset, fsize); rdev_munmap(fh, mapping);

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New patch to review for coreboot: google/reef: Enable console for reef
by Furquan Shaikh 01 Jun '16

01 Jun '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15044 -gerrit commit b1c3ae9b2160a6687bf7b95699747758b73b933e Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 31 23:38:26 2016 -0700 google/reef: Enable console for reef Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/mainboard/google/reef/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 5d8ded6..ab14416 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -11,6 +11,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM + select SOC_UART_DEBUG select SYSTEM_TYPE_LAPTOP config BOOT_MEDIA_SPI_BUS @@ -50,4 +51,8 @@ config MAX_CPUS int default 8 +config UART_FOR_CONSOLE + int + default 2 + endif # BOARD_GOOGLE_REEF

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New patch to review for coreboot: drivers/intel/fsp1_1: Make weak routines quiet
by Leroy P Leahy 01 Jun '16

01 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15043 -gerrit commit d1f6755a56ef784ffb3d9bc7ca508aeb5dd30fb6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 31 08:57:01 2016 -0700 drivers/intel/fsp1_1: Make weak routines quiet Now that there is a better way of finding optional routines, make the weak routines quiet so that it may be used for the optional implementation. TEST=Build and run on Galileo Gen2 Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/ramstage.c | 3 --- src/drivers/intel/fsp1_1/romstage.c | 12 ------------ 2 files changed, 15 deletions(-) diff --git a/src/drivers/intel/fsp1_1/ramstage.c b/src/drivers/intel/fsp1_1/ramstage.c index 6e2de29..b4a6af1 100644 --- a/src/drivers/intel/fsp1_1/ramstage.c +++ b/src/drivers/intel/fsp1_1/ramstage.c @@ -30,7 +30,6 @@ /* SOC initialization after FSP silicon init */ __attribute__((weak)) void soc_after_silicon_init(void) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Display SMM memory map */ @@ -209,7 +208,6 @@ void intel_silicon_init(void) __attribute__((weak)) void mainboard_silicon_init_params( SILICON_INIT_UPD *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); }; /* Display the UPD parameters for SiliconInit */ @@ -223,5 +221,4 @@ __attribute__((weak)) void soc_display_silicon_init_params( /* Initialize the UPD parameters for SiliconInit */ __attribute__((weak)) void soc_silicon_init_params(SILICON_INIT_UPD *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index 6584c55..c380ff7 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -194,14 +194,12 @@ void after_cache_as_ram_stage(void) /* Initialize the power state */ __attribute__((weak)) struct chipset_power_state *fill_power_state(void) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return NULL; } __attribute__((weak)) void mainboard_check_ec_image( struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); #if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC) struct pei_data *pei_data; @@ -217,8 +215,6 @@ __attribute__((weak)) void mainboard_check_ec_image( __attribute__((weak)) void mainboard_romstage_entry( struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); - post_code(0x31); /* Initliaze memory */ @@ -360,14 +356,12 @@ __attribute__((weak)) void mainboard_add_dimm_info( struct memory_info *mem_info, int channel, int dimm, int index) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Get the memory configuration data */ __attribute__((weak)) int mrc_cache_get_current_with_version( const struct mrc_saved_data **cache, uint32_t version) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; } @@ -375,14 +369,12 @@ __attribute__((weak)) int mrc_cache_get_current_with_version( __attribute__((weak)) int mrc_cache_stash_data_with_version(const void *data, size_t size, uint32_t version) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; } /* Transition RAM from off or self-refresh to active */ __attribute__((weak)) void raminit(struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); post_code(0x34); die("ERROR - No RAM initialization specified!\n"); } @@ -397,13 +389,11 @@ void ramstage_cache_invalid(void) /* Display the memory configuration */ __attribute__((weak)) void report_memory_config(void) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* Choose top of stack and setup MTRRs */ __attribute__((weak)) void *setup_stack_and_mtrrs(void) { - printk(BIOS_ERR, "WEAK: %s/%s called\n", __FILE__, __func__); die("ERROR - Must specify top of stack!\n"); return NULL; } @@ -411,11 +401,9 @@ __attribute__((weak)) void *setup_stack_and_mtrrs(void) /* SOC initialization after RAM is enabled */ __attribute__((weak)) void soc_after_ram_init(struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); } /* SOC initialization before RAM is enabled */ __attribute__((weak)) void soc_pre_ram_init(struct romstage_params *params) { - printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); }

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New patch to review for coreboot: drivers/intel/fsp1_1: Update weak MRC cache routines
by Leroy P Leahy 01 Jun '16

01 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15042 -gerrit commit b098ccca03adc2708f32469bc1a2c8d374dbf169 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 31 18:12:53 2016 -0700 drivers/intel/fsp1_1: Update weak MRC cache routines Update the weak functions for the MRC cache. TEST=Build and run on Galileo Gen2 Change-Id: I54a1252cfff1a2f68b163f0feb65e2bceb37f6a9 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/drivers/intel/fsp1_1/romstage.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index c035f60..6584c55 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -364,15 +364,16 @@ __attribute__((weak)) void mainboard_add_dimm_info( } /* Get the memory configuration data */ -__attribute__((weak)) int mrc_cache_get_current( - const struct mrc_saved_data **cache) +__attribute__((weak)) int mrc_cache_get_current_with_version( + const struct mrc_saved_data **cache, uint32_t version) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1; } /* Save the memory configuration data */ -__attribute__((weak)) int mrc_cache_stash_data(const void *data, size_t size) +__attribute__((weak)) int mrc_cache_stash_data_with_version(const void *data, + size_t size, uint32_t version) { printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); return -1;

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coreboot-gerrit June 2016