coreboot-gerrit June 2016

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Patch set updated for coreboot: soc/apollolake: SOC specific c-state table
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051 -gerrit commit e9491165b77f9b554ae73308d7a30d32bce9c707 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: SOC specific c-state table Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/acpi.c | 36 ++++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 2 ++ 3 files changed, 39 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..52a00d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SOC_INTEL_COMMON select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_ACPI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4d610f8..fe5ebf0 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -26,6 +26,14 @@ #include <soc/pm.h> #include <soc/nvs.h> +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -157,3 +165,31 @@ void southbridge_inject_dsdt(device_t device) acpigen_pop_len(); } } +#define CSTATE_REG(address_space, bit_width, bit_offset, access_size, address) +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), + } +}; + +acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return(cstate_map); +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..a9edbbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void enable_dev(device_t dev)

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Patch set updated for coreboot: soc/common: Common code for generation of acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 9e9a90b7c367879b7b39ed6cd9ba14ca5a6f7971 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/common: Common code for generation of acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 10 ++ src/soc/intel/common/acpi/acpi.c | 291 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 306 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..3854b98 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,14 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI) +uint32_t cpu_get_bus_clock(void); +int cpu_get_coord_type(void); +int cpu_config_tdp_levels(void); +uint32_t cpu_get_min_ratio(void); +uint32_t cpu_get_max_ratio(void); +uint32_t cpu_get_power_unit(void); +acpi_cstate_t *get_cstate_map(int *entries); +acpi_tstate_t *get_soc_tss_table(int *entries); +#endif /* CONFIG_SOC_INTEL_COMMON_ACPI */ #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..2a5ea47 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return (0); +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return(CPU_BCLK); +} + +__attribute__((weak)) uint32_t cpu_get_power_unit(void) +{ + msr_t msr; + msr = rdmsr(MSR_RAPL_POWER_UNIT); + return(2 << (msr.lo & 0xf)); +} + +__attribute__((weak)) acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = 0; + return 0; +} + +__attribute__((weak)) acpi_tstate_t *get_soc_tss_table(int *entries) +{ + *entries = 0; + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return (int)power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_unit = cpu_get_power_unit(); + msr = rdmsr(MSR_PKG_POWER_INFO); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = get_soc_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package( + entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = get_acpi_base_address(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +} +

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Patch set updated for coreboot: soc/common: Common code for generation of acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 2204165fa17744a7ad5a73872c5061737fc9d131 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/common: Common code for generation of acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 8 ++ src/soc/intel/common/acpi/acpi.c | 291 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 304 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..80544d7 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,12 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +uint32_t cpu_get_bus_clock(void); +int cpu_get_coord_type(void); +int cpu_config_tdp_levels(void); +uint32_t cpu_get_min_ratio(void); +uint32_t cpu_get_max_ratio(void); +uint32_t cpu_get_power_unit(void); +acpi_cstate_t *get_cstate_map(int *entries); +acpi_tstate_t *get_soc_tss_table(int *entries); #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..2a5ea47 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return (0); +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return(CPU_BCLK); +} + +__attribute__((weak)) uint32_t cpu_get_power_unit(void) +{ + msr_t msr; + msr = rdmsr(MSR_RAPL_POWER_UNIT); + return(2 << (msr.lo & 0xf)); +} + +__attribute__((weak)) acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = 0; + return 0; +} + +__attribute__((weak)) acpi_tstate_t *get_soc_tss_table(int *entries) +{ + *entries = 0; + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return (int)power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_unit = cpu_get_power_unit(); + msr = rdmsr(MSR_PKG_POWER_INFO); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = get_soc_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package( + entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = get_acpi_base_address(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +} +

1 0

Patch set updated for coreboot: soc/common: Common code for generation of acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 9e8038e9ce792e4c96c8118b11137d64d56b61b3 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/common: Common code for generation of acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 7 + src/soc/intel/common/acpi/acpi.c | 291 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 303 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..becb9b6 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,11 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +uint32_t cpu_get_bus_clock(void); +int cpu_get_coord_type(void); +int cpu_config_tdp_levels(void); +uint32_t cpu_get_min_ratio(void); +uint32_t cpu_get_max_ratio(void); +uint32_t cpu_get_power_unit(void); +acpi_cstate_t *get_cstate_map(int *entries); #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..2a5ea47 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return (0); +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return(CPU_BCLK); +} + +__attribute__((weak)) uint32_t cpu_get_power_unit(void) +{ + msr_t msr; + msr = rdmsr(MSR_RAPL_POWER_UNIT); + return(2 << (msr.lo & 0xf)); +} + +__attribute__((weak)) acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = 0; + return 0; +} + +__attribute__((weak)) acpi_tstate_t *get_soc_tss_table(int *entries) +{ + *entries = 0; + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return (int)power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_unit = cpu_get_power_unit(); + msr = rdmsr(MSR_PKG_POWER_INFO); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = get_soc_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package( + entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = get_acpi_base_address(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +} +

1 0

New patch to review for coreboot: soc/apollolake: Add get_acpi_base_address
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15052 -gerrit commit f34ff85e8a07fdb71027d10c079f03534b16db67 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:45:22 2016 -0700 soc/apollolake: Add get_acpi_base_address Change-Id: If54e3821b9971f3d2cf59df0f9ae1b45af3bf314 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/pmutil.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6b12886..6c24b6c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -144,5 +144,6 @@ void disable_pm1_control(uint32_t mask); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t get_acpi_base_address(void); #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a04..b380738 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -336,3 +336,8 @@ int fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps->prev_sleep_state; } + +uint32_t get_acpi_base_address(void) +{ + return ACPI_PMIO_BASE; +}

1 0

New patch to review for coreboot: soc/apollolake: SOC specific c-state table
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051 -gerrit commit 1bc40c673516fb9ce6487643b22e8479d6b6f72a Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: SOC specific c-state table Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/acpi.c | 36 ++++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 2 ++ 3 files changed, 39 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..52a00d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SOC_INTEL_COMMON select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_ACPI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4d610f8..fe5ebf0 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -26,6 +26,14 @@ #include <soc/pm.h> #include <soc/nvs.h> +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -157,3 +165,31 @@ void southbridge_inject_dsdt(device_t device) acpigen_pop_len(); } } +#define CSTATE_REG(address_space, bit_width, bit_offset, access_size, address) +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), + } +}; + +acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return(cstate_map); +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..a9edbbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void enable_dev(device_t dev)

1 0

New patch to review for coreboot: soc/common: Common code for generation of acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 823417e5476b92cd4dddcf25ce4e7e3abfa61c05 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/common: Common code for generation of acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 7 + src/soc/intel/common/acpi/acpi.c | 291 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 303 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..becb9b6 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,11 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +uint32_t cpu_get_bus_clock(void); +int cpu_get_coord_type(void); +int cpu_config_tdp_levels(void); +uint32_t cpu_get_min_ratio(void); +uint32_t cpu_get_max_ratio(void); +uint32_t cpu_get_power_unit(void); +acpi_cstate_t *get_cstate_map(int *entries); #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..2a5ea47 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return (0); +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return(CPU_BCLK); +} + +__attribute__((weak)) uint32_t cpu_get_power_unit(void) +{ + msr_t msr; + msr = rdmsr(MSR_RAPL_POWER_UNIT); + return(2 << (msr.lo & 0xf)); +} + +__attribute__((weak)) acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = 0; + return 0; +} + +__attribute__((weak)) acpi_tstate_t *get_soc_tss_table(int *entries) +{ + *entries = 0; + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return (int)power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_unit = cpu_get_power_unit(); + msr = rdmsr(MSR_PKG_POWER_INFO); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = get_soc_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package( + entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = get_acpi_base_address(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +} +

1 0

Patch merged into coreboot/master: Documentation/Intel/Board: Add Galileo checklist
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 40b41bc7992632c696201e84192192e28f7fdfa6 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Mon May 30 17:09:09 2016 -0700 Documentation/Intel/Board: Add Galileo checklist Add the Galileo implementation checklist. TEST=None Change-Id: I47e87a496cf3ae125d45c09fe6a36200f5fe724f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15012 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15012 for details. -gerrit

1 0

Patch set updated for coreboot: Add Board Checklist Support
by Leroy P Leahy 02 Jun '16

02 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15011 -gerrit commit 8e318ec4d7fa8a32ce28f7e72264a7e1e232e30a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 26 17:12:17 2016 -0700 Add Board Checklist Support Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Makefile.inc | 197 +++++++++++++++++++++ src/Kconfig | 8 + src/drivers/intel/fsp1_1/Kconfig | 4 + .../fsp/fsp1_1/checklist/bootblock_complete.dat | 77 ++++++++ .../fsp/fsp1_1/checklist/ramstage_complete.dat | 53 ++++++ .../fsp/fsp1_1/checklist/ramstage_optional.dat | 46 +++++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 54 ++++++ .../fsp/fsp1_1/checklist/romstage_optional.dat | 34 ++++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 35 ++++ .../fsp/fsp1_1/checklist/verstage_optional.dat | 22 +++ 10 files changed, 530 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 19377c9..c9c1b12 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -563,6 +563,203 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug mv $@.tmp $@ ########################################################################### +# Build the board implementation checklist +########################################################################### + +# +# All symbols in the image +# +%.symbols: %.elf + $(NM_$(class)) $< | sed -r 's/^.{11}//' > $@ + +# +# Weak symbols in the image +# +%.weak: %.elf + $(NM_$(class)) $< | grep -F " W " | sed -r 's/^.{11}//' > $@ + +# +# Expected symbols in the image +# +%.expected: %.elf + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ "$(*F)" = "romstage" ]; then \ + if [ ! -e $(*D)/verstage.elf ]; then \ + if [ ! -e $(*D)/postcar.elf ]; then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat >> $@.tmp; \ + fi; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + uniq $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +# +# Optional symbols in the image +# +%.optional: %.elf + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ "$(*F)" = "romstage" ]; then \ + if [ ! -e $(*D)/verstage.elf ]; then \ + if [ ! -e $(*D)/postcar.elf ]; then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \ + fi; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + uniq $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +# +# Expected Symbols Optional Weak Done Type +# no yes no d/c yes Don't display +# yes no no no no Required - not implemented +# yes no yes no no Optional - not implemented +# yes yes yes yes no Optional - not implemented +# yes yes no no yes Required - implemented +# yes yes yes no yes Required - implemented +# +# Implemented routines are in the symbol table and are not weak +# +%.done: %.symbols %.expected %.weak %.optional + comm -12 $(*D)/$(*F).expected $(*D)/$(*F).symbols | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).weak | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +# +# Remove any routines that are implemented +# +%.optional2: %.optional %.done + comm -23 $^ | sed "s/^[ \t]*//" > $@ + +# +# Remove any implemented or optional routines +# +%.tbd: %.expected %.done %.optional2 + comm -23 $(*D)/$(*F).expected $(*D)/$(*F).done | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).optional2 | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +# +# Build the implementation table for each stage +# 1. Color code the rows +# * Done table rows are in green +# * Optional table rows are in yellow +# * TBD table rows are in red +# 2. Add the row termination +# 3. Sort the rows into alphabetical order +# +%.table_rows: %.optional2 %.done %.expected %.tbd + sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp + sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional2 >> $@.tmp + if [ -s $(*D)/$(basename $(*F)).tbd ]; then \ + sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).tbd >> $@.tmp; \ + fi + sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp + sort -t ">" -k4 $@.tmp > $@ + rm $@.tmp + +# +# Count the lines in the done file +# +done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') + +# +# Count the lines in the optional file +# +optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional2 | sed 's/ .*//') + +# +# Count the lines in the expected file +# +expected_lines = $$(wc -l $(*D)/$(basename $(*F)).expected | sed 's/ .*//') + +# Compute the percentage done by routine count +percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lines)))) + +# +# Build the table +# 1. Add the table header +# 2. Add the table rows +# 3. Add the table trailer +# +%.html: %.table_rows + echo "<table border=1>" > $@ + echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ + echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ + cat $< >> $@ + echo "</table>" >> $@ + echo "<br>" >> $@ + +# +# Determine which HTML files to include into the webpage +# +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +html_table_files += $(objcbfs)/verstage.html +endif +ifeq ($(CONFIG_POSTCAR_STAGE),y) +html_table_files += $(objcbfs)/postcar.html +endif +html_table_files += $(objcbfs)/romstage.html $(objcbfs)/ramstage.html + +# +# Create a list with each file on a separate line +# +list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) + +# +# Get the date for the webpage +# +current_date_time = $$(date +"%Y/%m/%d %T %Z") + +# +# Build the web page from the implementation tables +# 1. Add the header to the web page +# 2. Add the tables to the web page +# 3. Add the trailer to the web page +# +$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) + echo "<html>" > $@ + echo "<head>" >> $@ + echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ + echo "</title>" >> $@ + echo "<body>" >> $@ + echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status<br>$(current_date_time)</h1>" >> $@ + for table in $(list_of_html_files); do \ + cat $$table >> $@; \ + done + echo "</body>" >> $@ + echo "</html>" >> $@ + +# +# Copy the output file into the Documentation directory +# +Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ + fi + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ + fi + cp $< $@ + +# Only build the checklist for boards under development +ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) + +# +# Determine where to place the output file +# +ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) +INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +else +INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +endif + +endif + +########################################################################### # Build the final rom image ########################################################################### diff --git a/src/Kconfig b/src/Kconfig index f93c2cc..2b9a136 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1175,3 +1175,11 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + +config MAKE_CHECKLIST_PUBLIC + bool + default n diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..86f6c7b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" +config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat new file mode 100644 index 0000000..8a4325f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -0,0 +1,77 @@ +arch_segment_loaded +backup_top_of_ram +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +mrc_cache_get_current +mrc_cache_stash_data +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +raminit +ramstage_cache_invalid +report_memory_config +save_chromeos_gpios +setup_stack_and_mtrrs +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_ram_init +soc_after_silicon_init +soc_display_memory_init_params +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_memory_init_params +soc_pre_ram_init +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000..64f8584 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,53 @@ +acpi_create_serialio_ssdt +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000..6608583 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,46 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000..e6bef6c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,54 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_fill_spd_data +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +migrate_power_state +mrc_cache_get_current_with_version +mrc_cache_stash_data_with_version +platform_prog_run +platform_segment_loaded +print_fsp_info +raminit +ramstage_cache_invalid +report_memory_config +romstage_common +save_chromeos_gpios +set_max_freq +setup_stack_and_mtrrs +smm_region +smm_region_size +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000..2634566 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,34 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000..2124f0f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,35 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +gpio_acpi_path +init_timer +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000..f589eaa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,22 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init

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Patch set updated for coreboot: generic: Add a Maxim 98357A codec driver
by Duncan Laurie 02 Jun '16

02 Jun '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15017 -gerrit commit 3c884151df14909cbc01f0d54a37e7f526d75958 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 11:27:47 2016 -0700 generic: Add a Maxim 98357A codec driver The Maxim Integrated 98357A codec is an I2S slave device that has no control channel for configuration and instead provides a GPIO that is used for channel selection and power down. This means it does not fit into a bus hierarchy easily and is instead represented as a generic device and found with a static bus scan using the devicetree. This driver provides configuration options for passing the "sdmode" GPIO descriptor as well as a second option for "sdmode delay" which can configure the timing of the sdmode toggling in relation to the I2S channel output. In addition an GPIO can be provided to indicate to the driver whether this device is present or not. This can be used for board designs that may have different codec possibilities that are selected by HW strap. Sample usage for this device driver: device pci 1f.3 on chip drivers/generic/max98357a register "sdmode_gpio" = "ACPI_GPIO_OUTPUT(GPP_C6)" register "sdmode_delay" = "100" device generic 0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.HDAS) { Device (MAXM) { Name (_HID, "MX98357A") Name (_UID, Zero) Name (_DDN, "Maxim Integrated 98357A Amplifier") Method (_STA) { Return (0xF) } Name (_CRS, ResourceTemplate () { GpioIo (Exclusive, PullDefault, 0, 0, IoRestrictionOutputOnly, "\\_SB.PCI0.GPIO", 0, ResourceConsumer) }) Name (_DSD, Package () { ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), Package () { Package () { "maxim,sdmode-gpio", \_SB.PCI0.HDAS.MAXM, 0, 0, 0 } Package () { "maxim,sdmode-delay", 100 } Package () { "sdmode-delay", 100 } } }) } } Change-Id: Ia0bafe49bea9bbe4a3cc0f9f9cdb6f6390da57b5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/generic/max98357a/Kconfig | 2 + src/drivers/generic/max98357a/Makefile.inc | 1 + src/drivers/generic/max98357a/chip.h | 13 ++++ src/drivers/generic/max98357a/max98357a.c | 109 +++++++++++++++++++++++++++++ 4 files changed, 125 insertions(+) diff --git a/src/drivers/generic/max98357a/Kconfig b/src/drivers/generic/max98357a/Kconfig new file mode 100644 index 0000000..a7104f1 --- /dev/null +++ b/src/drivers/generic/max98357a/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_GENERIC_MAX98357A + bool diff --git a/src/drivers/generic/max98357a/Makefile.inc b/src/drivers/generic/max98357a/Makefile.inc new file mode 100644 index 0000000..529e24a --- /dev/null +++ b/src/drivers/generic/max98357a/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_GENERIC_MAX98357A) += max98357a.c diff --git a/src/drivers/generic/max98357a/chip.h b/src/drivers/generic/max98357a/chip.h new file mode 100644 index 0000000..0abd616 --- /dev/null +++ b/src/drivers/generic/max98357a/chip.h @@ -0,0 +1,13 @@ +#include <arch/acpi_device.h> + +struct drivers_generic_max98357a_config { + /* SDMODE GPIO */ + struct acpi_gpio sdmode_gpio; + + /* SDMODE Delay */ + unsigned sdmode_delay; + + /* GPIO used to indicate if this device is present */ + unsigned device_present_gpio; + unsigned device_present_gpio_invert; +}; diff --git a/src/drivers/generic/max98357a/max98357a.c b/src/drivers/generic/max98357a/max98357a.c new file mode 100644 index 0000000..cbd7efd --- /dev/null +++ b/src/drivers/generic/max98357a/max98357a.c @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/device.h> +#include <device/path.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define MAX98357A_ACPI_NAME "MAXM" +#define MAX98357A_ACPI_HID "MX98357A" + +static void max98357a_fill_ssdt(struct device *dev) +{ + struct drivers_generic_max98357a_config *config = dev->chip_info; + const char *path = acpi_device_path(dev); + + if (!dev->enabled || !path || !config) + return; + + /* Device */ + acpigen_write_scope(acpi_device_scope(dev)); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", MAX98357A_ACPI_HID); + acpigen_write_name_integer("_UID", 0); + acpigen_write_name_string("_DDN", dev->chip_ops->name); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_gpio(&config->sdmode_gpio); + acpigen_write_resourcetemplate_footer(); + + /* _DSD for devicetree properties */ + acpi_dp_write_header(); + /* This points to the first pin in the first gpio entry in _CRS */ + acpi_dp_write_gpio("maxim,sdmode-gpio", path, 0, 0, 0); + /* This is the correctly formatted Device Property name */ + acpi_dp_write_integer("maxim,sdmode-delay", config->sdmode_delay); + /* This is used by the chromium kernel but is not upstream */ + acpi_dp_write_integer("sdmode-delay", config->sdmode_delay); + acpi_dp_write_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s\n", path, dev->chip_ops->name); +} + +static const char *max98357a_acpi_name(struct device *dev) +{ + return MAX98357A_ACPI_NAME; +} +#endif + +static struct device_operations max98357a_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &max98357a_acpi_name, + .acpi_fill_ssdt_generator = &max98357a_fill_ssdt, +#endif +}; + +static void max98357a_enable(struct device *dev) +{ + struct drivers_generic_max98357a_config *config = dev->chip_info; + + /* Check if device is present by reading GPIO */ + if (config->device_present_gpio) { + int present = gpio_get(config->device_present_gpio); + present ^= config->device_present_gpio_invert; + + printk(BIOS_INFO, "%s is %spresent\n", + dev->chip_ops->name, present ? "" : "not "); + + if (!present) { + dev->enabled = 0; + return; + } + } + + dev->ops = &max98357a_ops; +} + +struct chip_operations drivers_generic_max98357a_ops = { + CHIP_NAME("Maxim Integrated 98357A Amplifier") + .enable_dev = &max98357a_enable +};

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coreboot-gerrit June 2016