coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/common: Common code for generation of acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 95ac0057fdd07014beeb8ea4334e6411a77c083f Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/common: Common code for generation of acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 10 ++ src/soc/intel/common/acpi/acpi.c | 291 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 306 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..3854b98 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,14 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI) +uint32_t cpu_get_bus_clock(void); +int cpu_get_coord_type(void); +int cpu_config_tdp_levels(void); +uint32_t cpu_get_min_ratio(void); +uint32_t cpu_get_max_ratio(void); +uint32_t cpu_get_power_unit(void); +acpi_cstate_t *get_cstate_map(int *entries); +acpi_tstate_t *get_soc_tss_table(int *entries); +#endif /* CONFIG_SOC_INTEL_COMMON_ACPI */ #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..2a5ea47 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return (0); +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return(CPU_BCLK); +} + +__attribute__((weak)) uint32_t cpu_get_power_unit(void) +{ + msr_t msr; + msr = rdmsr(MSR_RAPL_POWER_UNIT); + return(2 << (msr.lo & 0xf)); +} + +__attribute__((weak)) acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = 0; + return 0; +} + +__attribute__((weak)) acpi_tstate_t *get_soc_tss_table(int *entries) +{ + *entries = 0; + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return (int)power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_unit = cpu_get_power_unit(); + msr = rdmsr(MSR_PKG_POWER_INFO); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = get_soc_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package( + entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = get_acpi_base_address(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +} +

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Patch set updated for coreboot: Add Board Checklist Support
by Leroy P Leahy 02 Jun '16

02 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15011 -gerrit commit 12f26f49ae044a1cb9715aa62a0e87133d76284e Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 26 17:12:17 2016 -0700 Add Board Checklist Support Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Makefile.inc | 1 + src/Kconfig | 30 +++ src/drivers/intel/fsp1_1/Kconfig | 4 + .../fsp/fsp1_1/checklist/bootblock_complete.dat | 77 ++++++ .../fsp/fsp1_1/checklist/ramstage_complete.dat | 53 +++++ .../fsp/fsp1_1/checklist/ramstage_optional.dat | 46 ++++ .../fsp/fsp1_1/checklist/romstage_complete.dat | 54 +++++ .../fsp/fsp1_1/checklist/romstage_optional.dat | 34 +++ .../fsp/fsp1_1/checklist/verstage_complete.dat | 35 +++ .../fsp/fsp1_1/checklist/verstage_optional.dat | 22 ++ util/checklist/Makefile.inc | 260 +++++++++++++++++++++ 11 files changed, 616 insertions(+) diff --git a/Makefile.inc b/Makefile.inc index 19377c9..d1d09ab 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -85,6 +85,7 @@ subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += payloads payloads/external subdirs-y += site-local +subdirs-y += util/checklist ####################################################################### # Add source classes and their build options diff --git a/src/Kconfig b/src/Kconfig index 6e6e944..4eda537 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1174,3 +1174,33 @@ config DEBUG_BOOT_STATE help Control debugging of the boot state machine. When selected displays the state boundaries in ramstage. + +config CREATE_BOARD_CHECKLIST + bool + default n + help + When selected, creates a webpage showing the implementation status for + the board. Routines highlighted in green are complete, yellow are + optional and red are required and must be implemented. A table is + produced for each stage of the boot process except the bootblock. The + red items may be used as an implementation checklist for the board. + +config MAKE_CHECKLIST_PUBLIC + bool + default n + help + When selected, build/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + is copied into the Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board + directory. + +config CHECKLIST_DATA_FILE_LOCATION + string + help + Location of the <stage>_complete.dat and <stage>_optional.dat files + that are consumed during checklist processing. <stage>_complete.dat + contains the symbols that are expected to be in the resulting image. + <stage>_optional.dat is a subset of <stage>_complete.dat and contains + a list of weak symbols which the resulting image may consume. Other + symbols contained only in <stage>_complete.dat will be flagged as + required and not implemented if a weak implementation is found in the + resulting image. diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index 9b2c463..86f6c7b 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,8 @@ config VBT_FILE depends on GOP_SUPPORT default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/vbt.bin" +config CHECKLIST_DATA_FILE_LOCATION + string + default "src/vendorcode/intel/fsp/fsp1_1/checklist" + endif #PLATFORM_USES_FSP1_1 diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat new file mode 100644 index 0000000..8a4325f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/bootblock_complete.dat @@ -0,0 +1,77 @@ +arch_segment_loaded +backup_top_of_ram +bootblock_mainboard_early_init +bootblock_mainboard_init +bootblock_soc_early_init +bootblock_soc_init +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +mrc_cache_get_current +mrc_cache_stash_data +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +raminit +ramstage_cache_invalid +report_memory_config +save_chromeos_gpios +setup_stack_and_mtrrs +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_ram_init +soc_after_silicon_init +soc_display_memory_init_params +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_memory_init_params +soc_pre_ram_init +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat new file mode 100644 index 0000000..64f8584 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_complete.dat @@ -0,0 +1,53 @@ +acpi_create_serialio_ssdt +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_fill_acpi_wake +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +timestamp_tick_freq_mhz +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat new file mode 100644 index 0000000..6608583 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/ramstage_optional.dat @@ -0,0 +1,46 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fw_cfg_acpi_tables +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +lb_board +lb_framebuffer +mainboard_add_dimm_info +mainboard_io_trap_handler +mainboard_post +mainboard_silicon_init_params +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +mainboard_suspend_resume +map_oprom_vendev +mirror_payload +northbridge_smi_handler +nvm_mmio_to_flash_offset +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +smbios_mainboard_bios_version +smbios_mainboard_manufacturer +smbios_mainboard_product_name +smbios_mainboard_serial_number +smbios_mainboard_set_uuid +smbios_mainboard_version +smm_disable_busmaster +soc_after_silicon_init +soc_display_silicon_init_params +soc_silicon_init_params +soc_skip_ucode_update +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +wifi_regulatory_domain +write_smp_table diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat new file mode 100644 index 0000000..e6bef6c --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_complete.dat @@ -0,0 +1,54 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +fill_power_state +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +init_timer +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_fill_spd_data +mainboard_io_trap_handler +mainboard_memory_init_params +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +migrate_power_state +mrc_cache_get_current_with_version +mrc_cache_stash_data_with_version +platform_prog_run +platform_segment_loaded +print_fsp_info +raminit +ramstage_cache_invalid +report_memory_config +romstage_common +save_chromeos_gpios +set_max_freq +setup_stack_and_mtrrs +smm_region +smm_region_size +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat new file mode 100644 index 0000000..2634566 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/romstage_optional.dat @@ -0,0 +1,34 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +get_top_of_ram +gpio_acpi_path +mainboard_add_dimm_info +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_romstage_entry +mainboard_save_dimm_info +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_after_ram_init +soc_display_memory_init_params +soc_display_mtrrs +soc_get_variable_mtrr_count +soc_memory_init_params +soc_pre_ram_init +southbridge_smi_handler +stage_cache_add +stage_cache_load_stage +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat new file mode 100644 index 0000000..2124f0f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_complete.dat @@ -0,0 +1,35 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +cbfs_master_header_locator +cbmem_fail_resume +clear_recovery_mode_switch +cpu_smi_handler +get_sw_write_protect_state +gpio_acpi_path +init_timer +mainboard_check_ec_image +mainboard_io_trap_handler +mainboard_post +mainboard_smi_apmc +mainboard_smi_gpi +mainboard_smi_sleep +map_oprom_vendev +platform_prog_run +platform_segment_loaded +save_chromeos_gpios +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init diff --git a/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat new file mode 100644 index 0000000..f589eaa --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp1_1/checklist/verstage_optional.dat @@ -0,0 +1,22 @@ +arch_segment_loaded +backup_top_of_ram +boot_device_init +car_mainboard_post_console_init +car_mainboard_pre_console_init +car_soc_post_console_init +car_soc_pre_console_init +mainboard_check_ec_image +mainboard_post +platform_prog_run +platform_segment_loaded +soc_display_mtrrs +soc_get_variable_mtrr_count +stage_cache_add +stage_cache_load_stage +timestamp_get +tsc_freq_mhz +vb2ex_hwcrypto_digest_extend +vb2ex_hwcrypto_digest_finalize +vb2ex_hwcrypto_digest_init +vboot_platform_prepare_reboot +verstage_mainboard_init diff --git a/util/checklist/Makefile.inc b/util/checklist/Makefile.inc new file mode 100644 index 0000000..f8e5ebd --- /dev/null +++ b/util/checklist/Makefile.inc @@ -0,0 +1,260 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +########################################################################### +# Build the board implementation checklist +########################################################################### + +# Only build the checklist for boards under development +ifeq ($(CONFIG_CREATE_BOARD_CHECKLIST),y) + +# +# Extract the symbol table from the image +# +%.symbol_table: %.elf %.debug + $(NM_$(class)) $< > $@ + $(NM_$(class)) $(*D)/$(*F).debug >> $@ + +# +# All symbols in the image +# +# 1. Remove the address and symbol type +# 2. Sort the table into alphabetical order +# 3. Remove any duplicates +# +%.symbols: %.symbol_table + sed 's/^...........//' $< > $@.tmp + sort $@.tmp > $@.tmp2 + uniq $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +# +# Weak symbols in the image +# +# 1. Find the weak symbols +# 2. Remove the address and symbol type +# 3. Sort the table into alphabetical order +# 4. Remove any duplicates +# +%.weak: %.symbol_table + grep -F " W " $< | sed 's/^...........//' > $@.tmp + sort $@.tmp > $@.tmp2 + uniq $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +# +# Expected symbols in the image +# +# 1. Get the complete list of expected symbols in the image +# 2. Sort the table into alphabetical order +# 3. Remove any duplicates +# +%.expected: %.symbol_table + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_complete.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ "$(*F)" = "romstage" ]; then \ + if [ ! -e $(*D)/verstage.elf ]; then \ + if [ ! -e $(*D)/postcar.elf ]; then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_complete.dat >> $@.tmp; \ + fi; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + uniq $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +# +# Optional symbols in the image +# +# 1. Get the list of optional symbols in the image +# 2. Sort the table into alphabetical order +# 3. Remove any duplicates +# +%.optional: %.symbol_table + cp $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/$(basename $(*F))_optional.dat $@.tmp + # If no separate verstage, combine verstage and romstage routines into a single list + if [ "$(*F)" = "romstage" ]; then \ + if [ ! -e $(*D)/verstage.elf ]; then \ + if [ ! -e $(*D)/postcar.elf ]; then \ + cat $(CONFIG_CHECKLIST_DATA_FILE_LOCATION)/verstage_optional.dat >> $@.tmp; \ + fi; \ + fi; \ + fi + sort $@.tmp > $@.tmp2 + uniq $@.tmp2 > $@ + rm $@.tmp $@.tmp2 + +# +# Expected Symbols Optional Weak Done Type +# no yes no d/c yes Don't display +# yes no no no no Required - not implemented +# yes no yes no no Optional - not implemented +# yes yes yes yes no Optional - not implemented +# yes yes no no yes Required - implemented +# yes yes yes no yes Required - implemented +# +# Implemented routines are in the symbol table and are not weak +# +# 1. Remove expected symbols which are not in the image (not implemented yet) +# 2. Remove weak symbols from the list (not implemented yet) +# +%.done: %.symbols %.expected %.weak %.optional + comm -12 $(*D)/$(*F).expected $(*D)/$(*F).symbols | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).weak | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +# +# Remove any routines that are implemented +# +%.optional2: %.optional %.done + comm -23 $^ | sed "s/^[ \t]*//" > $@ + +# +# Remove any implemented or optional routines +# +%.tbd: %.expected %.done %.optional2 + comm -23 $(*D)/$(*F).expected $(*D)/$(*F).done | sed "s/^[ \t]*//" > $@.tmp + comm -23 $@.tmp $(*D)/$(*F).optional2 | sed "s/^[ \t]*//" > $@ + rm $@.tmp + +# +# Build the implementation table for each stage +# 1. Color code the rows +# * Done table rows are in green +# * Optional table rows are in yellow +# * TBD table rows are in red +# 2. Add the row termination +# 3. Sort the rows into alphabetical order +# +%.table_rows: %.optional2 %.done %.expected %.tbd + sed -e 's/^/<tr bgcolor=#c0ffc0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).done > $@.tmp + sed -e 's/^/<tr bgcolor=#ffffc0><td>Optional<\/td><td>/' $(*D)/$(basename $(*F)).optional2 >> $@.tmp + if [ -s $(*D)/$(basename $(*F)).tbd ]; then \ + sed -e 's/^/<tr bgcolor=#ffc0c0><td>Required<\/td><td>/' $(*D)/$(basename $(*F)).tbd >> $@.tmp; \ + fi + sed -e 's/$$/<\/td><\/tr>/' -i $@.tmp + sort -t ">" -k4 $@.tmp > $@ + rm $@.tmp + +# +# Count the lines in the done file +# +done_lines = $$(wc -l $(*D)/$(basename $(*F)).done | sed 's/ .*//') + +# +# Count the lines in the optional file +# +optional_lines = $$(wc -l $(*D)/$(basename $(*F)).optional2 | sed 's/ .*//') + +# +# Count the lines in the expected file +# +expected_lines = $$(wc -l $(*D)/$(basename $(*F)).expected | sed 's/ .*//') + +# Compute the percentage done by routine count +percent_complete = $$(($(done_lines) * 100 / ($(expected_lines) - $(optional_lines)))) + +# +# Build the table +# 1. Add the table header +# 2. Add the table rows +# 3. Add the table trailer +# +%.html: %.table_rows + echo "<table border=1>" > $@ + echo "<tr><th colspan=2>$(basename $(*F)): $(percent_complete)% Done</th></tr>" >> $@ + echo "<tr><th>Type</th><th>Routine</td></tr>" >> $@ + cat $< >> $@ + echo "</table>" >> $@ + +# +# Determine which HTML files to include into the webpage +# +ifeq ($(CONFIG_SEPARATE_VERSTAGE),y) +html_table_files += $(objcbfs)/verstage.html +endif +ifeq ($(CONFIG_POSTCAR_STAGE),y) +html_table_files += $(objcbfs)/postcar.html +endif +html_table_files += $(objcbfs)/romstage.html $(objcbfs)/ramstage.html + +# +# Create a list with each file on a separate line +# +list_of_html_files = $(subst _NEWLINE_,${\n},${html_table_files}) + +# +# Get the date for the webpage +# +current_date_time = $$(date +"%Y/%m/%d %T %Z") + +# +# Build the webpage from the implementation tables +# 1. Add the header to the webpage +# 2. Add the legend to the webpage +# 3. Use a table to place stage tables side-by-side +# 4. Add the stage tables to the webpage +# 5. Separate the stage tables +# 6. Terminate the outer table +# 7. Add the trailer to the webpage +# +$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(html_table_files) + echo "<html>" > $@ + echo "<head>" >> $@ + echo "<title>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status</title>" >> $@ + echo "</title>" >> $@ + echo "<body>" >> $@ + echo "<h1>$(CONFIG_MAINBOARD_PART_NUMBER) Implementation Status<br>$(current_date_time)</h1>" >> $@ + echo "<table>" >> $@ + echo " <tr><td colspan=2><b>Legend</b></td></tr>" >> $@ + echo " <tr><td bgcolor=\"#ffc0c0\">Red</td><td>Required - To-be-implemented</td></tr>" >> $@ + echo " <tr><td bgcolor=\"#ffffc0\">Yellow</td><td>Optional</td></tr>" >> $@ + echo " <tr><td bgcolor=\"#c0ffc0\">Green</td><td>Implemented</td></tr>" >> $@ + echo "</table>" >> $@ + echo "<table>" >> $@ + echo " <tr valign=\"top\">" >> $@ + for table in $(list_of_html_files); do \ + echo " <td>" >> $@; \ + cat $$table >> $@; \ + echo " </td>" >> $@; \ + echo " <td width=5> </td>" >> $@; \ + done + echo " </tr>" >> $@ + echo "</table>" >> $@ + echo "</body>" >> $@ + echo "</html>" >> $@ + +# +# Copy the output file into the Documentation directory +# +Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html: $(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR) ]; then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR); \ + fi + if [ ! -d Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board ]; then \ + mkdir Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board; \ + fi + cp $< $@ + +# +# Determine where to place the output file +# +ifeq ($(CONFIG_MAKE_CHECKLIST_PUBLIC),y) +INTERMEDIATE+=Documentation/$(CONFIG_MAINBOARD_VENDOR)/Board/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +else +INTERMEDIATE+=$(obj)/$(CONFIG_MAINBOARD_PART_NUMBER)_checklist.html +endif + +endif

1 0

Patch set updated for coreboot: soc/intel/common: Add common code for acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 33a0b0efb74c5b4cb9049b1362a4be36c1d671be Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/intel/common: Add common code for acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 10 ++ src/soc/intel/common/acpi/acpi.c | 291 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 306 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..3854b98 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,14 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI) +uint32_t cpu_get_bus_clock(void); +int cpu_get_coord_type(void); +int cpu_config_tdp_levels(void); +uint32_t cpu_get_min_ratio(void); +uint32_t cpu_get_max_ratio(void); +uint32_t cpu_get_power_unit(void); +acpi_cstate_t *get_cstate_map(int *entries); +acpi_tstate_t *get_soc_tss_table(int *entries); +#endif /* CONFIG_SOC_INTEL_COMMON_ACPI */ #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..2a5ea47 --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,291 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return (0); +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return(CPU_BCLK); +} + +__attribute__((weak)) uint32_t cpu_get_power_unit(void) +{ + msr_t msr; + msr = rdmsr(MSR_RAPL_POWER_UNIT); + return(2 << (msr.lo & 0xf)); +} + +__attribute__((weak)) acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = 0; + return 0; +} + +__attribute__((weak)) acpi_tstate_t *get_soc_tss_table(int *entries) +{ + *entries = 0; + return 0; +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return (int)power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_unit = cpu_get_power_unit(); + msr = rdmsr(MSR_PKG_POWER_INFO); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = get_soc_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package( + entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = get_acpi_base_address(), plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores/cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +} +

1 0

New patch to review for coreboot: intelmetool: Add the X99 ISA Bridge device id
by Omar Pakker 02 Jun '16

02 Jun '16

Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15053 -gerrit commit 29cfdfed2681bd305ab4f7ab335a0904db76f8e2 Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Thu Jun 2 21:06:54 2016 +0200 intelmetool: Add the X99 ISA Bridge device id This adds the ISA bridge device id for the Intel C160/X99 series chipset to the intelmetool. Change-Id: I2e7db0fe1692985ebb167b9a44ab412a45a9f3bd Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> --- util/intelmetool/intelmetool.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 22cff1a..4b9803b 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -114,6 +114,7 @@ extern int debug; #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 +#define PCI_DEVICE_ID_INTEL_X99 0x8d47 #define PCI_DEV_HAS_ME_DIFFICULT(x) ( \ ( (x) == PCI_DEVICE_ID_INTEL_ICH10R ) || \ @@ -168,7 +169,8 @@ extern int debug; ( (x) == PCI_DEVICE_ID_INTEL_DH89XXCC ) || \ ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL ) || \ ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM ) || \ - ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE )) + ((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE) || \ + ((x) == PCI_DEVICE_ID_INTEL_X99)) // Not sure if ME present, but should be able to disable it easily #define PCI_DEVICE_ID_INTEL_ICH8 0x2810

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Patch set updated for coreboot: soc/intel/common: Add _OSC method
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15021 -gerrit commit 608454d074c4ec27a344a1e200566755a68aed9c Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 18 13:45:20 2016 -0700 soc/intel/common: Add _OSC method Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/acpi/osc.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/soc/intel/common/acpi/osc.asl b/src/soc/intel/common/acpi/osc.asl new file mode 100644 index 0000000..bdc8ed3 --- /dev/null +++ b/src/soc/intel/common/acpi/osc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" + +Scope (\_SB.PCI0) { + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) { + i /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +}

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Patch set updated for coreboot: mainboard/intel/galileo: Set board version
by Leroy P Leahy 02 Jun '16

02 Jun '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15041 -gerrit commit a5597e9be1902cef74b9e3329fa20f6c83d2dbec Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 31 08:32:21 2016 -0700 mainboard/intel/galileo: Set board version Return the correct board version in SMBIOS. TEST=Build and run on Galileo Gen2 Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/mainboard.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/src/mainboard/intel/galileo/mainboard.c b/src/mainboard/intel/galileo/mainboard.c new file mode 100644 index 0000000..2a8ade7 --- /dev/null +++ b/src/mainboard/intel/galileo/mainboard.c @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <smbios.h> + +/* Set the board version */ +const char *smbios_mainboard_version(void) +{ + if (IS_ENABLED(CONFIG_GALILEO_GEN2)) + return "Gen 2"; + return "1.0"; +}

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Patch merged into coreboot/master: intel/apollolake: Add car.c to verstage
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit b54a2d1d76549fc6dfacb880439d8785a50a589f Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:55:43 2016 -0700 intel/apollolake: Add car.c to verstage Verstage on apollolake requires the functions defined in car.c to perform flush of l1d to l2 on loading romstage into CAR. Change-Id: I6d9a0b9dfb58c2126ad70172846e90663e588857 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15046 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15046 for details. -gerrit

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Patch merged into coreboot/master: cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit d5583a5e61c4dbb870ceddc13fbee49b0d46d52f Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 01:53:18 2016 -0700 cbfs: Use NO_XIP_EARLY_STAGES to decide if stage is XIP Modern platforms like Apollolake do not use XIP for early stages. In such cases, cbfs_prog_stage_load should check for NO_XIP_EARLY_STAGES instead of relying on ARCH_X86 to decide if a stage is XIP. Change-Id: I1729ce82b5f678ce8c37256090fcf353cc22b1ec Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15045 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15045 for details. -gerrit

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Patch merged into coreboot/master: google/reef: Select UART_FOR_CONSOLE for reef
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit ab90f96ba58eefb8526270e66b45b26fbf10b09a Author: Furquan Shaikh <furquan(a)google.com> Date: Tue May 31 23:38:26 2016 -0700 google/reef: Select UART_FOR_CONSOLE for reef Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15044 for details. -gerrit

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Patch merged into coreboot/master: lenovo/t420: correct the eSATA port
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 0bca3c914e2a336672988ab7d9f1b3d41f36b8a6 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Fri May 6 23:05:28 2016 +0800 lenovo/t420: correct the eSATA port The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU model and a dGPU model. Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/14632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr(a)das-labor.org> See https://review.coreboot.org/14632 for details. -gerrit

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coreboot-gerrit June 2016