coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: nb/intel/x4x: Fix unpopulated value
by Damien Zammit 02 Jun '16

02 Jun '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15058 -gerrit commit ab849af6e16ab5bfb43ff7e80c99c0563dbe2931 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jun 3 15:39:30 2016 +1000 nb/intel/x4x: Fix unpopulated value Previously, 0x0 was the value being used for an unpopulated dimm on spd[62], however some DDR2 dimms have 0x0 as a valid value. Now use 0xff which is an unused value even on DDR2/DDR3. Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/intel/x4x/raminit.c | 4 ++-- src/northbridge/intel/x4x/raminit_ddr2.c | 4 ++-- src/northbridge/intel/x4x/x4x.h | 19 ++++++++++--------- 3 files changed, 14 insertions(+), 13 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 6efdcd3..4f5575c 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -41,14 +41,14 @@ static void sdram_read_spds(struct sysinfo *s) FOR_EACH_DIMM(i) { if (s->spd_map[i] == 0) { /* Non-existent SPD address */ - s->dimms[i].card_type = 0; + s->dimms[i].card_type = RAW_CARD_UNPOPULATED; continue; } for (j = 0; j < 64; j++) { status = spd_read_byte(s->spd_map[i], j); if (status < 0) { /* No SPD here */ - s->dimms[i].card_type = 0; + s->dimms[i].card_type = RAW_CARD_UNPOPULATED; break; } s->dimms[i].spd_data[j] = (u8) status; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index 3dd00fb..5acb127 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -1506,7 +1506,7 @@ static void dradrb_ddr2(struct sysinfo *s) rankpop0 = 0; rankpop1 = 0; FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { + if (((s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < s->dimms[ch<<1].ranks))) { i = ch << 1; } else { i = (ch << 1) + 1; @@ -1541,7 +1541,7 @@ static void dradrb_ddr2(struct sysinfo *s) // DRB FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { - if ((s->dimms[ch<<1].card_type && ((r) < s->dimms[ch<<1].ranks))) { + if (((s->dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < s->dimms[ch<<1].ranks))) { i = ch << 1; } else { i = (ch << 1) + 1; diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 17810aa..e02ee02 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -144,9 +144,10 @@ #define TOTAL_CHANNELS 2 #define TOTAL_DIMMS 4 +#define RAW_CARD_UNPOPULATED 0xff -#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != 0) -#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != 0) +#define DIMM_IS_POPULATED(dimms, idx) (dimms[idx].card_type != RAW_CARD_UNPOPULATED) +#define IF_DIMM_POPULATED(dimms, idx) if (dimms[idx].card_type != RAW_CARD_UNPOPULATED) #define ONLY_DIMMA_IS_POPULATED(dimms, ch) ( \ (DIMM_IS_POPULATED(dimms, (ch == 0) ? 0 : 2) && \ !DIMM_IS_POPULATED(dimms, (ch == 0) ? 1 : 3))) @@ -160,9 +161,9 @@ for (idx = 0; idx < TOTAL_DIMMS; ++idx) #define FOR_EACH_POPULATED_DIMM(dimms, idx) \ FOR_EACH_DIMM(idx) IF_DIMM_POPULATED(dimms, idx) -#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define CHANNEL_IS_POPULATED(dimms, idx) ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) #define CHANNEL_IS_CARDF(dimms, idx) ((dimms[idx<<1].card_type == 0xf) || (dimms[(idx<<1) + 1].card_type == 0xf)) -#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != 0) || (dimms[(idx<<1) + 1].card_type != 0)) +#define IF_CHANNEL_POPULATED(dimms, idx) if ((dimms[idx<<1].card_type != RAW_CARD_UNPOPULATED) || (dimms[(idx<<1) + 1].card_type != RAW_CARD_UNPOPULATED)) #define FOR_EACH_CHANNEL(idx) \ for (idx = 0; idx < TOTAL_CHANNELS; ++idx) #define FOR_EACH_POPULATED_CHANNEL(dimms, idx) \ @@ -170,11 +171,11 @@ #define RANKS_PER_CHANNEL 4 #define RANK_IS_POPULATED(dimms, ch, r) \ - ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ - (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) + (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ + ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) #define IF_RANK_POPULATED(dimms, ch, r) \ - if ((dimms[ch<<1].card_type && ((r) < dimms[ch<<1].ranks)) || \ - (dimms[(ch<<1) + 1].card_type && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) + if (((dimms[ch<<1].card_type != RAW_CARD_UNPOPULATED) && ((r) < dimms[ch<<1].ranks)) || \ + ((dimms[(ch<<1) + 1].card_type != RAW_CARD_UNPOPULATED) && ((r) >= 2) && ((r) < (dimms[(ch<<1) + 1].ranks + 2)))) #define FOR_EACH_RANK_IN_CHANNEL(r) \ for (r = 0; r < RANKS_PER_CHANNEL; ++r) #define FOR_EACH_POPULATED_RANK_IN_CHANNEL(dimms, ch, r) \ @@ -243,7 +244,7 @@ struct timings { }; struct dimminfo { - unsigned int card_type; /* 0x0: unpopulated, + unsigned int card_type; /* 0xff: unpopulated, 0xa - 0xf: raw card type A - F */ enum chip_width width; enum chip_cap chip_capacity;

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Patch merged into coreboot/master: AGESA boards: Drop unused include
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 3fa4350d6ae358826f12f40f55d917bf85ba7efd Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 27 08:37:18 2016 +0300 AGESA boards: Drop unused include These files do not use definitions from OptionsIds.h. Also those definitions are required and already included for Ids.h. Change-Id: I149fcfe2ad72fe3d7390ee2043a86432aeae3f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14980 for details. -gerrit

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Patch merged into coreboot/master: intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init()
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 44bb9bdec86d2f0118fc6c1e8d6d0443cf81d235 Author: Ben Gardner <gardner.ben(a)gmail.com> Date: Wed Jun 1 09:25:28 2016 -0500 intel/fsp_baytrail/i2c: mask i2c interrupts in i2c_init() i2c_init() leaves the I2C device enabled. Combined with the default interrupt mask (0x8ff) and the fact that the interrupt line is shared, this leads to an interrupt storm in the OS until a proper I2C driver is loaded. This change clears the interrupt mask to prevent the interrupt storm. Change-Id: I0424a00753d06e26639750f065a7a08a710bfaba Signed-off-by: Ben Gardner <gardner.ben(a)gmail.com> Reviewed-on: https://review.coreboot.org/15047 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com> See https://review.coreboot.org/15047 for details. -gerrit

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Patch merged into coreboot/master: intel/apollolake: Clear TSEG reg early in bootblock
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit e3a692d7daf16d53764a4b0e30531491d4ae24bd Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Jun 1 15:09:21 2016 -0700 intel/apollolake: Clear TSEG reg early in bootblock TSEG register comes out of reset with a non-zero default value. This causes issues when cbmem_top returns non-zero value based on TSEG read before DRAM is initialized. Thus, clear TSEG reg early in bootblock to avoid unwanted side-effects. Change-Id: Id3c6c270774108e4caf56e2a07c5072edc65bb58 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/15049 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/15049 for details. -gerrit

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New patch to review for coreboot: board/amenia: Enable LPSS IOSF PMCTL S0ix
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15056 -gerrit commit d3c1b6abf6890d5fd44717d51bd5e8aed5bf415e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Jun 2 15:00:36 2016 -0700 board/amenia: Enable LPSS IOSF PMCTL S0ix Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 38a2de2..77ae0bf 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # LPSS IOSF PMCTL S0ix Enable + register "S0ixEnable" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF

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New patch to review for coreboot: soc/apollolake: Enable LPSS IOSF PMCTL S0ix
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055 -gerrit commit 95561bbab7a9534824e481a5eb6e7a25acdbf5a5 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Tue May 3 15:15:31 2016 -0700 soc/apollolake: Enable LPSS IOSF PMCTL S0ix Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 ++ src/soc/intel/apollolake/chip.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..6df3c4b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -108,6 +108,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) cfg = dev->chip_info; + silconfig->S0ixEnable = cfg->S0ixEnable; + silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin; silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin; silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin; diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index d74084e..1a30eb0 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -42,6 +42,9 @@ struct soc_intel_apollolake_config { /* Configure serial IRQ (SERIRQ) line. */ enum serirq_mode serirq_mode; + + /* Configure LPSS IOSF PMCTL S0ix Enable */ + uint8_t S0ixEnable; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */

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New patch to review for coreboot: soc/apollolake: Put CSE to low power state
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15054 -gerrit commit a1dec0d0cddc85a97af91fb1638bdb452fabe8f1 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Apr 29 14:48:20 2016 -0700 soc/apollolake: Put CSE to low power state fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE in low power state Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/chip.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..4fb1084 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -136,6 +136,10 @@ static void fsp_notify_dummy(void *arg) if (fsp_notify(ph) != FSP_SUCCESS) printk(BIOS_CRIT, "FspNotify failed!\n"); + /* Call END_OF_FIRMWARE Notify after READY_TO_BOOT Notify */ + if (ph == READY_TO_BOOT) + if (fsp_notify(END_OF_FIRMWARE) != FSP_SUCCESS) + printk(BIOS_CRIT, "FspNotify-END_OF_FIRMWARE failed!\n"); } BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, fsp_notify_dummy,

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Patch set updated for coreboot: soc/apollolake: Add SOC specific c-state table
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051 -gerrit commit cd6c82d8ac71eb3f4b07925421f752d5f4df8913 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: Add SOC specific c-state table Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/acpi.c | 41 ++++++++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 2 ++ 3 files changed, 44 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..52a00d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SOC_INTEL_COMMON select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_ACPI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4d610f8..07a5fcb 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -22,10 +22,19 @@ #include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> +#include <soc/intel/common/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -157,3 +166,35 @@ void southbridge_inject_dsdt(device_t device) acpigen_pop_len(); } } +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), + } +}; + +acpi_cstate_t *soc_get_cstate_map(int *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return cstate_map; +} + +uint16_t soc_get_acpi_base_address(void) +{ + return ACPI_PMIO_BASE; +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..a9edbbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void enable_dev(device_t dev)

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Patch set updated for coreboot: soc/apollolake: Add SOC specific c-state table
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051 -gerrit commit 2b73f8a9f997f7ab40e6f87917466fd897ac90e0 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: Add SOC specific c-state table Please refer Apollolake BIOS Writers Guide Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/acpi.c | 36 ++++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 2 ++ 3 files changed, 39 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..52a00d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SOC_INTEL_COMMON select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_ACPI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4d610f8..1c8b8e4 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -22,10 +22,19 @@ #include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> +#include <soc/intel/common/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -157,3 +166,30 @@ void southbridge_inject_dsdt(device_t device) acpigen_pop_len(); } } +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), + } +}; + +acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return(cstate_map); +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..a9edbbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void enable_dev(device_t dev)

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Patch set updated for coreboot: soc/intel/common: Add common code for acpi c/p/t-state entries
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15050 -gerrit commit 8a10bdf9173a0fb065c8c21316db17476bd08ea2 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:40:04 2016 -0700 soc/intel/common: Add common code for acpi c/p/t-state entries Change-Id: I87505bb31cd1b46d27cc5c9ba8d086df7393653e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/Kconfig | 4 + src/soc/intel/common/Makefile.inc | 1 + src/soc/intel/common/acpi.h | 55 +++++++ src/soc/intel/common/acpi/acpi.c | 297 ++++++++++++++++++++++++++++++++++++++ 4 files changed, 357 insertions(+) diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 0a5e935..e64aabf 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -80,4 +80,8 @@ config SOC_INTEL_COMMON_SMI bool default n +config SOC_INTEL_COMMON_ACPI + bool + default n + endif # SOC_INTEL_COMMON diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index deda50a..8e4a793 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -16,6 +16,7 @@ ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI) += ./acpi/acpi.c smm-$(CONFIG_SOC_INTEL_COMMON_SMI) += smihandler.c diff --git a/src/soc/intel/common/acpi.h b/src/soc/intel/common/acpi.h index f7d5038..96b0074 100644 --- a/src/soc/intel/common/acpi.h +++ b/src/soc/intel/common/acpi.h @@ -29,4 +29,59 @@ */ int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0); +#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_ACPI) + +/* + * cpu_get_bus_clock returns the bus clock frequency. This is the value the + * clock ratio is multiplied with. + */ +uint32_t cpu_get_bus_clock(void); + +/* + * cpu_get_coord_type returns coordination type (SW_ANY or SW_ALL or HW_ALL) + * which is used to populate _PSD object. + */ +int cpu_get_coord_type(void); + +/* + * cpu_config_tdp_levels returns the number of TDP levels supported + * by this processor + */ +int cpu_config_tdp_levels(void); + +/* + * cpu_get_min_ratio returns the minimum frequency ratio that is supported + * by this processor + */ +uint32_t cpu_get_min_ratio(void); + +/* + * cpu_get_max_ratio returns the nominal TDP ratio if available or the + * maximum non turbo frequency ratio for this processor + */ +uint32_t cpu_get_max_ratio(void); + +/* + * cpu_get_power_max calculates CPU TDP in mW + */ +uint32_t cpu_get_power_max(void); + +/* + * get_cstate_map returns a table of processor specific acpi_cstate_t entries + * and number of entries in the table + */ +acpi_cstate_t *soc_get_cstate_map(int *num_entries); + +/* + * get_soc_tss_table returns a table of processor specific acpi_tstate_t entries + * and number of entries in the table + */ +acpi_tstate_t *soc_get_tss_table(int *num_entries); + +/* + * soc_get_acpi_base_address returns the acpi base address for the SOC + */ +uint16_t soc_get_acpi_base_address(void); + +#endif /* CONFIG_SOC_INTEL_COMMON_ACPI */ #endif diff --git a/src/soc/intel/common/acpi/acpi.c b/src/soc/intel/common/acpi/acpi.c new file mode 100644 index 0000000..886d09d --- /dev/null +++ b/src/soc/intel/common/acpi/acpi.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/cpu.h> +#include <cpu/intel/turbo.h> +#include <cpu/x86/msr.h> +#include <soc/intel/common/acpi.h> +#include <soc/pm.h> + +#define MSR_PLATFORM_INFO 0xce +#define MSR_TURBO_RATIO_LIMIT 0x1ad +#define MSR_CONFIG_TDP_NOMINAL 0x648 +#define MSR_RAPL_POWER_UNIT 0x606 +#define MSR_PKG_POWER_INFO 0x614 + +/* P-state configuration */ +#define PSS_MAX_ENTRIES 8 +#define PSS_RATIO_STEP 2 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + +/* CPU Bus clock frequency(in MHz) */ +#define CPU_BCLK 100 + +__attribute__((weak)) int cpu_get_coord_type(void) +{ + return HW_ALL; +} + +__attribute__((weak)) int cpu_config_tdp_levels(void) +{ + return 0; +} + +__attribute__((weak)) uint32_t cpu_get_min_ratio(void) +{ + msr_t msr; + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + return ((msr.hi >> 8) & 0xff); /* Max Efficiency Ratio */ +} + +__attribute__((weak)) uint32_t cpu_get_max_ratio(void) +{ + msr_t msr; + uint32_t ratio_max; + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + msr = rdmsr(MSR_PLATFORM_INFO); + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + return ratio_max; +} + +__attribute__((weak)) uint32_t cpu_get_bus_clock(void) +{ + /* CPU bus clock is fixed at 100MHz */ + return CPU_BCLK; +} + +__attribute__((weak)) uint32_t cpu_get_power_max(void) +{ + msr_t msr; + int power_unit; + + msr = rdmsr(MSR_RAPL_POWER_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_INFO); + return ((msr.lo & 0x7fff) / power_unit) * 1000; +} + +__attribute__((weak)) acpi_cstate_t *soc_get_cstate_map(int *entries) +{ + *entries = 0; + return NULL; +} + +__attribute__((weak)) acpi_tstate_t *soc_get_tss_table(int *entries) +{ + *entries = 0; + return NULL; +} + +__attribute__((weak)) uint16_t soc_get_acpi_base_address(void) +{ +#define ACPI_BASE_ADDR 0x400 + return (ACPI_BASE_ADDR); +} + +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + return power; +} + +static int get_cores_per_package(void) +{ + struct cpuinfo_x86 c; + struct cpuid_result result; + int cores = 1; + + get_fms(&c, cpuid_eax(1)); + if (c.x86 != 6) + return 1; + + result = cpuid_ext(0xb, 1); + cores = result.ebx & 0xff; + + return cores; +} + +static void generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + coord_type = cpu_get_coord_type(); + ratio_min = cpu_get_min_ratio(); + ratio_max = cpu_get_max_ratio(); + clock_max = ratio_max * cpu_get_bus_clock(); + + /* Calculate CPU TDP in mW */ + power_max = cpu_get_power_max(); + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CPU_BCLK; + + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + /* Fix package length */ + acpigen_pop_len(); +} + +static void generate_c_state_entries(void) +{ + acpi_cstate_t *c_state_map; + int entries; + + c_state_map = soc_get_cstate_map(&entries); + + /* Generate C-state tables */ + acpigen_write_CST_package(c_state_map, entries); +} + +static void generate_t_state_entries(int core, int cores_per_package) +{ + acpi_tstate_t *soc_tss_table; + int entries; + + soc_tss_table = soc_get_tss_table(&entries); + if (entries == 0) + return; + + /* Indicate SW_ALL coordination for T-states */ + acpigen_write_TSD_package(core, cores_per_package, SW_ALL); + + /* Indicate FFixedHW so OS will use MSR */ + acpigen_write_empty_PTC(); + + /* Set NVS controlled T-state limit */ + acpigen_write_TPC("\\TLVL"); + + /* Write TSS table for MSR access */ + acpigen_write_TSS_package(entries, soc_tss_table); +} + +void generate_cpu_entries(device_t device) +{ + int core_id, cpu_id, pcontrol_blk = soc_get_acpi_base_address(); + int plen = 6; + int totalcores = dev_count_cpu(); + int cores_per_package = get_cores_per_package(); + int numcpus = totalcores / cores_per_package; + + printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", + numcpus, cores_per_package); + + for (cpu_id=0; cpu_id < numcpus; cpu_id++) { + for (core_id=0; core_id < cores_per_package; core_id++) { + if (core_id > 0) { + pcontrol_blk = 0; + plen = 0; + } + + /* Generate processor \_PR.CPUx */ + acpigen_write_processor( + (cpu_id)*cores_per_package + core_id, + pcontrol_blk, plen); + + /* Generate P-state tables */ + generate_p_state_entries( + core_id, cores_per_package); + + /* Generate C-state tables */ + generate_c_state_entries(); + + /* Generate T-state tables */ + generate_t_state_entries( + core_id, cores_per_package); + + acpigen_pop_len(); + } + } +}

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coreboot-gerrit June 2016