coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

New patch to review for coreboot: Apollolake: FSP UPD Signature update
by Brandon Breitenstein 03 Jun '16

03 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15066 -gerrit commit 595857d2225c0e9b83418a6d96f43387f77456cd Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri Jun 3 13:59:28 2016 -0700 Apollolake: FSP UPD Signature update FSP 2.0 spec has updated the signatures for the FSPM and FSPS blobs. In order to successfully pass through memory/silicon init the signatures need to be updated to the latest values. BUG=chrome-os-partner:52784 BRANCH=none TEST=built and booted Change-Id: Ib60d0d9afa4ee29dff26177826ba59db81b630e8 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h | 2 +- src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h index b1a1607..858810f 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspmUpd.h @@ -542,7 +542,7 @@ struct FSP_M_RESTRICTED_CONFIG { uint8_t ReservedFspmRestrictedUpd[138]; } __attribute__((packed)); -#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ +#define FSPM_UPD_SIGNATURE 0x4D5F4450554C5041 /* 'FSPM_UPD' */ /** Fsp M UPD Configuration **/ diff --git a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h index 2ada27f..dd86f21 100644 --- a/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h +++ b/src/soc/intel/apollolake/include/soc/fsp/FspsUpd.h @@ -1350,7 +1350,7 @@ struct FSP_S_RESTRICTED_CONFIG { uint8_t ReservedFspsRestrictedUpd[12]; } __attribute__((packed)); -#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ +#define FSPS_UPD_SIGNATURE 0x535F4450554C5041 /* 'FSPS_UPD' */ /** Fsp S UPD Configuration **/

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Patch set updated for coreboot: intel/amenia: Support 8MB and 16MB flash size
by Bora Guvendik 03 Jun '16

03 Jun '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15065 -gerrit commit 857b5d77bd92a38aebc29cd0a5ea5f0b30f05357 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Fri May 13 17:19:42 2016 -0700 intel/amenia: Support 8MB and 16MB flash size Use different set of blobs for 8MB and 16MB variants. In this case, descriptor.bin is the only difference Change IFD_BIOS_END based on image size Change ROMSIZE based on image size BUG=chrome-os-partner:52458 TEST=Boot to chromeOS using 8MB and 16MB images CQ-DEPEND=CL:*260785,CL:*259285,CL:344770 Change-Id: Ic2aedd5be589f5fb89af98c51bd9e01d3b0b8412 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..de691ce 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -3,7 +3,7 @@ if BOARD_INTEL_AMENIA config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE - select BOARD_ROMSIZE_KB_8192 + select BOARD_ROMSIZE_KB_16384 select MAINBOARD_HAS_CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC @@ -44,17 +44,20 @@ config APOLLOLAKE_A0 config IFD_BIN_PATH string "Path and filename of the descriptor.bin file" - default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.16MB" if APOLLOLAKE_A0 && BOARD_ROMSIZE_KB_16384 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.8MB" if APOLLOLAKE_A0 && BOARD_ROMSIZE_KB_8192 default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0" if !APOLLOLAKE_A0 config FMDFILE string - default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.16MB.fmd" if APOLLOLAKE_A0 && BOARD_ROMSIZE_KB_16384 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.8MB.fmd" if APOLLOLAKE_A0 && BOARD_ROMSIZE_KB_8192 default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex - default 0x77F000 + default 0xF7F000 if APOLLOLAKE_A0 && BOARD_ROMSIZE_KB_16384 + default 0x77F000 if APOLLOLAKE_A0 && BOARD_ROMSIZE_KB_8192 config IFD_BIOS_START hex

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New patch to review for coreboot: intel/amenia: Support 8MB and 16MB flash size
by Bora Guvendik 03 Jun '16

03 Jun '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15065 -gerrit commit 4141534ac71525576f574c031fd844c1c3c3acbe Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Fri May 13 17:19:42 2016 -0700 intel/amenia: Support 8MB and 16MB flash size Use different set of blobs for 8MB and 16MB variants. In this case, descriptor.bin is the only difference Change IFD_BIOS_END based on image size Change ROMSIZE based on image size BUG=chrome-os-partner:52458 TEST=Boot to chromeOS using 8MB and 16MB images CQ-DEPEND=CL:*260785,CL:*259285,CL:344770 Change-Id: Ic2aedd5be589f5fb89af98c51bd9e01d3b0b8412 Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..f184a83 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -3,7 +3,6 @@ if BOARD_INTEL_AMENIA config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE - select BOARD_ROMSIZE_KB_8192 select MAINBOARD_HAS_CHROMEOS select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_LPC @@ -42,19 +41,32 @@ config APOLLOLAKE_A0 bool default y +config FLASH_SIZE_16MB + select BOARD_ROMSIZE_KB_16384 + bool + default y + +config FLASH_SIZE_8MB + select BOARD_ROMSIZE_KB_8192 + bool + default n + config IFD_BIN_PATH string "Path and filename of the descriptor.bin file" - default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.16MB" if APOLLOLAKE_A0 && FLASH_SIZE_16MB + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.8MB" if APOLLOLAKE_A0 && FLASH_SIZE_8MB default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0" if !APOLLOLAKE_A0 config FMDFILE string - default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.16MB.fmd" if APOLLOLAKE_A0 && FLASH_SIZE_16MB + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.8MB.fmd" if APOLLOLAKE_A0 && FLASH_SIZE_8MB default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex - default 0x77F000 + default 0xF7F000 if APOLLOLAKE_A0 && FLASH_SIZE_16MB + default 0x77F000 if APOLLOLAKE_A0 && FLASH_SIZE_8MB config IFD_BIOS_START hex

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Patch set updated for coreboot: WIP: intel/amenia: Add changes for image assembly
by Bora Guvendik 03 Jun '16

03 Jun '16

Bora Guvendik (bora.guvendik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14897 -gerrit commit 8a53efff8dfe1f3e9b56a4b97b96eed480c60f04 Author: Bora Guvendik <bora.guvendik(a)intel.com> Date: Wed May 18 14:56:27 2016 -0700 WIP: intel/amenia: Add changes for image assembly Insert bootblock Build base images for different variants Generate fmd files for different variants BUG=chrome-os-partner:51844 BRANCH=none TEST=boots to chrome OS Change-Id: I0e92858486ecf4720b8bcdf64bae97d9476caabc Signed-off-by: Bora Guvendik <bora.guvendik(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 17 +++++++++++++++-- src/soc/intel/apollolake/Makefile.inc | 5 +++++ 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index ec76119..bfc4091 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -35,9 +35,22 @@ config FMAP_FILE string default "amenia" -config PREBUILT_SPI_IMAGE +config HAVE_IFD_BIN + default y + +config APOLLOLAKE_A0 + bool + default y + +config IFD_BIN_PATH + string "Path and filename of the descriptor.bin file" + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0" if !APOLLOLAKE_A0 + +config FMDFILE string - default "amenia.bin.orig.a0" + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.a0.fmd" if APOLLOLAKE_A0 + default "3rdparty/blobs/baseboard-reef/reef.bin.orig.b0.fmd" if !APOLLOLAKE_A0 config IFD_BIOS_END hex diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 80617a7..db8addf 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -66,4 +66,9 @@ files_added:: $(CBFSTOOL) $(obj)/coreboot.rom write -r $(CONFIG_LBP2_FMAP_NAME) -f $(CONFIG_LBP2_FILE_NAME) --fill-upward endif +build_complete:: + $(CBFSTOOL) $(obj)/coreboot.rom write \ + -r bootblock \ + -f $(objcbfs)/bootblock.bin + endif

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Patch set updated for coreboot: soc/apollolake: Force USB Port 0 to host mode (disable OTG)
by Alexandru Gagniuc 03 Jun '16

03 Jun '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15064 -gerrit commit 991bc81754a0ffc7a958fc36e6a45077d7cc69c5 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed May 4 17:10:27 2016 -0700 soc/apollolake: Force USB Port 0 to host mode (disable OTG) Due to a hardware bug, automatic OTG negotiaion does not work, and USB port 0 is unusable. The workaround is to disable OTG mode, which forces the port into host mode. In host mode, it operates normally via the XHCI interface. Change-Id: I983ebcc42647d224d1e4cde46e7a74b0474f04d7 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d7c61c1..2ba92b3 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -99,6 +99,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) /* Load VBT before devicetree-specific config. */ silconfig->GraphicsConfigPtr = (uintptr_t)vbt; + /* Force USB_P0 to host mode. (hardware bug: OTG negotiation fails). */ + silconfig->UsbOtg = 0; struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); if (!dev || !dev->chip_info) {

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New patch to review for coreboot: soc/apollolake: Force USB Port 0 to host mode (disable OTG)
by Alexandru Gagniuc 03 Jun '16

03 Jun '16

Alexandru Gagniuc (alexandrux.gagniuc(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15064 -gerrit commit 385fcb0b36462f9fab537ef4e480d8fb3ed59fc1 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed May 4 17:10:27 2016 -0700 soc/apollolake: Force USB Port 0 to host mode (disable OTG) Due to a hardware bug, automatic OTG negiotiaion does not work, and USB port 0 is unusable. The workaround is to disable OTG mode, which forces the port into host mode. In host mode, it operates normally via the XHCI interface. Change-Id: I983ebcc42647d224d1e4cde46e7a74b0474f04d7 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> --- src/soc/intel/apollolake/chip.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d7c61c1..248182b 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -101,6 +101,9 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) silconfig->GraphicsConfigPtr = (uintptr_t)vbt; struct device *dev = dev_find_slot(NB_BUS, NB_DEVFN); + /* Force USB_P0 to host mode. (hardware bug: OTG negotiation fails). */ + silconfig->UsbOtg = 0; + if (!dev || !dev->chip_info) { printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n"); return;

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New patch to review for coreboot: lenovo/x60: add hda_verb.c
by Arthur Heymans 03 Jun '16

03 Jun '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15063 -gerrit commit 4f3452fc544d4e799445c3271b1022496932473c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Jun 3 18:37:38 2016 +0200 lenovo/x60: add hda_verb.c This creates a config for the x60 audio based on values taken from vendor bios. What is improved: - internal microphone is chosen by default - when jack is inserted it chosen instead of internal speaker Before this had to be done manually. Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/x60/hda_verb.c | 35 +++++++++++++++++++++++++++++++++-- 1 file changed, 33 insertions(+), 2 deletions(-) diff --git a/src/mainboard/lenovo/x60/hda_verb.c b/src/mainboard/lenovo/x60/hda_verb.c index 072a306..c4b1f3a 100644 --- a/src/mainboard/lenovo/x60/hda_verb.c +++ b/src/mainboard/lenovo/x60/hda_verb.c @@ -1,7 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <device/azalia_device.h> -const u32 cim_verb_data[0] = {}; +const u32 cim_verb_data[] = { + 0x11d41981, /* Codec Vendor / Device ID: Analog Devices AD1981 */ + 0x17aa2025, /* Subsystem ID */ + 0x0000000b, /* Number of 4 dword sets */ -const u32 pc_beep_verbs[0] = {}; + AZALIA_SUBVENDOR(0x0, 0x17aa2025), + AZALIA_PIN_CFG(0, 0x05, 0xc3014110), + AZALIA_PIN_CFG(0, 0x06, 0x4221401f), + AZALIA_PIN_CFG(0, 0x07, 0x591311f0), + AZALIA_PIN_CFG(0, 0x08, 0xc3a15020), + AZALIA_PIN_CFG(0, 0x09, 0x41813021), + AZALIA_PIN_CFG(0, 0x0a, 0x014470f0), + AZALIA_PIN_CFG(0, 0x16, 0x59f311f0), + AZALIA_PIN_CFG(0, 0x17, 0x59931122), + AZALIA_PIN_CFG(0, 0x18, 0x41a19023), + AZALIA_PIN_CFG(0, 0x19, 0x9933e12e) +}; +const u32 pc_beep_verbs[0] = {}; AZALIA_ARRAY_SIZES;

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Patch set updated for coreboot: board/intel/amenia: Enable LPSS PMCTL for S0ix
by Hannah Williams 03 Jun '16

03 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15056 -gerrit commit b78f7eeef9cf6149058194771a43cfcfc31c7c5f Author: Hannah Williams <hannah.williams(a)intel.com> Date: Thu Jun 2 15:00:36 2016 -0700 board/intel/amenia: Enable LPSS PMCTL for S0ix This setting will enable S0ix for LPSS Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/mainboard/intel/amenia/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 38a2de2..77ae0bf 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -7,6 +7,9 @@ chip soc/intel/apollolake register "pcie_rp0_clkreq_pin" = "3" # wifi/bt register "pcie_rp2_clkreq_pin" = "0" # SSD + # LPSS IOSF PMCTL S0ix Enable + register "S0ixEnable" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF

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Patch merged into coreboot/master: AMD boards: Drop comment on include file
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit 11f3443db67e275c3a16767ba9a19eb1bb0d88be Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu May 26 11:21:02 2016 +0300 AMD boards: Drop comment on include file The included file does not declare pm_ioread(), and the modified file does not call it either. Change-Id: I9723caf1062db23b4a3648e07c2dc4c02f862619 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14968 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14968 for details. -gerrit

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Patch merged into coreboot/master: aopen/dxplplusu: Disable HW scrubber
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit b62c5e89492225f62659adef0e3ba9d13ba38359 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue May 31 17:20:45 2016 +0300 aopen/dxplplusu: Disable HW scrubber See initialize_ecc() for the awful hack that got us around cache-as-ram being invalidated as we do ECC HW scrubbing. It once worked, but compiler nowadays puts more registers on the stack. Not much interest to try fix ECC for this particular board. Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/15014 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15014 for details. -gerrit

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coreboot-gerrit June 2016