coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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1491 discussions

New patch to review for coreboot: google/reef: Add asl code to enable google ChromeEC
by Shaunak Saha 03 Jun '16

03 Jun '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15069 -gerrit commit 376b7d4b552b440ba10bf2f15731bc27e90bbdde Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Fri Jun 3 17:11:12 2016 -0700 google/reef: Add asl code to enable google ChromeEC This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35 Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/mainboard/google/reef/acpi/ec.asl | 26 ++++++++++++++++++++++++++ src/mainboard/google/reef/acpi/mainboard.asl | 26 ++++++++++++++++++++++++++ src/mainboard/google/reef/dsdt.asl | 3 +++ src/mainboard/google/reef/ec.h | 4 ++++ 4 files changed, 59 insertions(+) diff --git a/src/mainboard/google/reef/acpi/ec.asl b/src/mainboard/google/reef/acpi/ec.asl new file mode 100644 index 0000000..fe53cb5 --- /dev/null +++ b/src/mainboard/google/reef/acpi/ec.asl @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* mainboard configuration */ +#include "../ec.h" + +/* Enable EC backed ALS device in ACPI */ +#define EC_ENABLE_ALS_DEVICE + +/* Enable EC backed PD MCU device in ACPI */ +#define EC_ENABLE_PD_MCU_DEVICE + +/* ACPI code for EC functions */ +#include <ec/google/chromeec/acpi/ec.asl> diff --git a/src/mainboard/google/reef/acpi/mainboard.asl b/src/mainboard/google/reef/acpi/mainboard.asl index 05ea06a..06b2efc 100644 --- a/src/mainboard/google/reef/acpi/mainboard.asl +++ b/src/mainboard/google/reef/acpi/mainboard.asl @@ -14,3 +14,29 @@ */ #include "acpi/superio.asl" + +Scope (\_SB) +{ + Device (LID0) + { + Name (_HID, EisaId ("PNP0C0D")) + Method (_LID, 0) + { + Return (\_SB.PCI0.LPCB.EC0.LIDS) + } + } + + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + +/* + * LPC Trusted Platform Module + */ +Scope (\_SB.PCI0.LPCB) +{ + #include <drivers/pc80/tpm/acpi/tpm.asl> + #include "ec.asl" +} diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 41bb523..8aa4259 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -25,6 +25,9 @@ DefinitionBlock( /* global NVS and variables */ #include <soc/intel/skylake/acpi/globalnvs.asl> + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + Scope (\_SB) { Device (PCI0) { diff --git a/src/mainboard/google/reef/ec.h b/src/mainboard/google/reef/ec.h index 51d4028..5a32697 100644 --- a/src/mainboard/google/reef/ec.h +++ b/src/mainboard/google/reef/ec.h @@ -18,6 +18,10 @@ #include <ec/google/chromeec/ec_commands.h> +/* This is the GPE status bit. + TODO: Fix this to proper bit matching GPE routing table */ +#define EC_SCI_GPI 15 + #define MAINBOARD_EC_SCI_EVENTS \ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\

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New patch to review for coreboot: Revert "soc/intel/apollolake: Do not use StackBase FSP-M parameter"
by Brandon Breitenstein 03 Jun '16

03 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15068 -gerrit commit c5ca8e5c5925056932682742ed40adf1bbd9cbdb Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Sat Jun 4 00:52:21 2016 +0200 Revert "soc/intel/apollolake: Do not use StackBase FSP-M parameter" This reverts commit 5ede3d8ccebde6f26c6b24f6458e57d99d5f3957. No longer needed due to FSP being updated to accept StackBase field Change-Id: Ic832d8dc4ca87631f5fef80d4d41558d9a72630a --- src/soc/intel/apollolake/romstage.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index da53799..8ec94a7 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -238,13 +238,9 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) * requests. * TODO: add checks to avoid overlap/conflict of CAR usage. */ - - /* fsp does not work with StackBase modified, so use default */ -#if 0 - /* FIXME: remove this once FSP is fixed */ mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; -#endif + arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {

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New patch to review for coreboot: Apollolake: Define StackBase for FSP
by Brandon Breitenstein 03 Jun '16

03 Jun '16

Brandon Breitenstein (brandon.breitenstein(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15067 -gerrit commit 451552e20942737bee49fda05d02bf691b3748c2 Author: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Date: Fri May 27 13:40:34 2016 -0700 Apollolake: Define StackBase for FSP FSP fixed an issue where StackBase being defined caused crashes on boot. Now that this is fixed StackBase must be defined so a valid Base address is there for Memory Init phase. BUG=none BRANCH=none TEST=built and booted with new FSP code Change-Id: I8df4e527fe08ad64bbbed10aa0a63fb10343b7db Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7537 Auto-Verified: chromeos <chromeos(a)intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov(a)intel.com> Tested-by: Petrov, Andrey <andrey.petrov(a)intel.com> Reviewed-on: https://chromium.devtools.intel.com/7600 --- src/soc/intel/apollolake/romstage.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 434d11f..f95a87f 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -242,12 +242,10 @@ void platform_fsp_memory_init_params_cb(struct FSPM_UPD *mupd) */ /* fsp does not work with StackBase modified, so use default */ -#if 0 - /* FIXME: remove this once FSP is fixed */ + mupd->FspmArchUpd.StackBase = _car_region_end - mupd->FspmArchUpd.StackSize; -#endif - arch_upd->Bootmode = FSP_BOOT_WITH_FULL_CONFIGURATION; + arch_upd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION; if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) { if (!mrc_cache_get_current_with_version(&mrc_cache, 0)) {

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Patch set updated for coreboot: ARM: Add function to get cntfrq value
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14920 -gerrit commit 48ca13631da0dbeaa07b26bb398f13adb7c7a860 Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Thu Oct 9 17:07:36 2014 +0530 ARM: Add function to get cntfrq value Adding a function definition to get the value of cntfrq register. BUG=None BRANCH=None TEST=None Change-Id: I578976d5714fef52ff4e58d17f2d3c13a32ebbf7 Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- src/arch/arm64/armv8/lib/clock.c | 9 +++++++++ src/arch/arm64/include/arch/clock.h | 1 + 2 files changed, 10 insertions(+) diff --git a/src/arch/arm64/armv8/lib/clock.c b/src/arch/arm64/armv8/lib/clock.c index 7cd4bc6..cce5dc2 100644 --- a/src/arch/arm64/armv8/lib/clock.c +++ b/src/arch/arm64/armv8/lib/clock.c @@ -25,3 +25,12 @@ void set_cntfrq(uint32_t freq) { __asm__ __volatile__("msr cntfrq_el0, %0" :: "r"(freq)); } + +uint32_t get_cntfrq(void) +{ + uint32_t freq; + + __asm__ __volatile__("mrs %0, cntfrq_el0" : "=r"(freq)); + + return freq; +} diff --git a/src/arch/arm64/include/arch/clock.h b/src/arch/arm64/include/arch/clock.h index 77d09d8..3889a5d 100644 --- a/src/arch/arm64/include/arch/clock.h +++ b/src/arch/arm64/include/arch/clock.h @@ -19,5 +19,6 @@ #include <types.h> void set_cntfrq(uint32_t); +uint32_t get_cntfrq(void); #endif /* __ARM_CLOCK_H_ */

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Patch set updated for coreboot: Jazz: Add PMIC initialization
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14916 -gerrit commit 808c2589bcd735b0d8b642b1f3242c5080cea351 Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Mon Aug 11 20:24:11 2014 +0530 Jazz: Add PMIC initialization Adding initial PMIC setup using I2C for Exynos7 in this patch. TEST=Tested by checking the power of the IPs. UART will not unless it gets power from this PMIC. Change-Id: I4f23d6e636e1620402fc19693c56abefa0bf36b7 Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- src/mainboard/samsung/jazz/romstage.c | 57 ++++++++++++- src/mainboard/samsung/jazz/s2mps15.h | 155 ++++++++++++++++++++++++++++++++++ 2 files changed, 211 insertions(+), 1 deletion(-) diff --git a/src/mainboard/samsung/jazz/romstage.c b/src/mainboard/samsung/jazz/romstage.c index 5142b25..bf0c66b 100644 --- a/src/mainboard/samsung/jazz/romstage.c +++ b/src/mainboard/samsung/jazz/romstage.c @@ -28,11 +28,66 @@ #include <soc/gpio.h> #include <soc/i2c.h> #include <soc/periph.h> +#include <soc/pinmux.h> #include <soc/power.h> +#include "s2mps15.h" + +#define PMIC_I2C_BUS 4 + +struct pmic_write +{ + int or_orig; /* Whether to or in the original value */ + uint8_t reg; /* Register to write */ + uint8_t val; /* Value to write */ +}; + +/* + * Use read-modify-write for S2MPS15 control registers and clobber the + * output voltage setting (BUCK?DVS?) registers. + */ +struct pmic_write pmic_writes[] = +{ + { (PM_VDD_AP >= 1000 ? 0 : 1), S2MPS15_REG_LDO_DVS1, + (PM_VDD_AP >= 1000 ? 0x84 : 0x0) }, + { 0, S2MPS15_REG_LDO_DVS2, 0x84 }, + { 0, S2MPS15_REG_LDO_DVS3, 0x84 }, + { 0, S2MPS15_REG_LDO_DVS4, 0x84 }, + { 0, S2MPS15_REG_BUCK1_OUT, WR_BUCK_VOLT(PM_VDD_MIF) }, + { 0, S2MPS15_REG_BUCK2_OUT, WR_BUCK_VOLT(PM_VDD_AP) }, + { 0, S2MPS15_REG_BUCK4_OUT, WR_BUCK_VOLT(PM_VDD_INT) }, + { 0, S2MPS15_REG_BUCK5_OUT, WR_BUCK_VOLT(PM_VDD_DISP) }, + { 0, S2MPS15_REG_BUCK6_OUT, WR_BUCK_VOLT(PM_VDD_G3D) }, + { 1, S2MPS15_REG_RTC_BUF, + (LOW_JITTER_EN | BT_32KHZ_EN | CP_32KHZ_EN | AP_32KHZ_EN) }, + { 1, S2MPS15_REG_WRSTBI_CTRL, WRSTBI_EN }, + { 1, S2MPS15_REG_LDO3_CTRL, OUTPUT_PWREN_ON }, + { 1, S2MPS15_REG_LDO14_CTRL, OUTPUT_PWREN_ON }, + { 1, S2MPS15_REG_LDO15_CTRL, OUTPUT_PWREN_ON }, + { 1, S2MPS15_REG_LDO17_CTRL, OUTPUT_PWREN_ON }, +}; + static int setup_power(void) { - return 0; + int error = 0; + int i; + + /* Initialize I2C bus to configure PMIC. */ + exynos_pinmux_i2c4(); + i2c_init(PMIC_I2C_BUS, 400000, 0x00); /* 400KHz */ + + for (i = 0; i < ARRAY_SIZE(pmic_writes); i++) { + uint8_t data = 0; + uint8_t reg = pmic_writes[i].reg; + + if (pmic_writes[i].or_orig) + error |= i2c_read(PMIC_I2C_BUS, + S2MPS15_I2C_ADDR, reg, 1, &data, 1); + data |= pmic_writes[i].val; + error |= i2c_write(PMIC_I2C_BUS, S2MPS15_I2C_ADDR, reg, 1, &data, 1); + } + + return error; } void main(void) diff --git a/src/mainboard/samsung/jazz/s2mps15.h b/src/mainboard/samsung/jazz/s2mps15.h new file mode 100644 index 0000000..ca15d5b --- /dev/null +++ b/src/mainboard/samsung/jazz/s2mps15.h @@ -0,0 +1,155 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __S2MPS15_H_ +#define __S2MPS15_H_ + +enum { + S2MPS15_REG_ID = 0x0, + S2MPS15_REG_INT1, + S2MPS15_REG_INT2, + S2MPS15_REG_INT3, + S2MPS15_REG_INT1MSK, + S2MPS15_REG_INT2MSK, + S2MPS15_REG_INT3MSK, + + S2MPS15_REG_STATUS1, + S2MPS15_REG_STATUS2, + + S2MPS15_REG_PWRONSRC, + S2MPS15_REG_OFFSRC = 0xA, + S2MPS15_REG_BU_CHG, + S2MPS15_REG_RTC_BUF, + S2MPS15_REG_CTRL1, + S2MPS15_REG_CTRL2 = 0xE, + + S2MPS15_REG_RSVD1, + S2MPS15_REG_RSVD2, + S2MPS15_REG_RSVD3, + S2MPS15_REG_RSVD4, + S2MPS15_REG_RSVD5, + S2MPS15_REG_RSVD6, + S2MPS15_REG_RSVD7, + S2MPS15_REG_RSVD8, + S2MPS15_REG_RSVD9, + + S2MPS15_REG_WRSTBI_CTRL = 0x18, + + S2MPS15_REG_BUCK1_CTRL = 0x19, + S2MPS15_REG_BUCK1_OUT, + S2MPS15_REG_BUCK2_CTRL = 0x1B, + S2MPS15_REG_BUCK2_OUT, + S2MPS15_REG_BUCK3_CTRL = 0x1D, + S2MPS15_REG_BUCK3_OUT, + S2MPS15_REG_BUCK4_CTRL = 0x1F, + S2MPS15_REG_BUCK4_OUT, + S2MPS15_REG_BUCK5_CTRL = 0x21, + S2MPS15_REG_BUCK5_OUT, + S2MPS15_REG_BUCK6_CTRL = 0x23, + S2MPS15_REG_BUCK6_OUT, + S2MPS15_REG_BUCK7_CTRL = 0x25, + S2MPS15_REG_BUCK7_OUT, + S2MPS15_REG_BUCK8_CTRL = 0x27, + S2MPS15_REG_BUCK8_OUT, + S2MPS15_REG_BUCK9_CTRL = 0x29, + S2MPS15_REG_BUCK9_OUT, + S2MPS15_REG_BUCK10_CTRL = 0x2B, + S2MPS15_REG_BUCK10_OUT, + S2MPS15_REG_BB1_CTRL = 0x2D, + S2MPS15_REG_BB1_OUT, + S2MPS15_REG_BUCK_RAMP, + + S2MPS15_REG_LDO_DVS1 = 0x30, + S2MPS15_REG_LDO_DVS2, + S2MPS15_REG_LDO_DVS3, + S2MPS15_REG_LDO_DVS4, + + S2MPS15_REG_LDO1_CTRL = 0x34, + S2MPS15_REG_LDO2_CTRL, + S2MPS15_REG_LDO3_CTRL, + S2MPS15_REG_LDO4_CTRL, + S2MPS15_REG_LDO5_CTRL, + S2MPS15_REG_LDO6_CTRL, + S2MPS15_REG_LDO7_CTRL, + S2MPS15_REG_LDO8_CTRL, + S2MPS15_REG_LDO9_CTRL, + S2MPS15_REG_LDO10_CTRL = 0x3D, + S2MPS15_REG_LDO11_CTRL, + S2MPS15_REG_LDO12_CTRL, + S2MPS15_REG_LDO13_CTRL, + S2MPS15_REG_LDO14_CTRL, + S2MPS15_REG_LDO15_CTRL, + S2MPS15_REG_LDO16_CTRL, + S2MPS15_REG_LDO17_CTRL, + S2MPS15_REG_LDO18_CTRL, + S2MPS15_REG_LDO19_CTRL, + S2MPS15_REG_LDO20_CTRL = 0x47, + S2MPS15_REG_LDO21_CTRL, + S2MPS15_REG_LDO22_CTRL, + S2MPS15_REG_LDO23_CTRL, + S2MPS15_REG_LDO24_CTRL, + S2MPS15_REG_LDO25_CTRL, + S2MPS15_REG_LDO26_CTRL, + S2MPS15_REG_LDO27_CTRL, + + S2MPS15_REG_LDO_DCSH1 = 0x4F, + S2MPS15_REG_LDO_DCSH2, + S2MPS15_REG_LDO_DCSH3, + S2MPS15_REG_LDO_DCSH4, + + S2MPS15_NUM_OF_REGS, +}; + +/* I2C device address for pmic s2mps15 */ +#define S2MPS15_I2C_ADDR 0x66 + +/* LDO CTRL bit */ +#define OFF (0x0) +#define ON (0x1) +#define OUTPUT_OFF (~(3 << 6)) +#define OUTPUT_PWREN_ON (1 << 6) +#define OUTPUT_LOWPWR_MODE (2 << 6) +#define OUTPUT_NORMAL_MODE (3 << 6) + +/* + * RTC_BUF + */ +#define LOW_JITTER_EN (0x1 << 4) +#define BT_32KHZ_EN (0x1 << 2) +#define CP_32KHZ_EN (0x1 << 1) +#define AP_32KHZ_EN (0x1 << 0) + +/* + * WRSTBI + */ +#define WRSTBI_EN (0x1 << 5) + +#define VDD_BASE_VOLT 50000 +#define VDD_VOLT_STEP 625 +#define MIN_VOLT 500 +#define MAX_RD_VAL 0xB0 +#define RD_BUCK_VOLT(x) (((x > MAX_RD_VAL) ? 0 : \ + (((x - 0x10) * VDD_VOLT_STEP) + VDD_BASE_VOLT) / 100)) +#define WR_BUCK_VOLT(x) ((x < MIN_VOLT) ? 0x10 : \ + ((((x) * 100) - VDD_BASE_VOLT) / VDD_VOLT_STEP + 0x10)) + +#define PM_VDD_AP 900 +#define PM_VDD_MIF 1000 +#define PM_VDD_INT 1000 +#define PM_VDD_G3D 1000 +#define PM_VDD_DISP 1000 + +#endif /* __S2MPS15_H_ */

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Patch set updated for coreboot: libpayload: Jazz: Enable serial console
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14917 -gerrit commit 5a32d0b38add72169cebb648fa871c5cf4a07e9b Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Fri Sep 5 11:27:51 2014 +0530 libpayload: Jazz: Enable serial console Ramstage should share some data with depthcharge and libpayload. But in case of Jazz we do not wish to share any buffer and just want to enable serial console and for that we ask UART's base address from config. BUG=None BRANCH=None TEST=Saw prints over console from depthcharge Change-Id: Iea29572b830bdf617dfbf253151a30bbcbc2a69c Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- payloads/libpayload/drivers/serial/s5p.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/payloads/libpayload/drivers/serial/s5p.c b/payloads/libpayload/drivers/serial/s5p.c index 1d23352..cf9a537 100644 --- a/payloads/libpayload/drivers/serial/s5p.c +++ b/payloads/libpayload/drivers/serial/s5p.c @@ -25,9 +25,13 @@ * SUCH DAMAGE. */ +#include <arch/io.h> #include <libpayload.h> +#include <libpayload-config.h> #include <stdint.h> +#include "config.h" + struct s5p_uart { uint32_t ulcon; // line control @@ -89,10 +93,14 @@ static struct console_input_driver s5p_serial_input = void serial_init(void) { - if (!lib_sysinfo.serial || !lib_sysinfo.serial->baseaddr) - return; - - uart_regs = (struct s5p_uart *)lib_sysinfo.serial->baseaddr; + if (CONFIG_LP_S5P_SERIAL_CONSOLE_ADDRESS) + uart_regs = (struct s5p_uart *) (uintptr_t) + CONFIG_LP_S5P_SERIAL_CONSOLE_ADDRESS; + else if (lib_sysinfo.serial && lib_sysinfo.serial->baseaddr) + uart_regs = (struct s5p_uart *) (uintptr_t) + lib_sysinfo.serial->baseaddr; + + return; } void serial_console_init(void)

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Patch set updated for coreboot: libpayload: Jazz: Adding a config for new board
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14918 -gerrit commit 8f67ae94d4fc45e321c074b02274f505cc540eec Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Fri Sep 5 11:26:11 2014 +0530 libpayload: Jazz: Adding a config for new board Here we are adding config for a new board called Jazz. BUG=None BRANCH=None TEST=None Change-Id: Ic5059fae320bbdcb66b4ee7d1bbc25f17c36a0d2 Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- payloads/libpayload/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/payloads/libpayload/Kconfig b/payloads/libpayload/Kconfig index 276eb30..3d85e63 100644 --- a/payloads/libpayload/Kconfig +++ b/payloads/libpayload/Kconfig @@ -232,6 +232,11 @@ config S5P_SERIAL_CONSOLE depends on SERIAL_CONSOLE default n +config S5P_SERIAL_CONSOLE_ADDRESS + hex "Exynos S5P UART base address" + depends on S5P_SERIAL_CONSOLE + default 0x14C30000 + config IPQ806X_SERIAL_CONSOLE bool "IPQ806x SOC compatible serial port driver" depends on SERIAL_CONSOLE

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Patch set updated for coreboot: ARM64: Add lib helper functions for L2CTRL and L2ACTLR
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14919 -gerrit commit 621aba1eb3db0efb09431c826dbe16e2ef7f7a11 Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Thu Oct 9 17:10:30 2014 +0530 ARM64: Add lib helper functions for L2CTRL and L2ACTLR Adding few more lib helper function definitions to get and set L2 Control and L2 Auxiliary Control registers. BUG=None BRANCH=None TEST=None Change-Id: Ie8a3d4ef3ec685264bde330b3563630a141fdffa Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> --- src/arch/arm64/armv8/lib/sysctrl.c | 32 +++++++++++++++++++++++++ src/arch/arm64/include/armv8/arch/lib_helpers.h | 4 ++++ 2 files changed, 36 insertions(+) diff --git a/src/arch/arm64/armv8/lib/sysctrl.c b/src/arch/arm64/armv8/lib/sysctrl.c index e349a25..0ce3dcf 100644 --- a/src/arch/arm64/armv8/lib/sysctrl.c +++ b/src/arch/arm64/armv8/lib/sysctrl.c @@ -1060,4 +1060,36 @@ void raw_write_cntfrq_el0(uint32_t cntfrq_el0) { __asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" : : "r" (cntfrq_el0) : "memory"); +/* L2CTLR */ +uint32_t raw_read_l2ctlr_el1(void) +{ + uint32_t l2ctlr_el1; + + __asm__ __volatile__("mrs %0, S3_1_c11_c0_2\n\t" + : "=r" (l2ctlr_el1) : : "memory"); + + return l2ctlr_el1; +} + +void raw_write_l2ctlr_el1(uint32_t l2ctlr_el1) +{ + __asm__ __volatile__("msr S3_1_c11_c0_2, %0\n\t" + : : "r" (l2ctlr_el1) : "memory"); +} + +/* L2ACTLR */ +uint32_t raw_read_l2actlr_el1(void) +{ + uint32_t l2actlr_el1; + + __asm__ __volatile__("mrs %0, s3_1_c15_c0_0\n\t" + : "=r" (l2actlr_el1) : : "memory"); + + return l2actlr_el1; +} + +void raw_write_l2actlr_el1(uint32_t l2actlr_el1) +{ + __asm__ __volatile__("msr s3_1_c15_c0_0, %0\n\t" + : : "r" (l2actlr_el1) : "memory"); } diff --git a/src/arch/arm64/include/armv8/arch/lib_helpers.h b/src/arch/arm64/include/armv8/arch/lib_helpers.h index 94078e9..4e36714 100644 --- a/src/arch/arm64/include/armv8/arch/lib_helpers.h +++ b/src/arch/arm64/include/armv8/arch/lib_helpers.h @@ -479,6 +479,10 @@ void raw_write_far(uint64_t far, uint32_t el); uint64_t raw_read_hcr_el2(void); void raw_write_hcr_el2(uint64_t hcr_el2); uint64_t raw_read_aa64pfr0_el1(void); +uint32_t raw_read_l2ctlr_el1(void); +void raw_write_l2ctlr_el1(uint32_t l2ctlr_el1); +uint32_t raw_read_l2actlr_el1(void); +void raw_write_l2actlr_el1(uint32_t l2actlr_el1); uint64_t raw_read_mair_el1(void); void raw_write_mair_el1(uint64_t mair_el1); uint64_t raw_read_mair_el2(void);

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Patch set updated for coreboot: Exynos7: Add Trustzone initialization
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14912 -gerrit commit 31fcd9648d60aa17151b2186552882c46415cf7a Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Thu Aug 7 16:19:01 2014 +0530 Exynos7: Add Trustzone initialization Adding initial Trustzone setup for Exynos7 in this patch. Change-Id: Id8159a3a5b0707edcb908f56d4e2207cec104c1c Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/samsung/exynos7/Makefile.inc | 1 + src/soc/samsung/exynos7/bootblock.c | 4 ++ src/soc/samsung/exynos7/include/soc/trustzone.h | 73 +++++++++++++++++++++++++ src/soc/samsung/exynos7/trustzone.c | 65 ++++++++++++++++++++++ 4 files changed, 143 insertions(+) diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc index fdf4dda..93f21c2 100644 --- a/src/soc/samsung/exynos7/Makefile.inc +++ b/src/soc/samsung/exynos7/Makefile.inc @@ -29,6 +29,7 @@ bootblock-y += monotonic_timer.c bootblock-y += pinmux.c bootblock-y += power.c bootblock-y += timer.c +bootblock-y += trustzone.c ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y) bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c endif diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c index 71650e0..fab66a1 100644 --- a/src/soc/samsung/exynos7/bootblock.c +++ b/src/soc/samsung/exynos7/bootblock.c @@ -24,6 +24,7 @@ #include <soc/mct.h> #include <soc/pinmux.h> #include <soc/power.h> +#include <soc/trustzone.h> void bootblock_cpu_init(void) { @@ -56,6 +57,9 @@ void bootblock_cpu_init(void) /* Initialize SDRAM */ mem_ctrl_init_lpddr4(is_resume); + /* Initialize trustzone */ + trustzone_init(); + /* Set GPIOs for UART */ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART0)) exynos_pinmux_uart0(); diff --git a/src/soc/samsung/exynos7/include/soc/trustzone.h b/src/soc/samsung/exynos7/include/soc/trustzone.h new file mode 100644 index 0000000..df1cc7f --- /dev/null +++ b/src/soc/samsung/exynos7/include/soc/trustzone.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPU_SAMSUNG_EXYNOS7_TRUSTZONE_H_ +#define _CPU_SAMSUNG_EXYNOS7_TRUSTZONE_H_ + +#include <stddef.h> +#include <stdint.h> + +/* Distance between each Trust Zone PC register set */ +#define TZPC_MODULE_OFFSET 0x10000 + +/* TZPC : Register Offsets */ +#define EXYNOS7_NR_TZPC_BANKS 15 + +/* + * TZPC Register Value : + * R0_ALIVE_SIZE: 0x60 : Size of secure iRAM + * R0_AUDIO_SIZE: 0x0 : Size of non-secure iRAM + */ +#define R0_ALIVE_SIZE 0x60 +#define R0_AUDIO_SIZE 0x0 + +/* + * TZPC Decode Protection Register Value : + * DECPROTXSET: 0xFF : Set Decode region to non-secure + */ +#define DECPROTXSET 0xFF + +#define SHIFT_4KB 12 + +struct exynos_tzpc { + u32 r0size; + u8 res1[0x7FC]; + u32 decprot0stat; + u32 decprot0set; + u32 decprot0clr; + u32 decprot1stat; + u32 decprot1set; + u32 decprot1clr; + u32 decprot2stat; + u32 decprot2set; + u32 decprot2clr; + u32 decprot3stat; + u32 decprot3set; + u32 decprot3clr; + u8 res2[0x7B0]; + u32 periphid0; + u32 periphid1; + u32 periphid2; + u32 periphid3; + u32 pcellid0; + u32 pcellid1; + u32 pcellid2; + u32 pcellid3; +}; +check_member(exynos_tzpc, pcellid3, 0xffc); + +void trustzone_init(void); + +#endif /* _CPU_SAMSUNG_EXYNOS7_TRUSTZONE_H_ */ diff --git a/src/soc/samsung/exynos7/trustzone.c b/src/soc/samsung/exynos7/trustzone.c new file mode 100644 index 0000000..f701438 --- /dev/null +++ b/src/soc/samsung/exynos7/trustzone.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/cpu.h> +#include <soc/trustzone.h> + +/* Setting TZPC[TrustZone Protection Controller] + * We pretty much disable it all, as the kernel + * expects it that way -- and that's not the default. + */ +void trustzone_init(void) +{ + struct exynos_tzpc *tzpc; + uint64_t tzpc_hole1, tzpc_hole2, start = 0, end = 0; + + /* Calculate trustzone SFR end address. + * We have 16 modules which need to be initialized out of which + * only 10 are sequentially following the base address. + */ + end = EXYNOS7_TZPC_BASE + ((EXYNOS7_NR_TZPC_BANKS - 6) * TZPC_MODULE_OFFSET); + + /* Calculate trustzone SFR start address. + * We have 6 modules above the base address + we have two SFR holes + * between them. + */ + start = EXYNOS7_TZPC_BASE - (8 * TZPC_MODULE_OFFSET); + + /* Calculate the addresses of SFR holes */ + tzpc_hole1 = EXYNOS7_TZPC_BASE - (5 * TZPC_MODULE_OFFSET); + tzpc_hole2 = EXYNOS7_TZPC_BASE - (4 * TZPC_MODULE_OFFSET); + + for ( ; start <= end; start += TZPC_MODULE_OFFSET) { + if (start == tzpc_hole1 || start == tzpc_hole2) + continue; + tzpc = (struct exynos_tzpc *)start; + + /* Set the size of secure region */ + if (start == EXYNOS7_TZPC_BASE) + write32(&tzpc->r0size, + ((CONFIG_ROMSTAGE_BASE - PHY_IRAM_BASE) >> SHIFT_4KB)); + else if (start == (EXYNOS7_TZPC_BASE + TZPC_MODULE_OFFSET)) + write32(&tzpc->r0size, R0_ALIVE_SIZE); + else if (start == (EXYNOS7_TZPC_BASE + (2 * TZPC_MODULE_OFFSET))) + write32(&tzpc->r0size, R0_AUDIO_SIZE); + + /* Set Decode region to non-secure */ + write32(&tzpc->decprot0set, DECPROTXSET); + write32(&tzpc->decprot1set, DECPROTXSET); + write32(&tzpc->decprot2set, DECPROTXSET); + write32(&tzpc->decprot3set, DECPROTXSET); + } +}

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Patch set updated for coreboot: Exynos7: Add GIC initialization
by Stefan Reinauer 03 Jun '16

03 Jun '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14913 -gerrit commit 586243c73ecfa12116de5dae35407dbb6a8d5db2 Author: Akshay Saraswat <akshay.s(a)samsung.com> Date: Thu Aug 7 16:26:12 2014 +0530 Exynos7: Add GIC initialization Adding initial GIC setup for Exynos7 in this patch. Change-Id: I9bdcd8924950b5442914a2f669ecfad52ff8dd2e Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com> Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- src/soc/samsung/exynos7/Makefile.inc | 1 + src/soc/samsung/exynos7/bootblock.c | 4 ++++ src/soc/samsung/exynos7/gic.c | 32 ++++++++++++++++++++++++++++++ src/soc/samsung/exynos7/include/soc/gic.h | 33 +++++++++++++++++++++++++++++++ 4 files changed, 70 insertions(+) diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc index 93f21c2..f954bd3 100644 --- a/src/soc/samsung/exynos7/Makefile.inc +++ b/src/soc/samsung/exynos7/Makefile.inc @@ -23,6 +23,7 @@ bootblock-y += bootblock.c bootblock-y += clock.c bootblock-y += clock_init.c bootblock-y += dmc_init_lpddr4.c +bootblock-y += gic.c bootblock-y += gpio.c bootblock-y += mct.c bootblock-y += monotonic_timer.c diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c index fab66a1..2f3208b 100644 --- a/src/soc/samsung/exynos7/bootblock.c +++ b/src/soc/samsung/exynos7/bootblock.c @@ -21,6 +21,7 @@ #include <soc/clock.h> #include <soc/cpu.h> #include <soc/dmc.h> +#include <soc/gic.h> #include <soc/mct.h> #include <soc/pinmux.h> #include <soc/power.h> @@ -60,6 +61,9 @@ void bootblock_cpu_init(void) /* Initialize trustzone */ trustzone_init(); + /* Initialize GIC */ + gic_init(); + /* Set GPIOs for UART */ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART0)) exynos_pinmux_uart0(); diff --git a/src/soc/samsung/exynos7/gic.c b/src/soc/samsung/exynos7/gic.c new file mode 100644 index 0000000..17326ea --- /dev/null +++ b/src/soc/samsung/exynos7/gic.c @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/gic.h> + +/* Setting Generic Interrupt Controller */ +void gic_init(void) +{ + uint64_t addr, start = 0, end = 0; + + start = EXYNOS7_GIC_DIST_BASE + 0x80; + end = start + (NUM_GIC_INTERFACES * 0x4); + + for (addr = start; addr < end; addr += 0x4) + write32((void *)addr, GIC_DIST_VAL); + + write32((void *)EXYNOS7_GIC_CPU_INTERFACE, 0xb); + write32((void *)EXYNOS7_GIC_CPU_INTERFACE + 0x4, 0xff); +} diff --git a/src/soc/samsung/exynos7/include/soc/gic.h b/src/soc/samsung/exynos7/include/soc/gic.h new file mode 100644 index 0000000..8186dc5 --- /dev/null +++ b/src/soc/samsung/exynos7/include/soc/gic.h @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Samsung Electronics + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _CPU_SAMSUNG_EXYNOS7_GIC_H_ +#define _CPU_SAMSUNG_EXYNOS7_GIC_H_ + +#include <soc/cpu.h> + +#define EXYNOS7_GIC_DIST_BASE (EXYNOS7_GIC_BASE + 0x1000) +#define EXYNOS7_GIC_CPU_INTERFACE (EXYNOS7_GIC_BASE + 0x2000) +#define EXYNOS7_GICC_HPPIR (EXYNOS7_GIC_CPU_INTERFACE + 0x18) + +#define NUM_GIC_INTERFACES 16 +#define GIC_DIST_VAL 0xffffffff + +#define GIC_SPURIOUS_INTERRUPT 1023 + +/* Setting Generic Interrupt Controller */ +void gic_init(void); + +#endif /* _CPU_SAMSUNG_EXYNOS7_GIC_H_ */

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coreboot-gerrit June 2016