03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14914
-gerrit
commit cc69a01c6a3b23ccbd122cdcb749a1b4d9dd8b11
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 16:29:56 2014 +0530
Exynos7: Add I2C initialization
Adding initial I2C setup for Exynos7 in this patch.
Change-Id: I96970189a97d6446215c309f64d590a284756213
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/soc/samsung/exynos7/Makefile.inc | 2 +
src/soc/samsung/exynos7/i2c.c | 517 ++++++++++++++++++++++++++++++
src/soc/samsung/exynos7/include/soc/i2c.h | 80 +++++
3 files changed, 599 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index f954bd3..700c0a1 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -39,6 +39,7 @@ endif
romstage-y += alternate_cbfs.c
romstage-y += clock.c
romstage-y += gpio.c
+romstage-y += i2c.c
romstage-y += mct.c
romstage-y += monotonic_timer.c
romstage-y += pinmux.c
@@ -53,6 +54,7 @@ ramstage-y += alternate_cbfs.c
ramstage-y += clock.c
ramstage-y += cpu.c
ramstage-y += gpio.c
+ramstage-y += i2c.c
ramstage-y += mct.c
ramstage-y += monotonic_timer.c
ramstage-y += pinmux.c
diff --git a/src/soc/samsung/exynos7/i2c.c b/src/soc/samsung/exynos7/i2c.c
new file mode 100644
index 0000000..e44928e
--- /dev/null
+++ b/src/soc/samsung/exynos7/i2c.c
@@ -0,0 +1,517 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <timer.h>
+#include <arch/io.h>
+#include <soc/clock.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+
+#define I2C_WRITE 0
+#define I2C_READ 1
+
+#define I2C_OK 0
+#define I2C_NOK 1
+#define I2C_NACK 2
+#define I2C_NOK_LA 3 /* Lost arbitration */
+#define I2C_NOK_TOUT 4 /* time out */
+
+/* HSI2C specific register description */
+
+/* I2C_CTL Register bits */
+#define HSI2C_FUNC_MODE_I2C (1u << 0)
+#define HSI2C_MASTER (1u << 3)
+#define HSI2C_RXCHON (1u << 6) /* Write/Send */
+#define HSI2C_TXCHON (1u << 7) /* Read/Receive */
+#define HSI2C_SW_RST (1u << 31)
+
+/* I2C_FIFO_STAT Register bits */
+#define HSI2C_TX_FIFO_LEVEL (0x7f << 0)
+#define HSI2C_TX_FIFO_FULL (1u << 7)
+#define HSI2C_TX_FIFO_EMPTY (1u << 8)
+#define HSI2C_RX_FIFO_LEVEL (0x7f << 16)
+#define HSI2C_RX_FIFO_FULL (1u << 23)
+#define HSI2C_RX_FIFO_EMPTY (1u << 24)
+
+/* I2C_FIFO_CTL Register bits */
+#define HSI2C_RXFIFO_EN (1u << 0)
+#define HSI2C_TXFIFO_EN (1u << 1)
+#define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16)
+#define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4)
+
+/* I2C_TRAILING_CTL Register bits */
+#define HSI2C_TRAILING_COUNT (0xff)
+
+/* I2C_INT_EN Register bits */
+#define HSI2C_INT_TX_ALMOSTEMPTY_EN (1u << 0)
+#define HSI2C_INT_RX_ALMOSTFULL_EN (1u << 1)
+#define HSI2C_INT_TRAILING_EN (1u << 6)
+#define HSI2C_INT_I2C_EN (1u << 9)
+
+/* I2C_CONF Register bits */
+#define HSI2C_AUTO_MODE (1u << 31)
+#define HSI2C_10BIT_ADDR_MODE (1u << 30)
+#define HSI2C_HS_MODE (1u << 29)
+
+/* I2C_AUTO_CONF Register bits */
+#define HSI2C_READ_WRITE (1u << 16)
+#define HSI2C_STOP_AFTER_TRANS (1u << 17)
+#define HSI2C_MASTER_RUN (1u << 31)
+
+/* I2C_TIMEOUT Register bits */
+#define HSI2C_TIMEOUT_EN (1u << 31)
+
+/* I2C_TRANS_STATUS register bits */
+#define HSI2C_MASTER_BUSY (1u << 17)
+#define HSI2C_SLAVE_BUSY (1u << 16)
+#define HSI2C_TIMEOUT_AUTO (1u << 11)
+/* In INT_STATUS for Exynos7 */
+#define HSI2C_NO_DEV (1u << 10)
+#define HSI2C_NO_DEV_ACK (1u << 9)
+#define HSI2C_TRANS_ABORT (1u << 8)
+#define HSI2C_TRANS_DONE (1u << 7)
+#define HSI2C_INT_STATUS_BITS (HSI2C_TIMEOUT_AUTO | HSI2C_NO_DEV \
+ | HSI2C_NO_DEV_ACK | HSI2C_TRANS_ABORT \
+ | HSI2C_TRANS_DONE)
+#define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10)
+
+#define HSI2C_TIMEOUT 100
+
+/* The timeouts we live by */
+enum {
+ I2C_XFER_TIMEOUT_MS = 35, /* xfer to complete */
+ I2C_INIT_TIMEOUT_MS = 1000, /* bus free on init */
+ I2C_IDLE_TIMEOUT_MS = 100, /* waiting for bus idle */
+ I2C_STOP_TIMEOUT_US = 200, /* waiting for stop events */
+};
+
+static struct exynos_i2c_bus i2c_buses[] = {
+ {
+ .bus_num = 0,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C0_BASE,
+ .periph_id = PERIPH_ID_I2C0,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 1,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C1_BASE,
+ .periph_id = PERIPH_ID_I2C1,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 2,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C2_BASE,
+ .periph_id = PERIPH_ID_I2C2,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 3,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C3_BASE,
+ .periph_id = PERIPH_ID_I2C3,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 4,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C4_BASE,
+ .periph_id = PERIPH_ID_I2C4,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 5,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C5_BASE,
+ .periph_id = PERIPH_ID_I2C5,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 6,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C6_BASE,
+ .periph_id = PERIPH_ID_I2C6,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 7,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C7_BASE,
+ .periph_id = PERIPH_ID_I2C7,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 8,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C8_BASE,
+ .periph_id = PERIPH_ID_I2C8,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 9,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C9_BASE,
+ .periph_id = PERIPH_ID_I2C9,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 10,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C10_BASE,
+ .periph_id = PERIPH_ID_I2C10,
+ .is_highspeed = 1,
+ },
+ {
+ .bus_num = 11,
+ .hsregs = (struct exynos7_hsi2c *)EXYNOS7_HSI2C11_BASE,
+ .periph_id = PERIPH_ID_I2C11,
+ .is_highspeed = 1,
+ },
+};
+
+static int hsi2c_get_clk_details(struct exynos_i2c_bus *i2c_bus,
+ unsigned int bus_freq_hz)
+{
+ struct exynos7_hsi2c *hsregs = i2c_bus->hsregs;
+ unsigned long clkin = get_i2c_clk();
+ unsigned int i = 0, utemp0 = 0, utemp1 = 0;
+ unsigned int t_ftl_cycle;
+
+ /*
+ * FPCLK / FI2C =
+ * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE
+ * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2)
+ * uTemp1 = (TSCLK_L + TSCLK_H + 2)
+ * uTemp2 = TSCLK_L + TSCLK_H
+ */
+ t_ftl_cycle = (read32(&hsregs->usi_conf) >> 16) & 0x7;
+ utemp0 = (clkin / bus_freq_hz) - 8 - t_ftl_cycle;
+
+ /* CLK_DIV max is 256 */
+ for (i = 0; i < 256; i++) {
+ utemp1 = utemp0 / (i + 1);
+ if ((utemp1 < 512) && (utemp1 > 4)) {
+ i2c_bus->clk_cycle = utemp1 - 2;
+ i2c_bus->clk_div = i;
+ return 0;
+ }
+ }
+ printk(BIOS_ERR, "%s: failed?\n", __func__);
+ return -1;
+}
+
+static void hsi2c_ch_init(struct exynos_i2c_bus *i2c_bus,
+ unsigned int bus_freq_hz)
+{
+ struct exynos7_hsi2c *hsregs = i2c_bus->hsregs;
+ unsigned int t_sr_release;
+ unsigned int n_clkdiv;
+ unsigned int t_start_su, t_start_hd;
+ unsigned int t_stop_su;
+ unsigned int t_data_su, t_data_hd;
+ unsigned int t_scl_l, t_scl_h;
+ u32 i2c_timing_s1;
+ u32 i2c_timing_s2;
+ u32 i2c_timing_s3;
+ u32 i2c_timing_sla;
+
+ hsi2c_get_clk_details(i2c_bus, bus_freq_hz);
+
+ n_clkdiv = i2c_bus->clk_div;
+ t_scl_l = i2c_bus->clk_cycle / 2;
+ t_scl_h = i2c_bus->clk_cycle / 2;
+ t_start_su = t_scl_l;
+ t_start_hd = t_scl_l;
+ t_stop_su = t_scl_l;
+ t_data_su = t_scl_l / 2;
+ t_data_hd = t_scl_l / 2;
+ t_sr_release = i2c_bus->clk_cycle;
+
+ i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8;
+ i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0;
+ i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0;
+ i2c_timing_sla = t_data_hd << 0;
+
+ write32(&hsregs->usi_trailing_ctl, HSI2C_TRAILING_COUNT);
+
+ /* Clear to enable Timeout */
+ clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0);
+
+ write32(&hsregs->usi_conf, read32(&hsregs->usi_conf) | HSI2C_AUTO_MODE);
+
+ /* Currently operating in Fast speed mode. */
+ write32(&hsregs->usi_timing_fs1, i2c_timing_s1);
+ write32(&hsregs->usi_timing_fs2, i2c_timing_s2);
+ write32(&hsregs->usi_timing_fs3, i2c_timing_s3);
+ write32(&hsregs->usi_timing_sla, i2c_timing_sla);
+
+ /* Enable TXFIFO and RXFIFO */
+ write32(&hsregs->usi_fifo_ctl, HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN);
+
+ /* i2c_conf configure */
+ write32(&hsregs->usi_conf, read32(&hsregs->usi_conf) | HSI2C_AUTO_MODE);
+}
+
+/* SW reset for the high speed bus */
+static void i2c_reset(struct exynos_i2c_bus *i2c_bus)
+{
+ struct exynos7_hsi2c *i2c = i2c_bus->hsregs;
+ u32 i2c_ctl;
+
+ /* Set and clear the bit for reset */
+ i2c_ctl = read32(&i2c->usi_ctl);
+ i2c_ctl |= HSI2C_SW_RST;
+ write32(&i2c->usi_ctl, i2c_ctl);
+
+ i2c_ctl = read32(&i2c->usi_ctl);
+ i2c_ctl &= ~HSI2C_SW_RST;
+ write32(&i2c->usi_ctl, i2c_ctl);
+
+ /* Initialize the configure registers */
+ hsi2c_ch_init(i2c_bus, 100000); /* 100 KHz*/
+}
+
+void i2c_init(unsigned bus_num, int speed, int slaveadd)
+{
+ struct exynos_i2c_bus *i2c;
+
+ i2c = &i2c_buses[bus_num];
+
+ i2c_reset(i2c);
+
+ hsi2c_ch_init(i2c, speed);
+}
+
+/*
+ * Check whether the transfer is complete.
+ * Return values:
+ * 0 - transfer not done
+ * 1 - transfer finished successfully
+ * -1 - transfer failed
+ */
+static int hsi2c_check_transfer(struct exynos7_hsi2c *i2c)
+{
+ uint32_t status = read32(&i2c->usi_int_stat);
+ uint32_t trans_status = read32(&i2c->usi_trans_status);
+
+ if (status & (HSI2C_TRANS_ABORT | HSI2C_NO_DEV_ACK |
+ HSI2C_NO_DEV | HSI2C_TIMEOUT_AUTO)) {
+ if (status & HSI2C_TRANS_ABORT)
+ printk(BIOS_ERR,
+ "%s: Transaction aborted.\n", __func__);
+ if (status & HSI2C_NO_DEV_ACK)
+ printk(BIOS_ERR,
+ "%s: No ack from device.\n", __func__);
+ if (status & HSI2C_NO_DEV)
+ printk(BIOS_ERR,
+ "%s: No response from device.\n", __func__);
+ if (status & HSI2C_TIMEOUT_AUTO)
+ printk(BIOS_ERR,
+ "%s: Transaction time out.\n", __func__);
+ return -1;
+ }
+ return !(trans_status & HSI2C_MASTER_BUSY);
+}
+
+/*
+ * Wait for the transfer to finish.
+ * Return values:
+ * 0 - transfer not done
+ * 1 - transfer finished successfully
+ * -1 - transfer failed
+ */
+static int hsi2c_wait_for_transfer(struct exynos7_hsi2c *i2c)
+{
+ struct mono_time current, end;
+
+ timer_monotonic_get(¤t);
+ end = current;
+ mono_time_add_usecs(&end, HSI2C_TIMEOUT * 1000);
+ while (mono_time_before(¤t, &end)) {
+ int ret = hsi2c_check_transfer(i2c);
+ if (ret)
+ return ret;
+ udelay(5);
+ timer_monotonic_get(¤t);
+ }
+ return 0;
+}
+
+static int hsi2c_senddata(struct exynos7_hsi2c *i2c, const uint8_t *data,
+ int len)
+{
+ while (!hsi2c_check_transfer(i2c) && len) {
+ if (!(read32(&i2c->usi_fifo_stat) & HSI2C_TX_FIFO_FULL)) {
+ write32(&i2c->usi_txdata, *data++);
+ len--;
+ }
+ }
+ return len ? -1 : 0;
+}
+
+static int hsi2c_recvdata(struct exynos7_hsi2c *i2c, uint8_t *data, int len)
+{
+ while (!hsi2c_check_transfer(i2c) && len) {
+ if (!(read32(&i2c->usi_fifo_stat) & HSI2C_RX_FIFO_EMPTY)) {
+ *data++ = read32(&i2c->usi_rxdata);
+ len--;
+ }
+ }
+ return len ? -1 : 0;
+}
+
+static int hsi2c_write(struct exynos7_hsi2c *i2c,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char alen,
+ const uint8_t data[],
+ unsigned short len)
+{
+ uint32_t i2c_auto_conf;
+
+ write32(&i2c->usi_int_en, HSI2C_INT_STATUS_BITS);
+ if (hsi2c_wait_for_transfer(i2c) != 1)
+ return -1;
+
+ /* chip address */
+ write32(&i2c->i2c_addr, HSI2C_SLV_ADDR_MAS(chip));
+
+ /* usi_ctl enable i2c func, master write configure */
+ write32(&i2c->usi_ctl,
+ (HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER));
+
+ /* auto_conf for write length and stop configure */
+ i2c_auto_conf = ((len + alen) | HSI2C_STOP_AFTER_TRANS);
+ i2c_auto_conf &= ~HSI2C_READ_WRITE;
+ /* Master run, start xfer */
+ i2c_auto_conf |= HSI2C_MASTER_RUN;
+ write32(&i2c->usi_auto_conf, i2c_auto_conf);
+
+ if (hsi2c_senddata(i2c, addr, alen) ||
+ hsi2c_senddata(i2c, data, len) ||
+ hsi2c_wait_for_transfer(i2c) != 1)
+ return -1;
+
+ write32(&i2c->usi_ctl, HSI2C_FUNC_MODE_I2C);
+ return 0;
+}
+
+static int hsi2c_read(struct exynos7_hsi2c *i2c,
+ unsigned char chip,
+ unsigned char addr[],
+ unsigned char alen,
+ uint8_t data[],
+ unsigned short len,
+ int check)
+{
+ uint32_t i2c_auto_conf;
+
+ write32(&i2c->usi_int_en, HSI2C_INT_STATUS_BITS);
+ /* start read */
+ if (hsi2c_wait_for_transfer(i2c) != 1)
+ return -1;
+
+ /* chip address */
+ write32(&i2c->i2c_addr, HSI2C_SLV_ADDR_MAS(chip));
+
+ if (alen) {
+ /* usi_ctl enable i2c func, master write configure */
+ write32(&i2c->usi_ctl,
+ HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER);
+
+ /* auto_conf */
+ write32(&i2c->usi_auto_conf,
+ alen | HSI2C_MASTER_RUN | HSI2C_STOP_AFTER_TRANS);
+
+ if (hsi2c_senddata(i2c, addr, alen) ||
+ hsi2c_wait_for_transfer(i2c) != 1)
+ return -1;
+ }
+
+ /* usi_ctl enable i2c func, master WRITE configure */
+ write32(&i2c->usi_ctl,
+ (HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER));
+
+ /* auto_conf, length and stop configure */
+ i2c_auto_conf = (len | HSI2C_STOP_AFTER_TRANS | HSI2C_READ_WRITE);
+ i2c_auto_conf |= HSI2C_MASTER_RUN;
+ /* Master run, start xfer */
+ write32(&i2c->usi_auto_conf, i2c_auto_conf);
+
+ if (hsi2c_recvdata(i2c, data, len) ||
+ hsi2c_wait_for_transfer(i2c) != 1)
+ return -1;
+
+ write32(&i2c->usi_ctl, HSI2C_FUNC_MODE_I2C);
+ return 0;
+}
+
+int i2c_read(unsigned bus, unsigned chip, unsigned addr,
+ unsigned alen, uint8_t *buf, unsigned len)
+{
+ struct exynos_i2c_bus *i2c;
+ unsigned char xaddr[4];
+ int ret;
+
+ if (alen > 4) {
+ printk(BIOS_ERR, "I2C read: addr len %d not supported\n", alen);
+ return 1;
+ }
+
+ if (alen > 0) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
+
+ i2c = &i2c_buses[bus];
+ ret = hsi2c_read(i2c->hsregs, chip, &xaddr[4 - alen],
+ alen, buf, len, 0);
+ if (ret) {
+ i2c_reset(i2c);
+ printk(BIOS_ERR,
+ "I2C read (bus %02x, chip addr %02x) failed: %d\n",
+ bus, chip, ret);
+ return 1;
+ }
+ return 0;
+}
+
+int i2c_write(unsigned bus, unsigned chip, unsigned addr,
+ unsigned alen, const uint8_t *buf, unsigned len)
+{
+ struct exynos_i2c_bus *i2c;
+ unsigned char xaddr[4];
+ int ret;
+
+ if (alen > 4) {
+ printk(BIOS_ERR, "I2C write: addr len %d not supported\n",
+ alen);
+ return 1;
+ }
+
+ if (alen > 0) {
+ xaddr[0] = (addr >> 24) & 0xFF;
+ xaddr[1] = (addr >> 16) & 0xFF;
+ xaddr[2] = (addr >> 8) & 0xFF;
+ xaddr[3] = addr & 0xFF;
+ }
+
+ i2c = &i2c_buses[bus];
+ ret = hsi2c_write(i2c->hsregs, chip, &xaddr[4 - alen],
+ alen, buf, len);
+ if (ret != 0) {
+ i2c_reset(i2c);
+ printk(BIOS_ERR,
+ "I2C write (bus %02x, chip addr %02x) failed: %d\n",
+ bus, chip, ret);
+ return 1;
+ }
+ return 0;
+}
diff --git a/src/soc/samsung/exynos7/include/soc/i2c.h b/src/soc/samsung/exynos7/include/soc/i2c.h
new file mode 100644
index 0000000..6931e21
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/i2c.h
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_I2C_H_
+#define _CPU_SAMSUNG_EXYNOS7_I2C_H_
+
+#include <stddef.h>
+#include <soc/periph.h>
+
+struct exynos_i2c {
+ u32 iiccon;
+ u32 iicstat;
+ u32 iicadd;
+ u32 iicds;
+ u32 iiclc;
+} __attribute__ ((packed));
+
+struct exynos7_hsi2c {
+ u32 usi_ctl;
+ u32 usi_fifo_ctl;
+ u32 usi_trailing_ctl;
+ u32 usi_clk_ctl;
+ u32 usi_clk_slot;
+ u32 spi_ctl;
+ u32 uart_ctl;
+ u32 res1;
+ u32 usi_int_en;
+ u32 usi_int_stat;
+ u32 usi_modem_stat;
+ u32 usi_error_stat;
+ u32 usi_fifo_stat;
+ u32 usi_txdata;
+ u32 usi_rxdata;
+ u32 res2;
+ u32 usi_conf;
+ u32 usi_auto_conf;
+ u32 usi_timeout;
+ u32 usi_manual_cmd;
+ u32 usi_trans_status;
+ u32 usi_timing_hs1;
+ u32 usi_timing_hs2;
+ u32 usi_timing_hs3;
+ u32 usi_timing_fs1;
+ u32 usi_timing_fs2;
+ u32 usi_timing_fs3;
+ u32 usi_timing_sla;
+ u32 i2c_addr;
+} __attribute__ ((packed));
+check_member(exynos7_hsi2c, i2c_addr, 0x70);
+
+struct exynos_i2c_bus {
+ int bus_num;
+ struct exynos_i2c *regs;
+ enum periph_id periph_id;
+ struct exynos7_hsi2c *hsregs;
+ int is_highspeed; /* High speed type, rather than I2C */
+ int id;
+ unsigned clk_cycle;
+ unsigned clk_div;
+};
+
+void i2c_init(unsigned bus, int speed, int slaveadd);
+
+int i2c_read(unsigned bus, unsigned chip, unsigned addr,
+ unsigned alen, uint8_t *buf, unsigned len);
+int i2c_write(unsigned bus, unsigned chip, unsigned addr,
+ unsigned alen, const uint8_t *buf, unsigned len);
+#endif /* _CPU_SAMSUNG_EXYNOS7_I2C_H_ */
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14915
-gerrit
commit 8142256cea053aed705cb53049493b7ef7bbd95e
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 18:04:34 2014 +0530
Jazz: Add support for new mainboard
Adding new mainboard directory and corresponding files for
Exynos7 based Jazz reference board.
BUG=None
BRANCH=None
TEST=Compiled and booted coreboot over Jazz with this series
Change-Id: Iad84881bca253fa405c227815104e152b22fc4fc
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
---
src/mainboard/samsung/jazz/Kconfig | 36 +++++++++++++++
src/mainboard/samsung/jazz/Kconfig.name | 2 +
src/mainboard/samsung/jazz/Makefile.inc | 24 ++++++++++
src/mainboard/samsung/jazz/board_info.txt | 1 +
src/mainboard/samsung/jazz/devicetree.cb | 18 ++++++++
src/mainboard/samsung/jazz/mainboard.c | 73 +++++++++++++++++++++++++++++++
src/mainboard/samsung/jazz/memlayout.ld | 16 +++++++
src/mainboard/samsung/jazz/romstage.c | 64 +++++++++++++++++++++++++++
8 files changed, 234 insertions(+)
diff --git a/src/mainboard/samsung/jazz/Kconfig b/src/mainboard/samsung/jazz/Kconfig
new file mode 100644
index 0000000..1d528b7
--- /dev/null
+++ b/src/mainboard/samsung/jazz/Kconfig
@@ -0,0 +1,36 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright 2014 Samsung Electronics Ltd.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_SAMSUNG_JAZZ
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_SAMSUNG_EXYNOS7
+ select BOARD_ROMSIZE_KB_4096
+ select HAVE_INIT_TIMER
+
+config MAINBOARD_DIR
+ string
+ default samsung/jazz
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Jazz"
+
+config DRAM_SIZE_MB
+ int
+ default 2048
+
+endif # BOARD_SAMSUNG_JAZZ
diff --git a/src/mainboard/samsung/jazz/Kconfig.name b/src/mainboard/samsung/jazz/Kconfig.name
new file mode 100644
index 0000000..0229585
--- /dev/null
+++ b/src/mainboard/samsung/jazz/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_SAMSUNG_JAZZ
+ bool "Jazz"
diff --git a/src/mainboard/samsung/jazz/Makefile.inc b/src/mainboard/samsung/jazz/Makefile.inc
new file mode 100644
index 0000000..6879e79
--- /dev/null
+++ b/src/mainboard/samsung/jazz/Makefile.inc
@@ -0,0 +1,24 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Samsung Electronics
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+INCLUDES += -Isrc/soc/samsung/exynos7/include/
+
+bootblock-y += memlayout.ld
+
+romstage-y += memlayout.ld
+romstage-y += romstage.c
+
+ramstage-y += mainboard.c
+ramstage-y += memlayout.ld
diff --git a/src/mainboard/samsung/jazz/board_info.txt b/src/mainboard/samsung/jazz/board_info.txt
new file mode 100644
index 0000000..b351b8e
--- /dev/null
+++ b/src/mainboard/samsung/jazz/board_info.txt
@@ -0,0 +1 @@
+Category: eval
diff --git a/src/mainboard/samsung/jazz/devicetree.cb b/src/mainboard/samsung/jazz/devicetree.cb
new file mode 100644
index 0000000..672a48e
--- /dev/null
+++ b/src/mainboard/samsung/jazz/devicetree.cb
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2014 Samsung Electronics
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/samsung/exynos7
+ device cpu_cluster 0 on end
+end
diff --git a/src/mainboard/samsung/jazz/mainboard.c b/src/mainboard/samsung/jazz/mainboard.c
new file mode 100644
index 0000000..c2487ad
--- /dev/null
+++ b/src/mainboard/samsung/jazz/mainboard.c
@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/i2c.h>
+#include <cbmem.h>
+#include <delay.h>
+#include <vbe.h>
+#include <boot/coreboot_tables.h>
+#include <arch/transition.h>
+#include <armv8/arch/cpu.h>
+#include <soc/clock.h>
+#include <soc/cpu.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
+#include <soc/pinmux.h>
+#include <soc/power.h>
+#include <stdlib.h>
+#include <symbols.h>
+
+/* Arbitrary range of DMA memory for depthcharge's drivers */
+#define DMA_START (0x77300000)
+#define DMA_SIZE (0x00100000)
+
+extern void switch_el3_to_el2(void);
+
+/* this happens after cpu_init where exynos resources are set */
+static void mainboard_init(device_t dev)
+{
+ int mmc_index, mmc_ratio = 3;
+
+ /* Sst GPIOs for SD and eMMC */
+ exynos_pinmux_mmc0();
+ exynos_pinmux_mmc2();
+
+ /* Set Clocks for SD & eMMC */
+ mmc_index = 2;
+ set_mmc_clk(mmc_index, mmc_ratio);
+ mmc_index = 0;
+ set_mmc_clk(mmc_index, mmc_ratio);
+
+ /* Load VBAR with PSCI SMC handler */
+ raw_write_vbar_el3(readl(_esram - 0x10));
+
+ switch_el3_to_el2();
+ printk(BIOS_INFO, "Switched to EL%d\n", get_current_el());
+
+ return;
+}
+
+static void mainboard_enable(device_t dev)
+{
+ dev->ops->init = &mainboard_init;
+}
+
+struct chip_operations mainboard_ops = {
+ .name = "Samsung Jazz",
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/samsung/jazz/memlayout.ld b/src/mainboard/samsung/jazz/memlayout.ld
new file mode 100644
index 0000000..a309bd3
--- /dev/null
+++ b/src/mainboard/samsung/jazz/memlayout.ld
@@ -0,0 +1,16 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/samsung/exynos7/memlayout.ld>
diff --git a/src/mainboard/samsung/jazz/romstage.c b/src/mainboard/samsung/jazz/romstage.c
new file mode 100644
index 0000000..5142b25
--- /dev/null
+++ b/src/mainboard/samsung/jazz/romstage.c
@@ -0,0 +1,64 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <cbfs.h>
+#include <cbmem.h>
+#include <stdlib.h>
+#include <types.h>
+#include <string.h>
+
+#include <console/console.h>
+#include <arch/cache.h>
+#include <arch/exception.h>
+#include <arch/stages.h>
+#include <soc/clock.h>
+#include <soc/cpu.h>
+#include <soc/gpio.h>
+#include <soc/i2c.h>
+#include <soc/periph.h>
+#include <soc/power.h>
+
+static int setup_power(void)
+{
+ return 0;
+}
+
+void main(void)
+{
+ void *entry;
+ int power_init_failed = setup_power();
+
+#if CONFIG_EARLY_CONSOLE
+ console_init();
+#endif
+
+ if (power_init_failed)
+ die("Failed to intialize power.\n");
+
+#if 0
+ bl31_entrypoint();
+
+ /*
+ * For now, let's store PSCI handler address in memory somewhere
+ * because it's highly probable that by the time we are ready to
+ * switch the exception level vbar_el3 has already have overwritten
+ */
+ writel((uint32_t) (uintptr_t) &runtime_exceptions, (_esram - 0x10));
+#endif
+
+ entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage");
+
+ stage_exit(entry);
+}
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14907
-gerrit
commit 43c2b935cddc83ed4b5dede617553d0626713ed4
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 15:18:33 2014 +0530
Exynos7: Add DRAM initialization
Adding LPDDR4 initialization so that it could be used by upcoming
bootloader stages and kernel.
Change-Id: I1d05833cd7bbceffddc024488df9516cfc775176
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/soc/samsung/exynos7/Makefile.inc | 1 +
src/soc/samsung/exynos7/bootblock.c | 4 +
src/soc/samsung/exynos7/dmc_init_lpddr4.c | 590 ++++++++
src/soc/samsung/exynos7/include/soc/asp.h | 228 ++++
src/soc/samsung/exynos7/include/soc/dmc.h | 79 ++
src/soc/samsung/exynos7/include/soc/drex.h | 1077 +++++++++++++++
src/soc/samsung/exynos7/include/soc/phy.h | 2029 ++++++++++++++++++++++++++++
7 files changed, 4008 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index 0df62c5..f2b7b16 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -21,6 +21,7 @@ INCLUDES += -Isrc/soc/samsung/exynos7/include/
bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += clock_init.c
+bootblock-y += dmc_init_lpddr4.c
bootblock-y += power.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index ec64723..c197940 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -20,6 +20,7 @@
#include <soc/clock.h>
#include <soc/cpu.h>
+#include <soc/dmc.h>
#include <soc/power.h>
void bootblock_cpu_init(void)
@@ -44,4 +45,7 @@ void bootblock_cpu_init(void)
if (system_clock_init(is_resume))
while(1)
;
+
+ /* Initialize SDRAM */
+ mem_ctrl_init_lpddr4(is_resume);
}
diff --git a/src/soc/samsung/exynos7/dmc_init_lpddr4.c b/src/soc/samsung/exynos7/dmc_init_lpddr4.c
new file mode 100644
index 0000000..71d42b8
--- /dev/null
+++ b/src/soc/samsung/exynos7/dmc_init_lpddr4.c
@@ -0,0 +1,590 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <types.h>
+#include <delay.h>
+
+#include <soc/asp.h>
+#include <soc/clock.h>
+#include <soc/dmc.h>
+#include <soc/drex.h>
+#include <soc/phy.h>
+#include <soc/power.h>
+
+static volatile asp_regs_t * asp[] = {
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP0_BASE,
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP1_BASE,
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP2_BASE,
+ (volatile asp_regs_t *)EXYNOS7_DMC_ASP3_BASE
+};
+
+static volatile phy_regs_t * phy[] = {
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY0_BASE,
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY1_BASE,
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY2_BASE,
+ (volatile phy_regs_t *)EXYNOS7_DMC_PHY3_BASE
+};
+
+static volatile drex_regs_t * drex[] = {
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX0_BASE,
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX1_BASE,
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX2_BASE,
+ (volatile drex_regs_t *)EXYNOS7_DMC_DREX3_BASE
+};
+
+static volatile vtmon_regs_t * vtmon[] = {
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON0_BASE,
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON1_BASE,
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON2_BASE,
+ (volatile vtmon_regs_t *)EXYNOS7_DMC_VTMON3_BASE
+};
+
+/******************************************************************************
+ *
+ * @fn dmc_reset
+ *
+ * @brief control DRAM reset signal
+ *
+ * @param reset val
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_reset(int reset)
+{
+ write32(&vtmon[3]->DRAM_RESET, reset);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_preset
+ *
+ * @brief prepare DRAM controller & phy before initialization.
+ *
+ * @param channel number
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_preset(int ch)
+{
+ drex[ch]->CONCONTROL.dfi_init_start = 0;
+ drex[ch]->CONCONTROL.timeout_level0 = 0xfff;
+ drex[ch]->CONCONTROL.same_dir_prep = 0;
+ drex[ch]->CONCONTROL.io_pd_con = 0;
+ drex[ch]->CONCONTROL.aref_en = 0;
+
+ drex[ch]->MEMCONTROL.sp_en = 0;
+ drex[ch]->MEMCONTROL.pb_ref_en = 0;
+ drex[ch]->MEMCONTROL.dbi_en = 1;
+ drex[ch]->MEMCONTROL.bl = 4;
+ drex[ch]->MEMCONTROL.num_chunk = 0;
+ drex[ch]->MEMCONTROL.num_chip = 1;
+ drex[ch]->MEMCONTROL.mem_width = 1;
+ drex[ch]->MEMCONTROL.mem_type = 8;
+ drex[ch]->MEMCONTROL.add_lat_pall = 0;
+ drex[ch]->MEMCONTROL.dsref_en = 0;
+ drex[ch]->MEMCONTROL.dpwrdn_type = 0;
+ drex[ch]->MEMCONTROL.dpwrdn_en = 0;
+ drex[ch]->MEMCONTROL.clk_stop_en = 0;
+
+ write32(&drex[ch]->CGCONTROL, 0);
+
+ drex[ch]->ZQTIMING.t_zqcs = 0x20;
+ drex[ch]->ZQTIMING.t_zqoper = 0x80;
+ drex[ch]->ZQTIMING.t_zqinit = 0x100;
+ drex[ch]->ZQTIMING.t_zqlat = 0x4;
+
+ drex[ch]->TIMINGRFCPB.t_rfcpb0 = 2;
+ drex[ch]->TIMINGRFCPB.t_rfcpb1 = 2;
+
+ drex[ch]->TIMINGAREF.t_refi = 0x5d;
+ drex[ch]->TIMINGAREF.t_refipb = 11;
+
+ write32(&drex[ch]->CGCONTROL, 0);
+
+ write32(&drex[ch]->TIMINGROW1, TIMINGROW1_VAL);
+ write32(&drex[ch]->TIMINGDATA1, TIMINGDATA1_VAL);
+ write32(&drex[ch]->TIMINGPOWER1,
+ TIMINGPOWER1_VAL);
+
+ write32(&drex[ch]->TIMINGROW0, TIMINGROW0_VAL);
+ write32(&drex[ch]->TIMINGDATA0, TIMINGDATA0_VAL);
+ write32(&drex[ch]->TIMINGPOWER0,
+ TIMINGPOWER0_VAL);
+
+ drex[ch]->TIMINGSETSW.timing_set_sw_con = 1;
+ drex[ch]->TIMINGSETSW.timing_set_sw = 1;
+
+ drex[ch]->ETCTIMING.t_mrr = 0x2;
+ drex[ch]->ETCTIMING.t_srr = 0x2;
+ drex[ch]->ETCTIMING.t_src = 0x7;
+
+ drex[ch]->RDFETCH0.vref_setting = 0xc8;
+ drex[ch]->RDFETCH0.rd_fetch = 0x2;
+
+ write32(&asp[ch]->MEMBASECONFIG0,
+ MEMBASECONFIG0_VAL);
+ write32(&asp[ch]->MEMCONFIG0, MEMCONFIG0_VAL);
+ write32(&asp[ch]->MEMCONFIG1, MEMCONFIG1_VAL);
+ write32(&asp[ch]->MEMSIZE0, MEMSIZE0_VAL);
+
+ /* No-gate training */
+ phy[ch]->CAL_CON2.ctrl_shgate = 0;
+ phy[ch]->LP_CON0.ctrl_pulld_dqs = 0xf;
+ phy[ch]->CAL_CON2.ctrl_gateadj = 0;
+ phy[ch]->CAL_CON2.ctrl_gateduradj = 0x3;
+ phy[ch]->OFFSETC_CON0.ctrl_offsetc0 = 0;
+ phy[ch]->OFFSETC_CON0.ctrl_offsetc1 = 0;
+ phy[ch]->SHIFTC_CON0.ctrl_shiftc0 = 0;
+ phy[ch]->SHIFTC_CON0.ctrl_shiftc1 = 0;
+
+ phy[ch]->GNR_CON0.ctrl_cmosrcv = 1;
+ phy[ch]->GNR_CON0.ctrl_dfdqs = 1;
+
+ phy[ch]->CAL_CON2.ctrl_readadj = 0;
+ phy[ch]->CAL_CON2.ctrl_readduradj = 3;
+ phy[ch]->CAL_CON2.ctrl_rodt_disable = 1;
+
+ phy[ch]->ZQ_CON0.zq_mode_noterm = 1;
+ phy[ch]->ZQ_CON6.zq_ds1_noterm = 1;
+ phy[ch]->ZQ_CON6.zq_ds0_noterm = 1;
+
+ phy[ch]->GNR_CON0.ctrl_bstlen = 16;
+ phy[ch]->GNR_CON0.ctrl_rdlat = 16;
+ phy[ch]->GNR_CON0.ctrl_wrlat = 8;
+ phy[ch]->GNR_CON0.ctrl_twpre = 0;
+ phy[ch]->GNR_CON0.ctrl_otf_bl = 1;
+ phy[ch]->CAL_CON0.gate_rdchk_en = 1;
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_zq_cal
+ *
+ * @brief do ZQ calibration
+ *
+ * @param channel number, zq enable
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_zq_cal(int ch, int enable)
+{
+ if (enable) {
+ phy[ch]->ZQ_CON0.zq_clk_div_en = 1;
+ phy[ch]->ZQ_CON0.zq_manual_mode = 0;
+ phy[ch]->ZQ_CON0.zq_manual_str = 1;
+ } else {
+ phy[ch]->ZQ_CON0.zq_manual_mode = 0;
+ phy[ch]->ZQ_CON0.zq_clk_div_en = 0;
+ }
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_dfi_update
+ *
+ * @brief reset resync
+ *
+ * @param channel number
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_dfi_update(int ch)
+{
+ phy[ch]->OFFSETD_CON0.ctrl_resync = 1;
+ phy[ch]->OFFSETD_CON0.ctrl_resync = 0;
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_dfi_mode
+ *
+ * @brief update dfi mode
+ *
+ * @param channel number, mode, ignore_dic val
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_dfi_mode(int ch, int mode, int ignore)
+{
+ if (ignore == 1) {
+ drex[ch]->CONCONTROL.ignore_dic = ignore;
+ drex[ch]->CONCONTROL.update_mode = mode;
+ phy[ch]->OFFSETD_CON0.upd_mode = mode;
+ } else {
+ drex[ch]->CONCONTROL.update_mode = mode;
+ phy[ch]->OFFSETD_CON0.upd_mode = mode;
+ drex[ch]->CONCONTROL.ignore_dic = ignore;
+ }
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_mrw_command
+ *
+ * @brief send MRW command
+ *
+ * @param channel number, rank, ma, operation
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_mrw_command(unsigned char ch, unsigned char rank,
+ unsigned char ma, unsigned char op)
+{
+ unsigned char bank_bf;
+ unsigned short addr_bf;
+ unsigned char addr_bf_1_0;
+ unsigned char addr_bf_12_10;
+ unsigned char addr_bf_9_2;
+
+ bank_bf = (ma >> 3) & 0x7;
+ addr_bf_12_10 = ma & 0x7;
+ addr_bf_1_0 = ma >> 6;
+ addr_bf_9_2 = op;
+
+ addr_bf = 0;
+ addr_bf = (addr_bf_12_10 << 10) | (addr_bf_9_2 << 2) | (addr_bf_1_0);
+
+ if (rank < 0)
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_MRW_COMMAND << 24) | (1 << 21) | (bank_bf << 16) | addr_bf);
+ else
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_MRW_COMMAND << 24) | (rank << 20) | (bank_bf << 16) | addr_bf);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_xsref_command
+ *
+ * @brief send XSREF command
+ *
+ * @param channel number, rank
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_xsref_command(unsigned char ch, unsigned char rank)
+{
+ if (rank < 0)
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_REFSX_COMMAND << 24) | (1 << 21));
+ else
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_REFSX_COMMAND << 24) | (rank << 20));
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_mpc_command
+ *
+ * @brief send MPC command
+ *
+ * @param channel number, rank, operation
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_mpc_command(int ch, int rank, unsigned char op)
+{
+ if (rank < 0)
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_MPC_COMMAND << 24) | (1 << 21) | (op << 2));
+ else
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_MPC_COMMAND << 24) | (rank << 20) | (op << 2));
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_epd_command
+ *
+ * @brief send EPD command
+ *
+ * @param channel number, rank
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_epd_command(int ch, int rank)
+{
+ if (rank < 0)
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_CKEL_COMMAND << 24) | (1 << 21));
+ else
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_CKEL_COMMAND << 24) | (rank << 20));
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_xpd_command
+ *
+ * @brief send XPD command
+ *
+ * @param channel, rank
+ *
+ * @return none
+ *
+ *****************************************************************************/
+static void dmc_xpd_command(int ch, int rank)
+{
+ if (rank < 0)
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_XPD_COMMAND << 24) | (1 << 21));
+ else
+ write32(&drex[ch]->DIRECTCMD,
+ (DREX_XPD_COMMAND << 24) | (rank << 20));
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_read_dq_cal
+ *
+ * @brief do read DQ calibration
+ *
+ * @param channel, rank
+ *
+ * @return calibration status
+ *
+ *****************************************************************************/
+static int dmc_read_dq_cal(int ch, int rank)
+{
+ phy[ch]->CAL_CON0.fine_train_en = 0;
+
+ phy[ch]->CAL_CON0.rd_cal_mode = 1;
+
+ drex[ch]->INITTRAINCONFIG.init_read_train_chip0 = 1;
+ drex[ch]->INITTRAINCONTROL.init_train_start = 1;
+
+ do {
+ } while (drex[ch]->PHYSTATUS.training_complete != 1);
+
+ drex[ch]->INITTRAINCONFIG.init_read_train_chip0 = 0;
+ drex[ch]->INITTRAINCONTROL.init_train_start = 0;
+
+ return (read32((void *) (uintptr_t) &phy[ch]->CAL_FAIL_STAT0) & 0xff);
+}
+
+/******************************************************************************
+ *
+ * @fn dmc_write_dq_cal
+ *
+ * @brief do write DQ calibration
+ *
+ * @param channel, rank
+ *
+ * @return calibration status
+ *
+ *****************************************************************************/
+static int dmc_write_dq_cal(int ch, int rank)
+{
+ phy[ch]->CAL_CON0.fine_train_en = 0;
+
+ phy[ch]->CAL_CON0.wr_cal_mode = 1;
+
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip0 = 1;
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip1 = 1;
+
+ drex[ch]->INITTRAINCONTROL.init_train_start = 1;
+
+ do {
+ } while (drex[ch]->PHYSTATUS.training_complete != 1);
+
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip0 = 0;
+ drex[ch]->INITTRAINCONFIG.init_write_train_chip1 = 0;
+
+ drex[ch]->INITTRAINCONTROL.init_train_start = 0;
+
+ return (read32((void *) (uintptr_t) &phy[ch]->CAL_FAIL_STAT0) & 0xff);
+}
+
+/******************************************************************************
+ *
+ * @fn mem_ctrl_init_lpddr4
+ *
+ * @brief memory initialization
+ *
+ * @param none
+ *
+ * @return none
+ *
+ *****************************************************************************/
+void mem_ctrl_init_lpddr4(int is_resume)
+{
+ unsigned int val;
+ int channel = 0;
+
+ /* Disable address hash */
+ val = read32((void *) (uintptr_t) CCORE_REMAP);
+ val &= ~0x1;
+ write32((void *)(uintptr_t)CCORE_REMAP, val);
+
+ /* Set reset signal low */
+ if (!is_resume)
+ dmc_reset(0);
+
+ for (channel = 0; channel < NUM_DMC_CH; channel++) {
+
+ if ((channel == 1) || (channel == 2)) {
+ drex[channel]->CONCONTROL.ca_swap = 1;
+ phy[channel]->CAL_CON0.ca_swap_mode = 1;
+ drex[channel]->MEMCONTROL.mrr_byte = 1;
+ } else {
+ drex[channel]->CONCONTROL.ca_swap = 0;
+ phy[channel]->CAL_CON0.ca_swap_mode = 0;
+ drex[channel]->MEMCONTROL.mrr_byte = 0;
+ }
+
+ dmc_dfi_mode(channel, 0, 1);
+ if (!is_resume) {
+ dmc_epd_command(channel, -1);
+ }
+ }
+
+ udelay(10);
+
+ /* Set reset signal high */
+ if (!is_resume)
+ dmc_reset(1);
+
+ for (channel = 0; channel < NUM_DMC_CH; channel++) {
+ dmc_preset(channel);
+
+ if ((channel == 0) || (channel == 3)) {
+ dmc_zq_cal(channel, 1);
+ while (phy[channel]->ZQ_CON1.zq_done == 0);
+ dmc_zq_cal(channel, 0);
+ }
+
+ dmc_xpd_command(channel, 0);
+ udelay(1);
+ dmc_xpd_command(channel, 1);
+ udelay(1);
+
+ dmc_mpc_command(channel, 0, LPDDR4_MPC1_ZQCAL_START);
+ udelay(1);
+ dmc_mpc_command(channel, 0, LPDDR4_MPC1_ZQCAL_LATCH);
+ udelay(1);
+ dmc_mpc_command(channel, 1, LPDDR4_MPC1_ZQCAL_START);
+ udelay(1);
+ dmc_mpc_command(channel, 1, LPDDR4_MPC1_ZQCAL_LATCH);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 13, 0x40);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 13, 0x40);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 1, 0x26);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 1, 0x26);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 2, 0x12);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 2, 0x12);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 3, 0xf1);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 3, 0xf1);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 12, 0x5d);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 12, 0x5d);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 22, 0x20);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 22, 0x20);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 14, 0x4d);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 14, 0x4d);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 11, 0x01);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 11, 0x01);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 13, 0x00);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 13, 0x00);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 13, 0xc0);
+ udelay(1);
+
+ dmc_mrw_command(channel, 1, 13, 0xc0);
+ udelay(1);
+ }
+
+ dmc_driver_freq();
+
+ for (channel = 0; channel < NUM_DMC_CH; channel++) {
+ dmc_dfi_mode(channel, 1, 0);
+
+ drex[channel]->CONCONTROL.dfi_init_start = 1;
+ while (drex[channel]->PHYSTATUS.dfi_init_complete == 0);
+
+ dmc_dfi_update(channel);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 32, (unsigned char)0x55);
+ dmc_mrw_command(channel, 1, 32, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 15, (unsigned char)0x55);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 15, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 40, (unsigned char)0x55);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 40, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_mrw_command(channel, 0, 20, (unsigned char)0x55);
+ udelay(1);
+ dmc_mrw_command(channel, 1, 20, (unsigned char)0x55);
+ udelay(1);
+
+ dmc_read_dq_cal(channel, 0);
+
+ dmc_write_dq_cal(channel, 0);
+
+ dmc_dfi_update(channel);
+
+ if (is_resume) {
+ dmc_xsref_command(channel, 0);
+ dmc_xsref_command(channel, 1);
+ }
+
+ drex[channel]->CONCONTROL.aref_en = 1;
+ drex[channel]->ALL_INT_INDI.all_init_done = 1;
+ }
+}
diff --git a/src/soc/samsung/exynos7/include/soc/asp.h b/src/soc/samsung/exynos7/include/soc/asp.h
new file mode 100644
index 0000000..01d2039
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/asp.h
@@ -0,0 +1,228 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_ASP_H_
+#define _CPU_SAMSUNG_EXYNOS7_ASP_H_
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef struct {
+ ro_bf_t no_of_regions : ( 3 - 0 + 1 );
+ ro_bf_t reserved_4_7 : ( 7 - 4 + 1 );
+ ro_bf_t address_width : ( 13 - 8 + 1 );
+ ro_bf_t reserved_14_31 : ( 31 - 14 + 1 );
+} asp_tzconfig_t;
+
+typedef struct {
+ rw_bf_t reaction_value : ( 1 - 0 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} asp_tzaction_t;
+
+typedef struct {
+ rw_bf_t lockdown_regions : ( 8 - 0 + 1 );
+ ro_bf_t reserved_9_30 : ( 30 - 9 + 1 );
+ rw_bf_t enable : ( 31 - 31 + 1 );
+} asp_tzldrange_t;
+
+typedef struct {
+ rw_bf_t region_register : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzldselect_t;
+
+typedef struct {
+ ro_bf_t status_r0 : ( 0 - 0 + 1 );
+ ro_bf_t overrun_r0 : ( 1 - 1 + 1 );
+ ro_bf_t status_w0 : ( 2 - 2 + 1 );
+ ro_bf_t overrun_w0 : ( 3 - 3 + 1 );
+ ro_bf_t status_r1 : ( 4 - 4 + 1 );
+ ro_bf_t overrun_r1 : ( 5 - 5 + 1 );
+ ro_bf_t status_w1 : ( 6 - 6 + 1 );
+ ro_bf_t overrun_w1 : ( 7 - 7 + 1 );
+ ro_bf_t status_r2 : ( 8 - 8 + 1 );
+ ro_bf_t overrun_r2 : ( 9 - 9 + 1 );
+ ro_bf_t status_w2 : ( 10 - 10 + 1 );
+ ro_bf_t overrun_w2 : ( 11 - 11 + 1 );
+ ro_bf_t status_r3 : ( 12 - 12 + 1 );
+ ro_bf_t overrun_r3 : ( 13 - 13 + 1 );
+ ro_bf_t status_w3 : ( 14 - 14 + 1 );
+ ro_bf_t overrun_w3 : ( 15 - 15 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} asp_tzinitstatus_t;
+
+typedef struct {
+ ro_bf_t int_clear : ( 31 - 0 + 1 );
+} asp_tzinitclear_t;
+
+typedef struct {
+ ro_bf_t fail_addr_low : ( 31 - 0 + 1 );
+} asp_tzfailaddrlowr_t;
+
+typedef struct {
+ ro_bf_t fail_addr_high : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_31 : ( 31 - 3 + 1 );
+} asp_tzfailaddrhighr_t;
+
+typedef struct {
+ ro_bf_t reserved_0_19 : ( 19 - 0 + 1 );
+ ro_bf_t privileged : ( 20 - 20 + 1 );
+ ro_bf_t nonsecure : ( 21 - 21 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ ro_bf_t write : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_tzfailctrlr_t;
+
+typedef struct {
+ ro_bf_t axid : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} asp_tzfailidr_t;
+
+typedef struct {
+ ro_bf_t fail_addr_low : ( 31 - 0 + 1 );
+} asp_tzfailaddrloww_t;
+
+typedef struct {
+ ro_bf_t fail_addr_high : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_31 : ( 31 - 3 + 1 );
+} asp_tzfailaddrhighw_t;
+
+typedef struct {
+ ro_bf_t reserved_0_19 : ( 19 - 0 + 1 );
+ ro_bf_t privileged : ( 20 - 20 + 1 );
+ ro_bf_t nonsecure : ( 21 - 21 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ ro_bf_t write : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_tzfailctrlw_t;
+
+typedef struct {
+ ro_bf_t axid : ( 15 - 0 + 1 );
+ ro_bf_t rsvd0 : ( 31 - 16 + 1 );
+} asp_tzfailidw_t;
+
+typedef struct {
+ ro_bf_t reserved_0_15 : ( 15 - 0 + 1 );
+ rw_bf_t base_address_low : ( 31 - 16 + 1 );
+} asp_tzrslow_t;
+
+typedef struct {
+ rw_bf_t base_address_high : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_31 : ( 31 - 3 + 1 );
+} asp_tzrshigh_t;
+
+typedef struct {
+ ro_bf_t en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_3 : ( 3 - 1 + 1 );
+ ro_bf_t size : ( 22 - 4 + 1 );
+ ro_bf_t reserved_23_27 : ( 27 - 23 + 1 );
+ rw_bf_t sp : ( 31 - 28 + 1 );
+} asp_tzrsattr_t;
+
+typedef struct {
+ rw_bf_t int_test_en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzitcrg_t;
+
+typedef struct {
+ ro_bf_t secure_boot_lock : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzitip_t;
+
+typedef struct {
+ rw_bf_t itop_int : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} asp_tzitop_t;
+
+typedef struct {
+ rw_bf_t chunk_end : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_15 : ( 15 - 8 + 1 );
+ rw_bf_t chunk_start : ( 23 - 16 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} asp_membaseconfig0_t;
+
+typedef struct {
+ rw_bf_t chunk_end : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_15 : ( 15 - 8 + 1 );
+ rw_bf_t chunk_start : ( 23 - 16 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} asp_membaseconfig1_t;
+
+typedef struct {
+ rw_bf_t chip_bank : ( 3 - 0 + 1 );
+ rw_bf_t chip_row : ( 7 - 4 + 1 );
+ rw_bf_t chip_col : ( 11 - 8 + 1 );
+ rw_bf_t chip_map : ( 15 - 12 + 1 );
+ rw_bf_t bit_sel0 : ( 16 - 16 + 1 );
+ rw_bf_t bit_sel1 : ( 17 - 17 + 1 );
+ rw_bf_t bit_sel_en_0 : ( 18 - 18 + 1 );
+ rw_bf_t bit_sel_en_1 : ( 19 - 19 + 1 );
+ rw_bf_t bank_lsb : ( 22 - 20 + 1 );
+ ro_bf_t reserved_23 : ( 23 - 23 + 1 );
+ rw_bf_t rank_inter_en : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_memconfig0_t;
+
+typedef struct {
+ rw_bf_t chip_bank : ( 3 - 0 + 1 );
+ rw_bf_t chip_row : ( 7 - 4 + 1 );
+ rw_bf_t chip_col : ( 11 - 8 + 1 );
+ rw_bf_t chip_map : ( 15 - 12 + 1 );
+ rw_bf_t bit_sel0 : ( 16 - 16 + 1 );
+ rw_bf_t bit_sel1 : ( 17 - 17 + 1 );
+ rw_bf_t bit_sel_en_0 : ( 18 - 18 + 1 );
+ rw_bf_t bit_sel_en_1 : ( 19 - 19 + 1 );
+ rw_bf_t bank_lsb : ( 22 - 20 + 1 );
+ ro_bf_t reserved_23 : ( 23 - 23 + 1 );
+ rw_bf_t rank_inter_en : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_31 : ( 31 - 25 + 1 );
+} asp_memconfig1_t;
+
+typedef struct {
+ rw_bf_t chip0_size : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} asp_memsize0_t;
+
+
+typedef struct {
+ asp_tzfailaddrlowr_t TZFAILADDRLOWR;
+ asp_tzfailaddrhighr_t TZFAILADDRHIGHR;
+ asp_tzfailctrlr_t TZFAILCTRLR;
+ asp_tzfailidr_t TZFAILIDR;
+ asp_tzfailaddrloww_t TZFAILADDRLOWW;
+ asp_tzfailaddrhighw_t TZFAILADDRHIGHW;
+ asp_tzfailctrlw_t TZFAILCTRLW;
+ asp_tzfailidw_t TZFAILIDW;
+} asp_tzfail_set_t;
+
+typedef struct {
+ asp_tzrslow_t TZRSLOW;
+ asp_tzrshigh_t TZRSHIGH;
+ asp_tzrsattr_t TZRSATTR;
+ ro_bf_t reserved_0_31;
+} asp_tzrs_set_t;
+
+typedef struct {
+ ro_bf_t reserved_0x0_0xefc[960];
+ asp_membaseconfig0_t MEMBASECONFIG0;
+ asp_membaseconfig1_t MEMBASECONFIG1;
+ ro_bf_t reserved_0x8_0xc[2];
+ asp_memconfig0_t MEMCONFIG0;
+ asp_memconfig1_t MEMCONFIG1;
+ ro_bf_t reserved_0x18_0x1c[2];
+ asp_memsize0_t MEMSIZE0;
+} asp_regs_t;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_ASP_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/dmc.h b/src/soc/samsung/exynos7/include/soc/dmc.h
new file mode 100644
index 0000000..c758ea8
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/dmc.h
@@ -0,0 +1,79 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_DMC_H_
+#define _CPU_SAMSUNG_EXYNOS7_DMC_H_
+
+#define NUM_DMC_CH 4
+#define TIMEOUT 100000
+
+/* Timing Values */
+#define TIMINGROW0_VAL 0x1D2442C7
+#define TIMINGDATA0_VAL 0x2341A350
+#define TIMINGPOWER0_VAL 0x1C1F0233
+#define TIMINGROW1_VAL 0x1D2442C7
+#define TIMINGDATA1_VAL 0x2341A350
+#define TIMINGPOWER1_VAL 0x1C1F0233
+
+/* ASP Values */
+#define MEMBASECONFIG0_VAL 0x00010004
+#define MEMCONFIG0_VAL 0x01302333
+#define MEMCONFIG1_VAL 0x01302333
+#define MEMSIZE0_VAL 0x00000001
+
+/* BLK CCORE*/
+#define CCORE_REMAP (EXYNOS7_SYSREG_BASE + 0x720)
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef enum {
+ DREX_MRW_COMMAND = 0x0,
+ DREX_PALL_COMMAND = 0x1,
+ DREX_PRE_COMMAND = 0x2,
+ DREX_MPC_COMMAND = 0x3,
+ DREX_REFS_COMMAND = 0x4,
+ DREX_REFA_COMMAND = 0x5,
+ DREX_CKEL_COMMAND = 0x6,
+ DREX_XPD_COMMAND = 0x7,
+ DREX_REFSX_COMMAND = 0x8,
+ DREX_MRR_COMMAND = 0x9,
+} drex_direct_command_t;
+
+typedef enum {
+ LPDDR4_MPC1_NOP = 0,
+ LPDDR4_MPC1_RD_FIFO = 0x41,
+ LPDDR4_MPC1_RD_DQ_CALIBRATION = 0x43,
+ LPDDR4_MPC1_WR_FIFO = 0x47,
+ LPDDR4_MPC1_START_DQS_OSC = 0x4b,
+ LPDDR4_MPC1_STOP_DQS_OSC = 0x4d,
+ LPDDR4_MPC1_ZQCAL_START = 0x4f,
+ LPDDR4_MPC1_ZQCAL_LATCH = 0x51,
+} lpddr4_mpc_mode_t;
+
+typedef struct {
+ rw_bf_t reset : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} vtmon_dram_reset_t;
+
+typedef struct {
+ ro_bf_t reserved_0x0_0x3c[16];
+ vtmon_dram_reset_t DRAM_RESET;
+} vtmon_regs_t;
+
+void mem_ctrl_init_lpddr4(int is_resume);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_DMC_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/drex.h b/src/soc/samsung/exynos7/include/soc/drex.h
new file mode 100644
index 0000000..2f20207
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/drex.h
@@ -0,0 +1,1077 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_DREX_H_
+#define _CPU_SAMSUNG_EXYNOS7_DREX_H_
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef struct {
+ rw_bf_t ca_swap : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_2 : ( 2 - 1 + 1 );
+ rw_bf_t update_mode : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4 : ( 4 - 4 + 1 );
+ rw_bf_t aref_en : ( 5 - 5 + 1 );
+ rw_bf_t io_pd_con : ( 7 - 6 + 1 );
+ ro_bf_t empty : ( 8 - 8 + 1 );
+ ro_bf_t reserved_9_11 : ( 11 - 9 + 1 );
+ rw_bf_t same_dir_prep : ( 12 - 12 + 1 );
+ ro_bf_t reserved_13_15 : ( 15 - 13 + 1 );
+ rw_bf_t timeout_level0 : ( 27 - 16 + 1 );
+ rw_bf_t dfi_init_start : ( 28 - 28 + 1 );
+ ro_bf_t reserved_29_30 : ( 30 - 29 + 1 );
+ rw_bf_t ignore_dic : ( 31 - 31 + 1 );
+} drex_concontrol_t;
+
+typedef struct {
+ rw_bf_t clk_stop_en : ( 0 - 0 + 1 );
+ rw_bf_t dpwrdn_en : ( 1 - 1 + 1 );
+ rw_bf_t dpwrdn_type : ( 3 - 2 + 1 );
+ ro_bf_t reserved_4 : ( 4 - 4 + 1 );
+ rw_bf_t dsref_en : ( 5 - 5 + 1 );
+ rw_bf_t add_lat_pall : ( 7 - 6 + 1 );
+ rw_bf_t mem_type : ( 11 - 8 + 1 );
+ rw_bf_t mem_width : ( 15 - 12 + 1 );
+ rw_bf_t num_chip : ( 17 - 16 + 1 );
+ rw_bf_t num_chunk : ( 19 - 18 + 1 );
+ rw_bf_t bl : ( 22 - 20 + 1 );
+ rw_bf_t dbi_en : ( 23 - 23 + 1 );
+ ro_bf_t reserved_24 : ( 24 - 24 + 1 );
+ rw_bf_t mrr_byte : ( 25 - 25 + 1 );
+ ro_bf_t reserved_26 : ( 26 - 26 + 1 );
+ rw_bf_t pb_ref_en : ( 27 - 27 + 1 );
+ rw_bf_t sp_en : ( 28 - 28 + 1 );
+ rw_bf_t pause_ref_en : ( 29 - 29 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_memcontrol_t;
+
+typedef struct {
+ rw_bf_t busif_rd_cg_en : ( 0 - 0 + 1 );
+ rw_bf_t busif_wr_cg_en : ( 1 - 1 + 1 );
+ rw_bf_t scg_cg_en : ( 2 - 2 + 1 );
+ rw_bf_t mif_cg_en : ( 3 - 3 + 1 );
+ rw_bf_t phy_cg_en : ( 4 - 4 + 1 );
+ rw_bf_t asp_cg_en : ( 5 - 5 + 1 );
+ rw_bf_t scg_wr_cg_en : ( 6 - 6 + 1 );
+ rw_bf_t scg_rd_cg_en : ( 7 - 7 + 1 );
+ rw_bf_t mif_wr_cg_en : ( 8 - 8 + 1 );
+ rw_bf_t mif_rd_cg_en : ( 9 - 9 + 1 );
+ ro_bf_t reserved_10_31 : ( 31 - 10 + 1 );
+} drex_cgcontrol_t;
+
+typedef struct {
+ rw_bf_t cmd_addr : ( 15 - 0 + 1 );
+ rw_bf_t cmd_bank : ( 18 - 16 + 1 );
+ rw_bf_t rsvd2 : ( 19 - 19 + 1 );
+ rw_bf_t cmd_chip : ( 20 - 20 + 1 );
+ rw_bf_t cmd_chip_all : ( 21 - 21 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t cmd_type : ( 27 - 24 + 1 );
+ ro_bf_t reserved_28_31 : ( 31 - 28 + 1 );
+} drex_directcmd_t;
+
+typedef struct {
+ ro_bf_t reserved_0_15 : ( 15 - 0 + 1 );
+ rw_bf_t port_policy : ( 19 - 16 + 1 );
+ ro_bf_t reserved_20_27 : ( 27 - 20 + 1 );
+ rw_bf_t tp_en : ( 31 - 28 + 1 );
+} drex_prechconfig0_t;
+
+typedef struct {
+ rw_bf_t mem_term_chips : ( 0 - 0 + 1 );
+ rw_bf_t sl_dll_dyn_con : ( 1 - 1 + 1 );
+ rw_bf_t drv_bus_en : ( 2 - 2 + 1 );
+ rw_bf_t fp_resync : ( 3 - 3 + 1 );
+ rw_bf_t dqs_delay : ( 6 - 4 + 1 );
+ rw_bf_t pause_no_relock : ( 7 - 7 + 1 );
+ rw_bf_t reserved_8_11 : ( 11 - 8 + 1 );
+ rw_bf_t rec_gate_cyc : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_23 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_pd : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_28 : ( 28 - 25 + 1 );
+ rw_bf_t ctrl_shgate : ( 29 - 29 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_phycontrol0_t;
+
+typedef struct {
+ rw_bf_t tp_cnt0 : ( 7 - 0 + 1 );
+ rw_bf_t tp_cnt1 : ( 15 - 8 + 1 );
+ rw_bf_t tp_cnt2 : ( 23 - 16 + 1 );
+ rw_bf_t tp_cnt3 : ( 31 - 24 + 1 );
+} drex_prechconfig1_t;
+
+typedef struct {
+ rw_bf_t t_rfcpb0 : ( 5 - 0 + 1 );
+ ro_bf_t rsvd1 : ( 7 - 6 + 1 );
+ rw_bf_t t_rfcpb1 : ( 13 - 8 + 1 );
+ ro_bf_t reserved_14_31 : ( 31 - 14 + 1 );
+} drex_timingrfcpb_t;
+
+typedef struct {
+ rw_bf_t t_zqcs : ( 7 - 0 + 1 );
+ rw_bf_t t_zqoper : ( 17 - 8 + 1 );
+ rw_bf_t t_zqinit : ( 27 - 18 + 1 );
+ rw_bf_t t_zqlat : ( 31 - 28 + 1 );
+} drex_zqtiming_t;
+
+typedef struct {
+ rw_bf_t dpwrdn_cyc : ( 7 - 0 + 1 );
+ ro_bf_t rsvd0 : ( 15 - 8 + 1 );
+ rw_bf_t dsref_cyc : ( 31 - 16 + 1 );
+} drex_pwrdnconfig_t;
+
+typedef struct {
+ rw_bf_t t_refi : ( 15 - 0 + 1 );
+ rw_bf_t t_refipb : ( 31 - 16 + 1 );
+} drex_timingaref_t;
+
+typedef struct {
+ rw_bf_t t_ras : ( 5 - 0 + 1 );
+ rw_bf_t t_rc : ( 11 - 6 + 1 );
+ rw_bf_t t_rcd : ( 15 - 12 + 1 );
+ rw_bf_t t_rp : ( 19 - 16 + 1 );
+ rw_bf_t t_rrd : ( 23 - 20 + 1 );
+ rw_bf_t t_rfc : ( 31 - 24 + 1 );
+} drex_timingrow0_t;
+
+typedef struct {
+ rw_bf_t rl : ( 5 - 0 + 1 );
+ rw_bf_t r_to_w : ( 9 - 6 + 1 );
+ rw_bf_t wl : ( 13 - 10 + 1 );
+ rw_bf_t t_r2r_c2c : ( 15 - 14 + 1 );
+ rw_bf_t t_w2w_c2c : ( 18 - 16 + 1 );
+ rw_bf_t r_to_w_5th : ( 19 - 19 + 1 );
+ rw_bf_t t_rtp : ( 23 - 20 + 1 );
+ rw_bf_t t_wr : ( 27 - 24 + 1 );
+ rw_bf_t t_wtr : ( 31 - 28 + 1 );
+} drex_timingdata0_t;
+
+typedef struct {
+ rw_bf_t t_mrd : ( 3 - 0 + 1 );
+ rw_bf_t t_cke : ( 7 - 4 + 1 );
+ rw_bf_t t_xp : ( 15 - 8 + 1 );
+ rw_bf_t t_xsr : ( 25 - 16 + 1 );
+ rw_bf_t t_faw : ( 31 - 26 + 1 );
+} drex_timingpower0_t;
+
+typedef struct {
+ ro_bf_t reserved_0_2 : ( 2 - 0 + 1 );
+ ro_bf_t dfi_init_complete : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_13 : ( 13 - 4 + 1 );
+ ro_bf_t training_complete : ( 14 - 14 + 1 );
+ ro_bf_t reserved_15_30 : ( 30 - 15 + 1 );
+ rw_bf_t timing_set_sw : ( 31 - 31 + 1 );
+} drex_phystatus_t;
+
+typedef struct {
+ ro_bf_t reserved_0_3 : ( 3 - 0 + 1 );
+ rw_bf_t t_src : ( 7 - 4 + 1 );
+ rw_bf_t t_srr : ( 9 - 8 + 1 );
+ ro_bf_t reserved_10_11 : ( 11 - 10 + 1 );
+ rw_bf_t t_mrr : ( 13 - 12 + 1 );
+ ro_bf_t reserved_14_31 : ( 31 - 14 + 1 );
+} drex_etctiming_t;
+
+typedef struct {
+ ro_bf_t chip_busy_state : ( 3 - 0 + 1 );
+ ro_bf_t chip_pd_state : ( 7 - 4 + 1 );
+ ro_bf_t chip_sref_state : ( 11 - 8 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_chipstatus_t;
+
+typedef struct {
+ rw_bf_t rd_fetch : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3 : ( 3 - 3 + 1 );
+ rw_bf_t vref_setting : ( 11 - 4 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_rdfetch0_t;
+
+typedef struct {
+ rw_bf_t rd_fetch : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3 : ( 3 - 3 + 1 );
+ rw_bf_t vref_setting : ( 11 - 4 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_rdfetch1_t;
+
+typedef struct {
+ ro_bf_t mr_status : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_mrstatus_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t phy_wrcsgap_en : ( 1 - 1 + 1 );
+ rw_bf_t ca_odt_en : ( 3 - 2 + 1 );
+ rw_bf_t ca_stable : ( 4 - 4 + 1 );
+ rw_bf_t vrcg_reset : ( 5 - 5 + 1 );
+ rw_bf_t fsp_wr : ( 6 - 6 + 1 );
+ rw_bf_t fsp_op : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_etccontrol0_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t phy_wrcsgap_en : ( 1 - 1 + 1 );
+ rw_bf_t ca_odt_en : ( 3 - 2 + 1 );
+ rw_bf_t ca_stable : ( 4 - 4 + 1 );
+ rw_bf_t vrcg_reset : ( 5 - 5 + 1 );
+ rw_bf_t fsb_wr : ( 6 - 6 + 1 );
+ rw_bf_t fsp_op : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_etccontrol1_t;
+
+typedef struct {
+ rw_bf_t cfg_qos : ( 11 - 0 + 1 );
+ ro_bf_t rsvd1 : ( 15 - 12 + 1 );
+ rw_bf_t cfg_qos_th : ( 27 - 16 + 1 );
+ ro_bf_t reserved_28_31 : ( 31 - 28 + 1 );
+} drex_qoscontrol_t;
+
+typedef struct {
+ drex_qoscontrol_t qos;
+ ro_bf_t reserved;
+}drex_qoscontroln_t;
+
+typedef struct {
+ rw_bf_t timing_set_sw_con : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_3 : ( 3 - 1 + 1 );
+ rw_bf_t timing_set_sw : ( 4 - 4 + 1 );
+ ro_bf_t reserved_5_31 : ( 31 - 5 + 1 );
+} drex_timingsetsw_t;
+
+typedef struct {
+ rw_bf_t t_ras : ( 5 - 0 + 1 );
+ rw_bf_t t_rc : ( 11 - 6 + 1 );
+ rw_bf_t t_rcd : ( 15 - 12 + 1 );
+ rw_bf_t t_rp : ( 19 - 16 + 1 );
+ rw_bf_t t_rrd : ( 23 - 20 + 1 );
+ rw_bf_t t_rfc : ( 31 - 24 + 1 );
+} drex_timingrow1_t;
+
+typedef struct {
+ rw_bf_t rl : ( 5 - 0 + 1 );
+ rw_bf_t dqsck : ( 9 - 6 + 1 );
+ rw_bf_t wl : ( 13 - 10 + 1 );
+ rw_bf_t t_r2r_c2c : ( 15 - 14 + 1 );
+ rw_bf_t t_w2w_c2c : ( 18 - 16 + 1 );
+ rw_bf_t t_to_w_5th : ( 19 - 19 + 1 );
+ rw_bf_t t_rtp : ( 23 - 20 + 1 );
+ rw_bf_t t_wr : ( 27 - 24 + 1 );
+ rw_bf_t t_wtr : ( 31 - 28 + 1 );
+} drex_timingdata1_t;
+
+typedef struct {
+ rw_bf_t t_mrd : ( 3 - 0 + 1 );
+ rw_bf_t t_cke : ( 7 - 4 + 1 );
+ rw_bf_t t_xp : ( 15 - 8 + 1 );
+ rw_bf_t t_xsr : ( 25 - 16 + 1 );
+ rw_bf_t t_faw : ( 31 - 26 + 1 );
+} drex_timingpower1_t;
+
+typedef struct {
+ rw_bf_t brb_rsv_en_r0 : ( 0 - 0 + 1 );
+ rw_bf_t brb_rsv_en_r1 : ( 1 - 1 + 1 );
+ rw_bf_t brb_rsv_en_r2 : ( 2 - 2 + 1 );
+ rw_bf_t brb_rsv_en_r3 : ( 3 - 3 + 1 );
+ rw_bf_t brb_rsv_en_w0 : ( 4 - 4 + 1 );
+ rw_bf_t brb_rsv_en_w1 : ( 5 - 5 + 1 );
+ rw_bf_t brb_rsv_en_w2 : ( 6 - 6 + 1 );
+ rw_bf_t brb_rsv_en_w3 : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_brbrsvcontrol_t;
+
+typedef struct {
+ rw_bf_t brb_rsv_th_r0 : ( 3 - 0 + 1 );
+ rw_bf_t brb_rsv_th_r1 : ( 7 - 4 + 1 );
+ rw_bf_t brb_rsv_th_r2 : ( 11 - 8 + 1 );
+ rw_bf_t brb_rsv_th_r3 : ( 15 - 12 + 1 );
+ rw_bf_t brb_rsv_th_w0 : ( 19 - 16 + 1 );
+ rw_bf_t brb_rsv_th_w1 : ( 23 - 20 + 1 );
+ rw_bf_t brb_rsv_th_w2 : ( 27 - 24 + 1 );
+ rw_bf_t brb_rsv_th_w3 : ( 31 - 28 + 1 );
+} drex_brbrsvconfig_t;
+
+typedef struct {
+ rw_bf_t brb_qos_timer_dec : ( 11 - 0 + 1 );
+ ro_bf_t reserved_12_31 : ( 31 - 12 + 1 );
+} drex_brbqosconfig_t;
+
+typedef struct {
+ rw_bf_t data_rsv_en_r0 : ( 0 - 0 + 1 );
+ rw_bf_t data_rsv_en_r1 : ( 1 - 1 + 1 );
+ rw_bf_t data_rsv_en_r2 : ( 2 - 2 + 1 );
+ rw_bf_t data_rsv_en_r3 : ( 3 - 3 + 1 );
+ rw_bf_t data_rsv_en_w0 : ( 4 - 4 + 1 );
+ rw_bf_t data_rsv_en_w1 : ( 5 - 5 + 1 );
+ rw_bf_t data_rsv_en_w2 : ( 6 - 6 + 1 );
+ rw_bf_t data_rsv_en_w3 : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_datarsvcontrol_t;
+
+typedef struct {
+ rw_bf_t data_rsv_th_r0 : ( 7 - 0 + 1 );
+ rw_bf_t data_rsv_th_r1 : ( 15 - 8 + 1 );
+ rw_bf_t data_rsv_th_r2 : ( 23 - 16 + 1 );
+ rw_bf_t data_rsv_th_r3 : ( 31 - 24 + 1 );
+} drex_rdatarsvconfig_t;
+
+typedef struct {
+ rw_bf_t data_rsv_th_w0 : ( 7 - 0 + 1 );
+ rw_bf_t data_rsv_th_w1 : ( 15 - 8 + 1 );
+ rw_bf_t data_rsv_th_w2 : ( 23 - 16 + 1 );
+ rw_bf_t data_rsv_th_w3 : ( 31 - 24 + 1 );
+} drex_wdatarsvconfig_t;
+
+typedef struct {
+ ro_bf_t reserved_0_3 : ( 3 - 0 + 1 );
+ rw_bf_t t_wlo : ( 7 - 4 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_wrlvlconfig0_t;
+
+typedef struct {
+ rw_bf_t wrlvl_wrdata_en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_wrlvlconfig1_t;
+
+typedef struct {
+ ro_bf_t wrlvl_fsm : ( 4 - 0 + 1 );
+ ro_bf_t reserved_5_31 : ( 31 - 5 + 1 );
+} drex_wrlvlstatus_t;
+
+typedef struct {
+ rw_bf_t perev_clk_en : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_ppcclkcon_t;
+
+typedef struct {
+ rw_bf_t perev0_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig0_t;
+
+typedef struct {
+ rw_bf_t perev1_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig1_t;
+
+typedef struct {
+ rw_bf_t perev2_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig2_t;
+
+typedef struct {
+ rw_bf_t perev3_sel : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_perevconfig3_t;
+
+typedef struct {
+ ro_bf_t ctrl_io_rdata : ( 31 - 0 + 1 );
+} drex_ctrl_io_rdata_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t emergent_r_config : ( 31 - 1 + 1 );
+} drex_emergent_config0_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ rw_bf_t emergent_w_config : ( 31 - 1 + 1 );
+} drex_emergent_config1_t;
+
+typedef struct {
+ rw_bf_t bp_en : ( 0 - 0 + 1 );
+ rw_bf_t bp_under_emergent : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_bp_control_t;
+
+typedef struct {
+ rw_bf_t bp_on_th_brb : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t bp_off_th_brb : ( 10 - 8 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t bp_on_th_data : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t bp_off_th_data : ( 29 - 24 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_bp_config_r_t;
+
+typedef struct {
+ rw_bf_t bp_on_th_brb : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t bp_off_th_brb : ( 10 - 8 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t bp_on_th_data : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t bp_off_th_data : ( 29 - 24 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} drex_bp_config_w_t;
+
+typedef struct {
+ drex_bp_control_t BP_CONTROL;
+ drex_bp_config_r_t BP_CONFIG_R;
+ drex_bp_config_w_t BP_CONFIG_W;
+ ro_bf_t reserved;
+}drex_bp_control_set_t;
+
+typedef struct {
+ rw_bf_t diable_fifo_emergent : ( 3 - 0 + 1 );
+ ro_bf_t reserved_4_31 : ( 31 - 4 + 1 );
+} drex_fifo_emer_config_t;
+
+typedef struct {
+ rw_bf_t ca_pipeline : ( 1 - 0 + 1 );
+ ro_bf_t reserved_2_3 : ( 3 - 2 + 1 );
+ rw_bf_t dq_pipeline : ( 6 - 4 + 1 );
+ ro_bf_t reserved_7_31 : ( 31 - 7 + 1 );
+} drex_pl_config_t;
+
+typedef struct {
+ rw_bf_t all_init_done : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_all_int_indi_t;
+
+typedef struct {
+ rw_bf_t t_rdlvl_en : ( 3 - 0 + 1 );
+ rw_bf_t t_rdlvl_rr : ( 8 - 4 + 1 );
+ ro_bf_t reserved_9_11 : ( 11 - 9 + 1 );
+ rw_bf_t t_wrtrn_en : ( 15 - 12 + 1 );
+ rw_bf_t t_wrtrn_wr : ( 19 - 16 + 1 );
+ rw_bf_t t_wrtrn_rw : ( 24 - 20 + 1 );
+ ro_bf_t reserved_25_27 : ( 27 - 25 + 1 );
+ rw_bf_t t_rdtrd : ( 31 - 28 + 1 );
+} drex_train_timing0_t;
+
+typedef struct {
+ rw_bf_t t_rdlvl_en : ( 3 - 0 + 1 );
+ rw_bf_t t_rdlvl_rr : ( 8 - 4 + 1 );
+ ro_bf_t reserved_9_11 : ( 11 - 9 + 1 );
+ rw_bf_t t_wrtrn_en : ( 15 - 12 + 1 );
+ rw_bf_t t_wrtrn_wr : ( 19 - 16 + 1 );
+ rw_bf_t t_wrtrn_rw : ( 24 - 20 + 1 );
+ ro_bf_t reserved_25_27 : ( 27 - 25 + 1 );
+ rw_bf_t t_rdtrd : ( 31 - 28 + 1 );
+} drex_train_timing1_t;
+
+typedef struct {
+ rw_bf_t t_ptrain_period : ( 23 - 0 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} drex_hw_ptrain_period0_t;
+
+typedef struct {
+ rw_bf_t t_ptrain_period : ( 23 - 0 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} drex_hw_ptrain_period1_t;
+
+typedef struct {
+ rw_bf_t init_gate_train_chip0 : ( 0 - 0 + 1 );
+ rw_bf_t init_read_train_chip0 : ( 1 - 1 + 1 );
+ rw_bf_t init_write_train_chip0 : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_15 : ( 15 - 3 + 1 );
+ rw_bf_t init_gate_train_chip1 : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t init_write_train_chip1 : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_31 : ( 31 - 19 + 1 );
+} drex_inittrainconfig_t;
+
+typedef struct {
+ rw_bf_t init_train_start : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_inittraincontrol_t;
+
+typedef struct {
+ rw_bf_t swp_gate_train : ( 0 - 0 + 1 );
+ rw_bf_t swp_read_train : ( 1 - 1 + 1 );
+ rw_bf_t swp_write_train : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_15 : ( 15 - 3 + 1 );
+ rw_bf_t gate_all_rank : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t write_all_rank : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_31 : ( 31 - 19 + 1 );
+} drex_swptrainconfig_t;
+
+typedef struct {
+ rw_bf_t swp_train_start : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} drex_swptraincontrol_t;
+
+typedef struct {
+ rw_bf_t retrain_gate : ( 0 - 0 + 1 );
+ rw_bf_t retrain_read : ( 1 - 1 + 1 );
+ rw_bf_t retrain_write : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t periodic_gate : ( 8 - 8 + 1 );
+ rw_bf_t periodic_read : ( 9 - 9 + 1 );
+ rw_bf_t periodic_write : ( 10 - 10 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t retrain_gate_all_rank : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t retrain_write_all_rank : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_23 : ( 23 - 19 + 1 );
+ rw_bf_t periodic_gate_all_rank : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25 : ( 25 - 25 + 1 );
+ rw_bf_t periodic_write_all_rank : ( 26 - 26 + 1 );
+ ro_bf_t reserved_27_31 : ( 31 - 27 + 1 );
+} drex_hwptrainconfig0_t;
+
+typedef struct {
+ rw_bf_t retrain_gate : ( 0 - 0 + 1 );
+ rw_bf_t retrain_read : ( 1 - 1 + 1 );
+ rw_bf_t retrain_write : ( 2 - 2 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t periodic_gate : ( 8 - 8 + 1 );
+ rw_bf_t periodic_read : ( 9 - 9 + 1 );
+ rw_bf_t periodic_write : ( 10 - 10 + 1 );
+ ro_bf_t reserved_11_15 : ( 15 - 11 + 1 );
+ rw_bf_t retrain_gate_all_rank : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17 : ( 17 - 17 + 1 );
+ rw_bf_t retrain_write_all_rank : ( 18 - 18 + 1 );
+ ro_bf_t reserved_19_23 : ( 23 - 19 + 1 );
+ rw_bf_t periodic_gate_all_rank : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25 : ( 25 - 25 + 1 );
+ rw_bf_t periodic_write_all_rank : ( 26 - 26 + 1 );
+ ro_bf_t reserved_27_31 : ( 31 - 27 + 1 );
+} drex_hwptrainconfig1_t;
+
+typedef struct {
+ rw_bf_t retrain_en : ( 0 - 0 + 1 );
+ rw_bf_t hw_periodic_train_en : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_hwptraincontrol0_t;
+
+typedef struct {
+ rw_bf_t retrain_en : ( 0 - 0 + 1 );
+ rw_bf_t hw_periodic_train_en : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_hwptraincontrol1_t;
+
+typedef struct {
+ rw_bf_t wrtra_wrdata_p1 : ( 15 - 0 + 1 );
+ rw_bf_t wrtra_wrdata_p0 : ( 31 - 16 + 1 );
+} drex_wrtra_pattern0_t;
+
+typedef struct {
+ rw_bf_t wrtra_wrdata_p3 : ( 15 - 0 + 1 );
+ rw_bf_t wrtra_wrdata_p2 : ( 31 - 16 + 1 );
+} drex_wrtra_pattern1_t;
+
+typedef struct {
+ rw_bf_t wrtra_wrdata_dm_p3 : ( 1 - 0 + 1 );
+ rw_bf_t wrtra_wrdata_dm_p2 : ( 3 - 2 + 1 );
+ rw_bf_t wrtra_wrdata_dm_p1 : ( 5 - 4 + 1 );
+ rw_bf_t wrtra_wrdata_dm_p0 : ( 7 - 6 + 1 );
+ rw_bf_t rsvd : ( 31 - 8 + 1 );
+} drex_wrtra_pattern2_t;
+
+typedef struct {
+ ro_bf_t csysreq : ( 0 - 0 + 1 );
+ ro_bf_t csysack : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_3 : ( 3 - 2 + 1 );
+ ro_bf_t lpi_state : ( 6 - 4 + 1 );
+ ro_bf_t reserved_7 : ( 7 - 7 + 1 );
+ ro_bf_t agent_axl_state : ( 14 - 8 + 1 );
+ ro_bf_t reserved_15 : ( 15 - 15 + 1 );
+ ro_bf_t pause_req : ( 16 - 16 + 1 );
+ ro_bf_t pause_ack : ( 17 - 17 + 1 );
+ ro_bf_t reserved_18_19 : ( 19 - 18 + 1 );
+ ro_bf_t pause_state : ( 22 - 20 + 1 );
+ ro_bf_t reserved_23_31 : ( 31 - 23 + 1 );
+} drex_lpi_pause_state_t;
+
+typedef struct {
+ ro_bf_t fifo_empty_ar : ( 3 - 0 + 1 );
+ ro_bf_t fifo_empty_aw : ( 7 - 4 + 1 );
+ ro_bf_t brb_empty_rd : ( 8 - 8 + 1 );
+ ro_bf_t brb_empty_wr : ( 9 - 9 + 1 );
+ ro_bf_t fifo_empty_bresp : ( 14 - 10 + 1 );
+ ro_bf_t reserved_15_31 : ( 31 - 15 + 1 );
+} drex_empty_state_t;
+
+typedef struct {
+ ro_bf_t occupancy_p0 : ( 7 - 0 + 1 );
+ ro_bf_t occupancy_p1 : ( 15 - 8 + 1 );
+ ro_bf_t occupancy_p2 : ( 23 - 16 + 1 );
+ ro_bf_t occupancy_p3 : ( 31 - 24 + 1 );
+} drex_rbuf_occupancy_t;
+
+typedef struct {
+ ro_bf_t occupancy_p0 : ( 7 - 0 + 1 );
+ ro_bf_t occupancy_p1 : ( 15 - 8 + 1 );
+ ro_bf_t occupancy_p2 : ( 23 - 16 + 1 );
+ ro_bf_t occupancy_p3 : ( 31 - 24 + 1 );
+} drex_wbuf_occupancy_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ ro_bf_t emergent : ( 31 - 1 + 1 );
+} drex_emergent_r_t;
+
+typedef struct {
+ ro_bf_t reserved_0 : ( 0 - 0 + 1 );
+ ro_bf_t emergent : ( 31 - 1 + 1 );
+} drex_emergent_w_t;
+
+typedef struct {
+ ro_bf_t backpressure_r : ( 3 - 0 + 1 );
+ ro_bf_t backpressure_w : ( 7 - 4 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} drex_backpressure_t;
+
+typedef struct {
+ ro_bf_t fifo_p0 : ( 3 - 0 + 1 );
+ ro_bf_t fifo_p1 : ( 7 - 4 + 1 );
+ ro_bf_t fifo_p2 : ( 11 - 8 + 1 );
+ ro_bf_t fifo_p3 : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_rfifo_valid_state_t;
+
+typedef struct {
+ ro_bf_t fifo_p0 : ( 3 - 0 + 1 );
+ ro_bf_t fifo_p1 : ( 7 - 4 + 1 );
+ ro_bf_t fifo_p2 : ( 11 - 8 + 1 );
+ ro_bf_t fifo_p3 : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_wfifo_valid_state_t;
+
+typedef struct {
+ ro_bf_t fifo_p0 : ( 3 - 0 + 1 );
+ ro_bf_t fifo_p1 : ( 7 - 4 + 1 );
+ ro_bf_t fifo_p2 : ( 11 - 8 + 1 );
+ ro_bf_t fifo_p3 : ( 15 - 12 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_cfifo_valid_state_t;
+
+typedef struct {
+ rw_bf_t r_brb : ( 31 - 0 + 1 );
+} drex_r_brb_valid_state_t;
+
+typedef struct {
+ rw_bf_t w_brb : ( 31 - 0 + 1 );
+} drex_w_brb_valid_state_t;
+
+typedef struct {
+ rw_bf_t axmarker_or_axid : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} drex_info_config_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p0_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p0_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p1_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p1_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p2_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p2_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p3_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_fifo_info_p3_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p0_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p0_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p1_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p1_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p2_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p2_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p3_0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_fifo_info_p3_1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p0_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p1_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p2_t;
+
+typedef struct {
+ ro_bf_t fifo_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t fifo_brb1_1 : ( 31 - 16 + 1 );
+} drex_c_fifo_info_p3_t;
+
+typedef struct {
+ ro_bf_t r_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_1 : ( 31 - 16 + 1 );
+} drex_r_brb0_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb0_2 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_3 : ( 31 - 16 + 1 );
+} drex_r_brb0_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb0_4 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_5 : ( 31 - 16 + 1 );
+} drex_r_brb0_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb0_6 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb0_7 : ( 31 - 16 + 1 );
+} drex_r_brb0_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_1 : ( 31 - 16 + 1 );
+} drex_r_brb1_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_2 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_3 : ( 31 - 16 + 1 );
+} drex_r_brb1_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_4 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_5 : ( 31 - 16 + 1 );
+} drex_r_brb1_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t r_brb1_6 : ( 15 - 0 + 1 );
+ ro_bf_t r_brb1_7 : ( 31 - 16 + 1 );
+} drex_r_brb1_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_0 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_1 : ( 31 - 16 + 1 );
+} drex_w_brb0_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_2 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_3 : ( 31 - 16 + 1 );
+} drex_w_brb0_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_4 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_5 : ( 31 - 16 + 1 );
+} drex_w_brb0_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb0_6 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb0_7 : ( 31 - 16 + 1 );
+} drex_w_brb0_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_0 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_1 : ( 31 - 16 + 1 );
+} drex_w_brb1_1_0_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_2 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_3 : ( 31 - 16 + 1 );
+} drex_w_brb1_3_2_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_4 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_5 : ( 31 - 16 + 1 );
+} drex_w_brb1_5_4_axid_t;
+
+typedef struct {
+ ro_bf_t w_brb1_6 : ( 15 - 0 + 1 );
+ ro_bf_t w_brb1_7 : ( 31 - 16 + 1 );
+} drex_w_brb1_7_6_axid_t;
+
+typedef struct {
+ ro_bf_t phy_upd_req : ( 0 - 0 + 1 );
+ ro_bf_t phy_upd_ack : ( 1 - 1 + 1 );
+ ro_bf_t reserved_2_31 : ( 31 - 2 + 1 );
+} drex_phy_upd_state_t;
+
+typedef struct {
+ ro_bf_t dfi_rdlvl_gate_en : ( 0 - 0 + 1 );
+ ro_bf_t dfi_rdlvl_en : ( 1 - 1 + 1 );
+ ro_bf_t dfi_rdlvl_wr_en : ( 2 - 2 + 1 );
+ ro_bf_t dfi_lvl_periodic : ( 3 - 3 + 1 );
+ ro_bf_t dfi_train_csn : ( 5 - 4 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ ro_bf_t train_state : ( 16 - 8 + 1 );
+ ro_bf_t reserved_17_31 : ( 31 - 17 + 1 );
+} drex_train_state_t;
+
+typedef struct {
+ rw_bf_t ppc_enable : ( 0 - 0 + 1 );
+ rw_bf_t ppc_counter_reset : ( 1 - 1 + 1 );
+ rw_bf_t cc_reset : ( 2 - 2 + 1 );
+ rw_bf_t cc_divider : ( 3 - 3 + 1 );
+ ro_bf_t rsvd1 : ( 15 - 4 + 1 );
+ rw_bf_t start_mode : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17_31 : ( 31 - 17 + 1 );
+} drex_pmnc_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_cntens_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_cntenc_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_intens_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_intenc_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt0 : ( 0 - 0 + 1 );
+ rw_bf_t pmcnt1 : ( 1 - 1 + 1 );
+ rw_bf_t pmcnt2 : ( 2 - 2 + 1 );
+ rw_bf_t pmcnt3 : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_30 : ( 30 - 4 + 1 );
+ rw_bf_t ccnt : ( 31 - 31 + 1 );
+} drex_flag_ppc_t;
+
+typedef struct {
+ rw_bf_t ccnt : ( 31 - 0 + 1 );
+} drex_ccnt_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt0_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt1_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt2_ppc_t;
+
+typedef struct {
+ rw_bf_t pmcnt : ( 31 - 0 + 1 );
+} drex_pmcnt3_ppc_t;
+
+
+typedef struct {
+ drex_concontrol_t CONCONTROL;
+ drex_memcontrol_t MEMCONTROL;
+ drex_cgcontrol_t CGCONTROL;
+ ro_bf_t reserved_0xC;
+ drex_directcmd_t DIRECTCMD;
+ drex_prechconfig0_t PRECHCONFIG0;
+ drex_phycontrol0_t PHYCONTROL0;
+ drex_prechconfig1_t PRECHCONFIG1;
+ drex_timingrfcpb_t TIMINGRFCPB;
+ drex_zqtiming_t ZQTIMING;
+ drex_pwrdnconfig_t PWRDNCONFIG;
+ ro_bf_t reserved_0x2C;
+ drex_timingaref_t TIMINGAREF;
+ drex_timingrow0_t TIMINGROW0;
+ drex_timingdata0_t TIMINGDATA0;
+ drex_timingpower0_t TIMINGPOWER0;
+ drex_phystatus_t PHYSTATUS;
+ drex_etctiming_t ETCTIMING;
+ drex_chipstatus_t CHIPSTATUS;
+ drex_rdfetch0_t RDFETCH0;
+ drex_rdfetch1_t RDFETCH1;
+ drex_mrstatus_t MRSTATUS;
+ drex_etccontrol0_t ETCCONTROL0;
+ drex_etccontrol1_t ETCCONTROL1;
+ drex_qoscontroln_t QOSCONTROL[16];
+ drex_timingsetsw_t TIMINGSETSW;
+ drex_timingrow1_t TIMINGROW1;
+ drex_timingdata1_t TIMINGDATA1;
+ drex_timingpower1_t TIMINGPOWER1;
+ ro_bf_t reserved_0xF0_0xFC[4];
+ drex_brbrsvcontrol_t BRBRSVCONTROL;
+ drex_brbrsvconfig_t BRBRSVCONFIG;
+ drex_brbqosconfig_t BRBQOSCONFIG;
+ drex_datarsvcontrol_t DATARSVCONTROL;
+ drex_rdatarsvconfig_t RDATARSVCONFIG;
+ drex_wdatarsvconfig_t WDATARSVCONFIG;
+ ro_bf_t reserved_0x118_0x11C[2];
+ drex_wrlvlconfig0_t WRLVLCONFIG0;
+ drex_wrlvlconfig1_t WRLVLCONFIG1;
+ drex_wrlvlstatus_t WRLVLSTATUS;
+ ro_bf_t reserved_0x12C;
+ drex_ppcclkcon_t PPCCLKCON;
+ drex_perevconfig0_t PEREVCONFIG0;
+ drex_perevconfig1_t PEREVCONFIG1;
+ drex_perevconfig2_t PEREVCONFIG2;
+ drex_perevconfig3_t PEREVCONFIG3;
+ ro_bf_t reserved_0x144_0x14C[3];
+ drex_ctrl_io_rdata_t CTRL_IO_RDATA;
+ ro_bf_t reserved_0x154_0x1FC[43];
+ drex_emergent_config0_t EMERGENT_CONFIG0;
+ drex_emergent_config1_t EMERGENT_CONFIG1;
+ ro_bf_t reserved_0x208_0x20C[2];
+ drex_bp_control_set_t BPCON[4];
+ drex_fifo_emer_config_t FIFO_EMER_CONFIG;
+ ro_bf_t reserved_0x254_0x30C[47];
+ drex_pl_config_t PL_CONFIG;
+ ro_bf_t reserved_0x314_0x3FC[59];
+ drex_all_int_indi_t ALL_INT_INDI;
+ ro_bf_t reserved_0x404_0x40C[3];
+ drex_train_timing0_t TRAIN_TIMING0;
+ drex_train_timing1_t TRAIN_TIMING1;
+ ro_bf_t reserved_0x418_0x41C[2];
+ drex_hw_ptrain_period0_t HW_PTRAIN_PERIOD0;
+ drex_hw_ptrain_period1_t HW_PTRAIN_PERIOD1;
+ ro_bf_t reserved_0x428_0x42C[2];
+ drex_inittrainconfig_t INITTRAINCONFIG;
+ drex_inittraincontrol_t INITTRAINCONTROL;
+ drex_swptrainconfig_t SWPTRAINCONFIG;
+ drex_swptraincontrol_t SWPTRAINCONTROL;
+ drex_hwptrainconfig0_t HWPTRAINCONFIG0;
+ drex_hwptrainconfig1_t HWPTRAINCONFIG1;
+ ro_bf_t reserved_0x448_0x44C[2];
+ drex_hwptraincontrol0_t HWPTRAINCONTROL0;
+ drex_hwptraincontrol1_t HWPTRAINCONTROL1;
+ ro_bf_t reserved_0x458_0x45C[2];
+ drex_wrtra_pattern0_t WRTRA_PATTERN0;
+ drex_wrtra_pattern1_t WRTRA_PATTERN1;
+ drex_wrtra_pattern2_t WRTRA_PATTERN2;
+ ro_bf_t reserved_0x46C_0x4FC[37];
+ drex_lpi_pause_state_t LPI_PAUSE_STATE;
+ drex_empty_state_t EMPTY_STATE;
+ drex_rbuf_occupancy_t RBUF_OCCUPANCY;
+ drex_wbuf_occupancy_t WBUF_OCCUPANCY;
+ drex_emergent_r_t EMERGENT_R;
+ drex_emergent_w_t EMERGENT_W;
+ drex_backpressure_t BACKPRESSURE;
+ drex_rfifo_valid_state_t RFIFO_VALID_STATE;
+ drex_wfifo_valid_state_t WFIFO_VALID_STATE;
+ drex_cfifo_valid_state_t CFIFO_VALID_STATE;
+ drex_r_brb_valid_state_t R_BRB_VALID_STATE;
+ drex_w_brb_valid_state_t W_BRB_VALID_STATE;
+ drex_info_config_t INFO_CONFIG;
+ ro_bf_t reserved_0x534_0x53C[3];
+ drex_r_fifo_info_p0_0_t R_FIFO_INFO_P0_0;
+ drex_r_fifo_info_p0_1_t R_FIFO_INFO_P0_1;
+ drex_r_fifo_info_p1_0_t R_FIFO_INFO_P1_0;
+ drex_r_fifo_info_p1_1_t R_FIFO_INFO_P1_1;
+ drex_r_fifo_info_p2_0_t R_FIFO_INFO_P2_0;
+ drex_r_fifo_info_p2_1_t R_FIFO_INFO_P2_1;
+ drex_r_fifo_info_p3_0_t R_FIFO_INFO_P3_0;
+ drex_r_fifo_info_p3_1_t R_FIFO_INFO_P3_1;
+ drex_w_fifo_info_p0_0_t W_FIFO_INFO_P0_0;
+ drex_w_fifo_info_p0_1_t W_FIFO_INFO_P0_1;
+ drex_w_fifo_info_p1_0_t W_FIFO_INFO_P1_0;
+ drex_w_fifo_info_p1_1_t W_FIFO_INFO_P1_1;
+ drex_w_fifo_info_p2_0_t W_FIFO_INFO_P2_0;
+ drex_w_fifo_info_p2_1_t W_FIFO_INFO_P2_1;
+ drex_w_fifo_info_p3_0_t W_FIFO_INFO_P3_0;
+ drex_w_fifo_info_p3_1_t W_FIFO_INFO_P3_1;
+ drex_c_fifo_info_p0_t C_FIFO_INFO_P0;
+ drex_c_fifo_info_p1_t C_FIFO_INFO_P1;
+ drex_c_fifo_info_p2_t C_FIFO_INFO_P2;
+ drex_c_fifo_info_p3_t C_FIFO_INFO_P3;
+ drex_r_brb0_1_0_axid_t R_BRB0_1_0_AXID;
+ drex_r_brb0_3_2_axid_t R_BRB0_3_2_AXID;
+ drex_r_brb0_5_4_axid_t R_BRB0_5_4_AXID;
+ drex_r_brb0_7_6_axid_t R_BRB0_7_6_AXID;
+ drex_r_brb1_1_0_axid_t R_BRB1_1_0_AXID;
+ drex_r_brb1_3_2_axid_t R_BRB1_3_2_AXID;
+ drex_r_brb1_5_4_axid_t R_BRB1_5_4_AXID;
+ drex_r_brb1_7_6_axid_t R_BRB1_7_6_AXID;
+ drex_w_brb0_1_0_axid_t W_BRB0_1_0_AXID;
+ drex_w_brb0_3_2_axid_t W_BRB0_3_2_AXID;
+ drex_w_brb0_5_4_axid_t W_BRB0_5_4_AXID;
+ drex_w_brb0_7_6_axid_t W_BRB0_7_6_AXID;
+ drex_w_brb1_1_0_axid_t W_BRB1_1_0_AXID;
+ drex_w_brb1_3_2_axid_t W_BRB1_3_2_AXID;
+ drex_w_brb1_5_4_axid_t W_BRB1_5_4_AXID;
+ drex_w_brb1_7_6_axid_t W_BRB1_7_6_AXID;
+ ro_bf_t reserved_0x5D0_0x6FC[76];
+ drex_phy_upd_state_t PHY_UPD_STATE;
+ drex_train_state_t TRAIN_STATE;
+} drex_regs_t;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_DREX_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/phy.h b/src/soc/samsung/exynos7/include/soc/phy.h
new file mode 100644
index 0000000..f639aaa
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/phy.h
@@ -0,0 +1,2029 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_PHY_H_
+#define _CPU_SAMSUNG_EXYNOS7_PHY_H_
+
+typedef volatile unsigned int rw_bf_t;
+typedef const unsigned int ro_bf_t;
+typedef const unsigned int wo_bf_t;
+
+typedef struct {
+ rw_bf_t ctrl_rdlat : ( 5 - 0 + 1 );
+ rw_bf_t ctrl_cmosrcv : ( 6 - 6 + 1 );
+ rw_bf_t ctrl_ckdis : ( 7 - 7 + 1 );
+ rw_bf_t ctrl_bstlen : ( 13 - 8 + 1 );
+ rw_bf_t ctrl_otf_bl : ( 14 - 14 + 1 );
+ rw_bf_t ctrl_twpre : ( 15 - 15 + 1 );
+ rw_bf_t ctrl_wrlat : ( 20 - 16 + 1 );
+ ro_bf_t reserved_21_23 : ( 23 - 21 + 1 );
+ rw_bf_t ctrl_ddr_mode : ( 25 - 24 + 1 );
+ rw_bf_t ctrl_dfdqs : ( 26 - 26 + 1 );
+ ro_bf_t reserved_27 : ( 27 - 27 + 1 );
+ rw_bf_t ctrl_upd_range : ( 29 - 28 + 1 );
+ rw_bf_t ctrl_upd_time : ( 31 - 30 + 1 );
+} phy_gnr_con0_t;
+
+typedef struct {
+ rw_bf_t wrlvl_mode : ( 0 - 0 + 1 );
+ rw_bf_t gate_cal_mode : ( 1 - 1 + 1 );
+ rw_bf_t ca_cal_mode : ( 2 - 2 + 1 );
+ rw_bf_t rd_cal_mode : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4 : ( 4 - 4 + 1 );
+ rw_bf_t wr_cal_mode : ( 5 - 5 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t wrlvl_start : ( 8 - 8 + 1 );
+ ro_bf_t reserved_9_15 : ( 15 - 9 + 1 );
+ ro_bf_t wrlvl_rep : ( 16 - 16 + 1 );
+ ro_bf_t reserved_17_18 : ( 18 - 17 + 1 );
+ rw_bf_t ctrl_dqs_osc_en : ( 19 - 19 + 1 );
+ rw_bf_t byte_rdlvl_en : ( 20 - 20 + 1 );
+ rw_bf_t ca_swap_mode : ( 21 - 21 + 1 );
+ rw_bf_t cal_vtc_en : ( 22 - 22 + 1 );
+ rw_bf_t freq_offset_en : ( 23 - 23 + 1 );
+ rw_bf_t dgate_en : ( 24 - 24 + 1 );
+ rw_bf_t fastdeskewen : ( 25 - 25 + 1 );
+ ro_bf_t reserved_26 : ( 26 - 26 + 1 );
+ rw_bf_t gate_rdchk_en : ( 27 - 27 + 1 );
+ rw_bf_t fine_train_en : ( 28 - 28 + 1 );
+ rw_bf_t wr_per_rank_en : ( 29 - 29 + 1 );
+ rw_bf_t wr_cs_n_default : ( 31 - 30 + 1 );
+} phy_cal_con0_t;
+
+typedef struct {
+ rw_bf_t rdlvl_periodic_incr_adj : ( 6 - 0 + 1 );
+ ro_bf_t reserved_7 : ( 7 - 7 + 1 );
+ rw_bf_t glvl_periodic_incr_adj : ( 14 - 8 + 1 );
+ ro_bf_t reserved_15 : ( 15 - 15 + 1 );
+ rw_bf_t rdlvl_pass_adj : ( 19 - 16 + 1 );
+ rw_bf_t rdlvl_incr_adj : ( 26 - 20 + 1 );
+ ro_bf_t reserved_27 : ( 27 - 27 + 1 );
+ rw_bf_t rdlvl_start_adj : ( 31 - 28 + 1 );
+} phy_cal_con1_t;
+
+typedef struct {
+ ro_bf_t reserved_0_11 : ( 11 - 0 + 1 );
+ rw_bf_t ctrl_readadj : ( 15 - 12 + 1 );
+ rw_bf_t ctrl_readduradj : ( 19 - 16 + 1 );
+ rw_bf_t ctrl_gateadj : ( 23 - 20 + 1 );
+ rw_bf_t ctrl_gateduradj : ( 27 - 24 + 1 );
+ ro_bf_t reserved_28 : ( 28 - 28 + 1 );
+ rw_bf_t ctrl_shgate : ( 29 - 29 + 1 );
+ rw_bf_t ctrl_rodt_disable : ( 30 - 30 + 1 );
+ rw_bf_t ctrl_rpre_opt : ( 31 - 31 + 1 );
+} phy_cal_con2_t;
+
+typedef struct {
+ rw_bf_t pcfg_mode : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ rw_bf_t rd_sw_mode : ( 8 - 8 + 1 );
+ rw_bf_t wr_sw_mode : ( 9 - 9 + 1 );
+ ro_bf_t reserved_10_11 : ( 11 - 10 + 1 );
+ rw_bf_t upd_ack_cycle : ( 14 - 12 + 1 );
+ ro_bf_t reserved_15 : ( 15 - 15 + 1 );
+ rw_bf_t upd_req_cycle : ( 19 - 16 + 1 );
+ rw_bf_t dvfs_wait_cycle : ( 23 - 20 + 1 );
+ rw_bf_t phyupd_req_cycle : ( 28 - 24 + 1 );
+ ro_bf_t reserved_29_31 : ( 31 - 29 + 1 );
+} phy_cal_con3_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlat_plus0 : ( 2 - 0 + 1 );
+ rw_bf_t ctrl_wrlat_plus1 : ( 5 - 3 + 1 );
+ rw_bf_t ctrl_wrlat_plus2 : ( 8 - 6 + 1 );
+ rw_bf_t ctrl_wrlat_plus3 : ( 11 - 9 + 1 );
+ rw_bf_t ctrl_wrlat_plus4 : ( 14 - 12 + 1 );
+ rw_bf_t ctrl_wrlat_plus5 : ( 17 - 15 + 1 );
+ rw_bf_t ctrl_wrlat_plus6 : ( 20 - 18 + 1 );
+ rw_bf_t ctrl_wrlat_plus7 : ( 23 - 21 + 1 );
+ rw_bf_t ctrl_wrlat_plus8 : ( 26 - 24 + 1 );
+ rw_bf_t ctrl_wrlat_plus9 : ( 27 - 27 + 1 );
+ ro_bf_t reserved_28_31 : ( 31 - 28 + 1 );
+} phy_wlat_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_pulld_dqs : ( 11 - 0 + 1 );
+ rw_bf_t pcl_pd : ( 12 - 12 + 1 );
+ rw_bf_t ds_pd : ( 13 - 13 + 1 );
+ rw_bf_t ds_io_pd : ( 14 - 14 + 1 );
+ rw_bf_t cs_io_pd : ( 15 - 15 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_lp_con0_t;
+
+typedef struct {
+ rw_bf_t rank0_dsen : ( 1 - 0 + 1 );
+ ro_bf_t reserved_2_11 : ( 11 - 2 + 1 );
+ rw_bf_t rank1_dsen : ( 13 - 12 + 1 );
+ ro_bf_t reserved_14_23 : ( 23 - 14 + 1 );
+ rw_bf_t rank_en : ( 25 - 24 + 1 );
+ ro_bf_t reserved_26_31 : ( 31 - 26 + 1 );
+} phy_gate_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetr0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetr1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetr2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetr3 : ( 31 - 24 + 1 );
+} phy_offsetr_con0_t;
+
+typedef struct {
+ ro_bf_t reserved_0_7 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetr5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetr6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetr7 : ( 31 - 24 + 1 );
+} phy_offsetr_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_offsetr_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_dq_lat_ds0 : ( 0 - 0 + 1 );
+ rw_bf_t ctrl_dq_lat_ds1 : ( 1 - 1 + 1 );
+ rw_bf_t ctrl_dq_lat_ds2 : ( 2 - 2 + 1 );
+ rw_bf_t ctrl_dq_lat_ds3 : ( 3 - 3 + 1 );
+ rw_bf_t ctrl_dq_lat_ds4 : ( 4 - 4 + 1 );
+ rw_bf_t ctrl_dq_lat_ds5 : ( 5 - 5 + 1 );
+ rw_bf_t ctrl_dq_lat_ds6 : ( 6 - 6 + 1 );
+ rw_bf_t ctrl_dq_lat_ds7 : ( 7 - 7 + 1 );
+ rw_bf_t ctrl_dq_lat_ds8 : ( 8 - 8 + 1 );
+ ro_bf_t reserved_9_31 : ( 31 - 9 + 1 );
+} phy_dqlat_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetw0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetw1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetw2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetw3 : ( 31 - 24 + 1 );
+} phy_offsetw_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetw4 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetw5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetw6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetw7 : ( 31 - 24 + 1 );
+} phy_offsetw_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetw8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_offsetw_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetr_dq : ( 5 - 0 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_offset_dq_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetc0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetc1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetc2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetc3 : ( 31 - 24 + 1 );
+} phy_offsetc_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetc4 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offsetc5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offsetc6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offsetc7 : ( 31 - 24 + 1 );
+} phy_offsetc_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_offsetc_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_shiftc0 : ( 2 - 0 + 1 );
+ rw_bf_t ctrl_shiftc1 : ( 5 - 3 + 1 );
+ rw_bf_t ctrl_shiftc2 : ( 8 - 6 + 1 );
+ rw_bf_t ctrl_shiftc3 : ( 11 - 9 + 1 );
+ rw_bf_t ctrl_shiftc4 : ( 14 - 12 + 1 );
+ rw_bf_t ctrl_shiftc5 : ( 17 - 15 + 1 );
+ rw_bf_t ctrl_shiftc6 : ( 20 - 18 + 1 );
+ rw_bf_t ctrl_shiftc7 : ( 23 - 21 + 1 );
+ rw_bf_t ctrl_shiftc8 : ( 26 - 24 + 1 );
+ ro_bf_t reserved_27_31 : ( 31 - 27 + 1 );
+} phy_shiftc_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offsetd : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_23 : ( 23 - 8 + 1 );
+ rw_bf_t ctrl_resync : ( 24 - 24 + 1 );
+ ro_bf_t reserved_25_27 : ( 27 - 25 + 1 );
+ rw_bf_t upd_mode : ( 28 - 28 + 1 );
+ ro_bf_t reserved_29_31 : ( 31 - 29 + 1 );
+} phy_offsetd_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offseto0 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offseto1 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offseto2 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offseto3 : ( 31 - 24 + 1 );
+} phy_offseto_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_offseto4 : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_offseto5 : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_offseto6 : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_offseto7 : ( 31 - 24 + 1 );
+} phy_offseto_con1_t;
+
+typedef struct {
+ ro_bf_t reserved_0_23 : ( 23 - 0 + 1 );
+ rw_bf_t ctrl_offseto8 : ( 31 - 24 + 1 );
+} phy_offseto_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl0_code : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_wrlvl1_code : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_wrlvl2_code : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_wrlvl3_code : ( 31 - 24 + 1 );
+} phy_wr_lvl_con0_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl4_code : ( 7 - 0 + 1 );
+ rw_bf_t ctrl_wrlvl5_code : ( 15 - 8 + 1 );
+ rw_bf_t ctrl_wrlvl6_code : ( 23 - 16 + 1 );
+ rw_bf_t ctrl_wrlvl7_code : ( 31 - 24 + 1 );
+} phy_wr_lvl_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl8_code : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_lvl_con2_t;
+
+typedef struct {
+ rw_bf_t ctrl_wrlvl_resync : ( 0 - 0 + 1 );
+ ro_bf_t reserved_1_31 : ( 31 - 1 + 1 );
+} phy_wr_lvl_con3_t;
+
+typedef struct {
+ rw_bf_t ca0deskewcode : ( 7 - 0 + 1 );
+ rw_bf_t ca1deskewcode : ( 15 - 8 + 1 );
+ rw_bf_t ca2deskewcode : ( 23 - 16 + 1 );
+ rw_bf_t ca3deskewcode : ( 31 - 24 + 1 );
+} phy_ca_dskew_con0_t;
+
+typedef struct {
+ rw_bf_t ca4deskewcode : ( 7 - 0 + 1 );
+ rw_bf_t ca5deskewcode : ( 15 - 8 + 1 );
+ rw_bf_t ckdeskewcode : ( 23 - 16 + 1 );
+ rw_bf_t cs0deskewcode : ( 31 - 24 + 1 );
+} phy_ca_dskew_con1_t;
+
+typedef struct {
+ rw_bf_t cs1deskewcode : ( 7 - 0 + 1 );
+ rw_bf_t cke0deskewcode : ( 15 - 8 + 1 );
+ rw_bf_t cke1deskewcode : ( 23 - 16 + 1 );
+ rw_bf_t rsvd0 : ( 31 - 24 + 1 );
+} phy_ca_dskew_con2_t;
+
+typedef struct {
+ rw_bf_t rstdeskewcode : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_ca_dskew_con4_t;
+
+typedef struct {
+ rw_bf_t wrtrn_rddata_adj_w1 : ( 15 - 0 + 1 );
+ rw_bf_t wrtrn_rddata_adj_w0 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con0_t;
+
+typedef struct {
+ rw_bf_t wrtrn_rddata_adj_w3 : ( 15 - 0 + 1 );
+ rw_bf_t wrtrn_rddata_adj_w2 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con1_t;
+
+typedef struct {
+ rw_bf_t wrtrn_rddata_dm_adj_w3 : ( 1 - 0 + 1 );
+ rw_bf_t wrtrn_rddata_dm_adj_w2 : ( 3 - 2 + 1 );
+ rw_bf_t wrtrn_rddata_dm_adj_w1 : ( 5 - 4 + 1 );
+ rw_bf_t wrtrn_rddata_dm_adj_w0 : ( 7 - 6 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_pattern_con2_t;
+
+typedef struct {
+ rw_bf_t rdtrn_rddata_adj_w1 : ( 15 - 0 + 1 );
+ rw_bf_t rdtrn_rddata_adj_w0 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con3_t;
+
+typedef struct {
+ rw_bf_t rdtrn_rddata_adj_w3 : ( 15 - 0 + 1 );
+ rw_bf_t rdtrn_rddata_adj_w2 : ( 31 - 16 + 1 );
+} phy_cal_pattern_con4_t;
+
+typedef struct {
+ rw_bf_t rdtrn_rddata_dm_adj_w3 : ( 1 - 0 + 1 );
+ rw_bf_t rdtrn_rddata_dm_adj_w2 : ( 3 - 2 + 1 );
+ rw_bf_t rdtrn_rddata_dm_adj_w1 : ( 5 - 4 + 1 );
+ rw_bf_t rdtrn_rddata_dm_adj_w0 : ( 7 - 6 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_pattern_con5_t;
+
+typedef struct {
+ rw_bf_t ctrl_half : ( 0 - 0 + 1 );
+ rw_bf_t ctrl_ref : ( 4 - 1 + 1 );
+ rw_bf_t ctrl_dll_on : ( 5 - 5 + 1 );
+ rw_bf_t ctrl_start : ( 6 - 6 + 1 );
+ rw_bf_t ctrl_force : ( 15 - 7 + 1 );
+ rw_bf_t ctrl_inc : ( 22 - 16 + 1 );
+ ro_bf_t reserved_23 : ( 23 - 23 + 1 );
+ rw_bf_t ctrl_start_point : ( 30 - 24 + 1 );
+ ro_bf_t reserved_31 : ( 31 - 31 + 1 );
+} phy_mdll_con0_t;
+
+typedef struct {
+ ro_bf_t ctrl_locked : ( 0 - 0 + 1 );
+ ro_bf_t ctrl_flock : ( 1 - 1 + 1 );
+ ro_bf_t ctrl_clock : ( 2 - 2 + 1 );
+ ro_bf_t harmonic_lock : ( 3 - 3 + 1 );
+ ro_bf_t reserved_4_7 : ( 7 - 4 + 1 );
+ ro_bf_t ctrl_lock_value : ( 16 - 8 + 1 );
+ ro_bf_t reserved_17_21 : ( 21 - 17 + 1 );
+ rw_bf_t lock_value_init_override : ( 22 - 22 + 1 );
+ ro_bf_t ctrl_lock_value_init : ( 31 - 23 + 1 );
+} phy_mdll_con1_t;
+
+typedef struct {
+ rw_bf_t dvfs0_offset : ( 7 - 0 + 1 );
+ rw_bf_t dvfs1_offset : ( 15 - 8 + 1 );
+ rw_bf_t dvfs0_dqs_osc_en : ( 16 - 16 + 1 );
+ rw_bf_t dvfs1_dqs_osc_en : ( 17 - 17 + 1 );
+ rw_bf_t dvfs0_half : ( 18 - 18 + 1 );
+ rw_bf_t dvfs1_half : ( 19 - 19 + 1 );
+ rw_bf_t dvfs0_dll_on : ( 20 - 20 + 1 );
+ rw_bf_t dvfs1_dll_on : ( 21 - 21 + 1 );
+ rw_bf_t dvfs0_rodt_disable : ( 22 - 22 + 1 );
+ rw_bf_t dvfs1_rodt_disable : ( 23 - 23 + 1 );
+ rw_bf_t dvfs_mode : ( 25 - 24 + 1 );
+ ro_bf_t reserved_26_27 : ( 27 - 26 + 1 );
+ rw_bf_t dvfs0_dgatelvl_en : ( 28 - 28 + 1 );
+ rw_bf_t dvfs1_dgatelvl_en : ( 29 - 29 + 1 );
+ rw_bf_t dvfs0_wr_per_rank_en : ( 30 - 30 + 1 );
+ rw_bf_t dvfs1_wr_per_rank_en : ( 31 - 31 + 1 );
+} phy_dvfs_con0_t;
+
+typedef struct {
+ rw_bf_t dvfs0_gateadj : ( 3 - 0 + 1 );
+ rw_bf_t dvfs0_gateduradj : ( 7 - 4 + 1 );
+ rw_bf_t dvfs1_gateadj : ( 11 - 8 + 1 );
+ rw_bf_t dvfs1_gateduradj : ( 15 - 12 + 1 );
+ rw_bf_t dvfs0_rdat : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t dvfs1_rdat : ( 29 - 24 + 1 );
+ rw_bf_t dvfs0_cmosrcv : ( 30 - 30 + 1 );
+ rw_bf_t dvfs1_cmosrcv : ( 31 - 31 + 1 );
+} phy_dvfs_con1_t;
+
+typedef struct {
+ rw_bf_t freq_train : ( 11 - 0 + 1 );
+ ro_bf_t reserved_12_17 : ( 17 - 12 + 1 );
+ rw_bf_t dvfs0_start_point : ( 24 - 18 + 1 );
+ rw_bf_t dvfs1_start_point : ( 31 - 25 + 1 );
+} phy_dvfs_con2_t;
+
+typedef struct {
+ rw_bf_t dvfs0_freq : ( 11 - 0 + 1 );
+ rw_bf_t dvfs1_freq : ( 23 - 12 + 1 );
+ ro_bf_t reserved_24_25 : ( 25 - 24 + 1 );
+ rw_bf_t dvfs0_shgate : ( 26 - 26 + 1 );
+ rw_bf_t dvfs1_shgate : ( 27 - 27 + 1 );
+ rw_bf_t dvfs0_rpre_opt : ( 28 - 28 + 1 );
+ rw_bf_t dvfs1_rpre_opt : ( 29 - 29 + 1 );
+ rw_bf_t dvfs0_twpre : ( 30 - 30 + 1 );
+ rw_bf_t dvfs1_twpre : ( 31 - 31 + 1 );
+} phy_dvfs_con3_t;
+
+typedef struct {
+ rw_bf_t dvfs0_ds0_vref : ( 5 - 0 + 1 );
+ rw_bf_t dvfs0_ds1_vref : ( 11 - 6 + 1 );
+ rw_bf_t dvfs1_ds0_vref : ( 17 - 12 + 1 );
+ rw_bf_t dvfs1_ds1_vref : ( 23 - 18 + 1 );
+ ro_bf_t reserved_24_30 : ( 30 - 24 + 1 );
+ rw_bf_t dvfs_fsbst_en : ( 31 - 31 + 1 );
+} phy_dvfs_con4_t;
+
+typedef struct {
+ rw_bf_t dvfs0_pulld_dqs : ( 3 - 0 + 1 );
+ rw_bf_t dvfs1_pulld_dqs : ( 7 - 4 + 1 );
+ rw_bf_t dvfs0_readadj : ( 11 - 8 + 1 );
+ rw_bf_t dvfs1_readadj : ( 15 - 12 + 1 );
+ rw_bf_t dvfs0_readduradj : ( 19 - 16 + 1 );
+ rw_bf_t dvfs1_readduradj : ( 23 - 20 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} phy_dvfs_con5_t;
+
+typedef struct {
+ ro_bf_t t0_rdata_en : ( 5 - 0 + 1 );
+ ro_bf_t t1_rdata_en : ( 11 - 6 + 1 );
+ ro_bf_t t2_rdata_en : ( 17 - 12 + 1 );
+ ro_bf_t t3_rdata_en : ( 23 - 18 + 1 );
+ ro_bf_t t_rddata_en : ( 28 - 24 + 1 );
+ ro_bf_t reserved_29_31 : ( 31 - 29 + 1 );
+} phy_t_rddata_con0_t;
+
+typedef struct {
+ ro_bf_t t4_rdata_en : ( 5 - 0 + 1 );
+ ro_bf_t t5_rdata_en : ( 11 - 6 + 1 );
+ ro_bf_t t6_rdata_en : ( 17 - 12 + 1 );
+ ro_bf_t t7_rdata_en : ( 23 - 18 + 1 );
+ ro_bf_t reserved_24_31 : ( 31 - 24 + 1 );
+} phy_t_rddata_con1_t;
+
+typedef struct {
+ ro_bf_t t8_rdata_en : ( 5 - 0 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_t_rddata_con2_t;
+
+typedef struct {
+ ro_bf_t dq_fail_status_sl0 : ( 7 - 0 + 1 );
+ ro_bf_t dq_fail_status_sl1 : ( 15 - 8 + 1 );
+ ro_bf_t dq_fail_status_sl2 : ( 23 - 16 + 1 );
+ ro_bf_t dq_fail_status_sl3 : ( 31 - 24 + 1 );
+} phy_cal_fail_stat0_t;
+
+typedef struct {
+ ro_bf_t dq_fail_status_sl4 : ( 7 - 0 + 1 );
+ ro_bf_t dq_fail_status_sl5 : ( 15 - 8 + 1 );
+ ro_bf_t dq_fail_status_sl6 : ( 23 - 16 + 1 );
+ ro_bf_t dq_fail_status_sl7 : ( 31 - 24 + 1 );
+} phy_cal_fail_stat1_t;
+
+typedef struct {
+ ro_bf_t dq_fail_status_sl8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_fail_stat2_t;
+
+typedef struct {
+ ro_bf_t dm_fail_status : ( 8 - 0 + 1 );
+ ro_bf_t reserved_9_31 : ( 31 - 9 + 1 );
+} phy_cal_fail_stat3_t;
+
+typedef struct {
+ ro_bf_t gt_vwmc0_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t gt_vwmc1_cs0 : ( 15 - 8 + 1 );
+ ro_bf_t gt_vwmc2_cs0 : ( 23 - 16 + 1 );
+ ro_bf_t gt_vwmc3_cs0 : ( 31 - 24 + 1 );
+} phy_cal_gt_wvmc0_t;
+
+typedef struct {
+ ro_bf_t gt_vwmc4_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t gt_vwmc5_cs0 : ( 15 - 8 + 1 );
+ ro_bf_t gt_vwmc6_cs0 : ( 23 - 16 + 1 );
+ ro_bf_t gt_vwmc7_cs0 : ( 31 - 24 + 1 );
+} phy_cal_gt_wvmc1_t;
+
+typedef struct {
+ ro_bf_t gt_vwmc8_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t rsvd0 : ( 31 - 8 + 1 );
+} phy_cal_gt_wvmc2_t;
+
+typedef struct {
+ ro_bf_t gt_cyc0_cs0 : ( 2 - 0 + 1 );
+ ro_bf_t reserved_3_7 : ( 7 - 3 + 1 );
+ ro_bf_t gt_cyc1_cs0 : ( 10 - 8 + 1 );
+ ro_bf_t reserved_11_31 : ( 31 - 11 + 1 );
+} phy_cal_gt_cyc_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmc3 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmc0_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmc7 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmc1_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_rd_vwmc2_t;
+
+typedef struct {
+ ro_bf_t rd_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwml3 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwml0_t;
+
+typedef struct {
+ ro_bf_t rd_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwml7 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwml1_t;
+
+typedef struct {
+ ro_bf_t rd_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_rd_vwml2_t;
+
+typedef struct {
+ ro_bf_t rd_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmr3 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmr0_t;
+
+typedef struct {
+ ro_bf_t rd_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t rd_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t rd_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t rd_vwmr7 : ( 31 - 24 + 1 );
+} phy_cal_rd_vwmr1_t;
+
+typedef struct {
+ ro_bf_t rd_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_rd_vwmr2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc3 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmc0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc7 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmc1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_wr_vwmc2_t;
+
+typedef struct {
+ ro_bf_t wr_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml3 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwml0_t;
+
+typedef struct {
+ ro_bf_t wr_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml7 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwml1_t;
+
+typedef struct {
+ ro_bf_t wr_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_wr_vwml2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr3 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmr0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr7 : ( 31 - 24 + 1 );
+} phy_cal_wr_vwmr1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_wr_vwmr2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc3 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmc0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmc7 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmc1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_dm_vwmc2_t;
+
+typedef struct {
+ ro_bf_t wr_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml3 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwml0_t;
+
+typedef struct {
+ ro_bf_t wr_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwml7 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwml1_t;
+
+typedef struct {
+ ro_bf_t wr_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_dm_vwml2_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr3 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmr0_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t wr_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t wr_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t wr_vwmr7 : ( 31 - 24 + 1 );
+} phy_cal_dm_vwmr1_t;
+
+typedef struct {
+ ro_bf_t wr_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_cal_dm_vwmr2_t;
+
+typedef struct {
+ ro_bf_t rd0deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd0deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd0deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd0deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con0_t;
+
+typedef struct {
+ ro_bf_t rd0deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd0deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd0deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd0deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con1_t;
+
+typedef struct {
+ ro_bf_t rd0deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con2_t;
+
+typedef struct {
+ ro_bf_t rd1deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd1deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd1deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd1deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con3_t;
+
+typedef struct {
+ ro_bf_t rd1deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd1deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd1deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd1deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con4_t;
+
+typedef struct {
+ ro_bf_t rd1deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con5_t;
+
+typedef struct {
+ ro_bf_t rd2deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd2deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd2deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd2deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con6_t;
+
+typedef struct {
+ ro_bf_t rd2deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd2deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd2deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd2deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con7_t;
+
+typedef struct {
+ ro_bf_t rd2deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con8_t;
+
+typedef struct {
+ ro_bf_t rd3deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd3deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd3deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd3deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con9_t;
+
+typedef struct {
+ ro_bf_t rd3deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd3deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd3deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd3deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con10_t;
+
+typedef struct {
+ ro_bf_t rd4deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con11_t;
+
+typedef struct {
+ ro_bf_t rd4deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd4deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd4deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd4deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con12_t;
+
+typedef struct {
+ ro_bf_t rd4deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd4deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd4deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd4deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con13_t;
+
+typedef struct {
+ ro_bf_t rd4deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con14_t;
+
+typedef struct {
+ ro_bf_t rd5deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd5deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd5deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd5deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con15_t;
+
+typedef struct {
+ ro_bf_t rd5deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd5deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd5deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd5deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con16_t;
+
+typedef struct {
+ ro_bf_t rd5deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con17_t;
+
+typedef struct {
+ ro_bf_t rd6deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd6deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd6deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd6deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con18_t;
+
+typedef struct {
+ ro_bf_t rd6deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd6deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd6deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd6deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con19_t;
+
+typedef struct {
+ ro_bf_t rd6deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con20_t;
+
+typedef struct {
+ ro_bf_t rd7deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t rd7deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t rd7deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t rd7deskew3 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con21_t;
+
+typedef struct {
+ ro_bf_t rd7deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t rd7deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t rd7deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t rd7deskew7 : ( 31 - 24 + 1 );
+} phy_rd_deskew_con22_t;
+
+typedef struct {
+ ro_bf_t rd7deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_rd_deskew_con23_t;
+
+typedef struct {
+ ro_bf_t wr0deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr0deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr0deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr0deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con0_t;
+
+typedef struct {
+ ro_bf_t wr0deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr0deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr0deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr0deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con1_t;
+
+typedef struct {
+ ro_bf_t wr0deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con2_t;
+
+typedef struct {
+ ro_bf_t wr1deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr1deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr1deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr1deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con3_t;
+
+typedef struct {
+ ro_bf_t wr1deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr1deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr1deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr1deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con4_t;
+
+typedef struct {
+ ro_bf_t wr1deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con5_t;
+
+typedef struct {
+ ro_bf_t wr2deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr2deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr2deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr2deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con6_t;
+
+typedef struct {
+ ro_bf_t wr2deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr2deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr2deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr2deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con7_t;
+
+typedef struct {
+ ro_bf_t wr2deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con8_t;
+
+typedef struct {
+ ro_bf_t wr3deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr3deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr3deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr3deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con9_t;
+
+typedef struct {
+ ro_bf_t wr3deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr3deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr3deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr3deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con10_t;
+
+typedef struct {
+ ro_bf_t wr3deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con11_t;
+
+typedef struct {
+ ro_bf_t wr4deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr4deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr4deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr4deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con12_t;
+
+typedef struct {
+ ro_bf_t wr4deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr4deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr4deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr4deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con13_t;
+
+typedef struct {
+ ro_bf_t wr4deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con14_t;
+
+typedef struct {
+ ro_bf_t wr5deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr5deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr5deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr5deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con15_t;
+
+typedef struct {
+ ro_bf_t wr5deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr5deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr5deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr5deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con16_t;
+
+typedef struct {
+ ro_bf_t wr5deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con17_t;
+
+typedef struct {
+ ro_bf_t wr6deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr6deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr6deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr6deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con18_t;
+
+typedef struct {
+ ro_bf_t wr6deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr6deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr6deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr6deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con19_t;
+
+typedef struct {
+ ro_bf_t wr6deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con20_t;
+
+typedef struct {
+ ro_bf_t wr7deskew0 : ( 7 - 0 + 1 );
+ ro_bf_t wr7deskew1 : ( 15 - 8 + 1 );
+ ro_bf_t wr7deskew2 : ( 23 - 16 + 1 );
+ ro_bf_t wr7deskew3 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con21_t;
+
+typedef struct {
+ ro_bf_t wr7deskew4 : ( 7 - 0 + 1 );
+ ro_bf_t wr7deskew5 : ( 15 - 8 + 1 );
+ ro_bf_t wr7deskew6 : ( 23 - 16 + 1 );
+ ro_bf_t wr7deskew7 : ( 31 - 24 + 1 );
+} phy_wr_deskew_con22_t;
+
+typedef struct {
+ ro_bf_t wr7deskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_wr_deskew_con23_t;
+
+typedef struct {
+ ro_bf_t dmdeskew0 : ( 7 - 0 + 1 );
+ ro_bf_t dmdeskew1 : ( 15 - 8 + 1 );
+ ro_bf_t dmdeskew2 : ( 23 - 16 + 1 );
+ ro_bf_t dmdeskew3 : ( 31 - 24 + 1 );
+} phy_dm_deskew_con0_t;
+
+typedef struct {
+ ro_bf_t dmdeskew4 : ( 7 - 0 + 1 );
+ ro_bf_t dmdeskew5 : ( 15 - 8 + 1 );
+ ro_bf_t dmdeskew6 : ( 23 - 16 + 1 );
+ ro_bf_t dmdeskew7 : ( 31 - 24 + 1 );
+} phy_dm_deskew_con1_t;
+
+typedef struct {
+ ro_bf_t dmdeskew8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_deskew_con2_t;
+
+typedef struct {
+ ro_bf_t d0_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat0_t;
+
+typedef struct {
+ ro_bf_t d0_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat1_t;
+
+typedef struct {
+ ro_bf_t d0_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat2_t;
+
+typedef struct {
+ ro_bf_t d1_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat3_t;
+
+typedef struct {
+ ro_bf_t d1_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat4_t;
+
+typedef struct {
+ ro_bf_t d1_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat5_t;
+
+typedef struct {
+ ro_bf_t d2_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat6_t;
+
+typedef struct {
+ ro_bf_t d2_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat7_t;
+
+typedef struct {
+ ro_bf_t d2_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat8_t;
+
+typedef struct {
+ ro_bf_t d3_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat9_t;
+
+typedef struct {
+ ro_bf_t d3_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat10_t;
+
+typedef struct {
+ ro_bf_t d3_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat11_t;
+
+typedef struct {
+ ro_bf_t d4_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat12_t;
+
+typedef struct {
+ ro_bf_t d4_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat13_t;
+
+typedef struct {
+ ro_bf_t d4_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat14_t;
+
+typedef struct {
+ ro_bf_t d5_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat15_t;
+
+typedef struct {
+ ro_bf_t d5_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat16_t;
+
+typedef struct {
+ ro_bf_t d5_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat17_t;
+
+typedef struct {
+ ro_bf_t d6_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat18_t;
+
+typedef struct {
+ ro_bf_t d6_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat19_t;
+
+typedef struct {
+ ro_bf_t d6_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat20_t;
+
+typedef struct {
+ ro_bf_t d7_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmc3 : ( 31 - 24 + 1 );
+} phy_vwmc_stat21_t;
+
+typedef struct {
+ ro_bf_t d7_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmc7 : ( 31 - 24 + 1 );
+} phy_vwmc_stat22_t;
+
+typedef struct {
+ ro_bf_t d7_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmc_stat23_t;
+
+typedef struct {
+ ro_bf_t dm_vwmc0 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmc1 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmc2 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmc3 : ( 31 - 24 + 1 );
+} phy_dm_vwmc_stat0_t;
+
+typedef struct {
+ ro_bf_t dm_vwmc4 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmc5 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmc6 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmc7 : ( 31 - 24 + 1 );
+} phy_dm_vwmc_stat1_t;
+
+typedef struct {
+ ro_bf_t dm_vwmc8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_vwmc_stat2_t;
+
+typedef struct {
+ ro_bf_t d0_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat0_t;
+
+typedef struct {
+ ro_bf_t d0_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat1_t;
+
+typedef struct {
+ ro_bf_t d0_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat2_t;
+
+typedef struct {
+ ro_bf_t d1_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat3_t;
+
+typedef struct {
+ ro_bf_t d1_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat4_t;
+
+typedef struct {
+ ro_bf_t d1_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat5_t;
+
+typedef struct {
+ ro_bf_t d2_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat6_t;
+
+typedef struct {
+ ro_bf_t d2_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat7_t;
+
+typedef struct {
+ ro_bf_t d2_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat8_t;
+
+typedef struct {
+ ro_bf_t d3_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat9_t;
+
+typedef struct {
+ ro_bf_t d3_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat10_t;
+
+typedef struct {
+ ro_bf_t d3_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat11_t;
+
+typedef struct {
+ ro_bf_t d4_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat12_t;
+
+typedef struct {
+ ro_bf_t d4_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat13_t;
+
+typedef struct {
+ ro_bf_t d4_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat14_t;
+
+typedef struct {
+ ro_bf_t d5_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat15_t;
+
+typedef struct {
+ ro_bf_t d5_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat16_t;
+
+typedef struct {
+ ro_bf_t d5_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat17_t;
+
+typedef struct {
+ ro_bf_t d6_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat18_t;
+
+typedef struct {
+ ro_bf_t d6_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat19_t;
+
+typedef struct {
+ ro_bf_t d6_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat20_t;
+
+typedef struct {
+ ro_bf_t d7_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwml3 : ( 31 - 24 + 1 );
+} phy_vwml_stat21_t;
+
+typedef struct {
+ ro_bf_t d7_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwml7 : ( 31 - 24 + 1 );
+} phy_vwml_stat22_t;
+
+typedef struct {
+ ro_bf_t d7_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwml_stat23_t;
+
+typedef struct {
+ ro_bf_t dm_vwml0 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwml1 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwml2 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwml3 : ( 31 - 24 + 1 );
+} phy_dm_vwml_stat1_t;
+
+typedef struct {
+ ro_bf_t dm_vwml4 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwml5 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwml6 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwml7 : ( 31 - 24 + 1 );
+} phy_dm_vwml_stat2_t;
+
+typedef struct {
+ ro_bf_t dm_vwml8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_vwml_stat3_t;
+
+typedef struct {
+ ro_bf_t d0_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat0_t;
+
+typedef struct {
+ ro_bf_t d0_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d0_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d0_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d0_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat1_t;
+
+typedef struct {
+ ro_bf_t d0_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat2_t;
+
+typedef struct {
+ ro_bf_t d1_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat3_t;
+
+typedef struct {
+ ro_bf_t d1_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d1_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d1_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d1_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat4_t;
+
+typedef struct {
+ ro_bf_t d1_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat5_t;
+
+typedef struct {
+ ro_bf_t d2_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat6_t;
+
+typedef struct {
+ ro_bf_t d2_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d2_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d2_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d2_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat7_t;
+
+typedef struct {
+ ro_bf_t d2_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat8_t;
+
+typedef struct {
+ ro_bf_t d3_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat9_t;
+
+typedef struct {
+ ro_bf_t d3_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d3_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d3_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d3_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat10_t;
+
+typedef struct {
+ ro_bf_t d3_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat11_t;
+
+typedef struct {
+ ro_bf_t d4_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat12_t;
+
+typedef struct {
+ ro_bf_t d4_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d4_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d4_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d4_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat13_t;
+
+typedef struct {
+ ro_bf_t d4_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat14_t;
+
+typedef struct {
+ ro_bf_t d5_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat15_t;
+
+typedef struct {
+ ro_bf_t d5_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d5_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d5_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d5_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat16_t;
+
+typedef struct {
+ ro_bf_t d5_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat17_t;
+
+typedef struct {
+ ro_bf_t d6_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat18_t;
+
+typedef struct {
+ ro_bf_t d6_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d6_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d6_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d6_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat19_t;
+
+typedef struct {
+ ro_bf_t d6_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat20_t;
+
+typedef struct {
+ ro_bf_t d7_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmr3 : ( 31 - 24 + 1 );
+} phy_vwmr_stat21_t;
+
+typedef struct {
+ ro_bf_t d7_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t d7_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t d7_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t d7_vwmr7 : ( 31 - 24 + 1 );
+} phy_vwmr_stat22_t;
+
+typedef struct {
+ ro_bf_t d7_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_vwmr_stat23_t;
+
+typedef struct {
+ ro_bf_t dm_vwmr0 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmr1 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmr2 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmr3 : ( 31 - 24 + 1 );
+} phy_dm_vwmr_stat0_t;
+
+typedef struct {
+ ro_bf_t dm_vwmr4 : ( 7 - 0 + 1 );
+ ro_bf_t dm_vwmr5 : ( 15 - 8 + 1 );
+ ro_bf_t dm_vwmr6 : ( 23 - 16 + 1 );
+ ro_bf_t dm_vwmr7 : ( 31 - 24 + 1 );
+} phy_dm_vwmr_stat1_t;
+
+typedef struct {
+ ro_bf_t dm_vwmr8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dm_vwmr_stat2_t;
+
+typedef struct {
+ ro_bf_t dq_io_rd0 : ( 7 - 0 + 1 );
+ ro_bf_t dq_io_rd1 : ( 15 - 8 + 1 );
+ ro_bf_t dq_io_rd2 : ( 23 - 16 + 1 );
+ ro_bf_t dq_io_rd3 : ( 31 - 24 + 1 );
+} phy_dq_io_rdata0_t;
+
+typedef struct {
+ ro_bf_t dq_io_rd4 : ( 7 - 0 + 1 );
+ ro_bf_t dq_io_rd5 : ( 15 - 8 + 1 );
+ ro_bf_t dq_io_rd6 : ( 23 - 16 + 1 );
+ ro_bf_t dq_io_rd7 : ( 31 - 24 + 1 );
+} phy_dq_io_rdata1_t;
+
+typedef struct {
+ ro_bf_t dq_io_rd8 : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_dq_io_rdata2_t;
+
+typedef struct {
+ rw_bf_t version_info : ( 31 - 0 + 1 );
+} phy_version_info_stat0_t;
+
+typedef struct {
+ rw_bf_t zq_auto_en : ( 0 - 0 + 1 );
+ rw_bf_t zq_manual_str : ( 1 - 1 + 1 );
+ rw_bf_t zq_manual_mode : ( 3 - 2 + 1 );
+ rw_bf_t zq_udt_dly : ( 11 - 4 + 1 );
+ rw_bf_t zq_force_impp : ( 14 - 12 + 1 );
+ rw_bf_t zq_force_impn : ( 17 - 15 + 1 );
+ rw_bf_t zq_clk_div_en : ( 18 - 18 + 1 );
+ rw_bf_t zq_mode_noterm : ( 19 - 19 + 1 );
+ rw_bf_t zq_lpddr3 : ( 20 - 20 + 1 );
+ rw_bf_t zq_mode_term : ( 23 - 21 + 1 );
+ rw_bf_t zq_mode_dds : ( 26 - 24 + 1 );
+ rw_bf_t zq_clk_en : ( 27 - 27 + 1 );
+ rw_bf_t zq_mode_pdds : ( 30 - 28 + 1 );
+ rw_bf_t zq_mode_lp4 : ( 31 - 31 + 1 );
+} phy_zq_con0_t;
+
+typedef struct {
+ ro_bf_t zq_done : ( 0 - 0 + 1 );
+ ro_bf_t zq_pending : ( 1 - 1 + 1 );
+ ro_bf_t zq_error : ( 2 - 2 + 1 );
+ ro_bf_t zq_nmon : ( 5 - 3 + 1 );
+ ro_bf_t zq_pmon : ( 8 - 6 + 1 );
+ ro_bf_t reserved_9_15 : ( 15 - 9 + 1 );
+ rw_bf_t zq_vref : ( 21 - 16 + 1 );
+ ro_bf_t reserved_22_31 : ( 31 - 22 + 1 );
+} phy_zq_con1_t;
+
+typedef struct {
+ rw_bf_t ctrl_zq_clk_div : ( 15 - 0 + 1 );
+ rw_bf_t ctrl_zq_timer : ( 31 - 16 + 1 );
+} phy_zq_con2_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_pdds : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds0_dds : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds1_pdds : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds1_dds : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds2_pdds : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds2_dds : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds3_pdds : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds3_dds : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con3_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_pdds : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds4_dds : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds5_pdds : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds5_dds : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds6_pdds : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds6_dds : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds7_pdds : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds7_dds : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con4_t;
+
+typedef struct {
+ rw_bf_t zq_ds8_pdds : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds8_dds : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_zq_con5_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_lp4 : ( 0 - 0 + 1 );
+ rw_bf_t zq_ds0_noterm : ( 1 - 1 + 1 );
+ rw_bf_t zq_ds0_rgddr3 : ( 2 - 2 + 1 );
+ rw_bf_t zq_ds0_term : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds1_lp4 : ( 8 - 8 + 1 );
+ rw_bf_t zq_ds1_noterm : ( 9 - 9 + 1 );
+ rw_bf_t zq_ds1_rgddr3 : ( 10 - 10 + 1 );
+ rw_bf_t zq_ds1_term : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds2_lp4 : ( 16 - 16 + 1 );
+ rw_bf_t zq_ds2_noterm : ( 17 - 17 + 1 );
+ rw_bf_t zq_ds2_rgddr3 : ( 18 - 18 + 1 );
+ rw_bf_t zq_ds2_term : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds3_lp4 : ( 24 - 24 + 1 );
+ rw_bf_t zq_ds3_noterm : ( 25 - 25 + 1 );
+ rw_bf_t zq_ds3_rgddr3 : ( 26 - 26 + 1 );
+ rw_bf_t zq_ds3_term : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con6_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_lp4 : ( 0 - 0 + 1 );
+ rw_bf_t zq_ds4_noterm : ( 1 - 1 + 1 );
+ rw_bf_t zq_ds4_rgddr3 : ( 2 - 2 + 1 );
+ rw_bf_t zq_ds4_term : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds5_lp4 : ( 8 - 8 + 1 );
+ rw_bf_t zq_ds5_noterm : ( 9 - 9 + 1 );
+ rw_bf_t zq_ds5_rgddr3 : ( 10 - 10 + 1 );
+ rw_bf_t zq_ds5_term : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds6_lp4 : ( 16 - 16 + 1 );
+ rw_bf_t zq_ds6_noterm : ( 17 - 17 + 1 );
+ rw_bf_t zq_ds6_rgddr3 : ( 18 - 18 + 1 );
+ rw_bf_t zq_ds6_term : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds7_lp4 : ( 24 - 24 + 1 );
+ rw_bf_t zq_ds7_noterm : ( 25 - 25 + 1 );
+ rw_bf_t zq_ds7_rgddr3 : ( 26 - 26 + 1 );
+ rw_bf_t zq_ds7_term : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con7_t;
+
+typedef struct {
+ rw_bf_t zq_ds8_lp4 : ( 0 - 0 + 1 );
+ rw_bf_t zq_ds8_noterm : ( 1 - 1 + 1 );
+ rw_bf_t zq_ds8_rgddr3 : ( 2 - 2 + 1 );
+ rw_bf_t zq_ds8_term : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_31 : ( 31 - 6 + 1 );
+} phy_zq_con8_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_vref : ( 5 - 0 + 1 );
+ rw_bf_t zq_ds0_vref_fsbst : ( 6 - 6 + 1 );
+ rw_bf_t zq_ds0_vref_pd : ( 7 - 7 + 1 );
+ rw_bf_t zq_ds1_vref : ( 13 - 8 + 1 );
+ rw_bf_t zq_ds1_vref_fsbst : ( 14 - 14 + 1 );
+ rw_bf_t zq_ds1_vref_pd : ( 15 - 15 + 1 );
+ rw_bf_t zq_ds2_vref : ( 21 - 16 + 1 );
+ rw_bf_t zq_ds2_vref_fsbst : ( 22 - 22 + 1 );
+ rw_bf_t zq_ds2_vref_pd : ( 23 - 23 + 1 );
+ rw_bf_t zq_ds3_vref : ( 29 - 24 + 1 );
+ rw_bf_t zq_ds3_vref_fsbst : ( 30 - 30 + 1 );
+ rw_bf_t zq_ds3_vref_pd : ( 31 - 31 + 1 );
+} phy_zq_con9_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_vref : ( 5 - 0 + 1 );
+ rw_bf_t zq_ds4_vref_fsbst : ( 6 - 6 + 1 );
+ rw_bf_t zq_ds4_vref_pd : ( 7 - 7 + 1 );
+ rw_bf_t zq_ds5_vref : ( 13 - 8 + 1 );
+ rw_bf_t zq_ds5_vref_fsbst : ( 14 - 14 + 1 );
+ rw_bf_t zq_ds5_vref_pd : ( 15 - 15 + 1 );
+ rw_bf_t zq_ds6_vref : ( 21 - 16 + 1 );
+ rw_bf_t zq_ds6_vref_fsbst : ( 22 - 22 + 1 );
+ rw_bf_t zq_ds6_vref_pd : ( 23 - 23 + 1 );
+ rw_bf_t zq_ds7_vref : ( 29 - 24 + 1 );
+ rw_bf_t zq_ds7_vref_fsbst : ( 30 - 30 + 1 );
+ rw_bf_t zq_ds7_vref_pd : ( 31 - 31 + 1 );
+} phy_zq_con10_t;
+
+typedef struct {
+ rw_bf_t zq_ds8_vref : ( 5 - 0 + 1 );
+ rw_bf_t zq_ds8_vref_fsbst : ( 6 - 6 + 1 );
+ rw_bf_t zq_ds8_vref_pd : ( 7 - 7 + 1 );
+ ro_bf_t reserved_8_31 : ( 31 - 8 + 1 );
+} phy_zq_con11_t;
+
+typedef struct {
+ rw_bf_t zq_ds0_impp : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds0_impn : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds1_impp : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds1_impn : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds2_impp : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds2_impn : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds3_impp : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds3_impn : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con12_t;
+
+typedef struct {
+ rw_bf_t zq_ds4_impp : ( 2 - 0 + 1 );
+ rw_bf_t zq_ds4_impn : ( 5 - 3 + 1 );
+ ro_bf_t reserved_6_7 : ( 7 - 6 + 1 );
+ rw_bf_t zq_ds5_impp : ( 10 - 8 + 1 );
+ rw_bf_t zq_ds5_impn : ( 13 - 11 + 1 );
+ ro_bf_t reserved_14_15 : ( 15 - 14 + 1 );
+ rw_bf_t zq_ds6_impp : ( 18 - 16 + 1 );
+ rw_bf_t zq_ds6_impn : ( 21 - 19 + 1 );
+ ro_bf_t reserved_22_23 : ( 23 - 22 + 1 );
+ rw_bf_t zq_ds7_impp : ( 26 - 24 + 1 );
+ rw_bf_t zq_ds7_impn : ( 29 - 27 + 1 );
+ ro_bf_t reserved_30_31 : ( 31 - 30 + 1 );
+} phy_zq_con13_t;
+
+typedef struct {
+ rw_bf_t dqs_osc_cnt_init_cs1 : ( 15 - 0 + 1 );
+ rw_bf_t dqs_osc_cnt_init_cs0 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con0_t;
+
+typedef struct {
+ rw_bf_t dqs_osc_cnt_new_cs0 : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con1_t;
+
+typedef struct {
+ rw_bf_t dqs_osc_cnt_new_cs1 : ( 15 - 0 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con2_t;
+
+typedef struct {
+ rw_bf_t dqs_init_runtime : ( 7 - 0 + 1 );
+ ro_bf_t reserved_8_20 : ( 20 - 8 + 1 );
+ ro_bf_t dqs_osc_cnt_applied_cs0 : ( 21 - 21 + 1 );
+ ro_bf_t dqs_osc_cnt_applied_cs1 : ( 22 - 22 + 1 );
+ ro_bf_t dqs_osc_overflow_cs0 : ( 23 - 23 + 1 );
+ ro_bf_t dqs_osc_overflow_cs1 : ( 24 - 24 + 1 );
+ rw_bf_t dqs_upd_range : ( 31 - 25 + 1 );
+} phy_dqs_osc_con3_t;
+
+typedef struct {
+ ro_bf_t offsetw_osc_cs0 : ( 7 - 0 + 1 );
+ ro_bf_t offsetw_osc_cs1 : ( 15 - 8 + 1 );
+ ro_bf_t reserved_16_31 : ( 31 - 16 + 1 );
+} phy_dqs_osc_con4_t;
+
+typedef struct {
+ rw_bf_t cbt_ca_vref : ( 7 - 0 + 1 );
+ rw_bf_t cbt_cmd_ca_vref : ( 8 - 8 + 1 );
+ rw_bf_t cbt_ca_vref_mode_ds_0 : ( 9 - 9 + 1 );
+ rw_bf_t cbt_ca_vref_mode_ds_1 : ( 10 - 10 + 1 );
+ ro_bf_t reserved_11_13 : ( 13 - 11 + 1 );
+ rw_bf_t cbt_cmd_clear : ( 14 - 14 + 1 );
+ rw_bf_t cbt_cmd_ca_vwmr : ( 15 - 15 + 1 );
+ rw_bf_t cbt_cmd_ca_vwml : ( 16 - 16 + 1 );
+ rw_bf_t cbt_cmd_cs_vwmr : ( 17 - 17 + 1 );
+ rw_bf_t cbt_cmd_cs_vwml : ( 18 - 18 + 1 );
+ rw_bf_t cbt_reset : ( 19 - 19 + 1 );
+ rw_bf_t cbt_odt_ca : ( 21 - 20 + 1 );
+ rw_bf_t cbt_cke : ( 23 - 22 + 1 );
+ rw_bf_t cbt_ca_pattern : ( 29 - 24 + 1 );
+ rw_bf_t cbt_cs : ( 31 - 30 + 1 );
+} phy_cbt_con0_t;
+
+
+typedef struct {
+ phy_gnr_con0_t GNR_CON0;
+ phy_cal_con0_t CAL_CON0;
+ phy_cal_con1_t CAL_CON1;
+ phy_cal_con2_t CAL_CON2;
+ phy_cal_con3_t CAL_CON3;
+ phy_wlat_con0_t WLAT_CON0;
+ phy_lp_con0_t LP_CON0;
+ phy_gate_con0_t GATE_CON0;
+ phy_offsetr_con0_t OFFSETR_CON0;
+ phy_offsetr_con1_t OFFSETR_CON1;
+ phy_offsetr_con2_t OFFSETR_CON2;
+ phy_dqlat_con0_t DQLAT_CON0;
+ phy_offsetw_con0_t OFFSETW_CON0;
+ phy_offsetw_con1_t OFFSETW_CON1;
+ phy_offsetw_con2_t OFFSETW_CON2;
+ phy_offset_dq_con0_t OFFSET_DQ_CON0;
+ phy_offsetc_con0_t OFFSETC_CON0;
+ phy_offsetc_con1_t OFFSETC_CON1;
+ phy_offsetc_con2_t OFFSETC_CON2;
+ phy_shiftc_con0_t SHIFTC_CON0;
+ phy_offsetd_con0_t OFFSETD_CON0;
+ ro_bf_t reserved_0x54;
+ phy_offseto_con0_t OFFSETO_CON0;
+ phy_offseto_con1_t OFFSETO_CON1;
+ phy_offseto_con2_t OFFSETO_CON2;
+ ro_bf_t reserved_0x64_0x68[2];
+ phy_wr_lvl_con0_t WR_LVL_CON0;
+ phy_wr_lvl_con1_t WR_LVL_CON1;
+ phy_wr_lvl_con2_t WR_LVL_CON2;
+ phy_wr_lvl_con3_t WR_LVL_CON3;
+ phy_ca_dskew_con0_t CA_DSKEW_CON0;
+ phy_ca_dskew_con1_t CA_DSKEW_CON1;
+ phy_ca_dskew_con2_t CA_DSKEW_CON2;
+ ro_bf_t reserved_0x88_0x90[3];
+ phy_ca_dskew_con4_t CA_DSKEW_CON4;
+ phy_cal_pattern_con0_t CAL_PATTERN_CON0;
+ phy_cal_pattern_con1_t CAL_PATTERN_CON1;
+ phy_cal_pattern_con2_t CAL_PATTERN_CON2;
+ phy_cal_pattern_con3_t CAL_PATTERN_CON3;
+ phy_cal_pattern_con4_t CAL_PATTERN_CON4;
+ phy_cal_pattern_con5_t CAL_PATTERN_CON5;
+ phy_mdll_con0_t MDLL_CON0;
+ phy_mdll_con1_t MDLL_CON1;
+ phy_dvfs_con0_t DVFS_CON0;
+ phy_dvfs_con1_t DVFS_CON1;
+ phy_dvfs_con2_t DVFS_CON2;
+ phy_dvfs_con3_t DVFS_CON3;
+ phy_dvfs_con4_t DVFS_CON4;
+ phy_dvfs_con5_t DVFS_CON5;
+ phy_t_rddata_con0_t T_RDDATA_CON0;
+ phy_t_rddata_con1_t T_RDDATA_CON1;
+ phy_t_rddata_con2_t T_RDDATA_CON2;
+ ro_bf_t reserved_0xDC;
+ phy_cal_fail_stat0_t CAL_FAIL_STAT0;
+ phy_cal_fail_stat1_t CAL_FAIL_STAT1;
+ phy_cal_fail_stat2_t CAL_FAIL_STAT2;
+ phy_cal_fail_stat3_t CAL_FAIL_STAT3;
+ phy_cal_gt_wvmc0_t CAL_GT_WVMC0;
+ phy_cal_gt_wvmc1_t CAL_GT_WVMC1;
+ phy_cal_gt_wvmc2_t CAL_GT_WVMC2;
+ phy_cal_gt_cyc_t CAL_GT_CYC;
+ phy_cal_rd_vwmc0_t CAL_RD_VWMC0;
+ phy_cal_rd_vwmc1_t CAL_RD_VWMC1;
+ phy_cal_rd_vwmc2_t CAL_RD_VWMC2;
+ ro_bf_t reserved_0x10C;
+ phy_cal_rd_vwml0_t CAL_RD_VWML0;
+ phy_cal_rd_vwml1_t CAL_RD_VWML1;
+ phy_cal_rd_vwml2_t CAL_RD_VWML2;
+ ro_bf_t reserved_0x11C;
+ phy_cal_rd_vwmr0_t CAL_RD_VWMR0;
+ phy_cal_rd_vwmr1_t CAL_RD_VWMR1;
+ phy_cal_rd_vwmr2_t CAL_RD_VWMR2;
+ ro_bf_t reserved_0x12C;
+ phy_cal_wr_vwmc0_t CAL_WR_VWMC0;
+ phy_cal_wr_vwmc1_t CAL_WR_VWMC1;
+ phy_cal_wr_vwmc2_t CAL_WR_VWMC2;
+ ro_bf_t reserved_0x13C;
+ phy_cal_wr_vwml0_t CAL_WR_VWML0;
+ phy_cal_wr_vwml1_t CAL_WR_VWML1;
+ phy_cal_wr_vwml2_t CAL_WR_VWML2;
+ ro_bf_t reserved_0x14C;
+ phy_cal_wr_vwmr0_t CAL_WR_VWMR0;
+ phy_cal_wr_vwmr1_t CAL_WR_VWMR1;
+ phy_cal_wr_vwmr2_t CAL_WR_VWMR2;
+ ro_bf_t reserved_0x15C;
+ phy_cal_dm_vwmc0_t CAL_DM_VWMC0;
+ phy_cal_dm_vwmc1_t CAL_DM_VWMC1;
+ phy_cal_dm_vwmc2_t CAL_DM_VWMC2;
+ ro_bf_t reserved_0x16C;
+ phy_cal_dm_vwml0_t CAL_DM_VWML0;
+ phy_cal_dm_vwml1_t CAL_DM_VWML1;
+ phy_cal_dm_vwml2_t CAL_DM_VWML2;
+ ro_bf_t reserved_0x17C;
+ phy_cal_dm_vwmr0_t CAL_DM_VWMR0;
+ phy_cal_dm_vwmr1_t CAL_DM_VWMR1;
+ phy_cal_dm_vwmr2_t CAL_DM_VWMR2;
+ ro_bf_t reserved_0x18C;
+ phy_rd_deskew_con0_t RD_DESKEW_CON0;
+ phy_rd_deskew_con1_t RD_DESKEW_CON1;
+ phy_rd_deskew_con2_t RD_DESKEW_CON2;
+ phy_rd_deskew_con3_t RD_DESKEW_CON3;
+ phy_rd_deskew_con4_t RD_DESKEW_CON4;
+ phy_rd_deskew_con5_t RD_DESKEW_CON5;
+ phy_rd_deskew_con6_t RD_DESKEW_CON6;
+ phy_rd_deskew_con7_t RD_DESKEW_CON7;
+ phy_rd_deskew_con8_t RD_DESKEW_CON8;
+ phy_rd_deskew_con9_t RD_DESKEW_CON9;
+ phy_rd_deskew_con10_t RD_DESKEW_CON10;
+ phy_rd_deskew_con11_t RD_DESKEW_CON11;
+ phy_rd_deskew_con12_t RD_DESKEW_CON12;
+ phy_rd_deskew_con13_t RD_DESKEW_CON13;
+ phy_rd_deskew_con14_t RD_DESKEW_CON14;
+ phy_rd_deskew_con15_t RD_DESKEW_CON15;
+ phy_rd_deskew_con16_t RD_DESKEW_CON16;
+ phy_rd_deskew_con17_t RD_DESKEW_CON17;
+ phy_rd_deskew_con18_t RD_DESKEW_CON18;
+ phy_rd_deskew_con19_t RD_DESKEW_CON19;
+ phy_rd_deskew_con20_t RD_DESKEW_CON20;
+ phy_rd_deskew_con21_t RD_DESKEW_CON21;
+ phy_rd_deskew_con22_t RD_DESKEW_CON22;
+ phy_rd_deskew_con23_t RD_DESKEW_CON23;
+ phy_wr_deskew_con0_t WR_DESKEW_CON0;
+ phy_wr_deskew_con1_t WR_DESKEW_CON1;
+ phy_wr_deskew_con2_t WR_DESKEW_CON2;
+ phy_wr_deskew_con3_t WR_DESKEW_CON3;
+ phy_wr_deskew_con4_t WR_DESKEW_CON4;
+ phy_wr_deskew_con5_t WR_DESKEW_CON5;
+ phy_wr_deskew_con6_t WR_DESKEW_CON6;
+ phy_wr_deskew_con7_t WR_DESKEW_CON7;
+ phy_wr_deskew_con8_t WR_DESKEW_CON8;
+ phy_wr_deskew_con9_t WR_DESKEW_CON9;
+ phy_wr_deskew_con10_t WR_DESKEW_CON10;
+ phy_wr_deskew_con11_t WR_DESKEW_CON11;
+ phy_wr_deskew_con12_t WR_DESKEW_CON12;
+ phy_wr_deskew_con13_t WR_DESKEW_CON13;
+ phy_wr_deskew_con14_t WR_DESKEW_CON14;
+ phy_wr_deskew_con15_t WR_DESKEW_CON15;
+ phy_wr_deskew_con16_t WR_DESKEW_CON16;
+ phy_wr_deskew_con17_t WR_DESKEW_CON17;
+ phy_wr_deskew_con18_t WR_DESKEW_CON18;
+ phy_wr_deskew_con19_t WR_DESKEW_CON19;
+ phy_wr_deskew_con20_t WR_DESKEW_CON20;
+ phy_wr_deskew_con21_t WR_DESKEW_CON21;
+ phy_wr_deskew_con22_t WR_DESKEW_CON22;
+ phy_wr_deskew_con23_t WR_DESKEW_CON23;
+ phy_dm_deskew_con0_t DM_DESKEW_CON0;
+ phy_dm_deskew_con1_t DM_DESKEW_CON1;
+ phy_dm_deskew_con2_t DM_DESKEW_CON2;
+ phy_vwmc_stat0_t VWMC_STAT0;
+ phy_vwmc_stat1_t VWMC_STAT1;
+ phy_vwmc_stat2_t VWMC_STAT2;
+ phy_vwmc_stat3_t VWMC_STAT3;
+ phy_vwmc_stat4_t VWMC_STAT4;
+ phy_vwmc_stat5_t VWMC_STAT5;
+ phy_vwmc_stat6_t VWMC_STAT6;
+ phy_vwmc_stat7_t VWMC_STAT7;
+ phy_vwmc_stat8_t VWMC_STAT8;
+ phy_vwmc_stat9_t VWMC_STAT9;
+ phy_vwmc_stat10_t VWMC_STAT10;
+ phy_vwmc_stat11_t VWMC_STAT11;
+ phy_vwmc_stat12_t VWMC_STAT12;
+ phy_vwmc_stat13_t VWMC_STAT13;
+ phy_vwmc_stat14_t VWMC_STAT14;
+ phy_vwmc_stat15_t VWMC_STAT15;
+ phy_vwmc_stat16_t VWMC_STAT16;
+ phy_vwmc_stat17_t VWMC_STAT17;
+ phy_vwmc_stat18_t VWMC_STAT18;
+ phy_vwmc_stat19_t VWMC_STAT19;
+ phy_vwmc_stat20_t VWMC_STAT20;
+ phy_vwmc_stat21_t VWMC_STAT21;
+ phy_vwmc_stat22_t VWMC_STAT22;
+ phy_vwmc_stat23_t VWMC_STAT23;
+ phy_dm_vwmc_stat0_t DM_VWMC_STAT0;
+ phy_dm_vwmc_stat1_t DM_VWMC_STAT1;
+ phy_dm_vwmc_stat2_t DM_VWMC_STAT2;
+ phy_vwml_stat0_t VWML_STAT0;
+ phy_vwml_stat1_t VWML_STAT1;
+ phy_vwml_stat2_t VWML_STAT2;
+ phy_vwml_stat3_t VWML_STAT3;
+ phy_vwml_stat4_t VWML_STAT4;
+ phy_vwml_stat5_t VWML_STAT5;
+ phy_vwml_stat6_t VWML_STAT6;
+ phy_vwml_stat7_t VWML_STAT7;
+ phy_vwml_stat8_t VWML_STAT8;
+ phy_vwml_stat9_t VWML_STAT9;
+ phy_vwml_stat10_t VWML_STAT10;
+ phy_vwml_stat11_t VWML_STAT11;
+ phy_vwml_stat12_t VWML_STAT12;
+ phy_vwml_stat13_t VWML_STAT13;
+ phy_vwml_stat14_t VWML_STAT14;
+ phy_vwml_stat15_t VWML_STAT15;
+ phy_vwml_stat16_t VWML_STAT16;
+ phy_vwml_stat17_t VWML_STAT17;
+ phy_vwml_stat18_t VWML_STAT18;
+ phy_vwml_stat19_t VWML_STAT19;
+ phy_vwml_stat20_t VWML_STAT20;
+ phy_vwml_stat21_t VWML_STAT21;
+ phy_vwml_stat22_t VWML_STAT22;
+ phy_vwml_stat23_t VWML_STAT23;
+ phy_dm_vwml_stat1_t DM_VWML_STAT1;
+ phy_dm_vwml_stat2_t DM_VWML_STAT2;
+ phy_dm_vwml_stat3_t DM_VWML_STAT3;
+ phy_vwmr_stat0_t VWMR_STAT0;
+ phy_vwmr_stat1_t VWMR_STAT1;
+ phy_vwmr_stat2_t VWMR_STAT2;
+ phy_vwmr_stat3_t VWMR_STAT3;
+ phy_vwmr_stat4_t VWMR_STAT4;
+ phy_vwmr_stat5_t VWMR_STAT5;
+ phy_vwmr_stat6_t VWMR_STAT6;
+ phy_vwmr_stat7_t VWMR_STAT7;
+ phy_vwmr_stat8_t VWMR_STAT8;
+ phy_vwmr_stat9_t VWMR_STAT9;
+ phy_vwmr_stat10_t VWMR_STAT10;
+ phy_vwmr_stat11_t VWMR_STAT11;
+ phy_vwmr_stat12_t VWMR_STAT12;
+ phy_vwmr_stat13_t VWMR_STAT13;
+ phy_vwmr_stat14_t VWMR_STAT14;
+ phy_vwmr_stat15_t VWMR_STAT15;
+ phy_vwmr_stat16_t VWMR_STAT16;
+ phy_vwmr_stat17_t VWMR_STAT17;
+ phy_vwmr_stat18_t VWMR_STAT18;
+ phy_vwmr_stat19_t VWMR_STAT19;
+ phy_vwmr_stat20_t VWMR_STAT20;
+ phy_vwmr_stat21_t VWMR_STAT21;
+ phy_vwmr_stat22_t VWMR_STAT22;
+ phy_vwmr_stat23_t VWMR_STAT23;
+ phy_dm_vwmr_stat0_t DM_VWMR_STAT0;
+ phy_dm_vwmr_stat1_t DM_VWMR_STAT1;
+ phy_dm_vwmr_stat2_t DM_VWMR_STAT2;
+ phy_dq_io_rdata0_t DQ_IO_RDATA0;
+ phy_dq_io_rdata1_t DQ_IO_RDATA1;
+ phy_dq_io_rdata2_t DQ_IO_RDATA2;
+ phy_version_info_stat0_t VERSION_INFO_STAT0;
+ ro_bf_t reserved_0x3B0_0x3C4[6];
+ phy_zq_con0_t ZQ_CON0;
+ phy_zq_con1_t ZQ_CON1;
+ phy_zq_con2_t ZQ_CON2;
+ phy_zq_con3_t ZQ_CON3;
+ phy_zq_con4_t ZQ_CON4;
+ phy_zq_con5_t ZQ_CON5;
+ phy_zq_con6_t ZQ_CON6;
+ phy_zq_con7_t ZQ_CON7;
+ phy_zq_con8_t ZQ_CON8;
+ phy_zq_con9_t ZQ_CON9;
+ phy_zq_con10_t ZQ_CON10;
+ phy_zq_con11_t ZQ_CON11;
+ phy_zq_con12_t ZQ_CON12;
+ phy_zq_con13_t ZQ_CON13;
+ ro_bf_t reserved_0x400_0x5F0[125];
+ phy_dqs_osc_con0_t DQS_OSC_CON0;
+ phy_dqs_osc_con1_t DQS_OSC_CON1;
+ phy_dqs_osc_con2_t DQS_OSC_CON2;
+ phy_dqs_osc_con3_t DQS_OSC_CON3;
+ phy_dqs_osc_con4_t DQS_OSC_CON4;
+ phy_cbt_con0_t CBT_CON0;
+} phy_regs_t;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_PHY_H_ */
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14906
-gerrit
commit 1f5465155c8c4de2d38139db58e82579555b08fb
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 14:35:41 2014 +0530
Exynos7: Add clock initialization
Adding intial system clock setup for Exynos7 and support for
setting clocks specific to various IPs.
Change-Id: Ie1c05820fef1a58b0976bb267f72b790eb341724
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/soc/samsung/exynos7/Makefile.inc | 4 +
src/soc/samsung/exynos7/bootblock.c | 10 +
src/soc/samsung/exynos7/clock.c | 323 ++++++
src/soc/samsung/exynos7/clock_init.c | 1148 ++++++++++++++++++++++
src/soc/samsung/exynos7/include/soc/clock.h | 1039 ++++++++++++++++++++
src/soc/samsung/exynos7/include/soc/clock_init.h | 434 ++++++++
6 files changed, 2958 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index 0fe90ad..0df62c5 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -19,12 +19,16 @@ INCLUDES += -Isrc/soc/samsung/exynos7/include/
# BOOTBLOCK : UART related and minimum required hardware init
bootblock-y += bootblock.c
+bootblock-y += clock.c
+bootblock-y += clock_init.c
bootblock-y += power.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
+romstage-y += clock.c
romstage-y += power.c
# RAMSTAGE : Prepare and load payload
+ramstage-y += clock.c
ramstage-y += cpu.c
ramstage-y += power.c
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index 8af70de..ec64723 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -18,13 +18,18 @@
#include <bootblock_common.h>
#include <stdlib.h>
+#include <soc/clock.h>
#include <soc/cpu.h>
#include <soc/power.h>
void bootblock_cpu_init(void)
{
+ int is_resume = 0;
+
/* Set PS_HOLD and check reset status */
power_init();
+ if (power_read_reset_status() == EXYNOS7_CHECK_SLEEP)
+ is_resume = 1;
/* SCR_EL3.NS|IRQ|FIQ|EA */
raw_write_scr_el3(raw_read_scr_el3() | 0xf);
@@ -34,4 +39,9 @@ void bootblock_cpu_init(void)
/* Set Counter Frequency */
set_cntfrq(EXYNOS7_COUNTER_FREQ);
+
+ /* Initialize system clocks */
+ if (system_clock_init(is_resume))
+ while(1)
+ ;
}
diff --git a/src/soc/samsung/exynos7/clock.c b/src/soc/samsung/exynos7/clock.c
new file mode 100644
index 0000000..d7926d2
--- /dev/null
+++ b/src/soc/samsung/exynos7/clock.c
@@ -0,0 +1,323 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <stdlib.h>
+#include <timer.h>
+#include <arch/io.h>
+#include <console/console.h>
+#include <soc/clock.h>
+#include <soc/clock_init.h>
+#include <soc/periph.h>
+
+static unsigned long exynos7_get_mmc_clk(int dev_index)
+{
+ struct exynos7_clock_top1 *clk =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+ unsigned int sel, sel_mmc;
+ unsigned int ratio;
+ unsigned long sclk;
+
+ if (dev_index < 2) {
+ sel = read32(&clk->clk_mux_sel_top1_fsys1);
+ sel_mmc = (sel >> (MMCX_BIT_SHIFT + (1 - dev_index) * 4)) & 0x3;
+ } else {
+ sel = read32(&clk->clk_mux_sel_top1_fsys0);
+ sel_mmc = (sel >> MMCX_BIT_SHIFT) & 0x3;
+ }
+
+ /* get src pll clock */
+ if (sel_mmc == 0) {
+ /* BUS0 has 2 dividor */
+ sclk = get_pll_clk(BUS0_PLL)/2;
+ } else if(sel_mmc == 1) {
+ sclk = get_pll_clk(BUS1_PLL);
+ } else if(sel_mmc == 2) {
+ sclk = get_pll_clk(CCI_PLL);
+ } else if(sel_mmc == 3) {
+ sclk = get_pll_clk(MFC_PLL);
+ } else {
+ printk(BIOS_ERR, "Unsupported mmc mux (%d)\n", sel);
+ return 0;
+ }
+
+ /*
+ * CLK_DIV_TOP1_FSYS0
+ * SCLK_MMC2[25:16]
+ * CLK_DIV_TOP1_FSYS1
+ * SCLK_MMC0[21:12]
+ * SCLK_MMC1[9:0]
+ */
+ if (dev_index < 2) {
+ ratio = read32(&clk->clk_div_top1_fsys1);
+ /* get SCLK_MMCx_RATIO */
+ ratio = (ratio >> (MMCX_BIT_SHIFT + (1 - dev_index) * 4)) & 0xf;
+ } else {
+ ratio = read32(&clk->clk_div_top1_fsys0);
+ /* get SCLK_MMCx_RATIO */
+ ratio = (ratio >> MMCX_BIT_SHIFT) & 0xf;
+ }
+
+ return (sclk / (ratio + 1));
+}
+
+static unsigned long exynos7_get_pll_clk(int pllreg)
+{
+ struct exynos7_clock_ap *clk_ap =
+ (struct exynos7_clock_ap *)EXYNOS7_CMU_AP_BASE;
+ struct exynos7_clock_topc *clk_topc =
+ (struct exynos7_clock_topc *)EXYNOS7_CMU_TOPC_BASE;
+ unsigned long r, m, p, s = 0, fout;
+ unsigned int pll_ratio = 0;
+ unsigned int freq;
+
+ switch (pllreg) {
+ case AP_PLL:
+ r = read32(&clk_ap->pll_con0);
+ break;
+ case BUS0_PLL:
+ r = read32(&clk_topc->bus0_pll_con0);
+ pll_ratio = (read32(&clk_topc->clk_div_topc3) >> 0) & 0x7;
+ break;
+ case BUS1_PLL:
+ r = read32(&clk_topc->bus1_pll_con0);
+ pll_ratio = (read32(&clk_topc->clk_div_topc3) >> 8) & 0x7;
+ break;
+ case CCI_PLL:
+ r = read32(&clk_topc->cci_pll_con0);
+ pll_ratio = (read32(&clk_topc->clk_div_topc3) >> 12) & 0x7;
+ break;
+ case MFC_PLL:
+ r = read32(&clk_topc->mfc_pll_con0);
+ pll_ratio = (read32(&clk_topc->clk_div_topc3) >> 16) & 0x7;
+ break;
+ case MIF_PLL:
+ r = read32(&clk_topc->mif_pll_con0);
+ pll_ratio = (read32(&clk_topc->clk_div_topc3) >> 4) & 0x7;
+ break;
+ default:
+ printk(BIOS_ERR, "Unsupported PLL (%d)\n", pllreg);
+ return 0;
+ }
+
+ /* MIDV [25:16] */
+ m = (r >> 16) & 0x3ff;
+ /* PDIV [13:8] */
+ p = (r >> 8) & 0x3f;
+ /* SDIV [2:0] */
+ s = r & 0x7;
+
+ freq = CONFIG_SYS_CLK_FREQ;
+
+ /* FOUT = MDIV * FIN / (PDIV * 2^(SDIV)) */
+ fout = m * (freq / (p * (1 << s)));
+
+ return (fout / ((unsigned long)pll_ratio + 1));
+}
+
+static unsigned long exynos7_get_pwm_clk(void)
+{
+ struct exynos7_clock_top0 *clk =
+ (struct exynos7_clock_top0 *)EXYNOS7_CMU_TOP0_BASE;
+ unsigned int sel, ratio, pclk;
+
+ /*
+ * CLK_MUX_SEL_TOP03
+ * ACKL_PERIC0_66 [21:20]
+ *
+ * CLK_DIV_TOP03
+ * ACLK_PERIC0_66[25:20]
+ */
+ sel = read32(&clk->clk_mux_sel_top03);
+ ratio = read32(&clk->clk_div_top03);
+
+ sel = (sel >> PWM_BIT_SHIFT) & 0x3;
+ ratio = (ratio >> PWM_BIT_SHIFT) & 0x3f;
+
+ if (sel == 0)
+ pclk = get_pll_clk(BUS0_PLL);
+ else if (sel == 1)
+ pclk = get_pll_clk(BUS1_PLL);
+ else if (sel == 2)
+ pclk = get_pll_clk(CCI_PLL);
+ else if (sel == 3)
+ pclk = get_pll_clk(MFC_PLL);
+ else {
+ printk(BIOS_ERR, "Unsupported pwm mux (%d)\n", sel);
+ return 0;
+ }
+
+ return (pclk / ratio);
+}
+
+static unsigned long exynos7_get_uart_clk(int dev_index)
+{
+ struct exynos7_clock_top0 *clk =
+ (struct exynos7_clock_top0 *)EXYNOS7_CMU_TOP0_BASE;
+ unsigned int sel, ratio, sclk;
+
+ /*
+ * CLK_MUX_SEL_TOP0_PERIC3
+ * - UART0_SEL [17:16], UART1_SEL [13:12]
+ * - UART2_SEL [9:8], UART3_SEL [5:4]
+ *
+ * CLK_DIV_TOP0_PERIC3
+ * - UART0_RATIO [19:16], UART1_RATIO [15:12]
+ * - UART2_RATIO [11:8], UART3_RATIO [7:4]
+ */
+ sel = read32(&clk->clk_mux_sel_top0_peric3);
+ ratio = read32(&clk->clk_div_top0_peric3);
+
+ sel = (sel >> ((4 - dev_index) * 4)) & 0x3;
+ ratio = (ratio >> ((4 - dev_index) * 4)) & 0xf;
+
+ if (sel == 0)
+ sclk = get_pll_clk(BUS0_PLL);
+ else if (sel == 1)
+ sclk = get_pll_clk(BUS1_PLL);
+ else if (sel == 2)
+ sclk = get_pll_clk(CCI_PLL);
+ else if (sel == 3)
+ sclk = get_pll_clk(MFC_PLL);
+ else {
+ printk(BIOS_ERR, "Unsupported uart mux (%d)\n", sel);
+ return 0;
+ }
+
+ return (sclk / (ratio + 1));
+}
+
+static unsigned long exynos7_get_usbdrd_clk(void)
+{
+ struct exynos7_clock_top1 *clk =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+ unsigned int ratio;
+ unsigned long sclk;
+
+ sclk = get_pll_clk(BUS0_PLL);
+ ratio = read32(&clk->clk_div_top13);
+ ratio = (ratio >> 28) & 0xf;
+
+ return (sclk / (ratio + 1));
+}
+
+static void exynos7_set_mmc_clk(int dev_index, unsigned int div)
+{
+ struct exynos7_clock_top1 *clk =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+ unsigned int ratio, addr = 0;
+
+ /*
+ * CLK_DIV_TOP1_FSYS0
+ * SCLK_MMC2[25:16]
+ * CLK_DIV_TOP1_FSYS1
+ * SCLK_MMC0[21:12]
+ * SCLK_MMC1[9:0]
+ */
+ if (dev_index < 2) {
+ /*
+ * TODO: can't read this register without cating.
+ * Need to check with AP team why is this casting required.
+ */
+ addr = (unsigned int)(uintptr_t)&clk->clk_div_top1_fsys1;
+ ratio = read32((void *)(uintptr_t)addr);
+ /* clear SCLK_MMCx_RATIO */
+ ratio &= ~(0xf << (MMCX_BIT_SHIFT + (1 - dev_index) * 4));
+ /* set SCLK_MMCx_RATIO */
+ ratio |= ((div & 0xf) << (MMCX_BIT_SHIFT + (1 - dev_index) * 4));
+ } else {
+ addr = (unsigned int)(uintptr_t)&clk->clk_div_top1_fsys0;
+ ratio = read32((void *)(uintptr_t)addr);
+ /* clear SCLK_MMCx_RATIO */
+ ratio &= ~(0xf << MMCX_BIT_SHIFT);
+ /* set SCLK_MMCx_RATIO */
+ ratio |= ((div & 0xf) << MMCX_BIT_SHIFT);
+ }
+
+ write32((void *)(uintptr_t)addr, ratio);
+}
+
+/* Return ARM clock frequency */
+unsigned long get_arm_clk(void)
+{
+ return 0;
+}
+
+/* Return I2C clock frequency */
+unsigned long get_i2c_clk(void)
+{
+ return exynos7_get_pwm_clk();
+}
+
+/* Return MMC clock frequency */
+unsigned long get_mmc_clk(int dev_index)
+{
+ return exynos7_get_mmc_clk(dev_index);
+}
+
+/* Return PLL clock frequency */
+unsigned long get_pll_clk(int pllreg)
+{
+ return exynos7_get_pll_clk(pllreg);
+}
+
+/* Return PWM clock frequency */
+unsigned long get_pwm_clk(void)
+{
+ return exynos7_get_pwm_clk();
+}
+
+/* Return uart clock frequency */
+unsigned long get_uart_clk(int dev_index)
+{
+ return exynos7_get_uart_clk(dev_index);
+}
+
+/* Return USB clock frequency */
+unsigned long get_usbdrd_clk(void)
+{
+ return exynos7_get_usbdrd_clk();
+}
+
+/* Set MMC clock frequency */
+void set_mmc_clk(int dev_index, uint64_t div)
+{
+ exynos7_set_mmc_clk(dev_index, div);
+}
+
+/* Set DMC frequency */
+void dmc_driver_freq(void)
+{
+ unsigned int val;
+
+ val = MIF_ACLK_MIF_PLL_CLK_MUX_SEL(1)
+ | MIF_MIF_PLL_USER_SEL(1)
+ | MIF_SCLK_HPM_MIF_SEL(2)
+ | MIF_PCLK_MIF_SEL(2)
+ | MIF_ACLK_MIF_USER_SEL(1);
+ write32((void *)(uintptr_t)&mif0->clk_mux_sel_mif0, val);
+ write32((void *)(uintptr_t)&mif1->clk_mux_sel_mif1, val);
+ write32((void *)(uintptr_t)&mif2->clk_mux_sel_mif2, val);
+ write32((void *)(uintptr_t)&mif3->clk_mux_sel_mif3, val);
+
+ val = TOPC5_MIF_ACLK_MIF_PLL_SEL(1)
+ | TOPC5_MIF_PLL_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_SEL(1);
+ write32((void *)(uintptr_t)&topc->clk_mux_sel_topc5, val);
+
+ val = SCLK_BUS_PLL_G3D_RATIO(1);
+ write32((void *)(uintptr_t)&topc->clk_div_topc3, val);
+}
diff --git a/src/soc/samsung/exynos7/clock_init.c b/src/soc/samsung/exynos7/clock_init.c
new file mode 100644
index 0000000..c416f40
--- /dev/null
+++ b/src/soc/samsung/exynos7/clock_init.c
@@ -0,0 +1,1148 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <delay.h>
+#include <console/console.h>
+#include <soc/clock.h>
+#include <soc/clock_init.h>
+#include <soc/cpu.h>
+
+
+/* contains AP P, M, S values corresponding to different PLLs */
+static struct pll_spec gpll_ap_spec =
+{
+ .pdiv_min = 1,
+ .pdiv_max = 63,
+ .mdiv_min = 64,
+ .mdiv_max = 1023,
+ .sdiv_min = 0,
+ .sdiv_max = 6,
+ .fref_min = 4,
+ .fref_max = 12,
+ .fvco_min = 1600,
+ .fvco_max = 3304,
+ .fout_min = 25,
+ .fout_max = 3304,
+};
+
+static int clk_pll_find_pms(struct pll_spec *pll_spec, struct clk_pll_pms *pll_pms, uint32_t rate);
+
+static int clk_init_cpu(uint32_t ap_pll)
+{
+ uint32_t val, pll, div1, div2;
+
+ write32(&ap->clk_mux_sel_ap0, CLOCK_DISABLE_BIT);
+
+ switch (ap_pll) {
+ case 2400:
+ pll = set_pll(200, 2, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2300:
+ pll = set_pll(575, 6, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2200:
+ pll = set_pll(275, 3, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2100:
+ pll = set_pll(175, 2, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 2000:
+ pll = set_pll(250, 3, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1900:
+ pll = set_pll(475, 6, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(4)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1800:
+ pll = set_pll(150, 2, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1700:
+ pll = set_pll(425, 6, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1600:
+ pll = set_pll(200, 3, 0);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1500:
+ pll = set_pll(250, 2, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1400:
+ pll = set_pll(350, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1300:
+ pll = set_pll(325, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(3)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1200:
+ pll = set_pll(200, 2, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1100:
+ pll = set_pll(275, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(7) | AP_ATCLK_RATIO(7)
+ | AP_PCLK_AP_RATIO(7) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(7) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 1000:
+ pll = set_pll(250, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(6) | AP_ATCLK_RATIO(6)
+ | AP_PCLK_AP_RATIO(6) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(6) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 900:
+ pll = set_pll(150, 2, 1);
+ div1 = AP_PCLK_DBG_RATIO(6) | AP_ATCLK_RATIO(6)
+ | AP_PCLK_AP_RATIO(6) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(6) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 800:
+ pll = set_pll(200, 3, 1);
+ div1 = AP_PCLK_DBG_RATIO(5) | AP_ATCLK_RATIO(5)
+ | AP_PCLK_AP_RATIO(5) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(5) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 700:
+ pll = set_pll(350, 3, 2);
+ div1 = AP_PCLK_DBG_RATIO(5) | AP_ATCLK_RATIO(5)
+ | AP_PCLK_AP_RATIO(5) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(5) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 600:
+ pll = set_pll(200, 2, 2);
+ div1 = AP_PCLK_DBG_RATIO(4) | AP_ATCLK_RATIO(4)
+ | AP_PCLK_AP_RATIO(4) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(4) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 500:
+ pll = set_pll(250, 3, 2);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 400:
+ pll = set_pll(200, 3, 2);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 300:
+ pll = set_pll(200, 2, 3);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 200:
+ pll = set_pll(200, 3, 3);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ case 100:
+ pll = set_pll(200, 3, 4);
+ div1 = AP_PCLK_DBG_RATIO(3) | AP_ATCLK_RATIO(3)
+ | AP_PCLK_AP_RATIO(3) | AP_ACLK_AP_RATIO(2)
+ | AP_AP2_RATIO(0) | AP_AP1_RATIO(0);
+ div2 = AP_CNTCLK_RATIO(3) | AP_SCLK_HPM_AP_RATIO(2)
+ | AP_AP_PLL_RATIO(1);
+ break;
+ default:
+ return -1;
+ }
+
+ if((ap_pll % 100) != 0) {
+ struct clk_pll_pms pll_pms;
+ if(clk_pll_find_pms(&gpll_ap_spec, &pll_pms, ap_pll) < 0) {
+ return -1;
+ }
+
+ pll = set_pll(pll_pms.mdiv, pll_pms.pdiv, pll_pms.sdiv);
+ }
+
+ val = ((pll >> 8) & 0x3F) * 150;
+ write32(&ap->pll_lock, val);
+
+ pll = pll | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&ap->pll_con0, pll);
+ do
+ {
+ val = read32(&ap->pll_con0);
+ } while ((val >> 29) == 0);
+
+ write32(&ap->clk_div_ap0, div1);
+
+ write32(&ap->clk_div_ap1, div2);
+
+ val = AP_BUS_PLL_USER_SEL(1);
+ write32(&ap->clk_mux_sel_ap1, val);
+
+ val = AP_SEL(0);
+ write32(&ap->clk_mux_sel_ap2, val);
+
+ val = AP_PLL_SEL(1);
+ write32(&ap->clk_mux_sel_ap0, val);
+
+ return 0;
+}
+
+static void clk_init_aud(void)
+{
+ uint32_t val;
+
+ val = AUD_PCLK_DBG_AUD_RATIO(2)
+ | AUD_ACLK_AUD_RATIO(1)
+ | AUD_CA5_RATIO(1);
+ write32(&aud->clk_div_aud0, val);
+
+ val = AUD_CDCLK_RATIO(1)
+ | AUD_SCLK_SLIMBUS_RATIO(19)
+ | AUD_SCLK_UART_RATIO(1)
+ | AUD_SCLK_PCM_RATIO(49)
+ | AUD_SCLK_I2S_RATIO(9);
+ write32(&aud->clk_div_aud1, val);
+
+ val = AUD_PLL_USER_SEL(1)
+ | AUD_SCLK_PCM_SEL(0)
+ | AUD_SCLK_I2S_SEL(0);
+ write32(&aud->clk_mux_sel_aud, val);
+}
+
+static void clk_init_bus0(void)
+{
+ uint32_t val;
+
+ val = PCLK_BUS0_133_RATIO(3);
+ write32(&bus0->clk_div_bus0, val);
+ val = ACLK_BUS0_532_USER_SEL(1);
+ write32(&bus0->clk_mux_sel_bus0, val);
+}
+
+static void clk_init_bus1(void)
+{
+ uint32_t val;
+
+ val = PCLK_BUS1_133_RATIO(3);
+ write32(&bus1->clk_div_bus1, val);
+ val = ACLK_BUS1_200_USER_SEL(1) | ACLK_BUS1_532_USER_SEL(1);
+ write32(&bus1->clk_mux_sel_bus1, val);
+}
+
+static void clk_init_ccore(void)
+{
+ uint32_t val;
+
+ val = ACLK_CCORE_266_RATIO(1);
+ write32(&ccore->clk_div_ccore, val);
+ val = ACLK_CCORE_133_USER_SEL(1) | ACLK_CCORE_532_USER_SEL(1);
+ write32(&ccore->clk_mux_sel_ccore, val);
+}
+
+static void clk_init_disp(void)
+{
+ uint32_t val, bits;
+
+ write32(&disp->clk_mux_sel_disp0, CLOCK_DISABLE_BIT);
+
+ bits = set_pll(192, 6, 3);
+ val = ((bits >> 8) & 0x3F) * 150;
+ write32(&disp->disp_pll_lock, val);
+
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&disp->disp_pll_con0, bits);
+ val = 0;
+ write32(&disp->disp_pll_con1, val);
+ do
+ {
+ val = read32(&disp->disp_pll_con0);
+ } while ((val >> 29) == 0);
+
+ val = DISP_PCLK_DISP_RATIO(2);
+ write32(&disp->clk_div_disp, val);
+
+ val = DISP0_PLL_SEL(1)
+ | DISP0_ACLK_DISP_400_USER_SEL(1);
+ write32(&disp->clk_mux_sel_disp0, val);
+
+ val = DISP1_SCLK_DECON_INT_ECLK(1)
+ | DISP1_SCLK_DECON_EXT_ECLK(1)
+ | DISP1_SCLK_DECON_VCLK(1)
+ | DISP1_SCLK_DSD(1);
+ write32(&disp->clk_mux_sel_disp1, val);
+
+ val = DISP2_PHYCLK_HDMIPHY_PIXEL_CLKO(1)
+ | DISP2_PHYCLK_HDMIPHY_TMDS_CLKO(1)
+ | DISP2_PHYCLK_MIPIDPHY0_RXCLKESC0(1)
+ | DISP2_PHYCLK_MIPIDPHY0_BITCLKDIV8(1)
+ | DISP2_PHYCLK_MIPIDPHY1_RXCLKESC0(1)
+ | DISP2_PHYCLK_MIPIDPHY1_BITCLKDIV8(1);
+ write32(&disp->clk_mux_sel_disp2, val);
+
+ val = DISP3_SCLK_DECON_INT_ECLK(1)
+ | DISP3_SCLK_DECON_EXT_ECLK(1)
+ | DISP3_SCLK_DECON_INT_EXTCLKPLL(1)
+ | DISP3_SCLK_DECON_EXT_EXTCLKPLL(1);
+ write32(&disp->clk_mux_sel_disp3, val);
+}
+
+/* FSYS0 is Retention Block. No need to reconfigure */
+static void clk_init_fsys0(void)
+{
+ uint32_t val, bits;
+
+ write32(&fsys0->clk_mux_sel_fsys00, CLOCK_DISABLE_BIT);
+
+ bits = set_pll(240, 6, 1);
+ val =((bits >> 8) & 0x3F) * 150;
+ write32(&fsys0->hsic_pll_lock, val);
+
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&fsys0->hsic_pll_con0, bits);
+ do
+ {
+ val = read32(&fsys0->hsic_pll_con0);
+ } while ((val >> 29) == 0);
+
+
+ val = FSYS0_USB20_RATIO(9)
+ | FSYS0_PCLK_FSYS0_RATIO(0);
+ write32(&fsys0->clk_div_fsys0, val);
+
+ val = FSYS0_HSIC_PLL_SEL(1)
+ | FSYS0_ACLK_FSYS0_200(1)
+ | FSYS0_PHYCLK_SEL0(0)
+ | FSYS0_PHYCLK_SEL1(0);
+ write32(&fsys0->clk_mux_sel_fsys00, val);
+
+ val = FSYS0_SCLK_USBDRD300(1)
+ | FSYS0_SCLK_MMC2(1)
+ | FSYS0_SCLK_UFSUNIPRO11(1)
+ | FSYS0_SCLK_PHY_FSYS0(1);
+ write32(&fsys0->clk_mux_sel_fsys01, val);
+
+ val = FSYS0_PHYCLK_USBDRD300_UDRD30_PHYCLOCK(1)
+ | FSYS0_PHYCLK_USBDRD300_UDRD30_PIPE_PCLK(1)
+ | FSYS0_PHYCLK_USBHOST20_PHY_FREECLK__HSIC1(1)
+ | FSYS0_PHYCLK_USBHOST20_PHY_PHYCLK__HSIC1(1);
+ write32(&fsys0->clk_mux_sel_fsys02, val);
+
+ val = FSYS0_PHYCLK_UFS_TX0_SYMBOL(1)
+ | FSYS0_PHYCLK_UFS_RX0_SYMBOL(1)
+ | FSYS0_PHYCLK_LLI_TX0_SYMBOL(1)
+ | FSYS0_PHYCLK_LLI_RX0_SYMBOL(1)
+ | FSYS0_PHYCLK_PCIE_TX0(1)
+ | FSYS0_PHYCLK_PCIE_RX0(1);
+ write32(&fsys0->clk_mux_sel_fsys03, val);
+}
+
+/* FSYS1 is Retention Block. No need to reconfigure */
+static void clk_init_fsys1(void)
+{
+ uint32_t val;
+
+ val = FSYS1_PCLK_FSYS1_RATIO(0);
+ write32(&fsys1->clk_div_fsys1, val);
+
+ val = FSYS1_ACLK_FSYS1_200(1)
+ | FSYS1_PHYCLK_SEL0(0)
+ | FSYS1_PHYCLK_SEL1(2);
+ write32(&fsys1->clk_mux_sel_fsys10, val);
+
+ val = FSYS1_SCLK_MMC0(1)
+ | FSYS1_SCLK_MMC1(1)
+ | FSYS1_SCLK_UFSUNIPRO20(1)
+ | FSYS1_SCLK_PHY_FSYS1(1)
+ | FSYS1_SCLK_TLX400_WIFI1(1);
+ write32(&fsys1->clk_mux_sel_fsys11, val);
+
+ val = FSYS1_PHYCLK_UFS20_TX0_SYMBOL(1)
+ | FSYS1_PHYCLK_UFS20_RX0_SYMBOL(1)
+ | FSYS1_PHYCLK_UFS20_RX1_SYMBOL(1)
+ | FSYS1_PHYCLK_PCIE_WIFI1_TX0(1)
+ | FSYS1_PHYCLK_PCIE_WIFI1_RX0(1);
+ write32(&fsys1->clk_mux_sel_fsys12, val);
+}
+
+static void clk_init_g2d(void)
+{
+ uint32_t val;
+
+ val = G2D_PCLK_G2D_RATIO(1);
+ write32(&g2d->clk_div_g2d, val);
+
+ val = G2D_ACLK_G2D_266_USER_SEL(1)
+ | G2D_ACLK_G2D_400_USER_SEL(1);
+ write32(&g2d->clk_mux_sel_g2d, val);
+}
+
+static int clk_init_g3d(void)
+{
+ uint32_t val, bits;
+
+ write32(&g3d->clk_mux_sel_g3d, CLOCK_DISABLE_BIT);
+
+ switch (EXYNOS7_G3D_PLL) {
+ case 700:
+ bits = set_pll(175, 6, 0);
+ break;
+ case 652:
+ bits = set_pll(163, 6, 0);
+ break;
+ case 600:
+ bits = set_pll(150, 6, 0);
+ break;
+ case 532:
+ bits = set_pll(133, 6, 0);
+ break;
+ case 480:
+ bits = set_pll(240, 6, 1);
+ break;
+ case 420:
+ bits = set_pll(210, 6, 1);
+ break;
+ case 350:
+ bits = set_pll(175, 6, 1);
+ break;
+ case 260:
+ bits = set_pll(130, 6, 1);
+ break;
+ case 177:
+ bits = set_pll(177, 6, 2);
+ break;
+ case 100:
+ bits = set_pll(200, 6, 3);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((bits >> 8) & 0x3F) * 150;
+ write32(&g3d->g3d_pll_lock, val);
+
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&g3d->g3d_pll_con0, bits);
+ do
+ {
+ val = read32(&g3d->g3d_pll_con0);
+ } while ((val >> 29) == 0);
+
+ val = G3D_SCLK_HPM_G3D_RATIO(1)
+ | G3D_PCLK_G3D_RATIO(4)
+ | G3D_ACLK_G3D_RATIO(0);
+ write32(&g3d->clk_div_g3d, val);
+
+ val = G3D_SEL(0)
+ | G3D_SCLK_BUS_PLL_G3D_USER_SEL(1)
+ | G3D_PLL_SEL(1);
+ write32(&g3d->clk_mux_sel_g3d, val);
+
+ return 0;
+}
+
+static void clk_init_hevc(void)
+{
+ uint32_t val;
+
+ val = HEVC_PCLK_HEVC_RATIO(3);
+ write32(&hevc->clk_div_hevc, val);
+
+ val = HEVC_ACLK_HEVC_532_USER_SEL(1);
+ write32(&hevc->clk_mux_sel_hevc, val);
+}
+
+static void clk_init_imem(void)
+{
+ uint32_t val = ACLK_IMEM_100_USER_SEL(1)
+ | ACLK_IMEM_200_USER_SEL(1)
+ | ACLK_IMEM_266_USER_SEL(1);
+
+ write32(&imem->clk_mux_sel_imem, val);
+}
+
+static void clk_init_mfc(void)
+{
+ uint32_t val;
+
+ val = MFC_PCLK_MFC_PROMISE_RATIO(0)
+ |MFC_PCLK_MFC_RATIO(3);
+ write32(&mfc->clk_div_mfc, val);
+
+ val = MFC_ACLK_MFC_BUS_532_USER_SEL(1)
+ | MFC_ACLK_MFC_532_USER_SEL(1);
+ write32(&mfc->clk_mux_sel_mfc, val);
+}
+
+static int clk_init_mif(uint32_t mif_pll)
+{
+ uint32_t val, pll;
+
+ write32(&mif0->pause_mif0, PAUSE_MIF(1));
+ write32(&mif1->pause_mif1, PAUSE_MIF(1));
+ write32(&mif2->pause_mif2, PAUSE_MIF(1));
+ write32(&mif3->pause_mif3, PAUSE_MIF(1));
+
+ write32(&topc->clk_mux_sel_topc5, CLOCK_DISABLE_BIT);
+
+ switch (mif_pll) {
+ case 3304:
+ pll = set_pll(413, 3,0);
+ break;
+ case 2912:
+ pll = set_pll(364, 3, 0);
+ break;
+ case 2528:
+ pll = set_pll(316, 3, 0);
+ break;
+ case 2136:
+ pll = set_pll(178, 2, 0);
+ break;
+ case 1656:
+ pll = set_pll(207, 3, 0);
+ break;
+ case 1264:
+ pll = set_pll(316, 3, 1);
+ break;
+ case 1068:
+ pll = set_pll(178, 2, 1);
+ break;
+ case 832:
+ pll = set_pll(208, 3, 1);
+ break;
+ case 696:
+ pll = set_pll(348, 3, 2);
+ break;
+ case 552:
+ pll = set_pll(276, 3, 2);
+ break;
+ case 334:
+ pll = set_pll(334, 3, 3);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((pll >> 8) & 0x3F) * 150;
+ write32(&topc->mif_pll_lock, val);
+
+ pll = pll | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&topc->mif_pll_con0, pll);
+ do
+ {
+ val = read32(&topc->mif_pll_con0);
+ } while ((val >> 29) == 0);
+
+ pll = MIF_SCLK_HPM_MIF_RATIO(1) | MIF_PCLK_MIF_RATIO(4);
+ write32(&mif0->clk_div_mif0, pll);
+ write32(&mif1->clk_div_mif1, pll);
+ write32(&mif2->clk_div_mif2, pll);
+ write32(&mif3->clk_div_mif3, pll);
+
+ /*
+ * Apply F/F setting before pll mux setting to guarautee
+ * post-dividers margine
+ */
+ val = MIF_ACLK_MIF_PLL_CLK_MUX_SEL(0)
+ | MIF_MIF_PLL_USER_SEL(1)
+ | MIF_SCLK_HPM_MIF_SEL(2)
+ | MIF_PCLK_MIF_SEL(2)
+ | MIF_ACLK_MIF_USER_SEL(1);
+ write32(&mif0->clk_mux_sel_mif0, val);
+ write32(&mif1->clk_mux_sel_mif1, val);
+ write32(&mif2->clk_mux_sel_mif2, val);
+ write32(&mif3->clk_mux_sel_mif3, val);
+
+ val = TOPC5_MIF_ACLK_MIF_PLL_SEL(0)
+ | TOPC5_MIF_PLL_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_USER_SEL(1)
+ | TOPC5_MIF_ACLK_MIF_SEL(1)
+ | TOPC5_MIF_PLL_SEL(0);
+ write32(&topc->clk_mux_sel_topc5, val);
+
+ return 0;
+}
+
+static void clk_init_mscl(void)
+{
+ uint32_t val;
+
+ val = MSCL_PCLK_MSCL_RATIO(3);
+ write32(&mscl->clk_div_mscl, val);
+
+ val = MSCL_ACLK_MSCL_532_USER_SEL(1);
+ write32(&mscl->clk_mux_sel_mscl, val);
+}
+
+static void clk_init_peric0(void)
+{
+ write32(&peric0->clk_mux_sel_peric0,
+ PERIC0_SCLK_UART0_USER_SEL(1) | PERIC0_ACLK_PERIC0_66_USER_SEL(1));
+}
+
+static void clk_init_peric1(void)
+{
+ uint32_t val;
+
+ val = PERIC10_ACLK_PERIC1_66_USER_SEL(1);
+ write32(&peric1->clk_mux_sel_peric10, val);
+
+ val = PERIC11_SCLK_UART3_USER_SEL(1)
+ | PERIC11_SCLK_UART2_USER_SEL(1)
+ | PERIC11_SCLK_UART1_USER_SEL(1)
+ | PERIC11_SCLK_SPI4_USER_SEL(1)
+ | PERIC11_SCLK_SPI3_USER_SEL(1)
+ | PERIC11_SCLK_SPI2_USER_SEL(1)
+ | PERIC11_SCLK_SPI1_USER_SEL(1)
+ | PERIC11_SCLK_SPI0_USER_SEL(1);
+ write32(&peric1->clk_mux_sel_peric11, val);
+}
+
+static void clk_init_peris(void)
+{
+ write32(&peris->clk_mux_sel_peris, ACLK_PERIS_66_USER_SEL(1));
+}
+
+static void clk_init_top0(void)
+{
+ uint32_t val;
+
+ val = ACLK_DISP_400(0) | ACLK_PERIC0_66(7) | ACLK_PERIC1_66(7)
+ | ACLK_VPP0_400(0) | ACLK_VPP1_400(0);
+ write32(&top0->clk_div_top03, val);
+
+ val = ACLK_DISP_400(0) | ACLK_PERIC0_66(2) | ACLK_PERIC1_66(2)
+ | ACLK_VPP0_400(0) | ACLK_VPP1_400(0);
+ write32(&top0->clk_mux_sel_top03, val);
+
+ val = ACLK_ISP0_ISP0_590(0) | ACLK_ISP0_TPU_590(0)
+ | ACLK_ISP0_TREX_532(0) | ACLK_ISP1_ISP1_468(1)
+ | ACLK_ISP1_AHB_117(3);
+ write32(&top0->clk_div_top04, val);
+
+ val = ACLK_ISP0_ISP0_590(5) | ACLK_ISP0_TPU_590(0)
+ | ACLK_ISP0_TREX_532(2) | ACLK_ISP1_ISP1_468(5)
+ | ACLK_ISP1_AHB_117(3);
+ write32(&top0->clk_mux_sel_top04, val);
+
+ val = ACLK_CAM0_CSIS0_690(0) | ACLK_CAM0_BNSA_690(0)
+ | ACLK_CAM0_BNSB_690(2) | ACLK_CAM0_BNSD_690(0)
+ | ACLK_CAM0_CSIS1_174(2);
+ write32(&top0->clk_div_top05, val);
+
+ val = ACLK_CAM0_CSIS0_690(6) | ACLK_CAM0_BNSA_690(6)
+ | ACLK_CAM0_BNSB_690(2) | ACLK_CAM0_BNSD_690(6)
+ | ACLK_CAM0_CSIS1_174(2);
+ write32(&top0->clk_mux_sel_top05, val);
+
+ val = ACLK_CAM0_3AA0_690(0) | ACLK_CAM0_3AA1_468(2)
+ | ACLK_CAM0_TREX_532(0) | ACLK_CAM0_NOCP_133(3);
+ write32(&top0->clk_div_top06, val);
+
+ val = ACLK_CAM0_3AA0_690(6) | ACLK_CAM0_3AA1_468(2)
+ | ACLK_CAM0_TREX_532(2) | ACLK_CAM0_NOCP_133(2);
+ write32(&top0->clk_mux_sel_top06, val);
+
+ val = ACLK_CAM1_SCLVRA_491(0) | ACLK_CAM1_ARM_668(0)
+ | ACLK_CAM1_BUSPERI_334(1) | ACLK_CAM1_BNSCSIS_133(3)
+ | ACLK_CAM1_NOCP_133(3) | ACLK_CAM1_TREX_532(0);
+ write32(&top0->clk_div_top07, val);
+
+ val = ACLK_CAM1_SCLVRA_491(0) | ACLK_CAM1_ARM_668(1)
+ | ACLK_CAM1_BUSPERI_334(1) | ACLK_CAM1_BNSCSIS_133(2)
+ | ACLK_CAM1_NOCP_133(2) | ACLK_CAM1_TREX_532(0);
+ write32(&top0->clk_mux_sel_top07, val);
+
+ val = SCLK_DECON_INT_ECLK(0) | SCLK_DECON_EXT_ECLK(0)
+ | SCLK_DECON_VCLK(0) | SCLK_DSD(0) | SCLK_HDMI_SPDIF(15);
+ write32(&top0->clk_div_top0_disp, val);
+ val = SCLK_DECON_INT_ECLK(0) | SCLK_DECON_EXT_ECLK(0)
+ | SCLK_DECON_VCLK(0) | SCLK_DSD(0) | SCLK_HDMI_SPDIF(3);
+ write32(&top0->clk_mux_sel_top0_disp, val);
+
+ val = SCLK_ISP_SPI0(4) | SCLK_ISP_SPI1(4) | SCLK_ISP_UART(3);
+ write32(&top0->clk_div_top0_cam10, val);
+ val = SCLK_ISP_UART(2);
+ write32(&top0->clk_mux_sel_top0_cam10, val);
+
+ val = SCLK_ISP_PWM(15) | SCLK_ISP_MPWM(15) | SCLK_ISP_SENSOR0(15)
+ | SCLK_ISP_SENSOR1(15) | SCLK_ISP_SENSOR2(15);
+ write32(&top0->clk_div_top0_cam11, val);
+
+ write32(&top0->clk_mux_sel_top0_cam11, CLOCK_DISABLE_BIT);
+
+ val = SCLK_I2S1(15) | SCLK_PCM1(15) | SCLK_SPDIF(15);
+ write32(&top0->clk_div_top0_peric0, val);
+
+ val = SCLK_I2S1(1) | SCLK_PCM1(1) | SCLK_SPDIF(3);
+ write32(&top0->clk_mux_sel_top0_peric0, val);
+
+ val = SCLK_SPI0(4) | SCLK_SPI1(4);
+ write32(&top0->clk_div_top0_peric1, val);
+
+ write32(&top0->clk_mux_sel_top0_peric1, CLOCK_DISABLE_BIT);
+
+ val = SCLK_SPI2(4) | SCLK_SPI3(4);
+ write32(&top0->clk_div_top0_peric2, val);
+
+ write32(&top0->clk_mux_sel_top0_peric2, CLOCK_DISABLE_BIT);
+
+ val = SCLK_SPI4(4) | SCLK_UART0(3) | SCLK_UART1(3) | SCLK_UART2(3)
+ | SCLK_UART3(3);
+ write32(&top0->clk_div_top0_peric3, val);
+
+ val = SCLK_SPI4(0) | SCLK_UART0(2) | SCLK_UART1(2) | SCLK_UART2(2)
+ | SCLK_UART3(2);
+ write32(&top0->clk_mux_sel_top0_peric3, val);
+}
+
+static void clk_init_top1(void)
+{
+ uint32_t val;
+
+ val = ACLK_FSYS0_200(3) | ACLK_FSYS1_200(3);
+ write32(&top1->clk_div_top13, val);
+
+ val = ACLK_FSYS0_200(0) | ACLK_FSYS1_200(1);
+ write32(&top1->clk_mux_sel_top13, val);
+
+ val = SCLK_USBDRD300(9) | SCLK_MMC2(15)
+ | SCLK_UFSUNIPRO11(1) | SCLK_PHY_FSYS0(7)
+ | SCLK_PHY_FSYS0_26M(17);
+ write32(&top1->clk_div_top1_fsys0, val);
+
+ val = SCLK_USBDRD300(0) | SCLK_MMC2(0)
+ | SCLK_UFSUNIPRO11(1) | SCLK_PHY_FSYS0(0)
+ | SCLK_PHY_FSYS0_26M(3);
+ write32(&top1->clk_mux_sel_top1_fsys0, val);
+
+ val = SCLK_MMC0(15) | SCLK_MMC1(15) | SCLK_UFSUNIPRO20(1)
+ | SCLK_TLX400_WIFI1(3) | SCLK_PHY_FSYS1(7);
+ write32(&top1->clk_div_top1_fsys1, val);
+
+ val = SCLK_MMC0(0) | SCLK_MMC1(0) | SCLK_UFSUNIPRO20(1)
+ | SCLK_TLX400_WIFI1(0) | SCLK_PHY_FSYS1(0);
+ write32(&top1->clk_mux_sel_top1_fsys1, val);
+
+ val = SCLK_PHY_FSYS1_26M(17);
+ write32(&top1->clk_div_top1_fsys11, val);
+
+ val = SCLK_PHY_FSYS1_26M(3);
+ write32(&top1->clk_mux_sel_top1_fsys11, val);
+}
+
+static int clk_init_topc(void)
+{
+ uint32_t val, bits;
+
+ switch (EXYNOS7_CCI_PLL) {
+ case 532:
+ bits = set_pll(133, 6, 0);
+ break;
+ case 528:
+ bits = set_pll(66, 3, 0);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((bits >> 8) & 0x3F) * 150;
+ write32(&topc->cci_pll_lock, val);
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&topc->cci_pll_con0, bits);
+ do
+ {
+ val = read32(&topc->cci_pll_con0);
+ } while ((val >> 29) == 0);
+
+ switch (EXYNOS7_BUS0_PLL) {
+ case 1600:
+ bits = set_pll(200, 3, 0);
+ break;
+ case 800:
+ bits = set_pll(200, 3, 1);
+ break;
+ default:
+ return -1;
+ }
+
+ val = ((bits >> 8) & 0x3F) * 150;
+ write32(&topc->bus0_pll_lock, val);
+ bits = (bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1));
+ write32(&topc->bus0_pll_con0, bits);
+ do
+ {
+ val = read32(&topc->bus0_pll_con0);
+ } while ((val >> 29) == 0);
+
+
+ bits = set_pll(167, 6, 0);
+ val = ((bits >> 8) & 0x3F) * 150;
+ write32(&topc->bus1_pll_lock, val);
+ bits = (bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1));
+ write32(&topc->bus1_pll_con0, bits);
+ do
+ {
+ val = read32(&topc->bus1_pll_con0);
+ } while ((val >> 29) == 0);
+
+ bits = set_pll(234, 6, 1);
+ val = ((bits >> 8) & 0x3F) * 150;
+ write32(&topc->mfc_pll_lock, val);
+ bits = (bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1));
+ write32(&topc->mfc_pll_con0, bits);
+ do
+ {
+ val = read32(&topc->mfc_pll_con0);
+ } while ((val >> 29) == 0);
+
+ bits = set_pll(20, 1, 0);
+ val = ((bits >> 8) & 0x3F) * 3000;
+ write32(&topc->aud_pll_lock, val);
+ bits = bits | ENABLE(1) | ENABLE_SDIV_CLKSTOP(0)
+ | ENABLE_MDIV_CLKSTOP(1);
+ write32(&topc->aud_pll_con0, bits);
+ /* KDIV */
+ val = 31457;
+ write32(&topc->aud_pll_con1, val);
+ do
+ {
+ val = read32(&topc->aud_pll_con0);
+ } while ((val >> 29) == 0);
+
+ val = ACLK_IMEM_100(3) | ACLK_IMEM_200(3)
+ | ACLK_IMEM_266(1) | ACLK_BUS1_200(1)
+ | ACLK_CCORE_133(4);
+ write32(&topc->clk_div_topc0, val);
+
+ val = ACLK_IMEM_200(1) | ACLK_IMEM_266(2)
+ | ACLK_BUS1_532(2) | ACLK_BUS0_532(3)
+ | ACLK_CCORE_532(2);
+ write32(&topc->clk_mux_sel_topc2, val);
+
+ val = ACLK_PERIS_66(7) | ACLK_G2D_266(1);
+ write32(&topc->clk_div_topc1, val);
+
+ val = ACLK_PERIS_66(2) | ACLK_MSCL_532(2)
+ | ACLK_MFC_BUS_532(2) | ACLK_HEVC_532(2)
+ | ACLK_MFC_532(2) | ACLK_G2D_266(2);
+ write32(&topc->clk_mux_sel_topc3, val);
+
+ write32(&topc->clk_div_topc2, SCLK_CMU_APBIF(3));
+
+ write32(&topc->clk_mux_sel_topc4, CLOCK_DISABLE_BIT);
+
+ val = SCLK_BUS_PLL_G3D_RATIO(1) | SCLK_BUS0_PLL_MIF_RATIO(7);
+ write32(&topc->clk_div_topc3, val);
+
+ return 0;
+}
+
+static int clk_pll_find_pms(struct pll_spec *pll_spec, struct clk_pll_pms *pll_pms, uint32_t rate)
+{
+ uint32_t pdiv, mdiv, sdiv;
+ uint32_t fref, fvco, fout;
+
+ for(pdiv=pll_spec->pdiv_min; pdiv<=pll_spec->pdiv_max; pdiv++) {
+ fref = FIN / pdiv;
+ if((fref < pll_spec->fref_min) || (fref > pll_spec->fref_max)) {
+ continue;
+ }
+
+ for(mdiv=pll_spec->mdiv_min; mdiv<=pll_spec->mdiv_max; mdiv++) {
+ fvco = FIN * mdiv / pdiv;
+ if((fvco < pll_spec->fvco_min) || (fvco > pll_spec->fvco_max)) {
+ continue;
+ }
+
+ for(sdiv=pll_spec->sdiv_min; sdiv<=pll_spec->sdiv_max; sdiv++) {
+ fout = fvco >> sdiv;
+ if((fout >= pll_spec->fout_min) && (fout <= pll_spec->fout_max)) {
+ if(rate == fout) {
+ pll_pms->pdiv = pdiv;
+ pll_pms->mdiv = mdiv;
+ pll_pms->sdiv = sdiv;
+
+ return 0;
+ }
+ }
+ }
+ }
+ }
+
+ return -1;
+}
+
+
+int system_clock_init(int is_resume)
+{
+ uint32_t val, bits;
+
+ write32(&ap->armclk_stopctrl, CLOCK_DISABLE_BIT);
+ write32(&top0->clk_mux_sel_top00, CLOCK_DISABLE_BIT);
+ write32(&top1->clk_mux_sel_top10, CLOCK_DISABLE_BIT);
+
+ /*
+ * Apply F/F setting before pll mux setting to guarautee
+ * post-dividers margin
+ */
+ switch (EXYNOS7_BUS0_PLL) {
+ case 1600:
+ /* 400MHz=1600MHz/4 for TOPC's BUS0_PLL */
+ write32(&topc->clk_mux_sel_topc0,
+ TOPC0_SCLK_BUS0_PLL_CMUC_SEL(2));
+ val = TOPC1_SCLK_BUS_PLL_G3D_SEL(2)
+ | TOPC1_SCLK_BUS0_PLL_OUT_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_MIF_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_AP_SEL(1)
+ | TOPC1_AUD_PLL_SEL(1);
+ /* 800MHz=1600MHz/2 for TOP0,1's BUS0_PLL */
+ write32(&topc->clk_mux_sel_topc1, val);
+ break;
+ case 800:
+ /* 400MHz=800MHz/2 for TOPC's BUS0_PLL */
+ write32(&topc->clk_mux_sel_topc0,
+ TOPC0_SCLK_BUS0_PLL_CMUC_SEL(1));
+ val = TOPC1_SCLK_BUS_PLL_G3D_SEL(2);
+ /* 800MHz=800MHz/1 for TOP0,1's BUS0_PLL */
+ write32(&topc->clk_mux_sel_topc1, val);
+ break;
+ default:
+ return -1;
+ }
+
+ /* 400MHz=800MHz/2 for TOP0's BUS0_PLL */
+ write32(&top0->clk_mux_sel_top01, TOP01_HALF_BUS0_PLL_USER(1));
+ /* 800MHz=800MHz/1 for TOP1's BUS0_PLL */
+ write32(&top1->clk_mux_sel_top11, CLOCK_DISABLE_BIT);
+
+ /* CMU_TOPC */
+ if (clk_init_topc())
+ return -1;
+
+ /* CMU_TOP0 */
+ clk_init_top0();
+
+ /* CMU_TOP1 */
+ clk_init_top1();
+
+ /* CMU_CCORE */
+ clk_init_ccore();
+
+ /* CMU_IMEM */
+ clk_init_imem();
+
+ /* CMU_PERIC0 */
+ clk_init_peric0();
+
+ /* CMU_PERIC1 */
+ clk_init_peric1();
+
+ /* CMU_PERIS */
+ clk_init_peris();
+
+ /* CMU_BUS0 */
+ clk_init_bus0();
+
+ /* CMU_BUS1 */
+ clk_init_bus1();
+
+ /* CMU_AP */
+ if (clk_init_cpu(EXYNOS7_AP_PLL))
+ return -1;
+
+ /* CMU_MIF */
+ if (clk_init_mif(EXYNOS7_MIF_PLL))
+ return -1;
+
+ if(!is_resume) { /* Cold Boot */
+
+ /* CMU_G3D */
+ if (clk_init_g3d())
+ return -1;
+
+ /* CMU_DISP */
+ clk_init_disp();
+
+ /* CMU_AUD */
+ clk_init_aud();
+
+ /* CMU_FSYS0 */
+ clk_init_fsys0();
+
+ /* CMU_FSYS1 */
+ clk_init_fsys1();
+
+ /* CMU_G2D */
+ clk_init_g2d();
+
+ /* CMU_MSCL */
+ clk_init_mscl();
+
+ /* CMU_MFC */
+ clk_init_mfc();
+
+ /* CMU_HEVC */
+ clk_init_hevc();
+ }
+
+ switch (EXYNOS7_BUS0_PLL) {
+ case 1600:
+ val = TOPC0_SCLK_MFC_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_CCI_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS1_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS0_PLL_CMUC_SEL(2)
+ | TOPC0_MFC_PLL_SEL(1)
+ | TOPC0_CCI_PLL_SEL(1)
+ | TOPC0_BUS1_PLL_SEL(1)
+ | TOPC0_BUS0_PLL_SEL(1);
+ bits = TOPC1_SCLK_BUS_PLL_G3D_SEL(2)
+ | TOPC1_SCLK_BUS0_PLL_OUT_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_MIF_SEL(1)
+ | TOPC1_SCLK_BUS0_PLL_AP_SEL(1)
+ | TOPC1_AUD_PLL_SEL(1);
+ break;
+ case 800:
+ val = TOPC0_SCLK_MFC_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_CCI_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS1_PLL_CMUC_SEL(0)
+ | TOPC0_SCLK_BUS0_PLL_CMUC_SEL(1)
+ | TOPC0_MFC_PLL_SEL(1)
+ | TOPC0_CCI_PLL_SEL(1)
+ | TOPC0_BUS1_PLL_SEL(1)
+ | TOPC0_BUS0_PLL_SEL(1);
+ bits = TOPC1_SCLK_BUS_PLL_G3D_SEL(2)
+ | TOPC1_SCLK_BUS0_PLL_OUT_SEL(0)
+ | TOPC1_SCLK_BUS0_PLL_MIF_SEL(0)
+ | TOPC1_SCLK_BUS0_PLL_AP_SEL(0)
+ | TOPC1_AUD_PLL_SEL(0);
+ break;
+ default:
+ return -1;
+ }
+
+ write32(&topc->clk_mux_sel_topc0, val);
+ write32(&topc->clk_mux_sel_topc1, bits);
+
+ val = val | TOP00_BUS0_PLL_USER_SEL(1)
+ | TOP00_BUS1_PLL_USER_SEL(1)
+ | TOP00_CCI_PLL_USER_SEL(1)
+ | TOP00_MFC_PLL_USER_SEL(1)
+ | TOP00_AUD_PLL_USER_SEL(1);
+ write32(&top0->clk_mux_sel_top00, val);
+
+ val = TOP01_SCLK_CMU0_APBIF_SEL(0)
+ | TOP01_HALF_BUS0_PLL_USER(1)
+ | TOP01_HALF_BUS1_PLL_USER(0)
+ | TOP01_HALF_CCI_PLL_USER(0)
+ | TOP01_HALF_MFC_PLL_USER(0);
+ write32(&top0->clk_mux_sel_top01, val);
+
+ val = TOP10_BUS0_PLL_USER_SEL(1)
+ | TOP10_BUS1_PLL_USER_SEL(1)
+ | TOP10_CCI_PLL_USER_SEL(1)
+ | TOP10_MFC_PLL_USER_SEL(1);
+ write32(&top1->clk_mux_sel_top10, val);
+
+ write32(&top1->clk_mux_sel_top11, CLOCK_DISABLE_BIT);
+
+ return 0;
+}
diff --git a/src/soc/samsung/exynos7/include/soc/clock.h b/src/soc/samsung/exynos7/include/soc/clock.h
new file mode 100644
index 0000000..773d4e3
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/clock.h
@@ -0,0 +1,1039 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_CLOCK_H_
+#define _CPU_SAMSUNG_EXYNOS7_CLOCK_H_
+
+#include <stdint.h>
+
+#include <soc/cpu.h>
+
+enum periph_id;
+
+/* EXYNOS7 PLL */
+enum pll {
+ AP_PLL,
+ MIF_PLL,
+ MFC_PLL,
+ BUS0_PLL,
+ BUS1_PLL,
+ CCI_PLL
+};
+
+#define CLOCK_ENABLE_BIT 0x1
+#define CLOCK_DISABLE_BIT 0x0
+#define MCT_HZ 24000000
+#define CONFIG_SYS_CLK_FREQ 24000000
+#define MMCX_BIT_SHIFT 24
+#define PWM_BIT_SHIFT 20
+
+struct clk_pll_pms {
+ uint32_t pdiv;
+ uint32_t mdiv;
+ uint32_t sdiv;
+};
+
+struct pll_spec {
+ uint32_t pdiv_min;
+ uint32_t pdiv_max;
+ uint32_t mdiv_min;
+ uint32_t mdiv_max;
+ uint32_t sdiv_min;
+ uint32_t sdiv_max;
+ uint32_t fref_min;
+ uint32_t fref_max;
+ uint32_t fvco_min;
+ uint32_t fvco_max;
+ uint32_t fout_min;
+ uint32_t fout_max;
+};
+
+struct exynos7_clock_ap {
+ uint32_t pll_lock;
+ uint8_t res1[0xfc];
+ uint32_t pll_con0;
+ uint32_t pll_con1;
+ uint32_t pll_con2;
+ uint8_t res3[0xf4];
+ uint32_t clk_mux_sel_ap0;
+ uint32_t clk_mux_sel_ap1;
+ uint32_t clk_mux_sel_ap2;
+ uint8_t res4[0xf4];
+ uint32_t clk_mux_enable_ap0;
+ uint32_t clk_mux_enable_ap1;
+ uint32_t clk_mux_enable_ap2;
+ uint8_t res5[0xf4];
+ uint32_t clk_mux_stat_ap0;
+ uint32_t clk_mux_stat_ap1;
+ uint32_t clk_mux_stat_ap2;
+ uint8_t res6[0x1f4];
+ uint32_t clk_div_ap0;
+ uint32_t clk_div_ap1;
+ uint8_t res7[0xf8];
+ uint32_t clk_div_stat_ap0;
+ uint32_t clk_div_stat_ap1;
+ uint8_t res8[0x3f8];
+ uint32_t clk_en_ip_ap0;
+ uint32_t clk_en_ip_ap1;
+ uint8_t res9[0xf8];
+ uint32_t clkout_cmu_ap;
+ uint32_t clkout_cmu_ap_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t armclk_stopctrl;
+ uint8_t res15[0x1c];
+ uint32_t pwr_ctrl;
+ uint32_t pwr_ctrl2;
+ uint8_t res11[0x58];
+ uint32_t intr_spread_enable;
+ uint32_t intr_spread_use_standbywfi;
+ uint32_t intr_spread_blocking_duration;
+};
+
+static struct exynos7_clock_ap * const ap =
+ (struct exynos7_clock_ap *)EXYNOS7_CMU_AP_BASE;
+
+struct exynos7_clock_aud {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_aud;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_aud;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_aud;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_aud0;
+ uint32_t clk_div_aud1;
+ uint8_t res5[0xf8];
+ uint32_t clk_div_stat_aud0;
+ uint32_t clk_div_stat_aud1;
+ uint8_t res6[0x3f8];
+ uint32_t clk_en_ip_aud;
+ uint8_t res7[0xfc];
+ uint32_t clkout_cmu_aud;
+ uint32_t clkout_cmu_aud_div_stat;
+};
+
+static struct exynos7_clock_aud * const aud =
+ (struct exynos7_clock_aud *)EXYNOS7_CMU_AUD_BASE;
+
+struct exynos7_clock_bus0 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_bus0;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_bus0;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_bus0;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_bus0;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_bus0;
+ uint8_t res6[0x3fc];
+ uint32_t clk_en_ip_bus0;
+ uint8_t res7[0xfc];
+ uint32_t clkout_cmu_bus0;
+ uint32_t clkout_cmu_bus0_div_stat;
+};
+
+static struct exynos7_clock_bus0 * const bus0 =
+ (struct exynos7_clock_bus0 *)EXYNOS7_CMU_BUS0_BASE;
+
+struct exynos7_clock_bus1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_bus1;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_bus1;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_bus1;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_bus1;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_bus1;
+ uint8_t res6[0x3fc];
+ uint32_t clk_en_ip_bus1;
+ uint8_t res7[0xfc];
+ uint32_t clkout_cmu_bus1;
+ uint32_t clkout_cmu_bus1_div_stat;
+};
+
+static struct exynos7_clock_bus1 * const bus1 =
+ (struct exynos7_clock_bus1 *)EXYNOS7_CMU_BUS1_BASE;
+
+struct exynos7_clock_ccore {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_ccore;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_ccore;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_ccore;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_ccore;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_ccore;
+ uint8_t res6[0x3fc];
+ uint32_t clk_en_ip_ccore0;
+ uint32_t clk_en_ip_ccore1;
+ uint32_t clk_en_ip_ccore2;
+ uint8_t res7[0xf4];
+ uint32_t clkout_cmu_ccore;
+ uint32_t clkout_cmu_ccore_div_stat;
+};
+
+static struct exynos7_clock_ccore * const ccore =
+ (struct exynos7_clock_ccore *)EXYNOS7_CMU_CCORE_BASE;
+
+struct exynos7_clock_disp {
+ uint32_t disp_pll_lock;
+ uint32_t dphy_pll_lock;
+ uint8_t res1[0xf8];
+ uint32_t disp_pll_con0;
+ uint32_t disp_pll_con1;
+ uint32_t disp_pll_con2;
+ uint8_t res2[0x4];
+ uint32_t dphy_pll_con0;
+ uint32_t dphy_pll_con1;
+ uint8_t res3[0xe8];
+ uint32_t clk_mux_sel_disp0;
+ uint32_t clk_mux_sel_disp1;
+ uint32_t clk_mux_sel_disp2;
+ uint32_t clk_mux_sel_disp3;
+ uint32_t clk_mux_sel_disp4;
+ uint32_t clk_mux_sel_disp5;
+ uint8_t res4[0xe8];
+ uint32_t clk_mux_enable_disp0;
+ uint32_t clk_mux_enable_disp1;
+ uint32_t clk_mux_enable_disp2;
+ uint32_t clk_mux_enable_disp3;
+ uint32_t clk_mux_enable_disp4;
+ uint8_t res5[0xec];
+ uint32_t clk_mux_stat_disp0;
+ uint32_t clk_mux_stat_disp1;
+ uint32_t clk_mux_stat_disp2;
+ uint32_t clk_mux_stat_disp3;
+ uint32_t clk_mux_stat_disp4;
+ uint8_t res6[0xf4];
+ uint32_t clk_mux_ignore_disp2;
+ uint8_t res7[0x4];
+ uint32_t clk_mux_ignore_disp4;
+ uint8_t res8[0xec];
+ uint32_t clk_div_disp;
+ uint8_t res9[0xfc];
+ uint32_t clk_div_stat_disp;
+ uint8_t res10[0xfc];
+ uint32_t clk_en_aclk_disp;
+ uint32_t clk_en_aclk_disp_secure_smmu_ro_mmu;
+ uint32_t clk_en_aclk_disp_secure_smmu_rw_mmu;
+ uint32_t clk_en_aclk_disp_secure_smmu_ro_sfw;
+ uint32_t clk_en_aclk_disp_secure_smmu_rw_sfw;
+ uint8_t res11[0xec];
+ uint32_t clk_en_pclk_disp;
+ uint32_t clk_en_pclk_disp_secure_smmu_ro_mmu;
+ uint32_t clk_en_pclk_disp_secure_smmu_rw_mmu;
+ uint32_t clk_en_pclk_disp_secure_smmu_ro_sfw;
+ uint32_t clk_en_pclk_disp_secure_smmu_rw_sfw;
+ uint8_t res12[0xf0];
+ uint32_t clkout_en_sclk_disp1;
+ uint32_t clkout_en_sclk_disp2;
+ uint32_t clkout_en_sclk_disp3;
+ uint32_t clkout_en_sclk_disp4;
+ uint8_t res13[0x1ec];
+ uint32_t clkout_cmu_disp;
+ uint32_t clkout_cmu_disp_div_stat;
+};
+
+static struct exynos7_clock_disp * const disp =
+ (struct exynos7_clock_disp *)EXYNOS7_CMU_DISP_BASE;
+
+struct exynos7_clock_fsys0 {
+ uint32_t hsic_pll_lock;
+ uint8_t res1[0xfc];
+ uint32_t hsic_pll_con0;
+ uint32_t hsic_pll_con1;
+ uint8_t res2[0xf8];
+ uint32_t clk_mux_sel_fsys00;
+ uint32_t clk_mux_sel_fsys01;
+ uint32_t clk_mux_sel_fsys02;
+ uint32_t clk_mux_sel_fsys03;
+ uint8_t res3[0xf0];
+ uint32_t clk_mux_en_fsys00;
+ uint32_t clk_mux_en_fsys01;
+ uint32_t clk_mux_en_fsys02;
+ uint32_t clk_mux_en_fsys03;
+ uint8_t res4[0xf0];
+ uint32_t clk_mux_stat_fsys00;
+ uint32_t clk_mux_stat_fsys01;
+ uint32_t clk_mux_stat_fsys02;
+ uint32_t clk_mux_stat_fsys03;
+ uint8_t res5[0xf0];
+ uint32_t clk_mux_ignore_fsys00;
+ uint32_t clk_mux_ignore_fsys01;
+ uint32_t clk_mux_ignore_fsys02;
+ uint32_t clk_mux_ignore_fsys03;
+ uint8_t res6[0xf0];
+ uint32_t clk_div_fsys0;
+ uint8_t res7[0xfc];
+ uint32_t clk_div_stat_fsys0;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_aclk_fsys00;
+ uint32_t clk_en_aclk_fsys01;
+ uint8_t res9[0xf8];
+ uint32_t clk_en_pclk_fsys0;
+ uint8_t res10[0xfc];
+ uint32_t clk_en_sclk_fsys00;
+ uint32_t clk_en_sclk_fsys01;
+ uint32_t clk_en_sclk_fsys02;
+ uint32_t clk_en_sclk_fsys03;
+ uint8_t res11[0x1f0];
+ uint32_t clkout_cmu_fsys0;
+ uint32_t clkout_cmu_fsys0_div_stat;
+};
+
+static struct exynos7_clock_fsys0 * const fsys0 =
+ (struct exynos7_clock_fsys0 *)EXYNOS7_CMU_FSYS0_BASE;
+
+struct exynos7_clock_fsys1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_fsys10;
+ uint32_t clk_mux_sel_fsys11;
+ uint32_t clk_mux_sel_fsys12;
+ uint8_t res2[0xf4];
+ uint32_t clk_mux_en_fsys10;
+ uint32_t clk_mux_en_fsys11;
+ uint32_t clk_mux_en_fsys12;
+ uint8_t res3[0xf4];
+ uint32_t clk_mux_stat_fsys10;
+ uint32_t clk_mux_stat_fsys11;
+ uint32_t clk_mux_stat_fsys12;
+ uint8_t res4[0xf4];
+ uint32_t clk_mux_ignore_fsys10;
+ uint32_t clk_mux_ignore_fsys11;
+ uint32_t clk_mux_ignore_fsys12;
+ uint8_t res5[0xf4];
+ uint32_t clk_div_fsys1;
+ uint8_t res6[0xfc];
+ uint32_t clk_div_stat_fsys1;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_aclk_fsys1;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_pclk_fsys1;
+ uint8_t res9[0xfc];
+ uint32_t clk_en_sclk_fsys10;
+ uint32_t clk_en_sclk_fsys11;
+ uint32_t clk_en_sclk_fsys12;
+ uint32_t clk_en_sclk_fsys13;
+ uint8_t res10[0x1f0];
+ uint32_t clkout_cmu_fsys1;
+ uint32_t clkout_cmu_fsys1_div_stat;
+};
+
+static struct exynos7_clock_fsys1 * const fsys1 =
+ (struct exynos7_clock_fsys1 *)EXYNOS7_CMU_FSYS1_BASE;
+
+struct exynos7_clock_g2d {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_g2d;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_g2d;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_g2d;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_g2d;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_g2d;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_g2d;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_pclk_g2d;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_sclk_g2d;
+ uint8_t res9[0x1fc];
+ uint32_t clkout_cmu_g2d;
+ uint32_t clkout_cmu_g2d_div_stat;
+};
+
+static struct exynos7_clock_g2d * const g2d =
+ (struct exynos7_clock_g2d *)EXYNOS7_CMU_G2D_BASE;
+
+struct exynos7_clock_g3d {
+ uint32_t g3d_pll_lock;
+ uint8_t res1[0xfc];
+ uint32_t g3d_pll_con0;
+ uint32_t g3d_pll_con1;
+ uint32_t g3d_pll_con2;
+ uint8_t res2[0xf4];
+ uint32_t clk_mux_sel_g3d;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_enable_g3d;
+ uint8_t res4[0xfc];
+ uint32_t clk_mux_stat_g3d;
+ uint8_t res5[0x1fc];
+ uint32_t clk_div_g3d;
+ uint8_t res6[0xfc];
+ uint32_t clk_div_stat_g3d;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_aclk_g3d;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_pclk_g3d;
+ uint8_t res9[0xfc];
+ uint32_t clk_en_sclk_g3d;
+ uint8_t res10[0x1fc];
+ uint32_t clkout_cmu_g3d;
+ uint32_t clkout_cmu_g3d_div_stat;
+ uint8_t res11[0x3f8];
+ uint32_t clk_stopctrl;
+};
+
+static struct exynos7_clock_g3d * const g3d =
+ (struct exynos7_clock_g3d *)EXYNOS7_CMU_G3D_BASE;
+
+struct exynos7_clock_hevc {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_hevc;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_hevc;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_hevc;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_hevc;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_hevc;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_hevc;
+ uint8_t res7[0xfc];
+ uint32_t clk_en_pclk_hevc;
+ uint8_t res8[0xfc];
+ uint32_t clk_en_sclk_hevc;
+ uint8_t res9[0x1fc];
+ uint32_t clkout_cmu_hevc;
+ uint32_t clkout_cmu_hevc_div_stat;
+};
+
+static struct exynos7_clock_hevc * const hevc =
+ (struct exynos7_clock_hevc *)EXYNOS7_CMU_HEVC_BASE;
+
+struct exynos7_clock_imem {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_imem;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_imem;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_imem;
+ uint8_t res4[0x3fc];
+ uint32_t clk_en_aclk_imem0;
+ uint32_t clk_en_aclk_imem1;
+ uint32_t clk_en_aclk_imem_secure_int_mem;
+ uint32_t clk_en_aclk_imem_secure_sss;
+ uint32_t clk_en_aclk_imem_secure_slim_sss;
+ uint32_t clk_en_aclk_imem_secure_rtic;
+ uint32_t clk_en_aclk_imem_secure_sysmmu600_sss;
+ uint32_t clk_en_aclk_imem_secure_sysmmu600_slim_sss;
+ uint32_t clk_en_aclk_imem_secure_cm3_apm;
+ uint32_t clk_en_aclk_imem_secure_ahb_busmatrix_apm;
+ uint32_t clk_en_aclk_imem_secure_isramc_apm;
+ uint32_t clk_en_aclk_imem_secure_ahb2_apb_bridge_apm;
+ uint32_t clk_en_aclk_imem_secure_pdma_imem;
+ uint8_t res5[0xcc];
+ uint32_t clk_en_pclk_imem0;
+ uint32_t clk_en_pclk_imem1;
+ uint32_t clk_en_pclk_imem_secure_int_mem;
+ uint32_t clk_en_pclk_imem_secure_sss;
+ uint32_t clk_en_pclk_imem_secure_slim_sss;
+ uint32_t clk_en_pclk_imem_secure_rtic;
+ uint32_t clk_en_pclk_imem_secure_sysmmu600_sss;
+ uint32_t clk_en_pclk_imem_secure_sysmmu600_slim_sss;
+ uint32_t clk_en_pclk_imem_secure_cm3_apm;
+ uint32_t clk_en_pclk_imem_secure_ahb_busmatrix_apm;
+ uint32_t clk_en_pclk_imem_secure_isramc_apm;
+ uint32_t clk_en_pclk_imem_secure_ahb2_apb_bridge_apm;
+ uint32_t clk_en_pclk_imem_secure_pdma_imem;
+ uint8_t res6[0x2cc];
+ uint32_t clkout_cmu_imem;
+ uint32_t clkout_cmu_imem_div_stat;
+};
+
+static struct exynos7_clock_imem * const imem =
+ (struct exynos7_clock_imem *)EXYNOS7_CMU_IMEM_BASE;
+
+struct exynos7_clock_mfc {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mfc;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_mfc;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mfc;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mfc;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mfc;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mfc;
+ uint32_t clk_en_aclk_mfc_secure_smmu_mfc_0;
+ uint32_t clk_en_aclk_mfc_secure_sfw_mfc_0;
+ uint32_t clk_en_aclk_mfc_secure_smmu_mfc_1;
+ uint32_t clk_en_aclk_mfc_secure_sfw_mfc_1;
+ uint8_t res7[0xec];
+ uint32_t clk_en_pclk_mfc;
+ uint32_t clk_en_pclk_mfc_secure_smmu_mfc_0;
+ uint32_t clk_en_pclk_mfc_secure_sfw_mfc_0;
+ uint32_t clk_en_pclk_mfc_secure_smmu_mfc_1;
+ uint32_t clk_en_pclk_mfc_secure_sfw_mfc_1;
+ uint8_t res8[0x2ec];
+ uint32_t clkout_cmu_mfc;
+ uint32_t clkout_cmu_mfc_div_stat;
+};
+
+static struct exynos7_clock_mfc * const mfc =
+ (struct exynos7_clock_mfc *)EXYNOS7_CMU_MFC_BASE;
+
+struct exynos7_clock_mif0 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif0;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif0;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif0;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif0;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif0;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif0;
+ uint32_t clk_en_aclk_mif0_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif0;
+ uint32_t clk_en_pclk_mif0_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif0;
+ uint32_t clk_en_sclk_mif0_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif0;
+ uint32_t clkout_cmu_mif0_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif0;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif0;
+};
+
+static struct exynos7_clock_mif0 * const mif0 =
+ (struct exynos7_clock_mif0 *)EXYNOS7_CMU_MIF0_BASE;
+
+struct exynos7_clock_mif1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif1;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif1;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif1;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif1;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif1;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif1;
+ uint32_t clk_en_aclk_mif1_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif1;
+ uint32_t clk_en_pclk_mif1_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif1;
+ uint32_t clk_en_sclk_mif1_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif1;
+ uint32_t clkout_cmu_mif1_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif1;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif1;
+};
+
+static struct exynos7_clock_mif1 * const mif1 =
+ (struct exynos7_clock_mif1 *)EXYNOS7_CMU_MIF1_BASE;
+
+struct exynos7_clock_mif2 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif2;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif2;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif2;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif2;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif2;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif2;
+ uint32_t clk_en_aclk_mif2_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif2;
+ uint32_t clk_en_pclk_mif2_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif2;
+ uint32_t clk_en_sclk_mif2_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif2;
+ uint32_t clkout_cmu_mif2_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif2;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif2;
+};
+
+static struct exynos7_clock_mif2 * const mif2 =
+ (struct exynos7_clock_mif2 *)EXYNOS7_CMU_MIF2_BASE;
+
+struct exynos7_clock_mif3 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mif3;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_enable_mif3;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mif3;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mif3;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mif3;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mif3;
+ uint32_t clk_en_aclk_mif3_secure_drex_tz;
+ uint8_t res7[0xf8];
+ uint32_t clk_en_pclk_mif3;
+ uint32_t clk_en_pclk_mif3_secure_drex_tz;
+ uint8_t res8[0xf8];
+ uint32_t clk_en_sclk_mif3;
+ uint32_t clk_en_sclk_mif3_secure_drex_tz;
+ uint8_t res9[0x1f8];
+ uint32_t clkout_cmu_mif3;
+ uint32_t clkout_cmu_mif3_div_stat;
+ uint8_t res10[0x3f8];
+ uint32_t pause_mif3;
+ uint8_t res11[0x8];
+ uint32_t ddrphy_lock_ctrl_mif3;
+};
+
+static struct exynos7_clock_mif3 * const mif3 =
+ (struct exynos7_clock_mif3 *)EXYNOS7_CMU_MIF3_BASE;
+
+struct exynos7_clock_mscl {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_mscl;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_mscl;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_mscl;
+ uint8_t res4[0x1fc];
+ uint32_t clk_div_mscl;
+ uint8_t res5[0xfc];
+ uint32_t clk_div_stat_mscl;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_aclk_mscl;
+ uint32_t clk_en_aclk_mscl_secure_smmu_0_mmu;
+ uint32_t clk_en_aclk_mscl_secure_smmu_0_sfw;
+ uint32_t clk_en_aclk_mscl_secure_smmu_1_mmu;
+ uint32_t clk_en_aclk_mscl_secure_smmu_1_sfw;
+ uint32_t clk_en_aclk_mscl_secure_smmu_g2d_mmu;
+ uint32_t clk_en_aclk_mscl_secure_smmu_g2d_sfw;
+ uint8_t res7[0xe4];
+ uint32_t clk_en_pclk_mscl;
+ uint32_t clk_en_pclk_mscl_secure_smmu_0_mmu;
+ uint32_t clk_en_pclk_mscl_secure_smmu_0_sfw;
+ uint32_t clk_en_pclk_mscl_secure_smmu_1_mmu;
+ uint32_t clk_en_pclk_mscl_secure_smmu_1_sfw;
+ uint32_t clk_en_pclk_mscl_secure_smmu_g2d_mmu;
+ uint32_t clk_en_pclk_mscl_secure_smmu_g2d_sfw;
+ uint8_t res8[0xe4];
+ uint32_t clk_en_sclk_mscl;
+ uint8_t res9[0x1fc];
+ uint32_t clkout_cmu_mscl;
+ uint32_t clkout_cmu_mscl_div_stat;
+};
+
+static struct exynos7_clock_mscl * const mscl =
+ (struct exynos7_clock_mscl *)EXYNOS7_CMU_MSCL_BASE;
+
+struct exynos7_clock_peric0 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_peric0;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_peric0;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_peric0;
+ uint8_t res4[0x3fc];
+ uint32_t clk_en_aclk_peric0;
+ uint8_t res5[0xfc];
+ uint32_t clk_en_pclk_peric0;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_sclk_peric0;
+ uint8_t res7[0x1fc];
+ uint32_t clkout_cmu_peric0;
+ uint32_t clkout_cmu_peric0_div_stat;
+};
+
+static struct exynos7_clock_peric0 * const peric0 =
+ (struct exynos7_clock_peric0 *)EXYNOS7_CMU_PERIC0_BASE;
+
+struct exynos7_clock_peric1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_peric10;
+ uint32_t clk_mux_sel_peric11;
+ uint32_t clk_mux_sel_peric12;
+ uint8_t res2[0xf4];
+ uint32_t clk_mux_en_peric10;
+ uint32_t clk_mux_en_peric11;
+ uint32_t clk_mux_en_peric12;
+ uint8_t res3[0xf4];
+ uint32_t clk_mux_stat_peric10;
+ uint32_t clk_mux_stat_peric11;
+ uint32_t clk_mux_stat_peric12;
+ uint8_t res4[0x3f4];
+ uint32_t clk_en_aclk_peric1;
+ uint8_t res5[0xfc];
+ uint32_t clk_en_pclk_peric1;
+ uint8_t res6[0xfc];
+ uint32_t clk_en_sclk_peric1;
+ uint8_t res7[0x1fc];
+ uint32_t clkout_cmu_peric1;
+ uint32_t clkout_cmu_peric1_div_stat;
+};
+
+static struct exynos7_clock_peric1 * const peric1 =
+ (struct exynos7_clock_peric1 *)EXYNOS7_CMU_PERIC1_BASE;
+
+struct exynos7_clock_peris {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_peris;
+ uint8_t res2[0xfc];
+ uint32_t clk_mux_en_peris;
+ uint8_t res3[0xfc];
+ uint32_t clk_mux_stat_peris;
+ uint8_t res4[0x3fc];
+ uint32_t clk_en_aclk_peris;
+ uint8_t res5[0xfc];
+ uint32_t clk_en_pclk_peris;
+ uint32_t clk_en_pclk_peris_secure_tzpc;
+ uint32_t clk_en_pclk_peris_secure_otp;
+ uint32_t clk_en_pclk_peris_secure_rtc;
+ uint32_t clk_en_pclk_peris_secure_chipid;
+ uint8_t res6[0xec];
+ uint32_t clk_en_sclk_peris;
+ uint32_t clk_en_sclk_peris_secure_tzpc;
+ uint32_t clk_en_sclk_peris_secure_otp;
+ uint32_t clk_en_sclk_peris_secure_rtc;
+ uint32_t clk_en_sclk_peris_secure_chipid;
+ uint8_t res7[0x1ec];
+ uint32_t clkout_cmu_peris;
+ uint32_t clkout_cmu_peris_div_stat;
+};
+
+static struct exynos7_clock_peris * const peris =
+ (struct exynos7_clock_peris *)EXYNOS7_CMU_PERIS_BASE;
+
+struct exynos7_clock_topc {
+ uint32_t cci_pll_lock;
+ uint32_t bus0_pll_lock;
+ uint32_t bus1_pll_lock;
+ uint32_t mfc_pll_lock;
+ uint32_t aud_pll_lock;
+ uint32_t mif_pll_lock;
+ uint8_t res1[0xe8];
+ uint32_t cci_pll_con0;
+ uint32_t cci_pll_con1;
+ uint8_t res2[0x8];
+ uint32_t bus0_pll_con0;
+ uint32_t bus0_pll_con1;
+ uint8_t res3[0x8];
+ uint32_t bus1_pll_con0;
+ uint32_t bus1_pll_con1;
+ uint8_t res4[0x8];
+ uint32_t mfc_pll_con0;
+ uint32_t mfc_pll_con1;
+ uint8_t res5[0x8];
+ uint32_t aud_pll_con0;
+ uint32_t aud_pll_con1;
+ uint32_t aud_pll_con2;
+ uint8_t res6[0x4];
+ uint32_t mif_pll_con0;
+ uint32_t mif_pll_con1;
+ uint32_t mif_pll_con2;
+ uint8_t res7[0xa4];
+ uint32_t clk_mux_sel_topc0;
+ uint32_t clk_mux_sel_topc1;
+ uint32_t clk_mux_sel_topc2;
+ uint32_t clk_mux_sel_topc3;
+ uint32_t clk_mux_sel_topc4;
+ uint32_t clk_mux_sel_topc5;
+ uint8_t res8[0xe8];
+ uint32_t clk_mux_en_top_topc0;
+ uint32_t clk_mux_en_top_topc1;
+ uint32_t clk_mux_en_top_topc2;
+ uint32_t clk_mux_en_top_topc3;
+ uint32_t clk_mux_en_top_topc4;
+ uint32_t clk_mux_en_top_topc5;
+ uint8_t res9[0xe8];
+ uint32_t clk_mux_stat_top_topc0;
+ uint32_t clk_mux_stat_top_topc1;
+ uint32_t clk_mux_stat_top_topc2;
+ uint32_t clk_mux_stat_top_topc3;
+ uint32_t clk_mux_stat_top_topc4;
+ uint32_t clk_mux_stat_top_topc5;
+ uint8_t res10[0x1e8];
+ uint32_t clk_div_topc0;
+ uint32_t clk_div_topc1;
+ uint32_t clk_div_topc2;
+ uint32_t clk_div_topc3;
+ uint8_t res11[0xf0];
+ uint32_t clk_div_stat_topc0;
+ uint32_t clk_div_stat_topc1;
+ uint32_t clk_div_stat_topc2;
+ uint32_t clk_div_stat_topc3;
+ uint8_t res12[0xf0];
+ uint32_t clk_en_aclk_topc0;
+ uint32_t clk_en_aclk_topc1;
+ uint32_t clk_en_aclk_topc2;
+ uint8_t res13[0x1f4];
+ uint32_t clk_en_sclk_topc0;
+ uint32_t clk_en_sclk_topc1;
+ uint8_t res14[0xf8];
+ uint32_t clk_en_ip_topc;
+ uint8_t res15[0xfc];
+ uint32_t clkout_cmu_topc;
+ uint32_t clkout_all_blk_cmu;
+ uint8_t res16[0x8];
+ uint32_t clkout_cmu_topc_div_stat;
+ uint32_t clkout_all_blk_cmu_div_stat;
+ uint8_t res17[0xe8];
+ uint32_t cmu_topc_low_power_mode;
+ uint32_t cmu_topc_lp4_phy_div_sel;
+ uint32_t cmu_topc_rootclken_on;
+ uint8_t res18[0x2f8];
+ uint32_t drex_freq_ctrl1;
+ uint32_t pause;
+ uint8_t res19[0xf4];
+ uint32_t dvfs_ctrl_vdd_int;
+ uint8_t res20[0xc];
+ uint32_t dvfs_ctrl_vdd_disp_cam0;
+};
+
+static struct exynos7_clock_topc * const topc =
+ (struct exynos7_clock_topc *)EXYNOS7_CMU_TOPC_BASE;
+
+struct exynos7_clock_top0 {
+ uint8_t res1[0x4];
+ uint32_t isp_pll_lock;
+ uint32_t cam_pll_lock;
+ uint8_t res2[0x104];
+ uint32_t isp_pll_con0;
+ uint32_t isp_pll_con1;
+ uint8_t res3[0x8];
+ uint32_t cam_pll_con0;
+ uint32_t cam_pll_con1;
+ uint8_t res4[0xd8];
+ uint32_t clk_mux_sel_top00;
+ uint32_t clk_mux_sel_top01;
+ uint32_t clk_mux_sel_top02;
+ uint32_t clk_mux_sel_top03;
+ uint32_t clk_mux_sel_top04;
+ uint32_t clk_mux_sel_top05;
+ uint32_t clk_mux_sel_top06;
+ uint32_t clk_mux_sel_top07;
+ uint32_t clk_mux_sel_top0_disp;
+ uint32_t clk_mux_sel_top0_cam10;
+ uint32_t clk_mux_sel_top0_cam11;
+ uint8_t res5[0x4];
+ uint32_t clk_mux_sel_top0_peric0;
+ uint32_t clk_mux_sel_top0_peric1;
+ uint32_t clk_mux_sel_top0_peric2;
+ uint32_t clk_mux_sel_top0_peric3;
+ uint8_t res6[0xc0];
+ uint32_t clk_mux_en_top_top00;
+ uint32_t clk_mux_en_top_top01;
+ uint32_t clk_mux_en_top_top02;
+ uint32_t clk_mux_en_top_top03;
+ uint32_t clk_mux_en_top_top04;
+ uint32_t clk_mux_en_top_top05;
+ uint32_t clk_mux_en_top_top06;
+ uint32_t clk_mux_en_top_top07;
+ uint32_t clk_mux_en_top0_disp;
+ uint32_t clk_mux_en_top0_cam10;
+ uint32_t clk_mux_en_top0_cam11;
+ uint8_t res7[0x4];
+ uint32_t clk_mux_en_top0_peric0;
+ uint32_t clk_mux_en_top0_peric1;
+ uint32_t clk_mux_en_top0_peric2;
+ uint32_t clk_mux_en_top0_peric3;
+ uint8_t res8[0xc0];
+ uint32_t clk_mux_stat_top_top00;
+ uint32_t clk_mux_stat_top_top01;
+ uint32_t clk_mux_stat_top_top02;
+ uint32_t clk_mux_stat_top_top03;
+ uint32_t clk_mux_stat_top_top04;
+ uint32_t clk_mux_stat_top_top05;
+ uint32_t clk_mux_stat_top_top06;
+ uint32_t clk_mux_stat_top_top07;
+ uint32_t clk_mux_stat_top0_disp;
+ uint32_t clk_mux_stat_top0_cam10;
+ uint32_t clk_mux_stat_top0_cam11;
+ uint8_t res9[0x4];
+ uint32_t clk_mux_stat_top0_peric0;
+ uint32_t clk_mux_stat_top0_peric1;
+ uint32_t clk_mux_stat_top0_peric2;
+ uint32_t clk_mux_stat_top0_peric3;
+ uint8_t res10[0x1c0];
+ uint32_t clk_div_top00;
+ uint32_t clk_div_top01;
+ uint32_t clk_div_top02;
+ uint32_t clk_div_top03;
+ uint32_t clk_div_top04;
+ uint32_t clk_div_top05;
+ uint32_t clk_div_top06;
+ uint32_t clk_div_top07;
+ uint32_t clk_div_top0_disp;
+ uint32_t clk_div_top0_cam10;
+ uint32_t clk_div_top0_cam11;
+ uint8_t res11[0x4];
+ uint32_t clk_div_top0_peric0;
+ uint32_t clk_div_top0_peric1;
+ uint32_t clk_div_top0_peric2;
+ uint32_t clk_div_top0_peric3;
+ uint8_t re12[0xc0];
+ uint32_t clk_div_stat_top00;
+ uint32_t clk_div_stat_top01;
+ uint32_t clk_div_stat_top02;
+ uint32_t clk_div_stat_top03;
+ uint32_t clk_div_stat_top04;
+ uint32_t clk_div_stat_top05;
+ uint32_t clk_div_stat_top06;
+ uint32_t clk_div_stat_top07;
+ uint32_t clk_div_stat_top0_disp;
+ uint32_t clk_div_stat_top0_cam10;
+ uint32_t clk_div_stat_top0_cam11;
+ uint8_t res13[0x4];
+ uint32_t clk_div_stat_top0_peric0;
+ uint32_t clk_div_stat_top0_peric1;
+ uint32_t clk_div_stat_top0_peric2;
+ uint32_t clk_div_stat_top0_peric3;
+ uint8_t res14[0xc0];
+ uint32_t clk_en_aclk_top00;
+ uint32_t clk_en_aclk_top01;
+ uint32_t clk_en_aclk_top02;
+ uint32_t clk_en_aclk_top03;
+ uint32_t clk_en_aclk_top04;
+ uint32_t clk_en_aclk_top05;
+ uint32_t clk_en_aclk_top06;
+ uint32_t clk_en_aclk_top07;
+ uint8_t res15[0x200];
+ uint32_t clk_en_sclk_top0_disp;
+ uint32_t clk_en_sclk_top0_cam10;
+ uint32_t clk_en_sclk_top0_cam11;
+ uint8_t res16[0x4];
+ uint32_t clk_en_sclk_top0_peric0;
+ uint32_t clk_en_sclk_top0_peric1;
+ uint32_t clk_en_sclk_top0_peric2;
+ uint32_t clk_en_sclk_top0_peric3;
+ uint8_t res17[0xc0];
+ uint32_t clk_en_ip_top0;
+ uint8_t res18[0xfc];
+ uint32_t clkout_cmu_top0;
+ uint32_t clkout_cmu_top0_div_stat;
+ uint8_t res19[0xf8];
+ uint32_t mode_clock_en;
+ uint32_t cmu_top0_rootclken_on0;
+ uint32_t cmu_top0_rootclken_on1;
+ uint8_t res20[0xf4];
+ uint32_t cmu_top0_dvfs_ctrl_stat;
+};
+
+static struct exynos7_clock_top0 * const top0 =
+ (struct exynos7_clock_top0 *)EXYNOS7_CMU_TOP0_BASE;
+
+struct exynos7_clock_top1 {
+ uint8_t res1[0x200];
+ uint32_t clk_mux_sel_top10;
+ uint32_t clk_mux_sel_top11;
+ uint32_t clk_mux_sel_top12;
+ uint32_t clk_mux_sel_top13;
+ uint8_t res2[0x14];
+ uint32_t clk_mux_sel_top1_fsys0;
+ uint32_t clk_mux_sel_top1_fsys1;
+ uint32_t clk_mux_sel_top1_fsys11;
+ uint8_t res3[0xd0];
+ uint32_t clk_mux_en_top10;
+ uint32_t clk_mux_en_top11;
+ uint32_t clk_mux_en_top12;
+ uint32_t clk_mux_en_top13;
+ uint8_t res4[0x14];
+ uint32_t clk_mux_en_top1_fsys0;
+ uint32_t clk_mux_en_top1_fsys1;
+ uint32_t clk_mux_en_top1_fsys11;
+ uint8_t res5[0xd0];
+ uint32_t clk_mux_stat_top10;
+ uint32_t clk_mux_stat_top11;
+ uint32_t clk_mux_stat_top12;
+ uint32_t clk_mux_stat_top13;
+ uint8_t res6[0x14];
+ uint32_t clk_mux_stat_top1_fsys0;
+ uint32_t clk_mux_stat_top1_fsys1;
+ uint32_t clk_mux_stat_top1_fsys11;
+ uint8_t res7[0x1d0];
+ uint32_t clk_div_top10;
+ uint32_t clk_div_top11;
+ uint32_t clk_div_top12;
+ uint32_t clk_div_top13;
+ uint8_t res8[0x14];
+ uint32_t clk_div_top1_fsys0;
+ uint32_t clk_div_top1_fsys1;
+ uint32_t clk_div_top1_fsys11;
+ uint8_t res9[0xd0];
+ uint32_t clk_div_stat_top10;
+ uint32_t clk_div_stat_top11;
+ uint32_t clk_div_stat_top12;
+ uint32_t clk_div_stat_top13;
+ uint8_t res10[0x14];
+ uint32_t clk_div_stat_top1_fsys0;
+ uint32_t clk_div_stat_top1_fsys1;
+ uint32_t clk_div_stat_top1_fsys11;
+ uint8_t res11[0xd0];
+ uint32_t clk_en_aclk_top10;
+ uint32_t clk_en_aclk_top11;
+ uint32_t clk_en_aclk_top12;
+ uint32_t clk_en_aclk_top13;
+ uint8_t res12[0x214];
+ uint32_t clk_en_sclk_top1_fsys0;
+ uint32_t clk_en_sclk_top1_fsys1;
+ uint32_t clk_en_sclk_top1_fsys11;
+ uint8_t res13[0xd0];
+ uint32_t clk_en_ip_top1;
+ uint8_t res14[0xfc];
+ uint32_t clkout_cmu_top1;
+ uint32_t clkout_cmu_top1_div_stat;
+ uint8_t res15[0xfc];
+ uint32_t cmu_top1_rootclken_on;
+ uint8_t res16[0xf8];
+ uint32_t cmu_top1_dvfs_ctrl_stat;
+};
+
+static struct exynos7_clock_top1 * const top1 =
+ (struct exynos7_clock_top1 *)EXYNOS7_CMU_TOP1_BASE;
+
+unsigned long get_arm_clk(void);
+unsigned long get_i2c_clk(void);
+unsigned long get_mmc_clk(int dev_index);
+unsigned long get_pll_clk(int pllreg);
+unsigned long get_pwm_clk(void);
+unsigned long get_uart_clk(int dev_index);
+unsigned long get_usbdrd_clk(void);
+
+void set_mmc_clk(int dev_index, uint64_t div);
+void dmc_driver_freq(void);
+int system_clock_init(int is_resume);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_CLOCK_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/clock_init.h b/src/soc/samsung/exynos7/include/soc/clock_init.h
new file mode 100644
index 0000000..28c3626
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/clock_init.h
@@ -0,0 +1,434 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_CLOCK_INIT_H_
+#define _CPU_SAMSUNG_EXYNOS7_CLOCK_INIT_H_
+
+/* Position and set M, P & S divider values */
+#define set_pll(mdiv, pdiv, sdiv) (mdiv << 16 | pdiv << 8 | sdiv << 0)
+
+/* Define PLLs */
+#define EXYNOS7_CCI_PLL 532
+#define EXYNOS7_BUS0_PLL 1600
+#define EXYNOS7_ISP_PLL 0
+#define EXYNOS7_CAM_PLL 0
+#define EXYNOS7_G3D_PLL 532
+#define EXYNOS7_AP_PLL 900
+#define EXYNOS7_MIF_PLL 1264
+
+/* Set clock enable */
+#define ENABLE(x) (x << 31)
+#define ENABLE_SDIV_CLKSTOP(x) (x << 16)
+#define ENABLE_MDIV_CLKSTOP(x) (x << 5)
+
+/* MIF Pause */
+#define PAUSE_MIF(x) (x << 20)
+
+/* AP0 clock divider */
+#define AP_PCLK_DBG_RATIO(x) (x << 26)
+#define AP_ATCLK_RATIO(x) (x << 20)
+#define AP_PCLK_AP_RATIO(x) (x << 12)
+#define AP_ACLK_AP_RATIO(x) (x << 8)
+#define AP_AP2_RATIO(x) (x << 4)
+#define AP_AP1_RATIO(x) (x << 0)
+
+/* AP1 clock divider */
+#define AP_CNTCLK_RATIO(x) (x << 8)
+#define AP_SCLK_HPM_AP_RATIO(x) (x << 4)
+#define AP_AP_PLL_RATIO(x) (x << 0)
+
+/* AUD0 clock divider */
+#define AUD_PCLK_DBG_AUD_RATIO(x) (x << 8)
+#define AUD_ACLK_AUD_RATIO(x) (x << 4)
+#define AUD_CA5_RATIO(x) (x << 0)
+
+/* AUD1 clock divider */
+#define AUD_CDCLK_RATIO(x) (x << 24)
+#define AUD_SCLK_SLIMBUS_RATIO(x) (x << 16)
+#define AUD_SCLK_UART_RATIO(x) (x << 12)
+#define AUD_SCLK_PCM_RATIO(x) (x << 4)
+#define AUD_SCLK_I2S_RATIO(x) (x << 0)
+
+/* BUS0 clock divider */
+#define PCLK_BUS0_133_RATIO(x) (x << 0)
+
+/* BUS1 clock divider */
+#define PCLK_BUS1_133_RATIO(x) (x << 0)
+
+/* CCORE clock divider */
+#define ACLK_CCORE_266_RATIO(x) (x << 0)
+
+/* DISP clock divider */
+#define DISP_SCLK_DECON_INT_ECLK_RATIO(x) (x << 20)
+#define DISP_SCLK_DECON_EXT_ECLK_RATIO(x) (x << 16)
+#define DISP_SCLK_DECON_INT_EXTCLKPLL_RATIO(x) (x << 12)
+#define DISP_SCLK_DECON_EXT_EXTCLKPLL_RATIO(x) (x << 8)
+#define DISP_PCLK_DISP_RATIO(x) (x << 0)
+
+/* FSYS0 clock divider */
+#define FSYS0_USB20_RATIO(x) (x << 4)
+#define FSYS0_PCLK_FSYS0_RATIO(x) (x << 0)
+
+/* FSYS1 clock divider */
+#define FSYS1_PCLK_FSYS1_RATIO(x) (x << 0)
+
+/* G2D clock divider */
+#define G2D_PCLK_G2D_RATIO(x) (x << 0)
+
+/* G3D clock divider */
+#define G3D_SCLK_HPM_G3D_RATIO(x) (x << 8)
+#define G3D_PCLK_G3D_RATIO(x) (x << 4)
+#define G3D_ACLK_G3D_RATIO(x) (x << 0)
+
+/* HEVC clock divider */
+#define HEVC_PCLK_HEVC_RATIO(x) (x << 0)
+
+/* MFC clock divider */
+#define MFC_PCLK_MFC_PROMISE_RATIO(x) (x << 4)
+#define MFC_PCLK_MFC_RATIO(x) (x << 0)
+
+/* MIF clock divider */
+#define MIF_SCLK_HPM_MIF_RATIO(x) (x << 4)
+#define MIF_PCLK_MIF_RATIO(x) (x << 0)
+
+/* MSCL clock divider */
+#define MSCL_PCLK_MSCL_RATIO(x) (x << 0)
+
+/* TOPC3 clock divider */
+#define SCLK_AUD_PLL_RATIO(x) (x << 24)
+#define SCLK_BUS_PLL_G3D_RATIO(x) (x << 20)
+#define SCLK_MFC_PLL_RATIO(x) (x << 16)
+#define SCLK_CCI_PLL_RATIO(x) (x << 12)
+#define SCLK_BUS1_PLL_RATIO(x) (x << 8)
+#define SCLK_BUS0_PLL_MIF_RATIO(x) (x << 4)
+#define SCLK_BUS0_PLL_RATIO(x) (x << 0)
+
+/* AP Mux Select */
+#define AP_BUS_PLL_USER_SEL(x) (x << 0)
+#define AP_SEL(x) (x << 0)
+#define AP_PLL_SEL(x) (x << 0)
+
+/* AUD Mux select */
+#define AUD_PLL_USER_SEL(x) (x << 20)
+#define AUD_SCLK_PCM_SEL(x) (x << 16)
+#define AUD_SCLK_I2S_SEL(x) (x << 12)
+
+/* BUS0 Mux select */
+#define ACLK_BUS0_532_USER_SEL(x) (x << 0)
+
+/* BUS1 Mux select */
+#define ACLK_BUS1_200_USER_SEL(x) (x << 4)
+#define ACLK_BUS1_532_USER_SEL(x) (x << 0)
+
+/* CCORE Mux select */
+#define ACLK_CCORE_133_USER_SEL(x) (x << 1)
+#define ACLK_CCORE_532_USER_SEL(x) (x << 0)
+
+/* DISP0 Mux select */
+#define DISP0_PLL_SEL(x) (x << 28)
+#define DISP0_ACLK_DISP_400_USER_SEL(x) (x << 24)
+
+/* DISP1 Mux select */
+#define DISP1_SCLK_DECON_INT_ECLK(x) (x << 28)
+#define DISP1_SCLK_DECON_EXT_ECLK(x) (x << 24)
+#define DISP1_SCLK_DECON_VCLK(x) (x << 20)
+#define DISP1_SCLK_DSD(x) (x << 16)
+
+/* DISP2 Mux select */
+#define DISP2_PHYCLK_HDMIPHY_PIXEL_CLKO(x) (x << 20)
+#define DISP2_PHYCLK_HDMIPHY_TMDS_CLKO(x) (x << 16)
+#define DISP2_PHYCLK_MIPIDPHY0_RXCLKESC0(x) (x << 12)
+#define DISP2_PHYCLK_MIPIDPHY0_BITCLKDIV8(x) (x << 8)
+#define DISP2_PHYCLK_MIPIDPHY1_RXCLKESC0(x) (x << 4)
+#define DISP2_PHYCLK_MIPIDPHY1_BITCLKDIV8(x) (x << 0)
+
+/* DISP3 Mux select */
+#define DISP3_SCLK_DECON_INT_ECLK(x) (x << 20)
+#define DISP3_SCLK_DECON_EXT_ECLK(x) (x << 16)
+#define DISP3_SCLK_DECON_INT_EXTCLKPLL(x) (x << 12)
+#define DISP3_SCLK_DECON_EXT_EXTCLKPLL(x) (x << 8)
+
+/* FSYS00 Mux select */
+#define FSYS0_HSIC_PLL_SEL(x) (x << 28)
+#define FSYS0_ACLK_FSYS0_200(x) (x << 24)
+#define FSYS0_PHYCLK_SEL0(x) (x << 20)
+#define FSYS0_PHYCLK_SEL1(x) (x << 16)
+
+/* FSYS01 Mux select */
+#define FSYS0_SCLK_USBDRD300(x) (x << 28)
+#define FSYS0_SCLK_MMC2(x) (x << 24)
+#define FSYS0_SCLK_UFSUNIPRO11(x) (x << 20)
+#define FSYS0_SCLK_PHY_FSYS0(x) (x << 16)
+
+/* FSYS02 Mux select */
+#define FSYS0_PHYCLK_USBDRD300_UDRD30_PHYCLOCK(x) (x << 28)
+#define FSYS0_PHYCLK_USBDRD300_UDRD30_PIPE_PCLK(x) (x << 24)
+#define FSYS0_PHYCLK_USBHOST20_PHY_FREECLK__HSIC1(x) (x << 20)
+#define FSYS0_PHYCLK_USBHOST20_PHY_PHYCLK__HSIC1(x) (x << 16)
+
+/* FSYS03 Mux select */
+#define FSYS0_PHYCLK_UFS_TX0_SYMBOL(x) (x << 28)
+#define FSYS0_PHYCLK_UFS_RX0_SYMBOL(x) (x << 24)
+#define FSYS0_PHYCLK_LLI_TX0_SYMBOL(x) (x << 20)
+#define FSYS0_PHYCLK_LLI_RX0_SYMBOL(x) (x << 16)
+#define FSYS0_PHYCLK_PCIE_TX0(x) (x << 12)
+#define FSYS0_PHYCLK_PCIE_RX0(x) (x << 8)
+
+/* FSYS10 Mux select */
+#define FSYS1_ACLK_FSYS1_200(x) (x << 28)
+#define FSYS1_PHYCLK_SEL0(x) (x << 20)
+#define FSYS1_PHYCLK_SEL1(x) (x << 16)
+
+/* FSYS11 Mux select */
+#define FSYS1_SCLK_MMC0(x) (x << 28)
+#define FSYS1_SCLK_MMC1(x) (x << 24)
+#define FSYS1_SCLK_UFSUNIPRO20(x) (x << 20)
+#define FSYS1_SCLK_PHY_FSYS1(x) (x << 16)
+#define FSYS1_SCLK_TLX400_WIFI1(x) (x << 12)
+
+/* FSYS12 Mux select */
+#define FSYS1_PHYCLK_UFS20_TX0_SYMBOL(x) (x << 28)
+#define FSYS1_PHYCLK_UFS20_RX0_SYMBOL(x) (x << 24)
+#define FSYS1_PHYCLK_UFS20_RX1_SYMBOL(x) (x << 16)
+#define FSYS1_PHYCLK_PCIE_WIFI1_TX0(x) (x << 12)
+#define FSYS1_PHYCLK_PCIE_WIFI1_RX0(x) (x << 8)
+
+/* G2D Mux select */
+#define G2D_ACLK_G2D_266_USER_SEL(x) (x << 4)
+#define G2D_ACLK_G2D_400_USER_SEL(x) (x << 0)
+
+/* G3D Mux select */
+#define G3D_SEL(x) (x << 8)
+#define G3D_SCLK_BUS_PLL_G3D_USER_SEL(x) (x << 4)
+#define G3D_PLL_SEL(x) (x << 0)
+
+/* HEVC Mux select */
+#define HEVC_ACLK_HEVC_532_USER_SEL(x) (x << 0)
+
+/* IMEM Mux select */
+#define ACLK_IMEM_100_USER_SEL(x) (x << 8)
+#define ACLK_IMEM_200_USER_SEL(x) (x << 4)
+#define ACLK_IMEM_266_USER_SEL(x) (x << 0)
+
+/* MFC Mux select */
+#define MFC_ACLK_MFC_BUS_532_USER_SEL(x) (x << 4)
+#define MFC_ACLK_MFC_532_USER_SEL(x) (x << 0)
+
+/* MIF Mux select */
+#define MIF_ACLK_MIF_PLL_CLK_MUX_SEL(x) (x << 16)
+#define MIF_MIF_PLL_USER_SEL(x) (x << 12)
+#define MIF_SCLK_HPM_MIF_SEL(x) (x << 8)
+#define MIF_PCLK_MIF_SEL(x) (x << 4)
+#define MIF_ACLK_MIF_USER_SEL(x) (x << 0)
+
+/* MSCL Mux select */
+#define MSCL_ACLK_MSCL_532_USER_SEL(x) (x << 0)
+
+/* PERIC0 Mux select */
+#define PERIC0_SCLK_UART0_USER_SEL(x) (x << 16)
+#define PERIC0_ACLK_PERIC0_66_USER_SEL(x) (x << 0)
+
+/* PERIC10 Mux select */
+#define PERIC10_ACLK_PERIC1_66_USER_SEL(x) (x << 0)
+
+/* PERIC11 Mux select */
+#define PERIC11_SCLK_UART3_USER_SEL(x) (x << 28)
+#define PERIC11_SCLK_UART2_USER_SEL(x) (x << 24)
+#define PERIC11_SCLK_UART1_USER_SEL(x) (x << 20)
+#define PERIC11_SCLK_SPI4_USER_SEL(x) (x << 16)
+#define PERIC11_SCLK_SPI3_USER_SEL(x) (x << 12)
+#define PERIC11_SCLK_SPI2_USER_SEL(x) (x << 8)
+#define PERIC11_SCLK_SPI1_USER_SEL(x) (x << 4)
+#define PERIC11_SCLK_SPI0_USER_SEL(x) (x << 0)
+
+/* PERIS Mux select */
+#define ACLK_PERIS_66_USER_SEL(x) (x << 0)
+
+/* TOP00 Mux select */
+#define TOP00_ISP_PLL_SEL(x) (x << 24)
+#define TOP00_CAM_PLL_SEL(x) (x << 20)
+#define TOP00_BUS0_PLL_USER_SEL(x) (x << 16)
+#define TOP00_BUS1_PLL_USER_SEL(x) (x << 12)
+#define TOP00_CCI_PLL_USER_SEL(x) (x << 8)
+#define TOP00_MFC_PLL_USER_SEL(x) (x << 4)
+#define TOP00_AUD_PLL_USER_SEL(x) (x << 0)
+
+/* TOP01 Mux select */
+#define TOP01_SCLK_CMU0_APBIF_SEL(x) (x << 28)
+#define TOP01_HALF_BUS0_PLL_USER(x) (x << 16)
+#define TOP01_HALF_BUS1_PLL_USER(x) (x << 12)
+#define TOP01_HALF_CCI_PLL_USER(x) (x << 8)
+#define TOP01_HALF_MFC_PLL_USER(x) (x << 4)
+
+/* TOP10 Mux select */
+#define TOP10_BUS0_PLL_USER_SEL(x) (x << 16)
+#define TOP10_BUS1_PLL_USER_SEL(x) (x << 12)
+#define TOP10_CCI_PLL_USER_SEL(x) (x << 8)
+#define TOP10_MFC_PLL_USER_SEL(x) (x << 4)
+
+/* TOP11 Mux select */
+#define TOP11_SCLK_CMU1_APBIF_SEL(x) (x << 28)
+#define TOP11_HALF_BUS0_PLL_USER(x) (x << 16)
+#define TOP11_HALF_BUS1_PLL_USER(x) (x << 12)
+#define TOP11_HALF_CCI_PLL_USER(x) (x << 8)
+#define TOP11_HALF_MFC_PLL_USER(x) (x << 4)
+
+/* TOPC0 Mux select */
+#define TOPC0_SCLK_MFC_PLL_CMUC_SEL(x) (x << 28)
+#define TOPC0_SCLK_CCI_PLL_CMUC_SEL(x) (x << 24)
+#define TOPC0_SCLK_BUS1_PLL_CMUC_SEL(x) (x << 20)
+#define TOPC0_SCLK_BUS0_PLL_CMUC_SEL(x) (x << 16)
+#define TOPC0_MFC_PLL_SEL(x) (x << 12)
+#define TOPC0_CCI_PLL_SEL(x) (x << 8)
+#define TOPC0_BUS1_PLL_SEL(x) (x << 4)
+#define TOPC0_BUS0_PLL_SEL(x) (x << 0)
+
+/* TOPC1 Mux select */
+#define TOPC1_SCLK_BUS_PLL_G3D_SEL(x) (x << 20)
+#define TOPC1_SCLK_BUS0_PLL_OUT_SEL(x) (x << 16)
+#define TOPC1_SCLK_BUS0_PLL_MIF_SEL(x) (x << 12)
+#define TOPC1_SCLK_BUS0_PLL_AP_SEL(x) (x << 4)
+#define TOPC1_AUD_PLL_SEL(x) (x << 0)
+
+/* TOPC5 Mux select */
+#define TOPC5_MIF_ACLK_MIF_PLL_SEL(x) (x << 20)
+#define TOPC5_MIF_PLL_USER_SEL(x) (x << 16)
+#define TOPC5_MIF_ACLK_MIF_USER_SEL(x) (x << 12)
+#define TOPC5_MIF_ACLK_MIF_SEL(x) (x << 8)
+#define TOPC5_MIF_PLL_SEL(x) (x << 0)
+
+/* TOPC0 clock divider & TOPC2 Mux select */
+#define ACLK_IMEM_100(x) (x << 28)
+#define ACLK_IMEM_200(x) (x << 24)
+#define ACLK_IMEM_266(x) (x << 20)
+#define ACLK_BUS1_200(x) (x << 16)
+#define ACLK_BUS1_532(x) (x << 12)
+#define ACLK_BUS0_532(x) (x << 8)
+#define ACLK_CCORE_133(x) (x << 4)
+#define ACLK_CCORE_532(x) (x << 0)
+
+/* TOPC1 clock divider & TOPC3 Mux select */
+#define ACLK_PERIS_66(x) (x << 24)
+#define ACLK_MSCL_532(x) (x << 20)
+#define ACLK_MFC_BUS_532(x) (x << 16)
+#define ACLK_HEVC_532(x) (x << 12)
+#define ACLK_MFC_532(x) (x << 8)
+#define ACLK_G2D_266(x) (x << 4)
+#define ACLK_G2D_400(x) (x << 0)
+
+/* TOPC2 clock divider & TOPC4 Mux select */
+#define SCLK_CMU_APBIF(x) (x << 0)
+
+/* TOP03 clock divider & TOP03 Mux select */
+#define ACLK_DISP_400(x) (x << 28)
+#define ACLK_PERIC0_66(x) (x << 20)
+#define ACLK_PERIC1_66(x) (x << 12)
+#define ACLK_VPP0_400(x) (x << 8)
+#define ACLK_VPP1_400(x) (x << 4)
+
+/* TOP04 clock divider & TOP04 Mux select */
+#define ACLK_ISP0_ISP0_590(x) (x << 28)
+#define ACLK_ISP0_TPU_590(x) (x << 24)
+#define ACLK_ISP0_TREX_532(x) (x << 20)
+#define ACLK_ISP1_ISP1_468(x) (x << 16)
+#define ACLK_ISP1_AHB_117(x) (x << 12)
+
+/* TOP05 clock divider & TOP05 Mux select */
+#define ACLK_CAM0_CSIS0_690(x) (x << 28)
+#define ACLK_CAM0_BNSA_690(x) (x << 24)
+#define ACLK_CAM0_BNSB_690(x) (x << 20)
+#define ACLK_CAM0_BNSD_690(x) (x << 16)
+#define ACLK_CAM0_CSIS1_174(x) (x << 12)
+
+/* TOP06 clock divider & TOP06 Mux select */
+#define ACLK_CAM0_3AA0_690(x) (x << 28)
+#define ACLK_CAM0_3AA1_468(x) (x << 24)
+#define ACLK_CAM0_TREX_532(x) (x << 20)
+#define ACLK_CAM0_NOCP_133(x) (x << 16)
+
+/* TOP07 clock divider & TOP07 Mux select */
+#define ACLK_CAM1_SCLVRA_491(x) (x << 28)
+#define ACLK_CAM1_ARM_668(x) (x << 24)
+#define ACLK_CAM1_BUSPERI_334(x) (x << 20)
+#define ACLK_CAM1_BNSCSIS_133(x) (x << 16)
+#define ACLK_CAM1_NOCP_133(x) (x << 12)
+#define ACLK_CAM1_TREX_532(x) (x << 8)
+
+/* TOP0-DISP clock divider & TOP0-DISP Mux select */
+#define SCLK_DECON_INT_ECLK(x) (x << 28)
+#define SCLK_DECON_EXT_ECLK(x) (x << 24)
+#define SCLK_DECON_VCLK(x) (x << 20)
+#define SCLK_DSD(x) (x << 16)
+#define SCLK_HDMI_SPDIF(x) (x << 12)
+
+/* TOP0-CAM10 clock divider & TOP0-CAM10 Mux select */
+#define SCLK_ISP_SPI0(x) (x << 20)
+#define SCLK_ISP_SPI1(x) (x << 8)
+#define SCLK_ISP_UART(x) (x << 4)
+
+/* TOP0-CAM11 clock divider & TOP0-CAM11 Mux select */
+#define SCLK_ISP_PWM(x) (x << 28)
+#define SCLK_ISP_MPWM(x) (x << 24)
+#define SCLK_ISP_SENSOR0(x) (x << 16)
+#define SCLK_ISP_SENSOR1(x) (x << 8)
+#define SCLK_ISP_SENSOR2(x) (x << 0)
+
+/* TOP0-PERIC0 clock divider & TOP0-PERIC0 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_PCM1(x) (x << 8)
+#define SCLK_SPDIF(x) (x << 4)
+
+/* TOP0-PERIC1 clock divider & TOP0-PERIC1 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_SPI0(x) (x << 20)
+#define SCLK_SPI1(x) (x << 8)
+
+/* TOP0-PERIC2 clock divider & TOP0-PERIC2 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_SPI2(x) (x << 20)
+#define SCLK_SPI3(x) (x << 8)
+
+/* TOP0-PERIC3 clock divider & TOP0-PERIC3 Mux select */
+#define SCLK_I2S1(x) (x << 20)
+#define SCLK_SPI4(x) (x << 20)
+#define SCLK_UART0(x) (x << 16)
+#define SCLK_UART1(x) (x << 12)
+#define SCLK_UART2(x) (x << 8)
+#define SCLK_UART3(x) (x << 4)
+
+/* TOP13 clock divider & TOP13 Mux select */
+#define ACLK_FSYS0_200(x) (x << 28)
+#define ACLK_FSYS1_200(x) (x << 24)
+
+/* TOP1-FSYS0 clock divider & TOP1-FSYS0 Mux select */
+#define SCLK_USBDRD300(x) (x << 28)
+#define SCLK_MMC2(x) (x << 24)
+#define SCLK_UFSUNIPRO11(x) (x << 16)
+#define SCLK_PHY_FSYS0(x) (x << 8)
+#define SCLK_PHY_FSYS0_26M(x) (x << 0)
+
+/* TOP1-FSYS1 clock divider & TOP1-FSYS1 Mux select */
+#define SCLK_MMC0(x) (x << 28)
+#define SCLK_MMC1(x) (x << 24)
+#define SCLK_UFSUNIPRO20(x) (x << 16)
+#define SCLK_TLX400_WIFI1(x) (x << 8)
+#define SCLK_PHY_FSYS1(x) (x << 0)
+
+/* TOP1-FSYS11 clock divider & TOP1-FSYS11 Mux select */
+#define SCLK_PHY_FSYS1_26M(x) (x << 24)
+
+#define FIN 24
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_CLOCK_INIT_H_ */
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14911
-gerrit
commit a562245965bcddce971277c9bb18e32d6dc2f6c1
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 15:40:03 2014 +0530
Exynos7: Add alternate CBFS
Adding alternate CBFS specific to Exynos7 to enable downloading
images from different boot media.
TEST=Compiled and booted coreboot over jazz board.
Downloaded and booted "Romstage" and "Ramstage" from both
SD and EMMC.
Change-Id: I58c38d83055867cce465d613c05fa672dec1da9c
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
---
src/soc/samsung/exynos7/Makefile.inc | 3 +
src/soc/samsung/exynos7/alternate_cbfs.c | 293 +++++++++++++++++++++
.../samsung/exynos7/include/soc/alternate_cbfs.h | 83 ++++++
3 files changed, 379 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index f17c2b0..fdf4dda 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -18,6 +18,7 @@ ifeq ($(CONFIG_SOC_SAMSUNG_EXYNOS7),y)
INCLUDES += -Isrc/soc/samsung/exynos7/include/
# BOOTBLOCK : UART related and minimum required hardware init
+bootblock-y += alternate_cbfs.c
bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += clock_init.c
@@ -33,6 +34,7 @@ bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
endif
# ROMSTAGE : Run primitive tests and remaining basic stuff
+romstage-y += alternate_cbfs.c
romstage-y += clock.c
romstage-y += gpio.c
romstage-y += mct.c
@@ -45,6 +47,7 @@ romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
endif
# RAMSTAGE : Prepare and load payload
+ramstage-y += alternate_cbfs.c
ramstage-y += clock.c
ramstage-y += cpu.c
ramstage-y += gpio.c
diff --git a/src/soc/samsung/exynos7/alternate_cbfs.c b/src/soc/samsung/exynos7/alternate_cbfs.c
new file mode 100644
index 0000000..2a9dd60
--- /dev/null
+++ b/src/soc/samsung/exynos7/alternate_cbfs.c
@@ -0,0 +1,293 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <assert.h>
+#include <cbfs.h> /* This driver serves as a CBFS media source. */
+#include <stdlib.h>
+#include <string.h>
+#include <arch/cache.h>
+#include <console/console.h>
+#include <soc/alternate_cbfs.h>
+#include <soc/power.h>
+
+/* This allows USB A-A firmware upload from a compatible host in four parts:
+ * The first two are the bare BL1 and the Coreboot boot block, which are just
+ * written to their respective loading addresses. These transfers are initiated
+ * by the IROM / BL1, so this code has nothing to do with them.
+ *
+ * The third transfer is a valid CBFS image that contains only the romstage,
+ * and must be small enough to fit into alternate_cbfs_size[__BOOT_BLOCK__] in
+ * IRAM. It is loaded when this function gets called in the boot block, and
+ * the normal CBFS code extracts the romstage from it.
+ *
+ * The fourth transfer is also a CBFS image, but can be of arbitrary size and
+ * should contain all available stages/payloads/etc. It is loaded when this
+ * function is called a second time at the end of the romstage, and copied to
+ * alternate_cbfs_buffer[!__BOOT_BLOCK__] in DRAM. It will reside there for the
+ * rest of the firmware's lifetime and all subsequent stages (which will not
+ * have __PRE_RAM__ defined) can just directly reference it there.
+ */
+static int usb_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ static int first_run = 1;
+ int (*irom_load_usb)(void) = (void *) (uintptr_t)
+ READ32(irom_load_image_from_usb_ptr);
+
+ if (!first_run)
+ return 0;
+
+ dcache_mmu_disable();
+ if (!irom_load_usb()) {
+ dcache_mmu_enable();
+ printk(BIOS_EMERG, "Unable to load CBFS image via USB!\n");
+ return -1;
+ }
+ dcache_mmu_enable();
+
+ /*
+ * We need to trust the host/irom to copy the image to our
+ * alternate_cbfs_buffer address... there is no way to control or even
+ * check the transfer size or target address from our side.
+ */
+
+ printk(BIOS_DEBUG,
+ "USB A-A transfer successful, CBFS image should now be at %p\n",
+ alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
+/*
+ * SDMMC works very similar to USB A-A: we copy the CBFS image into memory
+ * and read it from there. While SDMMC would also allow direct block by block
+ * on-demand reading, we might run into problems if we call back into the IROM
+ * in very late boot stages (e.g. after initializing/changing MMC clocks)... so
+ * this seems like a safer approach. It also makes it easy to pass our image
+ * down to payloads.
+ */
+static int sdmmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / BLOCK_SIZE;
+ static int first_run = 1;
+ int (*irom_load_sdmmc)(u32 start, u32 count, void *dst) =
+ (void *) (uintptr_t) READ32(irom_sdmmc_read_blocks_ptr);
+
+ if (!first_run)
+ return 0;
+
+ if (!irom_load_sdmmc(1, count, alternate_cbfs_buffer)) {
+ printk(BIOS_EMERG, "Unable to load CBFS image from SDMMC!\n");
+ return -1;
+ }
+
+ printk(BIOS_INFO,
+ "SDMMC read successful, CBFS image should now be at %p\n",
+ alternate_cbfs_buffer);
+
+ first_run = 0;
+#endif
+ return 0;
+}
+
+static int alternate_cbfs_close(struct cbfs_media *media) { return 0; }
+
+static size_t alternate_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ ASSERT(offset + count < alternate_cbfs_size);
+ memcpy(dest, alternate_cbfs_buffer + offset, count);
+ return count;
+}
+
+static void *alternate_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ ASSERT(offset + count < alternate_cbfs_size);
+ return alternate_cbfs_buffer + offset;
+}
+
+static void *alternate_cbfs_unmap(struct cbfs_media *media,
+ const void *buffer) { return 0; }
+
+static int emmc_cbfs_open(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ /*
+ * In the bootblock, we just copy the small part that fits in the buffer
+ * and hope that it's enough (since the romstage is currently always the
+ * first component in the image, this should work out). In the romstage,
+ * we copy until our buffer is full (currently 12M) to avoid the pain of
+ * figuring out the true image size from in here. Since this is mainly a
+ * developer/debug boot mode, those shortcomings should be bearable.
+ */
+ const u32 count = alternate_cbfs_size / BLOCK_SIZE;
+ static int first_run = 1;
+ uint32_t existing_magic = CONFIG_CBFS_HEADER_ROM_OFFSET;
+ existing_magic -= (BLOCK_SIZE *
+ TYPECAST32(read32((void *) (CONFIG_BOOTBLOCK_BASE - 0x10))));
+ existing_magic -= BL1_SIZE;
+ existing_magic += TYPECAST32(alternate_cbfs_buffer);
+ existing_magic = read32((void *) (uintptr_t) existing_magic);
+
+ int (*irom_load_emmc)(u32 count, void * dst) =
+ (void *) (uintptr_t) READ32(irom_msh_read_from_fifo_emmc_ptr);
+
+ if (!first_run)
+ return 0;
+
+ if (CBFS_HEADER_MAGIC == ntohl(existing_magic)) {
+ printk(BIOS_EMERG, "CBFS image already loaded from eMMC, read successful!\n");
+ first_run = 0;
+ return 0;
+ }
+
+ if (!irom_load_emmc(count, alternate_cbfs_buffer)) {
+ printk(BIOS_EMERG, "Unable to load CBFS image from eMMC!\n");
+ return -1;
+ }
+
+ printk(BIOS_DEBUG,
+ "EMMC read successful, CBFS image should now be at %p\n",
+ alternate_cbfs_buffer);
+ first_run = 0;
+#endif
+ return 0;
+}
+
+static int emmc_cbfs_close(struct cbfs_media *media)
+{
+#ifdef __PRE_RAM__
+ void (*irom_load_emmc_end)(void) = (void *) (uintptr_t)
+ READ32(irom_msh_end_boot_op_emmc_ptr);
+
+ irom_load_emmc_end();
+#endif
+ return 0;
+}
+
+/* Bootblock has a 16 byte long header required by the BL1.
+ * First 4 bytes provide size of the bootblock, next 4 bytes contain checksum,
+ * third set of 4 bytes contain a string "head" and the last set is reserved.
+ * Now, we will read the size of bootblock from the header.
+ *
+ * Why we need this size ?
+ *
+ * Because we have a limitation that eMMC driver starts reading from the point
+ * where it stopped last time. So, we download rest of the coreboot image once
+ * in the DRAM and subtract the size of BL1 + bootblock from the expected
+ * offset.
+ *
+ * For Example :
+ * Expected image address in DRAM = 0x80000000
+ * Expected offset for CBFS header = 0xa0000
+ *
+ * But, our function pointer is only going to read rest of the image i.e.
+ * romstage, ramstage, payload etc.
+ *
+ * Therefore,
+ * New offset for CBFS header = 0xa0000 - size_of_BL1 - size_of_bootblock
+ */
+
+
+static void *emmc_cbfs_map(struct cbfs_media *media, size_t offset,
+ size_t count)
+{
+ offset -= (BLOCK_SIZE *
+ TYPECAST32(read32((void *) (CONFIG_BOOTBLOCK_BASE - 0x10))));
+ offset -= BL1_SIZE;
+ ASSERT(offset + count < alternate_cbfs_size);
+ return alternate_cbfs_buffer + offset;
+}
+
+static size_t emmc_cbfs_read(struct cbfs_media *media, void *dest,
+ size_t offset, size_t count)
+{
+ offset -= (BLOCK_SIZE *
+ TYPECAST32(read32((void *) (CONFIG_BOOTBLOCK_BASE - 0x10))));
+ offset -= BL1_SIZE;
+ ASSERT(offset + count < alternate_cbfs_size);
+ memcpy(dest, alternate_cbfs_buffer + offset, count);
+ return count;
+}
+
+static int initialize_exynos_sdmmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_SPEW, "Using Exynos alternate boot mode SDMMC\n");
+
+ media->open = sdmmc_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
+static int initialize_exynos_usb_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_DEBUG, "Using Exynos alternate boot mode USB A-A\n");
+
+ media->open = usb_cbfs_open;
+ media->close = alternate_cbfs_close;
+ media->read = alternate_cbfs_read;
+ media->map = alternate_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
+static int initialize_exynos_emmc_cbfs_media(struct cbfs_media *media)
+{
+ printk(BIOS_SPEW, "Using Exynos alternate boot mode eMMC\n");
+
+ media->open = emmc_cbfs_open;
+ media->close = emmc_cbfs_close;
+ media->read = emmc_cbfs_read;
+ media->map = emmc_cbfs_map;
+ media->unmap = alternate_cbfs_unmap;
+
+ return 0;
+}
+
+int init_default_cbfs_media(struct cbfs_media *media)
+{
+ uint32_t bootmode;
+
+ if (*iram_secondary_base == SECONDARY_BASE_BOOT_USB)
+ return initialize_exynos_usb_cbfs_media(media);
+
+ bootmode = read32((void *) (EXYNOS7_PMU_ALIVE_BASE)) & OM_STAT_MASK;
+
+ switch (bootmode) {
+ case OM_STAT_SDMMC:
+ return initialize_exynos_sdmmc_cbfs_media(media);
+ case OM_STAT_EMMC:
+ return initialize_exynos_emmc_cbfs_media(media);
+ default:
+ printk(BIOS_EMERG, "Exynos OM_STAT value not supported!\n");
+ }
+ return 0;
+}
diff --git a/src/soc/samsung/exynos7/include/soc/alternate_cbfs.h b/src/soc/samsung/exynos7/include/soc/alternate_cbfs.h
new file mode 100644
index 0000000..2d29c57
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/alternate_cbfs.h
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/io.h>
+#include <types.h>
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_ALTERNATE_CBFS_H_
+#define _CPU_SAMSUNG_EXYNOS7_ALTERNATE_CBFS_H_
+
+/* Size of a single block */
+#define BLOCK_SIZE 0x200
+
+/* Size of BL1 binary */
+#define BL1_SIZE (8 * 1024)
+
+/* OM Pin status for SD boot mode */
+#define OM_STAT_SDMMC 0x13
+
+/* OM Pin status for eMMC boot mode */
+#define OM_STAT_EMMC 0x1
+
+/* OM Pin status mask */
+#define OM_STAT_MASK 0x3f
+
+/* Starting address of IRAM */
+#define IRAM_BASE (0x21 << 20)
+
+/* Value for USB secondary boot mode.
+ * This is the fallback option when there is no BL1 in SD.
+ */
+#define SECONDARY_BASE_BOOT_USB 0xfeed0002
+
+/* Irom's function pointer for SD copy resides here */
+#define SD_COPY_ENTRY_POINT (IRAM_BASE + 0xa0)
+
+/* Irom's function pointer for eMMC copy resides here */
+#define EMMC_COPY_ENTRY_POINT (IRAM_BASE + 0xb4)
+
+/* Irom's function pointer for eMMC cleanup resides here */
+#define EMMC_CLEANUP_ENTRY_POINT (EMMC_COPY_ENTRY_POINT + 0x4)
+
+/* Irom's function pointer for SPI Flash copy resides here */
+#define SF_COPY_ENTRY_POINT (IRAM_BASE + 0xd0)
+
+/* Irom's function pointer for USB copy resides here */
+#define USB_COPY_ENTRY_POINT (IRAM_BASE + 0xdc)
+
+/* Read a 32 bit pointer */
+#define READ32(x) *((uint32_t *) (uintptr_t) x)
+
+/* Typecast to a 32 bit value */
+#define TYPECAST32(x) ((uint32_t) (uintptr_t) x)
+
+/* These are pointers to function pointers. Double indirection! */
+static void ** const irom_sdmmc_read_blocks_ptr =
+ (void **) SD_COPY_ENTRY_POINT;
+static void ** const irom_msh_read_from_fifo_emmc_ptr =
+ (void **) EMMC_COPY_ENTRY_POINT;
+static void ** const irom_msh_end_boot_op_emmc_ptr =
+ (void **) EMMC_CLEANUP_ENTRY_POINT;
+static void ** const irom_spi_sf_read_ptr =
+ (void **) SF_COPY_ENTRY_POINT;
+static void ** const irom_load_image_from_usb_ptr =
+ (void **) USB_COPY_ENTRY_POINT;
+
+static uint32_t * const iram_secondary_base = (uint32_t *) IRAM_BASE;
+
+static void * const alternate_cbfs_buffer = (void *) CONFIG_CBFS_CACHE_ADDRESS;
+static size_t const alternate_cbfs_size = CONFIG_CBFS_CACHE_SIZE;
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_ALTERNATE_CBFS_H_ */
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14910
-gerrit
commit bd406a7814fc9d7181deaa2286c5827adddda5d7
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 15:34:50 2014 +0530
Exynos7: Add UART initialization
This patch adds UART setup for Exynos7. It also enables UART-2 as
default serial port.
TEST=Built and booted Coreboot Over Jazz. Saw prints over console.
Change-Id: Id5f3f69d6d3aef9efa888259534d3ad93cfed8ba
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/soc/samsung/exynos7/Makefile.inc | 7 ++
src/soc/samsung/exynos7/include/soc/uart.h | 39 ++++++++
src/soc/samsung/exynos7/uart.c | 153 +++++++++++++++++++++++++++++
3 files changed, 199 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index 898260d..f17c2b0 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -28,6 +28,9 @@ bootblock-y += monotonic_timer.c
bootblock-y += pinmux.c
bootblock-y += power.c
bootblock-y += timer.c
+ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
+bootblock-$(CONFIG_BOOTBLOCK_CONSOLE) += uart.c
+endif
# ROMSTAGE : Run primitive tests and remaining basic stuff
romstage-y += clock.c
@@ -37,6 +40,9 @@ romstage-y += monotonic_timer.c
romstage-y += pinmux.c
romstage-y += power.c
romstage-y += timer.c
+ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
+romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
+endif
# RAMSTAGE : Prepare and load payload
ramstage-y += clock.c
@@ -47,6 +53,7 @@ ramstage-y += monotonic_timer.c
ramstage-y += pinmux.c
ramstage-y += power.c
ramstage-y += timer.c
+ramstage-$(CONFIG_CONSOLE_SERIAL_UART) += uart.c
$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
cp $< $@
diff --git a/src/soc/samsung/exynos7/include/soc/uart.h b/src/soc/samsung/exynos7/include/soc/uart.h
new file mode 100644
index 0000000..d3abb43
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/uart.h
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_UART_H_
+#define _CPU_SAMSUNG_EXYNOS7_UART_H_
+
+#include <stddef.h>
+
+struct exynos_uart {
+ unsigned int ulcon;
+ unsigned int ucon;
+ unsigned int ufcon;
+ unsigned int umcon;
+ unsigned int utrstat;
+ unsigned int uerstat;
+ unsigned int ufstat;
+ unsigned int umstat;
+ unsigned char utxh;
+ unsigned char res1[3];
+ unsigned char urxh;
+ unsigned char res2[3];
+ unsigned int ubrdiv;
+ unsigned char res3[0xffd0];
+};
+check_member(exynos_uart, ubrdiv, 0x28);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_UART_H_ */
diff --git a/src/soc/samsung/exynos7/uart.c b/src/soc/samsung/exynos7/uart.c
new file mode 100644
index 0000000..3c041a7
--- /dev/null
+++ b/src/soc/samsung/exynos7/uart.c
@@ -0,0 +1,153 @@
+/* This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <uart.h>
+#include <arch/io.h>
+#include <console/console.h> /* for __console definition */
+#include <soc/clock.h>
+#include <soc/cpu.h>
+#include <soc/periph.h>
+#include <soc/uart.h>
+
+#define RX_FIFO_COUNT_MASK 0xff
+#define RX_FIFO_FULL_MASK (1 << 8)
+#define TX_FIFO_FULL_MASK (1 << 24)
+
+static struct exynos_uart * base_port =
+ (struct exynos_uart *)CONFIG_CONSOLE_SERIAL_UART_ADDRESS;
+
+static void serial_setbrg_dev(void)
+{
+ struct exynos_uart *uart = base_port;
+ u32 uclk;
+ u32 baudrate = CONFIG_TTYS0_BAUD;
+ u32 val;
+
+ /* All UARTs share the same clock */
+ uclk = get_uart_clk(PERIPH_ID_UART2);
+ val = uclk / baudrate;
+
+ write32(&uart->ubrdiv, val / 16 - 1);
+}
+
+/*
+ * Initialise the serial port with the given baudrate. The settings
+ * are always 8 data bits, no parity, 1 stop bit, no start bits.
+ */
+static void exynos7_init_dev(void)
+{
+ struct exynos_uart *uart = base_port;
+
+ /* enable FIFOs */
+ write32(&uart->ufcon, 0x1);
+ write32(&uart->umcon, 0);
+ /* 8N1 */
+ write32(&uart->ulcon, 0x3);
+ /* No interrupts, no DMA, pure polling */
+ write32(&uart->ucon, 0x245);
+
+ serial_setbrg_dev();
+}
+
+static int exynos7_uart_err_check(int op)
+{
+ struct exynos_uart *uart = base_port;
+ unsigned int mask;
+
+ /*
+ * UERSTAT
+ * Break Detect [3]
+ * Frame Err [2] : receive operation
+ * Parity Err [1] : receive operation
+ * Overrun Err [0] : receive operation
+ */
+ if (op)
+ mask = 0x8;
+ else
+ mask = 0xf;
+
+ return read32(&uart->uerstat) & mask;
+}
+
+/*
+ * Read a single byte from the serial port. Returns 1 on success, 0
+ * otherwise. When the function is succesfull, the character read is
+ * written into its argument c.
+ */
+static unsigned char exynos7_uart_rx_byte(void)
+{
+ struct exynos_uart *uart = base_port;
+
+ /* wait for character to arrive */
+ while (!(read32(&uart->ufstat) & (RX_FIFO_COUNT_MASK |
+ RX_FIFO_FULL_MASK))) {
+ if (exynos7_uart_err_check(0))
+ return 0;
+ }
+
+ return readb(&uart->urxh) & 0xff;
+}
+
+/*
+ * Output a single byte to the serial port.
+ */
+static void exynos7_uart_tx_byte(unsigned char data)
+{
+ struct exynos_uart *uart = base_port;
+
+ /* wait for room in the tx FIFO */
+ while ((read32(&uart->ufstat) & TX_FIFO_FULL_MASK)) {
+ if (exynos7_uart_err_check(1))
+ return;
+ }
+
+ writeb(data, &uart->utxh);
+}
+
+#if !defined(__PRE_RAM__)
+
+static const struct console_driver exynos7_uart_console __console = {
+ .init = exynos7_init_dev,
+ .tx_byte = exynos7_uart_tx_byte,
+ .rx_byte = exynos7_uart_rx_byte,
+};
+
+uint32_t uartmem_getbaseaddr(void)
+{
+ return ((uint32_t) (uintptr_t) base_port);
+}
+
+#else
+
+void uart_init(void)
+{
+ exynos7_init_dev();
+}
+
+unsigned char uart_rx_byte(void)
+{
+ return exynos7_uart_rx_byte();
+}
+
+void uart_tx_byte(unsigned char data)
+{
+ exynos7_uart_tx_byte(data);
+}
+
+void uart_tx_flush(void)
+{
+}
+
+#endif
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14909
-gerrit
commit 38acc1148488a5c7f62b74f22bac8272cdd7f506
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 15:26:33 2014 +0530
Exynos7: Add GPIO/Pinmux setup
Adding GPIO/Pinmux support in Exynos7 to program GPIO
pads specific to various IPs.
Change-Id: I339adf3274563364809eb948ecc9a711b07a77e5
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/soc/samsung/exynos7/Makefile.inc | 6 +
src/soc/samsung/exynos7/bootblock.c | 9 +
src/soc/samsung/exynos7/gpio.c | 225 +++++++++++
src/soc/samsung/exynos7/include/soc/gpio.h | 538 +++++++++++++++++++++++++++
src/soc/samsung/exynos7/include/soc/pinmux.h | 55 +++
src/soc/samsung/exynos7/pinmux.c | 277 ++++++++++++++
6 files changed, 1110 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index eeb9fcf..898260d 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -22,23 +22,29 @@ bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += clock_init.c
bootblock-y += dmc_init_lpddr4.c
+bootblock-y += gpio.c
bootblock-y += mct.c
bootblock-y += monotonic_timer.c
+bootblock-y += pinmux.c
bootblock-y += power.c
bootblock-y += timer.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
romstage-y += clock.c
+romstage-y += gpio.c
romstage-y += mct.c
romstage-y += monotonic_timer.c
+romstage-y += pinmux.c
romstage-y += power.c
romstage-y += timer.c
# RAMSTAGE : Prepare and load payload
ramstage-y += clock.c
ramstage-y += cpu.c
+ramstage-y += gpio.c
ramstage-y += mct.c
ramstage-y += monotonic_timer.c
+ramstage-y += pinmux.c
ramstage-y += power.c
ramstage-y += timer.c
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index 7183731..71650e0 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -22,6 +22,7 @@
#include <soc/cpu.h>
#include <soc/dmc.h>
#include <soc/mct.h>
+#include <soc/pinmux.h>
#include <soc/power.h>
void bootblock_cpu_init(void)
@@ -54,4 +55,12 @@ void bootblock_cpu_init(void)
/* Initialize SDRAM */
mem_ctrl_init_lpddr4(is_resume);
+
+ /* Set GPIOs for UART */
+ if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART0))
+ exynos_pinmux_uart0();
+ else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART1))
+ exynos_pinmux_uart1();
+ else if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART2))
+ exynos_pinmux_uart2();
}
diff --git a/src/soc/samsung/exynos7/gpio.c b/src/soc/samsung/exynos7/gpio.c
new file mode 100644
index 0000000..9ffebd2
--- /dev/null
+++ b/src/soc/samsung/exynos7/gpio.c
@@ -0,0 +1,225 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <delay.h>
+#include <assert.h>
+#include <soc/gpio.h>
+#include <soc/cpu.h>
+
+#define CON_MASK(x) (0xf << ((x) << 2))
+#define CON_SFR(x, v) ((v) << ((x) << 2))
+
+#define DAT_MASK(x) (0x1 << (x))
+#define DAT_SET(x) (0x1 << (x))
+
+#define PULL_MASK(x) (0x3 << ((x) << 1))
+#define PULL_MODE(x, v) ((v) << ((x) << 1))
+
+#define DRV_MASK(x) (0x3 << ((x) << 1))
+#define DRV_SET(x, m) ((m) << ((x) << 1))
+#define RATE_MASK(x) (0x1 << (x + 16))
+#define RATE_SET(x) (0x1 << (x + 16))
+
+void exynos_gpio_cfg_pin(struct exynos_gpio_bank *bank, int gpio, int cfg)
+{
+ unsigned int value;
+
+ value = read32(&bank->con);
+ value &= ~CON_MASK(gpio);
+ value |= CON_SFR(gpio, cfg);
+ write32(&bank->con, value);
+}
+
+void exynos_gpio_direction_output(struct exynos_gpio_bank *bank, int gpio, int en)
+{
+ unsigned int value;
+
+ exynos_gpio_cfg_pin(bank, gpio, EXYNOS_GPIO_OUTPUT);
+
+ value = read32(&bank->dat);
+ value &= ~DAT_MASK(gpio);
+ if (en)
+ value |= DAT_SET(gpio);
+ write32(&bank->dat, value);
+}
+
+void exynos_gpio_direction_input(struct exynos_gpio_bank *bank, int gpio)
+{
+ exynos_gpio_cfg_pin(bank, gpio, EXYNOS_GPIO_INPUT);
+}
+
+void exynos_gpio_set_value(struct exynos_gpio_bank *bank, int gpio, int en)
+{
+ unsigned int value;
+
+ value = read32(&bank->dat);
+ value &= ~DAT_MASK(gpio);
+ if (en)
+ value |= DAT_SET(gpio);
+ write32(&bank->dat, value);
+}
+
+unsigned int exynos_gpio_get_value(struct exynos_gpio_bank *bank, int gpio)
+{
+ unsigned int value;
+
+ value = read32(&bank->dat);
+ return !!(value & DAT_MASK(gpio));
+}
+
+void exynos_gpio_set_pull(struct exynos_gpio_bank *bank, int gpio, int mode)
+{
+ unsigned int value;
+
+ value = read32(&bank->pull);
+ value &= ~PULL_MASK(gpio);
+
+ switch (mode) {
+ case EXYNOS_GPIO_PULL_DOWN:
+ case EXYNOS_GPIO_PULL_UP:
+ value |= PULL_MODE(gpio, mode);
+ break;
+ default:
+ break;
+ }
+
+ write32(&bank->pull, value);
+}
+
+void exynos_gpio_set_drv(struct exynos_gpio_bank *bank, int gpio, int mode)
+{
+ unsigned int value;
+
+ value = read32(&bank->drv);
+ value &= ~DRV_MASK(gpio);
+
+ switch (mode) {
+ case EXYNOS_GPIO_DRV_1X:
+ case EXYNOS_GPIO_DRV_2X:
+ case EXYNOS_GPIO_DRV_3X:
+ case EXYNOS_GPIO_DRV_4X:
+ value |= DRV_SET(gpio, mode);
+ break;
+ default:
+ return;
+ }
+
+ write32(&bank->drv, value);
+}
+
+void exynos_gpio_set_rate(struct exynos_gpio_bank *bank, int gpio, int mode)
+{
+ unsigned int value;
+
+ value = read32(&bank->drv);
+ value &= ~RATE_MASK(gpio);
+
+ switch (mode) {
+ case EXYNOS_GPIO_DRV_FAST:
+ case EXYNOS_GPIO_DRV_SLOW:
+ value |= RATE_SET(gpio);
+ break;
+ default:
+ return;
+ }
+
+ write32(&bank->drv, value);
+}
+
+static struct exynos_gpio_bank *exynos_gpio_get_bank(unsigned int gpio)
+{
+ const struct gpio_info *data;
+ unsigned int upto;
+ int i, count;
+
+ data = get_gpio_data();
+ count = get_bank_num();
+ for (i = upto = 0; i < count;
+ i++, upto = data->max_gpio, data++) {
+ printk(BIOS_INFO, "i=%d, upto=%d\n", i, upto);
+ if (gpio < data->max_gpio) {
+ struct exynos_gpio_bank *bank;
+ bank = (struct exynos_gpio_bank *)data->reg_addr;
+ bank += (gpio - upto) / GPIO_PER_BANK;
+ printk(BIOS_INFO, "gpio=%d, bank=%p\n", gpio, bank);
+ return bank;
+ }
+ }
+ return NULL;
+}
+
+int exynos_gpio_get_pin(unsigned gpio)
+{
+ return gpio % GPIO_PER_BANK;
+}
+
+/* Common GPIO API */
+int gpio_request(unsigned gpio, const char *label)
+{
+ return 0;
+}
+
+int gpio_free(unsigned gpio)
+{
+ return 0;
+}
+
+int gpio_direction_input(unsigned gpio)
+{
+ exynos_gpio_direction_input(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio));
+ return 0;
+}
+
+int gpio_direction_output(unsigned gpio, int value)
+{
+ exynos_gpio_direction_output(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio), value);
+ return 0;
+}
+
+int gpio_get_value(unsigned gpio)
+{
+ return (int) exynos_gpio_get_value(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio));
+}
+
+int gpio_set_value(unsigned gpio, int value)
+{
+ exynos_gpio_set_value(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio), value);
+
+ return 0;
+}
+
+void gpio_set_pull(int gpio, int value)
+{
+ exynos_gpio_set_pull(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio), value);
+}
+
+void gpio_cfg_pin(int gpio, int cfg)
+{
+ exynos_gpio_cfg_pin(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio), cfg);
+}
+
+void gpio_set_drv(int gpio, int drv)
+{
+ exynos_gpio_set_drv(exynos_gpio_get_bank(gpio),
+ exynos_gpio_get_pin(gpio), drv);
+}
diff --git a/src/soc/samsung/exynos7/include/soc/gpio.h b/src/soc/samsung/exynos7/include/soc/gpio.h
new file mode 100644
index 0000000..c9c98b6
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/gpio.h
@@ -0,0 +1,538 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_GPIO_H_
+#define _CPU_SAMSUNG_EXYNOS7_GPIO_H_
+
+#include <soc/cpu.h>
+
+struct exynos_gpio_bank {
+ unsigned int con;
+ unsigned int dat;
+ unsigned int pull;
+ unsigned int drv;
+ unsigned int pdn_con;
+ unsigned int pdn_pull;
+ unsigned char res1[8];
+};
+
+struct exynos7_gpio_part1 { /* 0x1058_0000 - ALIVE */
+ struct exynos_gpio_bank a0;
+ struct exynos_gpio_bank a1;
+ struct exynos_gpio_bank a2;
+ struct exynos_gpio_bank a3;
+};
+
+struct exynos7_gpio_part2 { /* 0x114B_0000 -AUD */
+ struct exynos_gpio_bank z0;
+ struct exynos_gpio_bank z1;
+};
+
+struct exynos7_gpio_part3 { /* 0x1347_0000 - BUS0 */
+ struct exynos_gpio_bank b0;
+ struct exynos_gpio_bank c0;
+ struct exynos_gpio_bank c1;
+ struct exynos_gpio_bank c2;
+ struct exynos_gpio_bank c3;
+ struct exynos_gpio_bank d0;
+ struct exynos_gpio_bank d1;
+ struct exynos_gpio_bank d2;
+ struct exynos_gpio_bank d4;
+ struct exynos_gpio_bank d5;
+ struct exynos_gpio_bank d6;
+ struct exynos_gpio_bank d7;
+ struct exynos_gpio_bank d8;
+ struct exynos_gpio_bank g0;
+ struct exynos_gpio_bank g3;
+};
+
+struct exynos7_gpio_part4 { /* 0x1487_0000 - BUS1 */
+ struct exynos_gpio_bank reserved;
+ struct exynos_gpio_bank f0;
+ struct exynos_gpio_bank f1;
+ struct exynos_gpio_bank f2;
+ struct exynos_gpio_bank f3;
+ struct exynos_gpio_bank f4;
+ struct exynos_gpio_bank f5;
+ struct exynos_gpio_bank g1;
+ struct exynos_gpio_bank g2;
+ struct exynos_gpio_bank h1;
+ struct exynos_gpio_bank v6;
+};
+
+struct exynos7_gpio_part5 { /* 0x14cd_0000 - NFC */
+ struct exynos_gpio_bank j0;
+};
+
+struct exynos7_gpio_part6 { /* 0x14ce_0000 - TOUCH */
+ struct exynos_gpio_bank j1;
+};
+
+struct exynos7_gpio_part7 { /* 0x14c9_0000 - FF */
+ struct exynos_gpio_bank g4;
+};
+
+struct exynos7_gpio_part8 { /* 0x14ca_0000 - ESE */
+ struct exynos_gpio_bank v7;
+};
+
+struct exynos7_gpio_part9 { /* 0x10e6_0000 - FSYS0 */
+ struct exynos_gpio_bank r4;
+};
+
+struct exynos7_gpio_part10 { /* 0x1569_0000 - FSYS1 */
+ struct exynos_gpio_bank r0;
+ struct exynos_gpio_bank r1;
+ struct exynos_gpio_bank r2;
+ struct exynos_gpio_bank r3;
+};
+
+/* functions */
+void exynos_gpio_cfg_pin(struct exynos_gpio_bank *bank, int gpio, int cfg);
+void exynos_gpio_direction_output(struct exynos_gpio_bank *bank, int gpio, int en);
+void exynos_gpio_direction_input(struct exynos_gpio_bank *bank, int gpio);
+void exynos_gpio_set_value(struct exynos_gpio_bank *bank, int gpio, int en);
+unsigned int exynos_gpio_get_value(struct exynos_gpio_bank *bank, int gpio);
+void exynos_gpio_set_pull(struct exynos_gpio_bank *bank, int gpio, int mode);
+void exynos_gpio_set_drv(struct exynos_gpio_bank *bank, int gpio, int mode);
+void exynos_gpio_set_rate(struct exynos_gpio_bank *bank, int gpio, int mode);
+int exynos_gpio_get_pin(unsigned gpio);
+
+/* GPIO pins per bank */
+#define GPIO_PER_BANK 8
+
+/* A list of valid GPIO numbers for the asm-generic/gpio.h interface */
+enum exynos7_gpio_pin {
+ /* GPIO_PART1_STARTS */
+ EXYNOS7_GPIO_A00, /* 0 */
+ EXYNOS7_GPIO_A01,
+ EXYNOS7_GPIO_A02,
+ EXYNOS7_GPIO_A03,
+ EXYNOS7_GPIO_A04,
+ EXYNOS7_GPIO_A05,
+ EXYNOS7_GPIO_A06,
+ EXYNOS7_GPIO_A07,
+ EXYNOS7_GPIO_A10, /* 8 */
+ EXYNOS7_GPIO_A11,
+ EXYNOS7_GPIO_A12,
+ EXYNOS7_GPIO_A13,
+ EXYNOS7_GPIO_A14,
+ EXYNOS7_GPIO_A15,
+ EXYNOS7_GPIO_A16,
+ EXYNOS7_GPIO_A17,
+ EXYNOS7_GPIO_A20, /* 16 0x10 */
+ EXYNOS7_GPIO_A21,
+ EXYNOS7_GPIO_A22,
+ EXYNOS7_GPIO_A23,
+ EXYNOS7_GPIO_A24,
+ EXYNOS7_GPIO_A25,
+ EXYNOS7_GPIO_A26,
+ EXYNOS7_GPIO_A27,
+ EXYNOS7_GPIO_A30, /* 24 0x18 */
+ EXYNOS7_GPIO_A31,
+ EXYNOS7_GPIO_A32,
+ EXYNOS7_GPIO_A33,
+ EXYNOS7_GPIO_A34,
+ EXYNOS7_GPIO_A35,
+ EXYNOS7_GPIO_A36,
+ EXYNOS7_GPIO_A37,
+
+ /* GPIO_PART2_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_1, /* 32 0x20 */
+ EXYNOS7_GPIO_Z00 = EXYNOS7_GPIO_MAX_PORT_PART_1,
+ EXYNOS7_GPIO_Z01,
+ EXYNOS7_GPIO_Z02,
+ EXYNOS7_GPIO_Z03,
+ EXYNOS7_GPIO_Z04,
+ EXYNOS7_GPIO_Z05,
+ EXYNOS7_GPIO_Z06,
+ EXYNOS7_GPIO_Z07,
+ EXYNOS7_GPIO_Z10, /* 40 0x28 */
+ EXYNOS7_GPIO_Z11,
+ EXYNOS7_GPIO_Z12,
+ EXYNOS7_GPIO_Z13,
+ EXYNOS7_GPIO_Z14,
+ EXYNOS7_GPIO_Z15,
+ EXYNOS7_GPIO_Z16,
+ EXYNOS7_GPIO_Z17,
+
+ /* GPIO_PART3_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_2, /* 48 0x30 */
+ EXYNOS7_GPIO_B00 = EXYNOS7_GPIO_MAX_PORT_PART_2,
+ EXYNOS7_GPIO_B01,
+ EXYNOS7_GPIO_B02,
+ EXYNOS7_GPIO_B03,
+ EXYNOS7_GPIO_B04,
+ EXYNOS7_GPIO_B05,
+ EXYNOS7_GPIO_B06,
+ EXYNOS7_GPIO_B07,
+ EXYNOS7_GPIO_C00, /* 56 0x38 */
+ EXYNOS7_GPIO_C01,
+ EXYNOS7_GPIO_C02,
+ EXYNOS7_GPIO_C03,
+ EXYNOS7_GPIO_C04,
+ EXYNOS7_GPIO_C05,
+ EXYNOS7_GPIO_C06,
+ EXYNOS7_GPIO_C07,
+ EXYNOS7_GPIO_C10, /* 64 0x40 */
+ EXYNOS7_GPIO_C11,
+ EXYNOS7_GPIO_C12,
+ EXYNOS7_GPIO_C13,
+ EXYNOS7_GPIO_C14,
+ EXYNOS7_GPIO_C15,
+ EXYNOS7_GPIO_C16,
+ EXYNOS7_GPIO_C17,
+ EXYNOS7_GPIO_C20, /* 72 0x48 */
+ EXYNOS7_GPIO_C21,
+ EXYNOS7_GPIO_C22,
+ EXYNOS7_GPIO_C23,
+ EXYNOS7_GPIO_C24,
+ EXYNOS7_GPIO_C25,
+ EXYNOS7_GPIO_C26,
+ EXYNOS7_GPIO_C27,
+ EXYNOS7_GPIO_C30, /* 80 0x50 */
+ EXYNOS7_GPIO_C31,
+ EXYNOS7_GPIO_C32,
+ EXYNOS7_GPIO_C33,
+ EXYNOS7_GPIO_C34,
+ EXYNOS7_GPIO_C35,
+ EXYNOS7_GPIO_C36,
+ EXYNOS7_GPIO_C37,
+ EXYNOS7_GPIO_D00, /* 88 0x58 */
+ EXYNOS7_GPIO_D01,
+ EXYNOS7_GPIO_D02,
+ EXYNOS7_GPIO_D03,
+ EXYNOS7_GPIO_D04,
+ EXYNOS7_GPIO_D05,
+ EXYNOS7_GPIO_D06,
+ EXYNOS7_GPIO_D07,
+ EXYNOS7_GPIO_D10, /* 96 0x60 */
+ EXYNOS7_GPIO_D11,
+ EXYNOS7_GPIO_D12,
+ EXYNOS7_GPIO_D13,
+ EXYNOS7_GPIO_D14,
+ EXYNOS7_GPIO_D15,
+ EXYNOS7_GPIO_D16,
+ EXYNOS7_GPIO_D17,
+ EXYNOS7_GPIO_D20, /* 104 0x68 */
+ EXYNOS7_GPIO_D21,
+ EXYNOS7_GPIO_D22,
+ EXYNOS7_GPIO_D23,
+ EXYNOS7_GPIO_D24,
+ EXYNOS7_GPIO_D25,
+ EXYNOS7_GPIO_D26,
+ EXYNOS7_GPIO_D27,
+ EXYNOS7_GPIO_D40, /* 112 0x70 */
+ EXYNOS7_GPIO_D41,
+ EXYNOS7_GPIO_D42,
+ EXYNOS7_GPIO_D43,
+ EXYNOS7_GPIO_D44,
+ EXYNOS7_GPIO_D45,
+ EXYNOS7_GPIO_D46,
+ EXYNOS7_GPIO_D47,
+ EXYNOS7_GPIO_D50, /* 120 0x78 */
+ EXYNOS7_GPIO_D51,
+ EXYNOS7_GPIO_D52,
+ EXYNOS7_GPIO_D53,
+ EXYNOS7_GPIO_D54,
+ EXYNOS7_GPIO_D55,
+ EXYNOS7_GPIO_D56,
+ EXYNOS7_GPIO_D57,
+ EXYNOS7_GPIO_D60, /* 128 0x80 */
+ EXYNOS7_GPIO_D61,
+ EXYNOS7_GPIO_D62,
+ EXYNOS7_GPIO_D63,
+ EXYNOS7_GPIO_D64,
+ EXYNOS7_GPIO_D65,
+ EXYNOS7_GPIO_D66,
+ EXYNOS7_GPIO_D67,
+ EXYNOS7_GPIO_D70, /* 136 0x88 */
+ EXYNOS7_GPIO_D71,
+ EXYNOS7_GPIO_D72,
+ EXYNOS7_GPIO_D73,
+ EXYNOS7_GPIO_D74,
+ EXYNOS7_GPIO_D75,
+ EXYNOS7_GPIO_D76,
+ EXYNOS7_GPIO_D77,
+ EXYNOS7_GPIO_D80, /* 144 0x90 */
+ EXYNOS7_GPIO_D81,
+ EXYNOS7_GPIO_D82,
+ EXYNOS7_GPIO_D83,
+ EXYNOS7_GPIO_D84,
+ EXYNOS7_GPIO_D85,
+ EXYNOS7_GPIO_D86,
+ EXYNOS7_GPIO_D87,
+ EXYNOS7_GPIO_G00, /* 152 0x98 */
+ EXYNOS7_GPIO_G01,
+ EXYNOS7_GPIO_G02,
+ EXYNOS7_GPIO_G03,
+ EXYNOS7_GPIO_G04,
+ EXYNOS7_GPIO_G05,
+ EXYNOS7_GPIO_G06,
+ EXYNOS7_GPIO_G07,
+ EXYNOS7_GPIO_G30, /* 160 0xA0 */
+ EXYNOS7_GPIO_G31,
+ EXYNOS7_GPIO_G32,
+ EXYNOS7_GPIO_G33,
+ EXYNOS7_GPIO_G34,
+ EXYNOS7_GPIO_G35,
+ EXYNOS7_GPIO_G36,
+ EXYNOS7_GPIO_G37,
+
+ /* GPIO_PART4_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_3, /* 168 0xA8 */
+ EXYNOS7_GPIO_F00 = (EXYNOS7_GPIO_MAX_PORT_PART_3 + 0x20),
+ EXYNOS7_GPIO_F01,
+ EXYNOS7_GPIO_F02,
+ EXYNOS7_GPIO_F03,
+ EXYNOS7_GPIO_F04,
+ EXYNOS7_GPIO_F05,
+ EXYNOS7_GPIO_F06,
+ EXYNOS7_GPIO_F07,
+ EXYNOS7_GPIO_F10, /* 208 0xD0 */
+ EXYNOS7_GPIO_F11,
+ EXYNOS7_GPIO_F12,
+ EXYNOS7_GPIO_F13,
+ EXYNOS7_GPIO_F14,
+ EXYNOS7_GPIO_F15,
+ EXYNOS7_GPIO_F16,
+ EXYNOS7_GPIO_F17,
+ EXYNOS7_GPIO_F20, /* 216 0xD8 */
+ EXYNOS7_GPIO_F21,
+ EXYNOS7_GPIO_F22,
+ EXYNOS7_GPIO_F23,
+ EXYNOS7_GPIO_F24,
+ EXYNOS7_GPIO_F25,
+ EXYNOS7_GPIO_F26,
+ EXYNOS7_GPIO_F27,
+ EXYNOS7_GPIO_F30, /* 224 0xE0 */
+ EXYNOS7_GPIO_F31,
+ EXYNOS7_GPIO_F32,
+ EXYNOS7_GPIO_F33,
+ EXYNOS7_GPIO_F34,
+ EXYNOS7_GPIO_F35,
+ EXYNOS7_GPIO_F36,
+ EXYNOS7_GPIO_F37,
+ EXYNOS7_GPIO_F40, /* 232 0xE8 */
+ EXYNOS7_GPIO_F41,
+ EXYNOS7_GPIO_F42,
+ EXYNOS7_GPIO_F43,
+ EXYNOS7_GPIO_F44,
+ EXYNOS7_GPIO_F45,
+ EXYNOS7_GPIO_F46,
+ EXYNOS7_GPIO_F47,
+ EXYNOS7_GPIO_F50, /* 240 0xF0 */
+ EXYNOS7_GPIO_F51,
+ EXYNOS7_GPIO_F52,
+ EXYNOS7_GPIO_F53,
+ EXYNOS7_GPIO_F54,
+ EXYNOS7_GPIO_F55,
+ EXYNOS7_GPIO_F56,
+ EXYNOS7_GPIO_F57,
+ EXYNOS7_GPIO_G10, /* 248 0xF8 */
+ EXYNOS7_GPIO_G11,
+ EXYNOS7_GPIO_G12,
+ EXYNOS7_GPIO_G13,
+ EXYNOS7_GPIO_G14,
+ EXYNOS7_GPIO_G15,
+ EXYNOS7_GPIO_G16,
+ EXYNOS7_GPIO_G17,
+ EXYNOS7_GPIO_G20, /* 256 0x100 */
+ EXYNOS7_GPIO_G21,
+ EXYNOS7_GPIO_G22,
+ EXYNOS7_GPIO_G23,
+ EXYNOS7_GPIO_G24,
+ EXYNOS7_GPIO_G25,
+ EXYNOS7_GPIO_G26,
+ EXYNOS7_GPIO_G27,
+ EXYNOS7_GPIO_H10, /* 264 0x108 */
+ EXYNOS7_GPIO_H11,
+ EXYNOS7_GPIO_H12,
+ EXYNOS7_GPIO_H13,
+ EXYNOS7_GPIO_H14,
+ EXYNOS7_GPIO_H15,
+ EXYNOS7_GPIO_H16,
+ EXYNOS7_GPIO_H17,
+ EXYNOS7_GPIO_V60, /* 272 0x110 */
+ EXYNOS7_GPIO_V61,
+ EXYNOS7_GPIO_V62,
+ EXYNOS7_GPIO_V63,
+ EXYNOS7_GPIO_V64,
+ EXYNOS7_GPIO_V65,
+ EXYNOS7_GPIO_V66,
+ EXYNOS7_GPIO_V67,
+
+ /* GPIO_PART5_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_4, /* 280 0x118 */
+ EXYNOS7_GPIO_J00 = EXYNOS7_GPIO_MAX_PORT_PART_4,
+ EXYNOS7_GPIO_J01,
+ EXYNOS7_GPIO_J02,
+ EXYNOS7_GPIO_J03,
+ EXYNOS7_GPIO_J04,
+ EXYNOS7_GPIO_J05,
+ EXYNOS7_GPIO_J06,
+ EXYNOS7_GPIO_J07,
+
+ /* GPIO_PART6_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_5, /* 288 0x120 */
+ EXYNOS7_GPIO_J10 = EXYNOS7_GPIO_MAX_PORT_PART_5,
+ EXYNOS7_GPIO_J11,
+ EXYNOS7_GPIO_J12,
+ EXYNOS7_GPIO_J13,
+ EXYNOS7_GPIO_J14,
+ EXYNOS7_GPIO_J15,
+ EXYNOS7_GPIO_J16,
+ EXYNOS7_GPIO_J17,
+
+ /* GPIO_PART7_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_6, /* 296 0x128 */
+ EXYNOS7_GPIO_G40 = EXYNOS7_GPIO_MAX_PORT_PART_6,
+ EXYNOS7_GPIO_G41,
+ EXYNOS7_GPIO_G42,
+ EXYNOS7_GPIO_G43,
+ EXYNOS7_GPIO_G44,
+ EXYNOS7_GPIO_G45,
+ EXYNOS7_GPIO_G46,
+ EXYNOS7_GPIO_G47,
+
+ /* GPIO_PART8_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_7, /* 304 0x130 */
+ EXYNOS7_GPIO_V70 = EXYNOS7_GPIO_MAX_PORT_PART_7,
+ EXYNOS7_GPIO_V71,
+ EXYNOS7_GPIO_V72,
+ EXYNOS7_GPIO_V73,
+ EXYNOS7_GPIO_V74,
+ EXYNOS7_GPIO_V75,
+ EXYNOS7_GPIO_V76,
+ EXYNOS7_GPIO_V77,
+
+ /* GPIO_PART9_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_8, /* 312 0x138 */
+ EXYNOS7_GPIO_R40 = EXYNOS7_GPIO_MAX_PORT_PART_8,
+ EXYNOS7_GPIO_R41,
+ EXYNOS7_GPIO_R42,
+ EXYNOS7_GPIO_R43,
+ EXYNOS7_GPIO_R44,
+ EXYNOS7_GPIO_R45,
+ EXYNOS7_GPIO_R46,
+ EXYNOS7_GPIO_R47,
+
+ /* GPIO_PART10_STARTS */
+ EXYNOS7_GPIO_MAX_PORT_PART_9, /* 320 0x140 */
+ EXYNOS7_GPIO_R00 = EXYNOS7_GPIO_MAX_PORT_PART_9,
+ EXYNOS7_GPIO_R01,
+ EXYNOS7_GPIO_R02,
+ EXYNOS7_GPIO_R03,
+ EXYNOS7_GPIO_R04,
+ EXYNOS7_GPIO_R05,
+ EXYNOS7_GPIO_R06,
+ EXYNOS7_GPIO_R07,
+ EXYNOS7_GPIO_R10, /* 328 0x148 */
+ EXYNOS7_GPIO_R11,
+ EXYNOS7_GPIO_R12,
+ EXYNOS7_GPIO_R13,
+ EXYNOS7_GPIO_R14,
+ EXYNOS7_GPIO_R15,
+ EXYNOS7_GPIO_R16,
+ EXYNOS7_GPIO_R17,
+ EXYNOS7_GPIO_R20, /* 336 0x150 */
+ EXYNOS7_GPIO_R21,
+ EXYNOS7_GPIO_R22,
+ EXYNOS7_GPIO_R23,
+ EXYNOS7_GPIO_R24,
+ EXYNOS7_GPIO_R25,
+ EXYNOS7_GPIO_R26,
+ EXYNOS7_GPIO_R27,
+ EXYNOS7_GPIO_R30, /* 344 0x158 */
+ EXYNOS7_GPIO_R31,
+ EXYNOS7_GPIO_R32,
+ EXYNOS7_GPIO_R33,
+ EXYNOS7_GPIO_R34,
+ EXYNOS7_GPIO_R35,
+ EXYNOS7_GPIO_R36,
+ EXYNOS7_GPIO_R37,
+
+ EXYNOS7_GPIO_MAX_PORT
+};
+
+struct gpio_info {
+ u64 reg_addr; /* Address of register for this part */
+ u32 max_gpio; /* Maximum GPIO in this part */
+};
+
+#define EXYNOS7_GPIO_NUM_PARTS 10
+static struct gpio_info exynos7_gpio_data[EXYNOS7_GPIO_NUM_PARTS] = {
+ { EXYNOS7_GPIO_ALIVE_BASE, EXYNOS7_GPIO_MAX_PORT_PART_1 },
+ { EXYNOS7_GPIO_AUD_BASE, EXYNOS7_GPIO_MAX_PORT_PART_2 },
+ { EXYNOS7_GPIO_BUS0_BASE, EXYNOS7_GPIO_MAX_PORT_PART_3 },
+ { EXYNOS7_GPIO_BUS1_BASE, EXYNOS7_GPIO_MAX_PORT_PART_4 },
+ { EXYNOS7_GPIO_NFC_BASE, EXYNOS7_GPIO_MAX_PORT_PART_5 },
+ { EXYNOS7_GPIO_TOUCH_BASE, EXYNOS7_GPIO_MAX_PORT_PART_6 },
+ { EXYNOS7_GPIO_FF_BASE, EXYNOS7_GPIO_MAX_PORT_PART_7 },
+ { EXYNOS7_GPIO_ESE_BASE, EXYNOS7_GPIO_MAX_PORT_PART_8 },
+ { EXYNOS7_GPIO_FSYS0_BASE, EXYNOS7_GPIO_MAX_PORT_PART_9 },
+ { EXYNOS7_GPIO_FSYS1_BASE, EXYNOS7_GPIO_MAX_PORT },
+};
+
+static inline struct gpio_info *get_gpio_data(void)
+{
+ return exynos7_gpio_data;
+}
+
+static inline unsigned int get_bank_num(void)
+{
+ return EXYNOS7_GPIO_NUM_PARTS;
+}
+
+#define name_to_gpio(n) exynos_name_to_gpio(n)
+#define gpio_describe(str) exynos_gpio_describe(str)
+
+void gpio_cfg_pin(int gpio, int cfg);
+void gpio_set_drv(int gpio, int drv);
+int gpio_set_value(unsigned gpio, int value);
+int gpio_get_value(unsigned gpio);
+int gpio_request(unsigned gpio, const char *label);
+int gpio_free(unsigned gpio);
+int gpio_direction_input(unsigned gpio);
+int gpio_direction_output(unsigned gpio, int value);
+
+/* Pin configurations */
+#define EXYNOS_GPIO_INPUT 0x0
+#define EXYNOS_GPIO_OUTPUT 0x1
+#define EXYNOS_GPIO_IRQ 0xf
+#define EXYNOS_GPIO_FUNC(x) (x)
+
+/* Pull mode */
+#define EXYNOS_GPIO_PULL_NONE 0x0
+#define EXYNOS_GPIO_PULL_DOWN 0x1
+#define EXYNOS_GPIO_PULL_UP 0x3
+
+/* Drive Strength level */
+#define EXYNOS_GPIO_DRV_1X 0x0
+#define EXYNOS_GPIO_DRV_3X 0x1
+#define EXYNOS_GPIO_DRV_2X 0x2
+#define EXYNOS_GPIO_DRV_4X 0x3
+#define EXYNOS_GPIO_DRV_FAST 0x0
+#define EXYNOS_GPIO_DRV_SLOW 0x1
+
+/**
+ * Set GPIO pull mode.
+ *
+ * @param gpio GPIO pin
+ * @param mode Either GPIO_PULL_DOWN or GPIO_PULL_UP
+ */
+void gpio_set_pull(int gpio, int mode);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_GPIO_H_ */
diff --git a/src/soc/samsung/exynos7/include/soc/pinmux.h b/src/soc/samsung/exynos7/include/soc/pinmux.h
new file mode 100644
index 0000000..c80600f
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/pinmux.h
@@ -0,0 +1,55 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_PINMUX_H_
+#define _CPU_SAMSUNG_EXYNOS7_PINMUX_H_
+
+/*
+ * Flags for setting specific configarations of peripherals.
+ * List will grow with support for more devices getting added.
+ */
+enum {
+ PINMUX_FLAG_NONE = 0x00000000,
+
+ /* Flags for eMMC */
+ PINMUX_FLAG_8BIT_MODE = 1 << 0, /* SDMMC 8-bit mode */
+
+ /* Flags for SROM controller */
+ PINMUX_FLAG_BANK = 3 << 0, /* bank number (0-3) */
+ PINMUX_FLAG_16BIT = 1 << 2, /* 16-bit width */
+};
+
+void exynos_pinmux_uart0(void);
+void exynos_pinmux_uart1(void);
+void exynos_pinmux_uart2(void);
+
+void exynos_pinmux_mmc0(void);
+void exynos_pinmux_mmc1(void);
+void exynos_pinmux_mmc2(void);
+
+void exynos_pinmux_i2c0(void);
+void exynos_pinmux_i2c1(void);
+void exynos_pinmux_i2c2(void);
+void exynos_pinmux_i2c3(void);
+void exynos_pinmux_i2c4(void);
+void exynos_pinmux_i2c5(void);
+void exynos_pinmux_i2c6(void);
+void exynos_pinmux_i2c7(void);
+void exynos_pinmux_i2c8(void);
+void exynos_pinmux_i2c9(void);
+void exynos_pinmux_i2c10(void);
+void exynos_pinmux_i2c11(void);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_PINMUX_H_ */
diff --git a/src/soc/samsung/exynos7/pinmux.c b/src/soc/samsung/exynos7/pinmux.c
new file mode 100644
index 0000000..e41f260
--- /dev/null
+++ b/src/soc/samsung/exynos7/pinmux.c
@@ -0,0 +1,277 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <assert.h>
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include <soc/pinmux.h>
+#include <soc/periph.h>
+
+static void exynos7_uart_config(int peripheral)
+{
+ struct exynos7_gpio_part3 *gpio_bus0 =
+ (struct exynos7_gpio_part3 *)EXYNOS7_GPIO_BUS0_BASE;
+ struct exynos_gpio_bank *bank = NULL;
+ int i, start = 0, count = 0, func = 0;
+
+ switch (peripheral) {
+ case PERIPH_ID_UART0:
+ bank = &gpio_bus0->d0;
+ start = 0;
+ count = 4;
+ func = 2;
+ break;
+ case PERIPH_ID_UART1:
+ bank = &gpio_bus0->d1;
+ start = 0;
+ count = 4;
+ func = 2;
+ break;
+ case PERIPH_ID_UART2:
+ bank = &gpio_bus0->d1;
+ start = 4;
+ count = 2;
+ func = 2;
+ break;
+ case PERIPH_ID_UART3:
+ bank = &gpio_bus0->d5;
+ start = 0;
+ count = 2;
+ func = 3;
+ break;
+ }
+ for (i = start; i < start + count; i++) {
+ exynos_gpio_set_pull(bank, i, EXYNOS_GPIO_PULL_NONE);
+ exynos_gpio_cfg_pin(bank, i, EXYNOS_GPIO_FUNC(func));
+ }
+}
+
+void exynos_pinmux_uart0(void)
+{
+ exynos7_uart_config(PERIPH_ID_UART0);
+}
+
+void exynos_pinmux_uart1(void)
+{
+ exynos7_uart_config(PERIPH_ID_UART1);
+}
+
+void exynos_pinmux_uart2(void)
+{
+ exynos7_uart_config(PERIPH_ID_UART2);
+}
+
+static int exynos7_mmc_config(int peripheral, int flags)
+{
+ struct exynos7_gpio_part9 *gpio_fsys0 =
+ (struct exynos7_gpio_part9 *)EXYNOS7_GPIO_FSYS0_BASE;
+ struct exynos7_gpio_part10 *gpio_fsys1 =
+ (struct exynos7_gpio_part10 *)EXYNOS7_GPIO_FSYS1_BASE;
+ struct exynos_gpio_bank *bank, *bank_data, *bank_ext_data;
+ int i, bank_bit, bank_bit_cnt;
+ int bank_data_bit, bank_ext_data_bit;
+
+ switch (peripheral) {
+ case PERIPH_ID_SDMMC0:
+ bank = &gpio_fsys1->r0;
+ bank_data = &gpio_fsys1->r1;
+ bank_ext_data = &gpio_fsys1->r1;
+ bank_bit = 0;
+ bank_bit_cnt = 4;
+ bank_data_bit = 0;
+ bank_ext_data_bit = 4;
+ break;
+ case PERIPH_ID_SDMMC1:
+ bank = &gpio_fsys1->r2;
+ bank_data = &gpio_fsys1->r3;
+ bank_ext_data = &gpio_fsys1->r3;
+ bank_bit = 0;
+ bank_bit_cnt = 2;
+ bank_data_bit = 0;
+ bank_ext_data_bit = 4;
+ break;
+ case PERIPH_ID_SDMMC2:
+ bank = &gpio_fsys0->r4;
+ bank_data = &gpio_fsys0->r4;
+ bank_ext_data = NULL;
+ bank_bit = 0;
+ bank_bit_cnt = 4;
+ bank_data_bit = 4;
+ break;
+ default:
+ printk(BIOS_DEBUG, "%s: invalid peripheral %d", __func__, peripheral);
+ return -1;
+ }
+ if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext_data) {
+ printk(BIOS_DEBUG, "SDMMC device %d does not support 8bit mode",
+ peripheral);
+ return -1;
+ }
+ for (i = bank_bit; i < bank_bit_cnt; i++) {
+ exynos_gpio_cfg_pin(bank, i, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_set_pull(bank, i, EXYNOS_GPIO_PULL_NONE);
+ exynos_gpio_set_drv(bank, i, EXYNOS_GPIO_DRV_4X);
+ }
+ for (i = bank_data_bit; i < (bank_data_bit + 4); i++) {
+ exynos_gpio_cfg_pin(bank_data, i, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_set_pull(bank_data, i, EXYNOS_GPIO_PULL_UP);
+ exynos_gpio_set_drv(bank_data, i, EXYNOS_GPIO_DRV_4X);
+ }
+ if (flags & PINMUX_FLAG_8BIT_MODE) {
+ for (i = bank_ext_data_bit; i < (bank_ext_data_bit + 4); i++) {
+ exynos_gpio_cfg_pin(bank_ext_data, i, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_set_pull(bank_ext_data, i, EXYNOS_GPIO_PULL_UP);
+ exynos_gpio_set_drv(bank_ext_data, i, EXYNOS_GPIO_DRV_4X);
+ }
+ }
+ return 0;
+}
+
+void exynos_pinmux_mmc0(void)
+{
+ exynos7_mmc_config(PERIPH_ID_SDMMC0, PINMUX_FLAG_8BIT_MODE);
+}
+
+void exynos_pinmux_mmc1(void)
+{
+ exynos7_mmc_config(PERIPH_ID_SDMMC1, PINMUX_FLAG_NONE);
+}
+
+void exynos_pinmux_mmc2(void)
+{
+ exynos7_mmc_config(PERIPH_ID_SDMMC2, PINMUX_FLAG_NONE);
+}
+
+static void exynos7_i2c_config(int peripheral)
+{
+ struct exynos7_gpio_part3 *gpio_bus0 =
+ (struct exynos7_gpio_part3 *)EXYNOS7_GPIO_BUS0_BASE;
+ struct exynos7_gpio_part5 *gpio_nfc =
+ (struct exynos7_gpio_part5 *)EXYNOS7_GPIO_NFC_BASE;
+ struct exynos7_gpio_part6 *gpio_touch =
+ (struct exynos7_gpio_part6 *)EXYNOS7_GPIO_TOUCH_BASE;
+
+ switch (peripheral) {
+ case PERIPH_ID_I2C0:
+ exynos_gpio_cfg_pin(&gpio_bus0->d2, 0, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_bus0->d2, 1, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C1:
+ exynos_gpio_cfg_pin(&gpio_bus0->d2, 2, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_bus0->d2, 3, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C2:
+ exynos_gpio_cfg_pin(&gpio_bus0->d0, 2, EXYNOS_GPIO_FUNC(0x3));
+ exynos_gpio_cfg_pin(&gpio_bus0->d0, 3, EXYNOS_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C3:
+ exynos_gpio_cfg_pin(&gpio_bus0->d1, 2, EXYNOS_GPIO_FUNC(0x3));
+ exynos_gpio_cfg_pin(&gpio_bus0->d1, 3, EXYNOS_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C4:
+ exynos_gpio_cfg_pin(&gpio_bus0->g3, 0, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_bus0->g3, 1, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C5:
+ exynos_gpio_cfg_pin(&gpio_bus0->g3, 2, EXYNOS_GPIO_FUNC(0x3));
+ exynos_gpio_cfg_pin(&gpio_bus0->g3, 3, EXYNOS_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C6:
+ exynos_gpio_cfg_pin(&gpio_nfc->j0, 0, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_nfc->j0, 1, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C7:
+ exynos_gpio_cfg_pin(&gpio_touch->j1, 0, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_touch->j1, 1, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C8:
+ exynos_gpio_cfg_pin(&gpio_bus0->d5, 2, EXYNOS_GPIO_FUNC(0x3));
+ exynos_gpio_cfg_pin(&gpio_bus0->d5, 3, EXYNOS_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C9:
+ exynos_gpio_cfg_pin(&gpio_bus0->d2, 6, EXYNOS_GPIO_FUNC(0x3));
+ exynos_gpio_cfg_pin(&gpio_bus0->d2, 7, EXYNOS_GPIO_FUNC(0x3));
+ break;
+ case PERIPH_ID_I2C10:
+ exynos_gpio_cfg_pin(&gpio_bus0->b0, 0, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_bus0->b0, 1, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ case PERIPH_ID_I2C11:
+ exynos_gpio_cfg_pin(&gpio_bus0->b0, 2, EXYNOS_GPIO_FUNC(0x2));
+ exynos_gpio_cfg_pin(&gpio_bus0->b0, 3, EXYNOS_GPIO_FUNC(0x2));
+ break;
+ }
+}
+
+void exynos_pinmux_i2c0(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C0);
+}
+
+void exynos_pinmux_i2c1(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C1);
+}
+
+void exynos_pinmux_i2c2(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C2);
+}
+
+void exynos_pinmux_i2c3(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C3);
+}
+
+void exynos_pinmux_i2c4(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C4);
+}
+
+void exynos_pinmux_i2c5(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C5);
+}
+
+void exynos_pinmux_i2c6(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C6);
+}
+
+void exynos_pinmux_i2c7(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C7);
+}
+
+void exynos_pinmux_i2c8(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C8);
+}
+
+void exynos_pinmux_i2c9(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C9);
+}
+
+void exynos_pinmux_i2c10(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C10);
+}
+
+void exynos_pinmux_i2c11(void)
+{
+ exynos7_i2c_config(PERIPH_ID_I2C11);
+}
1
0
03 Jun '16
Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14908
-gerrit
commit 51ab963149cb8c544c147aa672b5c0784ed20f8b
Author: Akshay Saraswat <akshay.s(a)samsung.com>
Date: Thu Aug 7 16:15:47 2014 +0530
Exynos7: Add timer initialization
Adding initial MCT setup for Exynos7.
Change-Id: I45df0ff9f95ca9165f3cc31d302b6616ee690d35
Signed-off-by: Akshay Saraswat <akshay.s(a)samsung.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
---
src/soc/samsung/exynos7/Makefile.inc | 9 ++++
src/soc/samsung/exynos7/bootblock.c | 6 +++
src/soc/samsung/exynos7/include/soc/mct.h | 88 +++++++++++++++++++++++++++++++
src/soc/samsung/exynos7/mct.c | 31 +++++++++++
src/soc/samsung/exynos7/monotonic_timer.c | 31 +++++++++++
src/soc/samsung/exynos7/timer.c | 52 ++++++++++++++++++
6 files changed, 217 insertions(+)
diff --git a/src/soc/samsung/exynos7/Makefile.inc b/src/soc/samsung/exynos7/Makefile.inc
index f2b7b16..eeb9fcf 100644
--- a/src/soc/samsung/exynos7/Makefile.inc
+++ b/src/soc/samsung/exynos7/Makefile.inc
@@ -22,16 +22,25 @@ bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += clock_init.c
bootblock-y += dmc_init_lpddr4.c
+bootblock-y += mct.c
+bootblock-y += monotonic_timer.c
bootblock-y += power.c
+bootblock-y += timer.c
# ROMSTAGE : Run primitive tests and remaining basic stuff
romstage-y += clock.c
+romstage-y += mct.c
+romstage-y += monotonic_timer.c
romstage-y += power.c
+romstage-y += timer.c
# RAMSTAGE : Prepare and load payload
ramstage-y += clock.c
ramstage-y += cpu.c
+ramstage-y += mct.c
+ramstage-y += monotonic_timer.c
ramstage-y += power.c
+ramstage-y += timer.c
$(objcbfs)/bootblock.raw.elf: $(objcbfs)/bootblock.elf
cp $< $@
diff --git a/src/soc/samsung/exynos7/bootblock.c b/src/soc/samsung/exynos7/bootblock.c
index c197940..7183731 100644
--- a/src/soc/samsung/exynos7/bootblock.c
+++ b/src/soc/samsung/exynos7/bootblock.c
@@ -21,6 +21,7 @@
#include <soc/clock.h>
#include <soc/cpu.h>
#include <soc/dmc.h>
+#include <soc/mct.h>
#include <soc/power.h>
void bootblock_cpu_init(void)
@@ -32,6 +33,11 @@ void bootblock_cpu_init(void)
if (power_read_reset_status() == EXYNOS7_CHECK_SLEEP)
is_resume = 1;
+ /* kick off the multi-core timer.
+ * We want to do this as early as we can.
+ */
+ mct_start();
+
/* SCR_EL3.NS|IRQ|FIQ|EA */
raw_write_scr_el3(raw_read_scr_el3() | 0xf);
diff --git a/src/soc/samsung/exynos7/include/soc/mct.h b/src/soc/samsung/exynos7/include/soc/mct.h
new file mode 100644
index 0000000..2308daa
--- /dev/null
+++ b/src/soc/samsung/exynos7/include/soc/mct.h
@@ -0,0 +1,88 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _CPU_SAMSUNG_EXYNOS7_MCT_H_
+#define _CPU_SAMSUNG_EXYNOS7_MCT_H_
+
+#include <stddef.h>
+#include <soc/cpu.h>
+
+struct exynos_mct {
+ uint32_t mct_cfg;
+ uint8_t reserved0[0xfc];
+ uint32_t g_cnt_l;
+ uint32_t g_cnt_u;
+ uint8_t reserved1[0x8];
+ uint32_t g_cnt_wstat;
+ uint8_t reserved2[0xec];
+ uint32_t g_comp0_l;
+ uint32_t g_comp0_u;
+ uint32_t g_comp0_addr_incr;
+ uint8_t reserved3[0x4];
+ uint32_t g_comp1_l;
+ uint32_t g_comp1_u;
+ uint32_t g_comp1_addr_incr;
+ uint8_t reserved4[0x4];
+ uint32_t g_comp2_l;
+ uint32_t g_comp2_u;
+ uint32_t g_comp2_addr_incr;
+ uint8_t reserved5[0x4];
+ uint32_t g_comp3_l;
+ uint32_t g_comp3_u;
+ uint32_t g_comp3_addr_incr;
+ uint8_t reserved6[0x4];
+ uint32_t g_tcon;
+ uint32_t g_int_cstat;
+ uint32_t g_int_enb;
+ uint32_t g_wstat;
+ uint8_t reserved7[0xb0];
+ uint32_t l0_tcntb;
+ uint32_t l0_tcnto;
+ uint32_t l0_icntb;
+ uint32_t l0_icnto;
+ uint32_t l0_frcntb;
+ uint32_t l0_frcnto;
+ uint8_t reserved8[0x8];
+ uint32_t l0_tcon;
+ uint8_t reserved9[0xc];
+ uint32_t l0_int_cstat;
+ uint32_t l0_int_enb;
+ uint8_t reserved10[0x8];
+ uint32_t l0_wstat;
+ uint8_t reserved11[0xbc];
+ uint32_t l1_tcntb;
+ uint32_t l1_tcnto;
+ uint32_t l1_icntb;
+ uint32_t l1_icnto;
+ uint32_t l1_frcntb;
+ uint32_t l1_frcnto;
+ uint8_t reserved12[0x8];
+ uint32_t l1_tcon;
+ uint8_t reserved13[0xc];
+ uint32_t l1_int_cstat;
+ uint32_t l1_int_enb;
+ uint8_t reserved14[0x8];
+ uint32_t l1_wstat;
+};
+check_member(exynos_mct, l1_wstat, 0x440);
+
+static struct exynos_mct * const exynos_mct =
+ (void *)EXYNOS7_MCT_BASE;
+
+
+void mct_start(void);
+uint64_t mct_raw_value(void);
+
+#endif /* _CPU_SAMSUNG_EXYNOS7_MCT_H_ */
diff --git a/src/soc/samsung/exynos7/mct.c b/src/soc/samsung/exynos7/mct.c
new file mode 100644
index 0000000..d911b92
--- /dev/null
+++ b/src/soc/samsung/exynos7/mct.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <soc/mct.h>
+
+uint64_t mct_raw_value(void)
+{
+ uint64_t upper = read32(&exynos_mct->g_cnt_u);
+ uint64_t lower = read32(&exynos_mct->g_cnt_l);
+
+ return (upper << 32) | lower;
+}
+
+void mct_start(void)
+{
+ write32(&exynos_mct->g_tcon, read32(&exynos_mct->g_tcon) | (0x1 << 8));
+}
diff --git a/src/soc/samsung/exynos7/monotonic_timer.c b/src/soc/samsung/exynos7/monotonic_timer.c
new file mode 100644
index 0000000..c8e94fc
--- /dev/null
+++ b/src/soc/samsung/exynos7/monotonic_timer.c
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <timer.h>
+
+#include <soc/clock.h>
+#include <soc/mct.h>
+
+static const uint32_t clocks_per_usec = MCT_HZ/1000000;
+
+void timer_monotonic_get(struct mono_time *mt)
+{
+ /* We don't have to call mct_start() here
+ * because it was already called int he bootblock
+ */
+
+ mono_time_set_usecs(mt, mct_raw_value() / clocks_per_usec);
+}
diff --git a/src/soc/samsung/exynos7/timer.c b/src/soc/samsung/exynos7/timer.c
new file mode 100644
index 0000000..d8add89
--- /dev/null
+++ b/src/soc/samsung/exynos7/timer.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Samsung Electronics
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <timer.h>
+#include <delay.h>
+#include <thread.h>
+#include <soc/clock.h>
+
+void init_timer(void)
+{
+ /* Nothing to do because we manually
+ * call mct_start() in the bootblock
+ */
+}
+
+/* delay x useconds */
+void udelay(unsigned usec)
+{
+ struct mono_time current, end;
+
+ if (!thread_yield_microseconds(usec))
+ return;
+
+ timer_monotonic_get(¤t);
+ end = current;
+ mono_time_add_usecs(&end, usec);
+
+ if (mono_time_after(¤t, &end)) {
+ printk(BIOS_EMERG, "udelay: 0x%08x is impossibly large\n",
+ usec);
+ /* There's not much we can do if usec is too big. Use a long,
+ * paranoid delay value and hope for the best... */
+ end = current;
+ mono_time_add_usecs(&end, USECS_PER_SEC);
+ }
+
+ while (mono_time_before(¤t, &end))
+ timer_monotonic_get(¤t);
+}
1
0
03 Jun '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15056
-gerrit
commit 9daaee628600d4c662af283763cf4fc74649ec7e
Author: Hannah Williams <hannah.williams(a)intel.com>
Date: Thu Jun 2 15:00:36 2016 -0700
board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS
Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/mainboard/intel/amenia/devicetree.cb | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb
index af06848..e4aeeaf 100644
--- a/src/mainboard/intel/amenia/devicetree.cb
+++ b/src/mainboard/intel/amenia/devicetree.cb
@@ -10,6 +10,9 @@ chip soc/intel/apollolake
# Integrated Sensor Hub
register "integrated_sensor_hub_enable" = "0"
+ # LPSS S0ix Enable
+ register "S0ixEnable" = "1"
+
device domain 0 on
device pci 00.0 on end # - Host Bridge
device pci 00.1 on end # - DPTF
1
0
Patch set updated for coreboot: soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree
by Hannah Williams 03 Jun '16
by Hannah Williams 03 Jun '16
03 Jun '16
Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15055
-gerrit
commit 70b43dd60061e2b0e22c387046282e3eaa76315c
Author: Saurabh Satija <saurabh.satija(a)intel.com>
Date: Tue May 3 15:15:31 2016 -0700
soc/apollolake: Allow enable\disable of LPSS S0ix from devicetree
Change-Id: Ib7aa1d1b32adcb541a155b8ba2ee011cb5bcf784
Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com>
Signed-off-by: Hannah Williams <hannah.williams(a)intel.com>
---
src/soc/intel/apollolake/chip.c | 2 ++
src/soc/intel/apollolake/chip.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c
index d7c61c1..659686f 100644
--- a/src/soc/intel/apollolake/chip.c
+++ b/src/soc/intel/apollolake/chip.c
@@ -108,6 +108,8 @@ void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
cfg = dev->chip_info;
+ silconfig->S0ixEnable = cfg->S0ixEnable;
+
silconfig->PcieRpClkReqNumber[0] = cfg->pcie_rp0_clkreq_pin;
silconfig->PcieRpClkReqNumber[1] = cfg->pcie_rp1_clkreq_pin;
silconfig->PcieRpClkReqNumber[2] = cfg->pcie_rp2_clkreq_pin;
diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h
index 3d9f5bd..4ac5d93 100644
--- a/src/soc/intel/apollolake/chip.h
+++ b/src/soc/intel/apollolake/chip.h
@@ -45,6 +45,8 @@ struct soc_intel_apollolake_config {
/* Integrated Sensor Hub */
uint8_t integrated_sensor_hub_enable;
+ /* Configure LPSS S0ix Enable */
+ uint8_t S0ixEnable;
};
#endif /* _SOC_APOLLOLAKE_CHIP_H_ */
1
0