coreboot-gerrit June 2016

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New patch to review for coreboot: nb/intel/common/mrc_cache: implement store_current_mrc_cache
by Patrick Rudolph 05 Jun '16

05 Jun '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15074 -gerrit commit ba008870a79c2edd688baeb378b79fc9df5020e2 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun May 29 17:05:06 2016 +0200 nb/intel/common/mrc_cache: implement store_current_mrc_cache Remove code duplication and use the common function store_current_mrc_cache instead. No functionality was changed. Change-Id: I4aa5463f1b1d5e1afbe44b4bfc659524d86204db Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/common/mrc_cache.c | 32 +++++++++++++++++++++++++ src/northbridge/intel/common/mrc_cache.h | 1 + src/northbridge/intel/haswell/raminit.c | 24 +------------------ src/northbridge/intel/nehalem/raminit.c | 23 +----------------- src/northbridge/intel/sandybridge/raminit.c | 25 ++----------------- src/northbridge/intel/sandybridge/raminit_mrc.c | 25 +------------------ 6 files changed, 38 insertions(+), 92 deletions(-) diff --git a/src/northbridge/intel/common/mrc_cache.c b/src/northbridge/intel/common/mrc_cache.c index 82b1005..4c3ee5d 100644 --- a/src/northbridge/intel/common/mrc_cache.c +++ b/src/northbridge/intel/common/mrc_cache.c @@ -250,3 +250,35 @@ struct mrc_data_container *find_current_mrc_cache(void) // 0. compare MRC data to last mrc-cache block (exit if same) return find_current_mrc_cache_local(cache_base, cache_size); } + +struct mrc_data_container * +store_current_mrc_cache(void *data, unsigned length) +{ + struct mrc_data_container *mrcdata; + int output_len = ALIGN(length, 16); + + /* Save the MRC S3 restore data to cbmem */ + mrcdata = cbmem_add + (CBMEM_ID_MRCDATA, + output_len + sizeof(struct mrc_data_container)); + + if (!mrcdata) + return NULL; + + printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", + data, mrcdata, output_len); + + mrcdata->mrc_signature = MRC_DATA_SIGNATURE; + mrcdata->mrc_data_size = output_len; + mrcdata->reserved = 0; + memcpy(mrcdata->mrc_data, data, length); + + /* Zero the unused space in aligned buffer. */ + if (output_len > length) + memset(mrcdata->mrc_data+length, 0, output_len - length); + + mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, + mrcdata->mrc_data_size); + + return mrcdata; +} diff --git a/src/northbridge/intel/common/mrc_cache.h b/src/northbridge/intel/common/mrc_cache.h index 408a420..1fb6667 100644 --- a/src/northbridge/intel/common/mrc_cache.h +++ b/src/northbridge/intel/common/mrc_cache.h @@ -13,5 +13,6 @@ struct mrc_data_container { } __attribute__ ((packed)); struct mrc_data_container *find_current_mrc_cache(void); +struct mrc_data_container *store_current_mrc_cache(void *data, unsigned length); #endif /* NORTHBRIDGE_INTEL_COMMON_MRC_CACHE_H */ diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 4644f05..464f7c8 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -31,30 +31,8 @@ void save_mrc_data(struct pei_data *pei_data) { - struct mrc_data_container *mrcdata; - int output_len = ALIGN(pei_data->mrc_output_len, 16); - /* Save the MRC S3 restore data to cbmem */ - mrcdata = cbmem_add - (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); - - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - pei_data->mrc_output, mrcdata, output_len); - - mrcdata->mrc_signature = MRC_DATA_SIGNATURE; - mrcdata->mrc_data_size = output_len; - mrcdata->reserved = 0; - memcpy(mrcdata->mrc_data, pei_data->mrc_output, - pei_data->mrc_output_len); - - /* Zero the unused space in aligned buffer. */ - if (output_len > pei_data->mrc_output_len) - memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, - output_len - pei_data->mrc_output_len); - - mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); + store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len); } static void prepare_mrc_cache(struct pei_data *pei_data) diff --git a/src/northbridge/intel/nehalem/raminit.c b/src/northbridge/intel/nehalem/raminit.c index a5a6276..0549de7 100644 --- a/src/northbridge/intel/nehalem/raminit.c +++ b/src/northbridge/intel/nehalem/raminit.c @@ -1688,8 +1688,6 @@ static void dump_timings(struct raminfo *info) static void save_timings(struct raminfo *info) { struct ram_training train; - struct mrc_data_container *mrcdata; - int output_len = ALIGN(sizeof(train), 16); int channel, slot, rank, lane, i; train = info->training; @@ -1717,26 +1715,7 @@ static void save_timings(struct raminfo *info) printk (BIOS_SPEW, "[6e8] = %x\n", train.reg_6e8); /* Save the MRC S3 restore data to cbmem */ - mrcdata = cbmem_add - (CBMEM_ID_MRCDATA, output_len + sizeof(struct mrc_data_container)); - - if (mrcdata != NULL) { - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - &train, mrcdata, output_len); - - mrcdata->mrc_signature = MRC_DATA_SIGNATURE; - mrcdata->mrc_data_size = output_len; - mrcdata->reserved = 0; - memcpy(mrcdata->mrc_data, &train, sizeof(train)); - - /* Zero the unused space in aligned buffer. */ - if (output_len > sizeof(train)) - memset(mrcdata->mrc_data + sizeof(train), 0, - output_len - sizeof(train)); - - mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); - } + store_current_mrc_cache(&train, sizeof(train)); } #if REAL diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 1ed77eb..6bb77b2 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -3938,31 +3938,10 @@ static void final_registers(ramctr_timing * ctrl) | 0xc); } -static void save_timings(ramctr_timing * ctrl) +static void save_timings(ramctr_timing *ctrl) { - struct mrc_data_container *mrcdata; - int output_len = ALIGN(sizeof (*ctrl), 16); - /* Save the MRC S3 restore data to cbmem */ - mrcdata = cbmem_add - (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); - - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - ctrl, mrcdata, output_len); - - mrcdata->mrc_signature = MRC_DATA_SIGNATURE; - mrcdata->mrc_data_size = output_len; - mrcdata->reserved = 0; - memcpy(mrcdata->mrc_data, ctrl, sizeof (*ctrl)); - - /* Zero the unused space in aligned buffer. */ - if (output_len > sizeof (*ctrl)) - memset(mrcdata->mrc_data+sizeof (*ctrl), 0, - output_len - sizeof (*ctrl)); - - mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); + store_current_mrc_cache(ctrl, sizeof(*ctrl)); } static void restore_timings(ramctr_timing * ctrl) diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index c26f012..8754e42 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -52,32 +52,9 @@ void save_mrc_data(struct pei_data *pei_data) { u16 c1, c2, checksum; - struct mrc_data_container *mrcdata; - int output_len = ALIGN(pei_data->mrc_output_len, 16); /* Save the MRC S3 restore data to cbmem */ - mrcdata = cbmem_add - (CBMEM_ID_MRCDATA, - output_len + sizeof(struct mrc_data_container)); - - if (mrcdata != NULL) { - printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n", - pei_data->mrc_output, mrcdata, output_len); - - mrcdata->mrc_signature = MRC_DATA_SIGNATURE; - mrcdata->mrc_data_size = output_len; - mrcdata->reserved = 0; - memcpy(mrcdata->mrc_data, pei_data->mrc_output, - pei_data->mrc_output_len); - - /* Zero the unused space in aligned buffer. */ - if (output_len > pei_data->mrc_output_len) - memset(mrcdata->mrc_data+pei_data->mrc_output_len, 0, - output_len - pei_data->mrc_output_len); - - mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data, - mrcdata->mrc_data_size); - } + store_current_mrc_cache(pei_data->mrc_output, pei_data->mrc_output_len); /* Save the MRC seed values to CMOS */ cmos_write32(CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);

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New patch to review for coreboot: device/device: add dev_verify_resources
by Patrick Rudolph 05 Jun '16

05 Jun '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15073 -gerrit commit 84b279cc718b9123630cf716ba42d975a919c332 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun May 29 17:00:11 2016 +0200 device/device: add dev_verify_resources Make sure that dynamic allocated resource fit into PCI mmio region. The caller has to provide the current lower PCI MMIO limit (TOLUD) and receives the lowest dynamic resource base address. Change-Id: Icde74e4748e9b273882af3f5955b530c3567886b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/device.c | 47 +++++++++++++++++++++++++++++++++++++++++++++ src/include/device/device.h | 1 + 2 files changed, 48 insertions(+) diff --git a/src/device/device.c b/src/device/device.c index 9ea32cc..1c314e4 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -1116,6 +1116,53 @@ void dev_enable(void) } /** + * Find and verify the smallest resource base address. + * + * Starting at the root, walk the tree and verify all devices/bridges by + * looking at the resource's base address. Ignore fixed resources. + * Print an error if the resource lays outside of the PCI decode range. + * + * @configured_mmio_base: Current PCI MMIO address used for verification + * + * Returns: The smallest resource base address found + */ +u32 dev_verify_resources(u32 configured_mmio_base) +{ + struct resource *res; + struct device *root; + struct device *child; + u32 real_mmio_base = 0xffffffff; + + root = &dev_root; + + /* Read the resources for the entire tree. */ + + printk(BIOS_DEBUG, "Reading resources...\n"); + read_resources(root->link_list); + printk(BIOS_DEBUG, "Done reading resources.\n"); + + /* Verify PCI MMIO configuration ... */ + + for (child = root->link_list->children; child; child = child->sibling) { + if (!(child->path.type == DEVICE_PATH_DOMAIN)) + continue; + post_log_path(child); + for (res = child->resource_list; res; res = res->next) { + if (res->flags & IORESOURCE_FIXED) + continue; + if (res->base < configured_mmio_base) { + show_one_resource(BIOS_ERR, child, res, + " doesn't fit into PCI MMIO space."); + } + if (res->base < real_mmio_base) + real_mmio_base = res->base; + } + } + + return real_mmio_base; +} + +/** * Initialize a specific device. * * The parent should be initialized first to avoid having an ordering problem. diff --git a/src/include/device/device.h b/src/include/device/device.h index 00ff3d9..8ccc421 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -169,6 +169,7 @@ void dev_initialize_chips(void); void dev_enumerate(void); void dev_configure(void); void dev_enable(void); +u32 dev_verify_resources(u32); void dev_initialize(void); void dev_optimize(void); void dev_finalize(void);

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Patch merged into coreboot/master: pcengines/apu1: Add SMBIOS SKU field
by gerrit＠coreboot.org 05 Jun '16

05 Jun '16

the following patch was just integrated into master: commit 9aba60ed6e4ab3c1b44e15c1ac0cd324581bb600 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 30 16:56:11 2016 +0300 pcengines/apu1: Add SMBIOS SKU field Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14997 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> See https://review.coreboot.org/14997 for details. -gerrit

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New patch to review for coreboot: Kconfig: Clarify FRAMEBUFFER_KEEP_VESA_MODE
by Denis Carikli 04 Jun '16

04 Jun '16

Denis Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15072 -gerrit commit fda91cbb1cf9dd1eec92b7200893688dc269b8a8 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Fri Jun 3 22:26:36 2016 +0200 Kconfig: Clarify FRAMEBUFFER_KEEP_VESA_MODE This makes it easier to gasp what the option does without having to read the help. Change-Id: I51598532d09d8d9d7c2359ca15b2da408cc700d1 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> --- src/device/Kconfig | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index b1f8dae..61120a4 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -505,16 +505,27 @@ config FRAMEBUFFER_VESA_MODE default 0x11B if FRAMEBUFFER_VESA_MODE_11B default 0x117 if FRAMEBUFFER_VESA_MODE_USER +choice + prompt "Framebuffer mode" + config FRAMEBUFFER_KEEP_VESA_MODE - prompt "Keep VESA framebuffer" + prompt "Framebuffer mode" bool depends on PCI_OPTION_ROM_RUN_YABEL || PCI_OPTION_ROM_RUN_REALMODE || (MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG && MAINBOARD_DO_NATIVE_VGA_INIT) help This option keeps the framebuffer mode set after coreboot finishes - execution. If this option is enabled, coreboot will pass a - framebuffer entry in its coreboot table and the payload will need a - framebuffer driver. If this option is disabled, coreboot will switch - back to text mode before handing control to a payload. + execution. + If this option is enabled, coreboot will pass a framebuffer entry in its + coreboot table and the payload will need a framebuffer driver. + +config FRAMEBUFFER_KEEP_TEXT_MODE + prompt "Text mode" + bool + help + If this option is enabled, coreboot will switch back to text mode + before handing control to a payload. + +endchoice config BOOTSPLASH prompt "Show graphical bootsplash"

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Patch merged into coreboot/master: soc/apollolake: Put CSE to low power state
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 5d9cc7866f9c2536c0fd809665c00ec88501226f Author: Hannah Williams <hannah.williams(a)intel.com> Date: Fri Apr 29 14:48:20 2016 -0700 soc/apollolake: Put CSE to low power state fsp_notify(END_OF_FIRMWARE) should be sent to FSP to enable putting CSE in low power state Change-Id: I76b8e85ccf077032616ba8e4a333d9264dc65ed2 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://review.coreboot.org/15054 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15054 for details. -gerrit

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Patch merged into coreboot/master: soc/apollolake/pmc: Store the ACPI bar during set_resources stage
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit a942bd49525706f88abe3558b17611ef64738072 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Wed May 18 14:41:48 2016 -0700 soc/apollolake/pmc: Store the ACPI bar during set_resources stage Because the resource for the ACPI BAR is fixed, pci_dev_set_resources does not store it to the device. This means we need to do part of the dance to get the ACPI IO region to work after coreboot. Of course, this BAR can be destroyed later by the OS probing it, but at least we try to get it working out of coreboot. Change-Id: Ibff18d30936f94d4f149a89313254531365f43e6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Reviewed-on: https://review.coreboot.org/15048 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15048 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/x4x: Fix unpopulated value
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 68e1dcfdd940db05c282c601b58dd86f97b44767 Author: Damien Zammit <damien(a)zamaudio.com> Date: Fri Jun 3 15:39:30 2016 +1000 nb/intel/x4x: Fix unpopulated value Previously, 0x0 was the value being used for an unpopulated dimm on spd[62], however some DDR2 dimms have 0x0 as a valid value. Now use 0xff which is an unused value even on DDR2/DDR3. Change-Id: I55a91a6c3fe3733a7bb2abc45ca352c955c07c99 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> Reviewed-on: https://review.coreboot.org/15058 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15058 for details. -gerrit

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Patch merged into coreboot/master: AGESA boards: Split dispatcher to romstage and ramstage
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 062ef1cca6c1cd70828288181129ba0d0addd4ab Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:18:02 2016 +0300 AGESA boards: Split dispatcher to romstage and ramstage The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14417 for details. -gerrit

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Patch merged into coreboot/master: intelmetool: Add the X99 ISA Bridge device id
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit a03609b49600f05ec37e1796676954a3dc14faa3 Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Thu Jun 2 21:06:54 2016 +0200 intelmetool: Add the X99 ISA Bridge device id This adds the ISA bridge device id for the Intel C160/X99 series chipset to the intelmetool. Change-Id: I2e7db0fe1692985ebb167b9a44ab412a45a9f3bd Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> Reviewed-on: https://review.coreboot.org/15053 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin.daisuki(a)googlemail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/15053 for details. -gerrit

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Patch set updated for coreboot: intelmetool: Add the X99 ISA Bridge device id
by Omar Pakker 04 Jun '16

04 Jun '16

Omar Pakker just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15053 -gerrit commit a3bbae8618dec88ec49c484b1522f1dfba2f8bef Author: Omar Pakker <omarpakker+coreboot(a)gmail.com> Date: Thu Jun 2 21:06:54 2016 +0200 intelmetool: Add the X99 ISA Bridge device id This adds the ISA bridge device id for the Intel C160/X99 series chipset to the intelmetool. Change-Id: I2e7db0fe1692985ebb167b9a44ab412a45a9f3bd Signed-off-by: Omar Pakker <omarpakker+coreboot(a)gmail.com> --- util/intelmetool/intelmetool.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/util/intelmetool/intelmetool.h b/util/intelmetool/intelmetool.h index 22cff1a..4b9803b 100644 --- a/util/intelmetool/intelmetool.h +++ b/util/intelmetool/intelmetool.h @@ -114,6 +114,7 @@ extern int debug; #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL 0x9c41 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM 0x9c43 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE 0x9c45 +#define PCI_DEVICE_ID_INTEL_X99 0x8d47 #define PCI_DEV_HAS_ME_DIFFICULT(x) ( \ ( (x) == PCI_DEVICE_ID_INTEL_ICH10R ) || \ @@ -168,7 +169,8 @@ extern int debug; ( (x) == PCI_DEVICE_ID_INTEL_DH89XXCC ) || \ ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_FULL ) || \ ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM ) || \ - ( (x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE )) + ((x) == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE) || \ + ((x) == PCI_DEVICE_ID_INTEL_X99)) // Not sure if ME present, but should be able to disable it easily #define PCI_DEVICE_ID_INTEL_ICH8 0x2810

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coreboot-gerrit June 2016