coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: gm45: enable setting all vram sizes from cmos
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 7afcfe0f9f78ef8d5029e90304a34caf07d14588 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu May 19 15:34:49 2016 +0200 gm45: enable setting all vram sizes from cmos Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> See https://review.coreboot.org/14900 for details. -gerrit

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New patch to review for coreboot: mainboard/lenovo/x220: code cleanup
by Jan Tatje 04 Jun '16

04 Jun '16

Jan Tatje just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15071 -gerrit commit 3ac3cb1b83dc7bea2de9bfb93b2863df3f7e6be0 Author: Jan Tatje <jan(a)jnt.io> Date: Sat Jun 4 19:29:03 2016 +0200 mainboard/lenovo/x220: code cleanup thermal.h still had references to X230 in include guard since it seems to have been copied from that port. Small whitespace changes in romstage.c. Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56 signed-off-by: Jan Tatje <jan(a)jnt.io> --- src/mainboard/lenovo/x220/romstage.c | 6 ++++-- src/mainboard/lenovo/x220/thermal.h | 4 ++-- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 27998d9..71ed1a8 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -75,12 +75,14 @@ const struct southbridge_usb_port mainboard_usb_ports[] = { { 1, 1, 6 }, }; -void mainboard_get_spd(spd_raw_data *spd) { +void mainboard_get_spd(spd_raw_data *spd) +{ read_spd (&spd[0], 0x50); read_spd (&spd[2], 0x51); } -void mainboard_early_init(int s3resume) { +void mainboard_early_init(int s3resume) +{ } void mainboard_config_superio(void) diff --git a/src/mainboard/lenovo/x220/thermal.h b/src/mainboard/lenovo/x220/thermal.h index 199c27e..82df303 100644 --- a/src/mainboard/lenovo/x220/thermal.h +++ b/src/mainboard/lenovo/x220/thermal.h @@ -14,8 +14,8 @@ * GNU General Public License for more details. */ -#ifndef X230_THERMAL_H -#define X230_THERMAL_H +#ifndef X220_THERMAL_H +#define X220_THERMAL_H /* Temperature which OS will shutdown at */ #define CRITICAL_TEMPERATURE 100

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Patch merged into coreboot/master: AGESA f12 f15: Add OEM customisation
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 90e63deebaf22a73c501c97a47ff72577a09ead6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon May 16 07:50:58 2016 +0300 AGESA f12 f15: Add OEM customisation Follow-up on commits a5d72a3 and 53052fe for f12 and f15. OEM Hooks are not BiosCallOuts. Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14888 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14888 for details. -gerrit

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Patch merged into coreboot/master: AGESA: Fix invalid use of CFG_ declarations
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 50036324070be4336096c111918dc1e1a3ea69a3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 18 13:35:21 2016 +0300 AGESA: Fix invalid use of CFG_ declarations The declarations of CFG_ evaluate to correct values only when included after the definitions of BLDCFG_ in buildOpts.c. So we never have CFG_PLAT_NUM_IO_APICS defined here. Change-Id: I94b3dee5a3207b37921eb24a0bcd73b5a217b2d3 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14887 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14887 for details. -gerrit

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Patch merged into coreboot/master: AGESA: Fix invalid BLDCFG_ and CFG_ use
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 206e157cc1922f0db8e92ecd23d9b76e493d2b4c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 18 14:04:45 2016 +0300 AGESA: Fix invalid BLDCFG_ and CFG_ use The definitions of CFG_ would evaluate to incorrect values when Options.h is included outside buildOpts.c, where all BLDCFG_ values are defined. Already done for f16kb. Change-Id: I5d725b9306027c7c46c6450ab17b692fa948cf5b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14886 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14886 for details. -gerrit

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Patch merged into coreboot/master: AGESA: Drop unused assembly files
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit b97dc871d99c91270bb80be6ce6d1937e5169b7a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Mon Apr 18 12:09:00 2016 +0300 AGESA: Drop unused assembly files Change-Id: I0a452b6234b02222be82ca8694868e1ffbfceaee Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14396 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14396 for details. -gerrit

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Patch merged into coreboot/master: AGESA: Remove unused platform configuration files
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit 6de9795143ba14037d7e934bf57c0966347c762a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 18 15:07:52 2016 +0300 AGESA: Remove unused platform configuration files Change-Id: Ie6effa802f6971c59b5c4e07ca7d98736e27859f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14885 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14885 for details. -gerrit

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Patch merged into coreboot/master: AGESA f10: Pick sample platform configuration
by gerrit＠coreboot.org 04 Jun '16

04 Jun '16

the following patch was just integrated into master: commit db1b344207cf1c21b0ac96b8bca90ad308566c67 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Wed May 18 14:01:11 2016 +0300 AGESA f10: Pick sample platform configuration Tree does not have any AGESA f10 boards. Keep the Danube platform as a sample configuration file for unlikely future use. Change-Id: I025aff48fcd0884b45e2a0a993d82f317ede48be Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/14884 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14884 for details. -gerrit

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Patch set updated for coreboot: soc/intel/common: Add _OSC method
by Hannah Williams 03 Jun '16

03 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15021 -gerrit commit 899e2fac1193078a218017bdd3f09b92dda93f77 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Wed May 18 13:45:20 2016 -0700 soc/intel/common: Add _OSC method Not masking any bits in Operating System Capabilities, which means we support all the capabilities that OS passed in Arg3 Change-Id: Ib87915e18e305db41b52891ac5430201dda64bb5 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/common/acpi/osc.asl | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/src/soc/intel/common/acpi/osc.asl b/src/soc/intel/common/acpi/osc.asl new file mode 100644 index 0000000..4179e94 --- /dev/null +++ b/src/soc/intel/common/acpi/osc.asl @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" + +Scope (\_SB.PCI0) { + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +}

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New patch to review for coreboot: rk3288: Remove duplicate timestamp_init()
by Julius Werner 03 Jun '16

03 Jun '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15070 -gerrit commit d0e080543ffcb8959da7213e2d862b47eaa956cd Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Jun 3 17:27:58 2016 -0700 rk3288: Remove duplicate timestamp_init() Fix bug introduced by merging CL:9606 and CL:10740 in the wrong order. Change-Id: I75dd22cd0cf30c7d91e4fa5171cb482a80eb64ca Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3288/bootblock.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index 65ca7a9..02fe9ff 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,8 +26,6 @@ void bootblock_soc_init(void) { - timestamp_init(timestamp_get()); - rkclk_init(); mmu_init();

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coreboot-gerrit June 2016