coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

1 participants
1491 discussions

Patch merged into coreboot/master: rockchip: gru: enable eDP display
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit b497b48027c592d3ad6fcfefe6c742fc78e371cb Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Mar 31 18:44:13 2016 +0800 rockchip: gru: enable eDP display This patch enables eDP display by: o. setting HPD pinmux, backlight, vdd for eDP o. setting vop mode o. enabling VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=The dev screen is shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Reviewed-on: https://review.coreboot.org/14858 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14858 for details. -gerrit

1 0

Patch merged into coreboot/master: rockchip: rk3399: initialize display for eDP
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit d1cec75ce8b69d3e90bc2189dd0b1af329ea8cce Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Wed May 4 16:21:36 2016 +0800 rockchip: rk3399: initialize display for eDP This patch adds functions to init the display. To set up the display, initialize the eDP and read the EDID. Based on these, we then set the clock for VOP, and finally enable VOP and backlight. For a mainboard, it should set the vop_id, vop_mode and framebuffer_bits_per_pixel in devicetree.cb. For VOP_MODE_AUTO_DETECT, it will try eDP first and then HDMI (which is not supported yet). EDIT: Updated Makefile to only build in new files if MAINBOARD_DO_NATIVE_VGA_INIT is enabled. All of these platforms should have it enabled, so this shouldn't make any difference except now, before the platform code is in place. BRANCH=none BUG=chrome-os-partner:51537 TEST=test with the other patch Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Commit-Id: c1020cc806775629f4d5dc57bd805a9a12169386 Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342336 Original-Commit-Ready: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Reviewed-on: https://review.coreboot.org/14857 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14857 for details. -gerrit

1 0

Patch set updated for coreboot: rockchip: gru: enable eDP display
by Martin Roth 03 Jun '16

03 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14858 -gerrit commit 90a40695c573d7395bd55727a013f65b768a6a3e Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Mar 31 18:44:13 2016 +0800 rockchip: gru: enable eDP display This patch enables eDP display by: o. setting HPD pinmux, backlight, vdd for eDP o. setting vop mode o. enabling VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=The dev screen is shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq(a)rock-chips.com> --- src/mainboard/google/gru/Kconfig | 2 ++ src/mainboard/google/gru/devicetree.cb | 3 ++ src/mainboard/google/gru/mainboard.c | 58 +++++++++++++++++++++++++++++++ src/soc/rockchip/rk3399/include/soc/grf.h | 2 ++ 4 files changed, 65 insertions(+) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index b0ea9ff..48ae698 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -24,7 +24,9 @@ config BOARD_SPECIFIC_OPTIONS select BOARD_ROMSIZE_KB_8192 select COMMON_CBFS_SPI_WRAPPER select HAVE_HARD_RESET + select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select MAINBOARD_HAS_NATIVE_VGA_INIT select SOC_ROCKCHIP_RK3399 select SPI_FLASH select SPI_FLASH_GIGADEVICE diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index b349888..be1d466 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -15,4 +15,7 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end + register "vop_id" = "0" + register "vop_mode" = "VOP_MODE_EDP" + register "framebuffer_bits_per_pixel" = "16" end diff --git a/src/mainboard/google/gru/mainboard.c b/src/mainboard/google/gru/mainboard.c index 6824cbf..0ccedd3 100644 --- a/src/mainboard/google/gru/mainboard.c +++ b/src/mainboard/google/gru/mainboard.c @@ -15,11 +15,15 @@ */ #include <boardid.h> +#include <delay.h> #include <device/device.h> +#include <device/i2c.h> #include <gpio.h> #include <soc/clock.h> +#include <soc/display.h> #include <soc/emmc.h> #include <soc/grf.h> +#include <soc/i2c.h> static void configure_emmc(void) { @@ -86,10 +90,64 @@ static void configure_sdmmc(void) write32(&rk3399_grf->iomux_sdmmc, IOMUX_SDMMC); } +static void configure_display(void) +{ + /* set pinmux for edp HPD*/ + gpio_input_pulldown(GPIO(4, C, 7)); + write32(&rk3399_grf->iomux_edp_hotplug, IOMUX_EDP_HOTPLUG); + + gpio_output(GPIO(4, D, 3), 1); /* CPU3_EDP_VDDEN for P3.3V_DISP */ +} + static void mainboard_init(device_t dev) { configure_sdmmc(); configure_emmc(); + configure_display(); +} + +static void enable_backlight_booster(void) +{ + const struct { + uint8_t reg; + uint8_t value; + } i2c_writes[] = { + {1, 0x84}, + {1, 0x85}, + {0, 0x26} + }; + int i; + const int booster_i2c_port = 0; + uint8_t i2c_buf[2]; + struct i2c_seg i2c_command = { .read = 0, .chip = 0x2c, + .buf = i2c_buf, .len = sizeof(i2c_buf) + }; + + /* + * This function is called on Gru right after BL_EN is asserted. It + * takes time for the switcher chip to come online, let's wait a bit + * to let the voltage settle, so that the chip can be accessed. + */ + udelay(1000); + + /* Select pinmux for i2c0, which is the display backlight booster. */ + write32(&rk3399_pmugrf->iomux_i2c0_sda, IOMUX_I2C0_SDA); + write32(&rk3399_pmugrf->iomux_i2c0_scl, IOMUX_I2C0_SCL); + i2c_init(0, 100*KHz); + + for (i = 0; i < ARRAY_SIZE(i2c_writes); i++) { + i2c_buf[0] = i2c_writes[i].reg; + i2c_buf[1] = i2c_writes[i].value; + i2c_transfer(booster_i2c_port, &i2c_command, 1); + } +} + +void mainboard_power_on_backlight(void) +{ + gpio_output(GPIO(1, C, 1), 1); /* BL_EN */ + + if (IS_ENABLED(CONFIG_BOARD_GOOGLE_GRU)) + enable_backlight_booster(); } static void mainboard_enable(device_t dev) diff --git a/src/soc/rockchip/rk3399/include/soc/grf.h b/src/soc/rockchip/rk3399/include/soc/grf.h index df1fb03..241c97f 100644 --- a/src/soc/rockchip/rk3399/include/soc/grf.h +++ b/src/soc/rockchip/rk3399/include/soc/grf.h @@ -140,6 +140,7 @@ struct rk3399_grf_regs { u32 iomux_pwm_1; u32 iomux_uart2b; u32 iomux_uart2c; + u32 iomux_edp_hotplug; u32 gpio4c_iomux; }; u32 gpio4d_iomux; @@ -346,4 +347,5 @@ static struct rk3399_pmusgrf_regs * const rk3399_pmusgrf = (void *)PMUSGRF_BASE; #define IOMUX_PWM_3_A RK_SETBITS(1 << 12) #define IOMUX_PWM_3_B RK_SETBITS(1 << 12) #define IOMUX_TSADC_INT RK_CLRSETBITS(3 << 12, 1 << 12) +#define IOMUX_EDP_HOTPLUG RK_CLRSETBITS(3 << 14, 2 << 14) #endif /* __SOC_ROCKCHIP_RK3399_GRF_H__ */

1 0

Patch set updated for coreboot: rockchip: rk3399: initialize display for eDP
by Martin Roth 03 Jun '16

03 Jun '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14857 -gerrit commit df7b53a8f49d0c53beb5882e24ba5d823dd6ef56 Author: Shunqian Zheng <zhengsq(a)rock-chips.com> Date: Wed May 4 16:21:36 2016 +0800 rockchip: rk3399: initialize display for eDP This patch adds functions to init the display. To set up the display, initialize the eDP and read the EDID. Based on these, we then set the clock for VOP, and finally enable VOP and backlight. For a mainboard, it should set the vop_id, vop_mode and framebuffer_bits_per_pixel in devicetree.cb. For VOP_MODE_AUTO_DETECT, it will try eDP first and then HDMI (which is not supported yet). EDIT: Updated Makefile to only build in new files if MAINBOARD_DO_NATIVE_VGA_INIT is enabled. All of these platforms should have it enabled, so this shouldn't make any difference except now, before the platform code is in place. BRANCH=none BUG=chrome-os-partner:51537 TEST=test with the other patch Change-Id: If935415026c945ab6ee128bd6bbdd792890aa24a Signed-off-by: Martin Roth <martinroth(a)google.com> Original-Commit-Id: c1020cc806775629f4d5dc57bd805a9a12169386 Original-Change-Id: Ic32d0a251cb8e08aa5f0b15b2c06c4e02c08a761 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/342336 Original-Commit-Ready: Vadim Bendebury <vbendeb(a)chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb(a)chromium.org> Original-Reviewed-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> --- src/soc/rockchip/rk3399/Makefile.inc | 3 + src/soc/rockchip/rk3399/chip.h | 32 ++++++ src/soc/rockchip/rk3399/display.c | 122 +++++++++++++++++++++++ src/soc/rockchip/rk3399/include/soc/addressmap.h | 5 + src/soc/rockchip/rk3399/include/soc/display.h | 25 +++++ src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 + src/soc/rockchip/rk3399/soc.c | 8 ++ 7 files changed, 196 insertions(+) diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc index 68f346c..8abafe3 100644 --- a/src/soc/rockchip/rk3399/Makefile.inc +++ b/src/soc/rockchip/rk3399/Makefile.inc @@ -55,6 +55,8 @@ ramstage-y += sdram.c ramstage-y += ../common/spi.c ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c ramstage-y += clock.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += display.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/edp.c ramstage-y += emmc.c ramstage-y += ../common/gpio.c ramstage-y += gpio.c @@ -62,6 +64,7 @@ ramstage-y += ../common/i2c.c ramstage-y += saradc.c ramstage-y += soc.c ramstage-y += timer.c +ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += ../common/vop.c BL31_MAKEARGS += PLAT=rk3399 ################################################################################ diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h new file mode 100644 index 0000000..46baa8c --- /dev/null +++ b/src/soc/rockchip/rk3399/chip.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_CHIP_H__ +#define __SOC_ROCKCHIP_RK3399_CHIP_H__ + +#include <soc/gpio.h> +#include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */ + +struct soc_rockchip_rk3399_config { + u32 vop_id; + gpio_t lcd_bl_pwm_gpio; + gpio_t lcd_bl_en_gpio; + u32 bl_power_on_udelay; + u32 bl_pwm_to_enable_udelay; + u32 framebuffer_bits_per_pixel; + u32 vop_mode; +}; + +#endif /* __SOC_ROCKCHIP_RK3399_CHIP_H__ */ diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c new file mode 100644 index 0000000..d69df93 --- /dev/null +++ b/src/soc/rockchip/rk3399/display.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cache.h> +#include <arch/mmu.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <delay.h> +#include <edid.h> +#include <gpio.h> +#include <stdlib.h> +#include <stddef.h> +#include <string.h> +#include <soc/addressmap.h> +#include <soc/clock.h> +#include <soc/display.h> +#include <soc/edp.h> +#include <soc/gpio.h> +#include <soc/grf.h> +#include <soc/mmu_operations.h> +#include <soc/soc.h> +#include <soc/vop.h> + +#include "chip.h" + +void rk_display_init(device_t dev, uintptr_t lcdbase, + unsigned long fb_size) +{ + struct edid edid; + uint32_t val; + struct soc_rockchip_rk3399_config *conf = dev->chip_info; + uintptr_t lower = ALIGN_DOWN(lcdbase, MiB); + uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB); + enum vop_modes detected_mode = VOP_MODE_UNKNOWN; + + printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase)); + memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ + dcache_clean_invalidate_by_mva((void *)lower, upper - lower); + mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM); + + switch (conf->vop_mode) { + case VOP_MODE_NONE: + return; + case VOP_MODE_AUTO_DETECT: + /* try EDP first, then HDMI */ + case VOP_MODE_EDP: + printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); + rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + + /* select edp signal from vop0(big) or vop1(little) */ + val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) : + RK_CLRBITS(1 << 5); + write32(&rk3399_grf->soc_con20, val); + + /* select edp clk from SoC internal 24M crystal, otherwise, + * it will source from edp's 24M clock (that depends on + * edp vendor, could be unstable) + */ + write32(&rk3399_grf->soc_con25, RK_SETBITS(1 << 11)); + + rk_edp_init(); + + if (rk_edp_get_edid(&edid) == 0) { + detected_mode = VOP_MODE_EDP; + break; + } + printk(BIOS_WARNING, "Cannot get EDID from EDP.\n"); + if (conf->vop_mode == VOP_MODE_EDP) + return; + /* fall thru */ + case VOP_MODE_HDMI: + printk(BIOS_WARNING, "HDMI display is NOT supported yet.\n"); + return; + default: + printk(BIOS_WARNING, "Cannot read any EDID info, aborting.\n"); + return; + } + + if (rkclk_configure_vop_dclk(conf->vop_id, + edid.mode.pixel_clock * KHz)) { + printk(BIOS_WARNING, "config vop err\n"); + return; + } + + edid.framebuffer_bits_per_pixel = conf->framebuffer_bits_per_pixel; + edid.bytes_per_line = + edid.mode.ha * conf->framebuffer_bits_per_pixel / 8; + edid.x_resolution = edid.mode.ha; + edid.y_resolution = edid.mode.va; + rkvop_mode_set(conf->vop_id, &edid, detected_mode); + + rkvop_enable(conf->vop_id, lcdbase, &edid); + + switch (detected_mode) { + case VOP_MODE_HDMI: + /* should not be here before HDMI supported */ + return; + case VOP_MODE_EDP: + default: + if (rk_edp_enable()) { + printk(BIOS_WARNING, "edp enable error\n"); + return; + } + mainboard_power_on_backlight(); + break; + } + + set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); +} diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index 28cbd7a..77fca9e 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -59,6 +59,11 @@ #define TSADC_BASE 0xff260000 #define SARADC_BASE 0xff100000 #define RK_PWM_BASE 0xff420000 +#define EDP_BASE 0xff970000 + +#define VOP_BIG_BASE 0xff900000 /* corresponds to vop_id 0 */ +#define VOP_LIT_BASE 0xff8f0000 /* corresponds to vop_id 1 */ + #define DDRC0_BASE_ADDR 0xffa80000 #define SERVER_MSCH0_BASE_ADDR 0xffa84000 diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h new file mode 100644 index 0000000..7ccde56 --- /dev/null +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Rockchip Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_ROCKCHIP_RK3399_DISPLAY_H__ +#define __SOC_ROCKCHIP_RK3399_DISPLAY_H__ + +#define REF_CLK_24M (0x1 << 0) + +void rk_display_init(device_t dev, uintptr_t lcdbase, + unsigned long fb_size); +void mainboard_power_on_backlight(void); + +#endif diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index edb246d..ac16394 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,6 +22,7 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) + FRAMEBUFFER(0x10200000, 8M) SRAM_START(0xFF8C0000) BOOTBLOCK(0xFF8C2004, 32K - 4) diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 5b6ddb2b..ef0c9c7 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -13,10 +13,12 @@ * GNU General Public License for more details. */ +#include <bootmode.h> #include <console/console.h> #include <cpu/cpu.h> #include <device/device.h> #include <soc/addressmap.h> +#include <soc/display.h> #include <stddef.h> #include <stdlib.h> #include <string.h> @@ -34,6 +36,12 @@ static void soc_init(device_t dev) * arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h */ mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB)); + + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) + rk_display_init(dev, (uintptr_t)_framebuffer, + _framebuffer_size); + else + printk(BIOS_INFO, "Display initialization disabled.\n"); } static struct device_operations soc_ops = {

1 0

Patch merged into coreboot/master: drivers/intel/fsp1_1: Make weak routines quiet
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit e747b7473eca356f1ef388bef04d2b354ec46ab5 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 31 08:57:01 2016 -0700 drivers/intel/fsp1_1: Make weak routines quiet Now that there is a better way of finding optional routines, make the weak routines quiet so that it may be used for the optional implementation. TEST=Build and run on Galileo Gen2 Change-Id: Ic58c7de216394f80aee3a78dd08bd4682783be42 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15043 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit 287cd7563e140be1ccc5631cd5ab80db4a5b17dd Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sat May 28 14:34:44 2016 -0700 mainboard/intel/galileo: Add CREATE_BOARD_CHECKLIST Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC and Galileo board. TEST=Build and run on Galileo Gen2. Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15004 for details. -gerrit

1 0

Patch merged into coreboot/master: Add Board Checklist Support
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit fc3741f379f972d9d7d962fa4e62cec7a01f5e86 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu May 26 17:12:17 2016 -0700 Add Board Checklist Support Build the <board>_checklist.html file which contains a checklist table for each stage of coreboot. This processing builds a set of implemented (done) routines which are marked green in the table. The remaining required routines (work-to-do) are marked red in the table and the optional routines are marked yellow in the table. The table heading for each stage contains a completion percentage in terms of count of routines (done .vs. required). Add some Kconfig values: * CREATE_BOARD_CHECKLIST - When selected creates the checklist file * MAKE_CHECKLIST_PUBLIC - Copies the checklist file into the Documenation directory * CHECKLIST_DATA_FILE_LOCATION - Location of the checklist data files: * <stage>_complete.dat - Lists all of the weak routines * <stage>_optional.dat - Lists weak routines which may be optionally implemented TEST=Build with Galileo Gen2. Change-Id: Ie056f8bb6d45ff7f3bc6390b5630b5063f54c527 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15011 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15011 for details. -gerrit

1 0

Patch merged into coreboot/master: mainboard/intel/galileo: Set board version
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit eb0e7bc9763de294ab74f67e38a78e6706246966 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Tue May 31 08:32:21 2016 -0700 mainboard/intel/galileo: Set board version Return the correct board version in SMBIOS. TEST=Build and run on Galileo Gen2 Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/15041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/15041 for details. -gerrit

1 0

Patch merged into coreboot/master: chromeec: Move EC image hash to separate file in CBFS
by gerrit＠coreboot.org 03 Jun '16

03 Jun '16

the following patch was just integrated into master: commit 8e97d00755867a41913156ecb08c74aab7398cb2 Author: Julius Werner <jwerner(a)chromium.org> Date: Tue May 31 18:11:10 2016 -0700 chromeec: Move EC image hash to separate file in CBFS The Chrome OS bootloader is changing its EC software sync mechanism to look for the hash of an EC image in a separate CBFS file, rather than using the CBFS hash attribute of the image itself (see http://crosreview.com/348061). This patch makes coreboot generate appropriate hash files for the new format when it builds and bundles a Chrome EC image. This also allows us to compress the EC image itself. Change-Id: I9aee6b8d24cdf41cb540db86a7569038fc7d9937 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/15039 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15039 for details. -gerrit

1 0

New patch to review for coreboot: soc/intel/apollolake: Add missing DRAM density constants
by Andrey Petrov 03 Jun '16

03 Jun '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15059 -gerrit commit e8f1489a8ae2882fe1cac50dbccdc4a50dd513e6 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Jun 3 07:14:12 2016 -0700 soc/intel/apollolake: Add missing DRAM density constants Add missing constants for DRAM density. This resolves boot issue, because misconfigured density results in incorrect memory mapping. Change-Id: I3bad911bf406bfc5677059490d0e89fcbf735b70 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/include/soc/meminit.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index 18c59a4..7830cc4 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -62,6 +62,8 @@ enum { /* LPDDR4 module density in bits. */ enum { + LP4_4Gb_DENSITY, + LP4_6Gb_DENSITY, LP4_8Gb_DENSITY, LP4_12Gb_DESNITY, LP4_16Gb_DENSITY,

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit June 2016