coreboot-gerrit June 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: i2c: Add a generic i2c driver
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 21a097aedc2b5a45bd55e1a6fb61a21f0ff43e07 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 09:50:59 2016 -0700 i2c: Add a generic i2c driver This adds a generic I2C driver that can be described in the devicetree and used to generate ACPI objects in the SSDT based on the information provided in the config registers. The I2C bus can be configured and the device can provide an interrupt and wake capability to the OS. A configuration option allows for a GPIO to be provided that will be checked to determine if the device is preset on the board before including it in the generated SSDT. The driver is generic enough to be used for basic I2C devices that do not have special configuration needs such as touchpads, touchscreens, sensors, some audio codec/amplifiers, etc. Sample usage for a touchpad device: device pci 15.1 on chip drivers/i2c/generic register "hid" = ""ELAN0000"" register "desc" = "ELAN Touchpad" register "irq" = "IRQ_EDGE_LOW(GPP_B3_IRQ)" register "wake" = "GPE0_DW0_05" device i2c 15.0 on end end end Will result in the following code in the SSDT: Scope (\_SB.PCI0.I2C1) { Device (D015) { Name (_HID, "ELAN0000") Name (_UID, 0) Name (_S0W, 4) Name (_PRW, Package () { 5, 3 }) Method (_STA) { Return (0x0f) } Name (_CRS, ResourceTemplate () { I2cSerialBus (0x15, ControllerInitiated, 400000, AddressingMode7Bit, "\\_S.PCI0.I2C1", 0, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow) { 51 } }) } } Change-Id: Ib32055720835b70e91ede5e4028ecd91894d70d5 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15016 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15016 for details. -gerrit

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Patch merged into coreboot/master: drivers/intel/wifi: Add support for generating SSDT table
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 5c026445f0d455976c3d29ebdf10dd89c9f29068 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 14:05:07 2016 -0700 drivers/intel/wifi: Add support for generating SSDT table Intel WiFi devices that support wake-on-wifi need to declare a Power Resource for this wake pin. Typically this has been done with a static declaration in the DSDT for each mainboard. By adding it to the existing intel/wifi driver it can be done based on a configuration register in the devicetree. Additionally the WiFi regulatory domain can be set in the SSDT directly instead of needing to use NVS to pass the value to the DSDT. Also add device IDs for Wilkins Peak 2 and Stone Peak 2 devices that are found on Chromebooks, and clean up a long line and some comment formatting. This was tested by booting on an HP Chromebook 13 device and comparing that the output in the SSDT matches what used to be in the DSDT. The WRDD value is read from VPD, if present, not from devicetree.cb. Additionally the case where CONFIG_DRIVERS_INTEL_WIFI is enabled but the wifi device is not described in devicetree.cb is tested to ensure it still generates the AML but does not include the _PRW wake pin. Example: devicetree.cb: device pci 1c.0 on chip drivers/intel/wifi register "wake" = "GPE0_DW0_16" device pci 00.0 on end end end VPD: "region"="us" SSDT.dsl: Scope (\_SB.PCI0.RP01) { Device (WIFI) { Name (_UID, Zero) Name (_DDN, "Intel WiFi") Name (_ADR, 0x00000000) Name (_PRW, Package () { 16, 3 }) Name (WRDD, Package () { Zero, Package () { 0x00000007, 0x00004150 } }) } } Change-Id: I8b5c916f1a04742507dc1ecc9a20c19d3822b18c Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15019 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15019 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: Add get_acpi_base_address
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15052 -gerrit commit efb6d3601726f5997de69b97783f7490adcf256a Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:45:22 2016 -0700 soc/apollolake: Add get_acpi_base_address Change-Id: If54e3821b9971f3d2cf59df0f9ae1b45af3bf314 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/pmutil.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6b12886..6c24b6c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -144,5 +144,6 @@ void disable_pm1_control(uint32_t mask); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t get_acpi_base_address(void); #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a04..b380738 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -336,3 +336,8 @@ int fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps->prev_sleep_state; } + +uint32_t get_acpi_base_address(void) +{ + return ACPI_PMIO_BASE; +}

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Patch merged into coreboot/master: wrdd: Export WRDD info in the header
by gerrit＠coreboot.org 02 Jun '16

02 Jun '16

the following patch was just integrated into master: commit 9fed935f5a1c2a45b6a5edcc7edd26d96cf28719 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Wed May 11 13:52:43 2016 -0700 wrdd: Export WRDD info in the header Export the WRDD spec revision and WiFi domain type in the header file so it can be used to generate ACPI tables by wifi drivers. Change-Id: I3222eca723c52fe74a004aa7bac7167264249fd1 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/15018 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/15018 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: SOC specific c-state table
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051 -gerrit commit 85652744a846522e358e1a7162f237755b9abf9e Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: SOC specific c-state table Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/acpi.c | 35 +++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 2 ++ 3 files changed, 38 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..52a00d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SOC_INTEL_COMMON select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_ACPI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4d610f8..3d3d739 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -26,6 +26,14 @@ #include <soc/pm.h> #include <soc/nvs.h> +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -157,3 +165,30 @@ void southbridge_inject_dsdt(device_t device) acpigen_pop_len(); } } +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), + } +}; + +acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return(cstate_map); +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..a9edbbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void enable_dev(device_t dev)

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Patch set updated for coreboot: soc/apollolake: SOC specific c-state table
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15051 -gerrit commit 5e69111f685d550d2b7b1e6d34439ba21cbd6deb Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:47:08 2016 -0700 soc/apollolake: SOC specific c-state table Change-Id: I5f82cdc4b34a53b5184ef1e918cae15a1df6cc5e Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/acpi.c | 35 +++++++++++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 2 ++ 3 files changed, 38 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 4643887..52a00d9 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select SMM_TSEG select SOC_INTEL_COMMON select SOC_INTEL_COMMON_SMI + select SOC_INTEL_COMMON_ACPI select SPI_FLASH select UDELAY_TSC select TSC_CONSTANT_RATE diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 4d610f8..3d3d739 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -26,6 +26,14 @@ #include <soc/pm.h> #include <soc/nvs.h> +#define CSTATE_RES(address_space, width, offset, address) \ + { \ + .space_id = address_space, \ + .bit_width = width, \ + .bit_offset = offset, \ + .addrl = address, \ + } + unsigned long acpi_fill_mcfg(unsigned long current) { /* PCI Segment Group 0, Start Bus Number 0, End Bus Number is 255 */ @@ -157,3 +165,30 @@ void southbridge_inject_dsdt(device_t device) acpigen_pop_len(); } } +static acpi_cstate_t cstate_map[] = { + { + /* C1 */ + .ctype = 1, /* ACPI C1 */ + .latency = 1, + .power = 1000, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_FIXED, 0, 0, 0), + }, + { + .ctype = 2, /* ACPI C2 */ + .latency = 50, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x415), + }, + { + .ctype = 3, /* ACPI C3 */ + .latency = 150, + .power = 10, + .resource = CSTATE_RES(ACPI_ADDRESS_SPACE_IO, 8, 0, 0x419), + } +}; + +acpi_cstate_t *get_cstate_map(int *entries) +{ + *entries = ARRAY_SIZE(cstate_map); + return(cstate_map); +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index f56e1f2..a9edbbb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <arch/acpi.h> #include <bootstate.h> #include <cbmem.h> #include <console/console.h> @@ -56,6 +57,7 @@ static struct device_operations cpu_bus_ops = { .enable_resources = DEVICE_NOOP, .init = apollolake_init_cpus, .scan_bus = NULL, + .acpi_fill_ssdt_generator = generate_cpu_entries, }; static void enable_dev(device_t dev)

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 02 Jun '16

02 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit 073675102e98ce25de464dcc1c1ee61283c923c4 Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 ++++ src/mainboard/intel/amenia/dsdt.asl | 14 ++++-- src/mainboard/intel/amenia/mainboard.c | 87 +++++++++++++++++++++++++++++++++- 3 files changed, 102 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..07d01e6 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -24,18 +24,22 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..82099ea 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,13 @@ */ #include <device/device.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +94,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -100,7 +104,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */ PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */ - /* Configure eMMC pins for proper pull UP/DN */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */ PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */ @@ -129,7 +132,44 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +static const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; +static struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "speaker-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) @@ -138,6 +178,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset_on_ssp(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), + &headset_tdm_cfg, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker_on_ssp(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, + AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

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Patch set updated for coreboot: mainboard/intel/amenia: Use common NHLT
by Saurabh Satija 02 Jun '16

02 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15024 -gerrit commit 72babc199aba4f42b148e6157c31403f35f5a4bb Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu May 26 16:08:45 2016 -0700 mainboard/intel/amenia: Use common NHLT Adding the ACPI NHLT table generation that the current hardware supports. Amenia has support for two audio codecs Nuvoton and Dialog for headphones and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/mainboard/intel/amenia/Kconfig | 8 ++++ src/mainboard/intel/amenia/dsdt.asl | 14 ++++-- src/mainboard/intel/amenia/mainboard.c | 87 +++++++++++++++++++++++++++++++++- 3 files changed, 102 insertions(+), 7 deletions(-) diff --git a/src/mainboard/intel/amenia/Kconfig b/src/mainboard/intel/amenia/Kconfig index bfc4091..edf9d91 100644 --- a/src/mainboard/intel/amenia/Kconfig +++ b/src/mainboard/intel/amenia/Kconfig @@ -14,6 +14,8 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_CHROMEOS select SYSTEM_TYPE_LAPTOP select TPM_ON_FAST_SPI + select ACPI_NHLT + select USE_COMMON_AUDIO config CHROMEOS bool @@ -64,4 +66,10 @@ config MAX_CPUS int default 8 +config INCLUDE_AUDIO_BLOBS + bool "Include blobs for audio." + select AUDIO_DMIC_2CH_16B + select AUDIO_SPEAKER + select AUDIO_HEADSET + endif # BOARD_INTEL_AMENIA diff --git a/src/mainboard/intel/amenia/dsdt.asl b/src/mainboard/intel/amenia/dsdt.asl index 19e7360..07d01e6 100644 --- a/src/mainboard/intel/amenia/dsdt.asl +++ b/src/mainboard/intel/amenia/dsdt.asl @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Intel Corp. + * Copyright (C) 2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -24,18 +24,22 @@ DefinitionBlock( 0x20110725 // OEM revision ) { + // global NVS and variables + #include <soc/intel/apollolake/acpi/globalnvs.asl> + Scope (\_SB) { Device (PCI0) { - #include <soc/intel/apollolake/acpi/northbridge.asl> - #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> } } /* Mainboard Specific devices */ #include "acpi/mainboard.asl" - /* Chipset specific sleep states */ - #include <soc/intel/apollolake/acpi/sleepstates.asl> + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> #include "acpi/superio.asl" diff --git a/src/mainboard/intel/amenia/mainboard.c b/src/mainboard/intel/amenia/mainboard.c index 22304f8..a4b9148 100644 --- a/src/mainboard/intel/amenia/mainboard.c +++ b/src/mainboard/intel/amenia/mainboard.c @@ -16,8 +16,13 @@ */ #include <device/device.h> +#include <drivers/audio.h> +#include <arch/acpi.h> +#include <console/console.h> #include <soc/gpio.h> #include <soc/pci_devs.h> +#include <stdlib.h> +#include <string.h> #include "ec.h" /* TODO: Move GPIO config to its own file once we get more GPIOs in the list */ @@ -89,7 +94,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_GPO(GPIO_154, 1, DEEP), /* BT_DISABLE_1P8_N */ PAD_CFG_GPI(GPIO_167, NONE, DEEP), /* DB_ID */ - PAD_CFG_NF(GPIO_172, UP_20K, DEEP, NF1), /* SDCARD_CLK */ PAD_CFG_NF(GPIO_173, UP_20K, DEEP, NF1), /* SDCARD_D0 */ PAD_CFG_NF(GPIO_174, UP_20K, DEEP, NF1), /* SDCARD_D1 */ @@ -100,7 +104,6 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_179, NATIVE, DEEP, NF1), /* SDCARD_CLK_FB */ PAD_CFG_GPO(GPIO_183, 1, DEEP), /* SDCARD_PWR_EN_N */ - /* Configure eMMC pins for proper pull UP/DN */ PAD_CFG_NF(GPIO_156, DN_20K, DEEP, NF1), /* EMMC0_CLK */ PAD_CFG_NF(GPIO_157, UP_20K, DEEP, NF1), /* EMMC0_D0 */ @@ -129,7 +132,44 @@ static const struct pad_config amenia_gpios[] = { PAD_CFG_NF(GPIO_199, UP_20K, DEEP, NF2), /* HV_DDI1_HPD */ PAD_CFG_NF(GPIO_200, UP_20K, DEEP, NF2), /* HV_DDI0_HPD */ PAD_CFG_NF(PMC_SPI_FS1, NATIVE, DEEP, NF2), /* HV_DDI2_HPD */ +}; + +static const struct nhlt_format_config dmic_2ch_cfg[] = { + /* 48 KHz 16-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 16, + .valid_bits_per_sample = 16, + .settings_file = "dmic-2ch-48khz-16b.bin", + }, +}; + +static const struct nhlt_format_config headset_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "headset-2ch-48khz-24b.bin", + }, +}; +static struct nhlt_tdm_config headset_tdm_cfg = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_format_config speaker_cfg[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .settings_file = "max98357-render-2ch-48khz-24b.bin", + }, }; static void mainboard_init(void *chip_info) @@ -138,6 +178,49 @@ static void mainboard_init(void *chip_info) mainboard_ec_init(); } +static unsigned long mainboard_write_acpi_tables( + device_t device, unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, dmic_2ch_cfg, ARRAY_SIZE(dmic_2ch_cfg), 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + /* NAU88l25 and Dialog have Headset codec. */ + if (nhlt_soc_add_headset_on_ssp(nhlt, headset_cfg, ARRAY_SIZE(headset_cfg), + &headset_tdm_cfg, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + /* MAXIM Smart Amps for left and right. */ + if (nhlt_soc_add_speaker_on_ssp(nhlt, speaker_cfg, ARRAY_SIZE(speaker_cfg), NULL, + AUDIO_LINK_SSP5)) + printk(BIOS_ERR, "Couldn't add speaker codec.\n"); + + end_addr = nhlt_soc_serialize(nhlt, start_addr); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + +static void mainboard_enable(device_t dev) +{ + dev->ops->write_acpi_tables = (void *) mainboard_write_acpi_tables; +} + struct chip_operations mainboard_ops = { .init = mainboard_init, + .enable_dev = mainboard_enable, }; +

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Patch set updated for coreboot: soc/apollolake: Add get_acpi_base_address
by Hannah Williams 02 Jun '16

02 Jun '16

Hannah Williams (hannah.williams(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15052 -gerrit commit fb1dfd15f59d7ad75e6b028b6979a6f81ed7b383 Author: Hannah Williams <hannah.williams(a)intel.com> Date: Mon Apr 18 13:45:22 2016 -0700 soc/apollolake: Add get_acpi_base_address Change-Id: If54e3821b9971f3d2cf59df0f9ae1b45af3bf314 Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> --- src/soc/intel/apollolake/include/soc/pm.h | 1 + src/soc/intel/apollolake/pmutil.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/include/soc/pm.h b/src/soc/intel/apollolake/include/soc/pm.h index 6b12886..6c24b6c 100644 --- a/src/soc/intel/apollolake/include/soc/pm.h +++ b/src/soc/intel/apollolake/include/soc/pm.h @@ -144,5 +144,6 @@ void disable_pm1_control(uint32_t mask); void enable_gpe(uint32_t mask); void disable_gpe(uint32_t mask); void disable_all_gpe(void); +uint32_t get_acpi_base_address(void); #endif diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 16c8a04..b380738 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -336,3 +336,8 @@ int fill_power_state(struct chipset_power_state *ps) printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state); return ps->prev_sleep_state; } + +uint32_t get_acpi_base_address(void) +{ + return ACPI_PMIO_BASE; +}

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Patch set updated for coreboot: apollolake/amenia: Add NHLT table region to ACPI global nvs
by Saurabh Satija 02 Jun '16

02 Jun '16

Saurabh Satija (saurabh.satija(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15025 -gerrit commit 972d1d61812ae1b242d7605e37f44f205b9755ba Author: Saurabh Satija <saurabh.satija(a)intel.com> Date: Thu Mar 31 15:41:30 2016 -0700 apollolake/amenia: Add NHLT table region to ACPI global nvs Adding address and length of NHLT table in ACPI. Change-Id: Ic0959a8aae18d54e10e3fcd95bfc98a6b6e0385a Signed-off-by: Saurabh Satija <saurabh.satija(a)intel.com> --- src/soc/intel/apollolake/acpi/globalnvs.asl | 4 +++- src/soc/intel/apollolake/include/soc/nvs.h | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl index 2ef5031..3efca51 100644 --- a/src/soc/intel/apollolake/acpi/globalnvs.asl +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -26,8 +26,10 @@ External (NVSA) OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) Field (GNVS, ByteAcc, NoLock, Preserve) { - /* Nothing here yet, folks */ + /* Miscellaneous */ Offset (0x00), + NHLA, 64, // 0x00 - NHLT Address + NHLL, 32, // 0x08 - NHLT Length /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h index 8b3a3af..23e40e8 100644 --- a/src/soc/intel/apollolake/include/soc/nvs.h +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -28,7 +28,9 @@ struct global_nvs_t { /* Miscellaneous */ - uint8_t unused[256]; + u64 nhla; /* 0x00 - NHLT Address */ + u32 nhll; /* 0x08 - NHLT Length */ + uint8_t unused[244]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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coreboot-gerrit June 2016