coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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1270 discussions

New patch to review for coreboot: nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14545 -gerrit commit 1b2ec690e53b2cbd2e79276952eebc14d4a58dbd Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 01:40:30 2016 -0500 nb/amd/mct_ddr3: Warn if MaxRdLatency training fails on Family 15h Change-Id: Idb948acd1a508379f600fbd2fd40fb26b7571d7c Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 77ae483..be95647 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1690,6 +1690,9 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, break; Set_NB32_index_wait_DCT(dev, Channel, index_reg, 0x00000050, 0x13131313); } + dword = Get_NB32_DCT(dev, Channel, 0x268) & 0x3ffff; + if (dword) + printk(BIOS_ERR, "WARNING: MaxRdLatency training FAILED! Attempting to continue but your system may be unstable...\n"); /* 2.10.5.8.5.1.5 */ nb_pstate = 0;

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New patch to review for coreboot: nb/amd/mct_ddr3: Stop receiver enable cycle training after window found
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14544 -gerrit commit 96b0d7c2fcc9c715877a2f1ff6e0bec03c042f4e Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 01:38:58 2016 -0500 nb/amd/mct_ddr3: Stop receiver enable cycle training after window found During receiver enable cycle training on Family 15h the entire range of possible delays is searched, even though the single passing window is often found nearly immediately. Skip the remainder of the delay range after the passing window has been located. Change-Id: If98217fa8e7de77366762d3c7bb01049a1dc080f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 7ef2900..69a5fe3 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1617,6 +1617,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t rx_en_offset; uint8_t internal_lane; uint8_t dct_training_success; + uint8_t lane_success_count; uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; @@ -1695,6 +1696,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { /* Initialize variables */ memset(dqs_results_array, 0, sizeof(dqs_results_array)); + lane_success_count = 0; /* 2.10.5.8.3 (1) */ dword = Get_NB32_index_wait_DCT(dev, dct, index_reg, 0x0d0f0030 | (lane << 8)); @@ -1721,6 +1723,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 (4 B) */ dqs_results_array[current_phy_phase_delay[lane]] = TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); + + if (dqs_results_array[current_phy_phase_delay[lane]]) + lane_success_count++; + + /* Don't bother testing larger values if the end of the passing window was already found */ + if (!dqs_results_array[current_phy_phase_delay[lane]] && (lane_success_count > 1)) + break; } uint16_t phase_delay;

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New patch to review for coreboot: nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14543 -gerrit commit edde5c3ce196e23cf565aace4d6dd68d0ac258ed Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 01:35:21 2016 -0500 nb/amd/mct_ddr3: Do not constantly reset read data timing registers to 0 During DQS receiver enable cycle training on Family 15h platforms the read data timing registers were inadvertently set to zero on every lane training attempt. Ensure that the read data timing registers are correctly set after each lane is trained in receiver enable cycle training. This allows more than one RDIMM to function on a given DCT channel. Change-Id: I87d732f0383e9785a73b57e6f48855f3e872f1f9 Tested-On: ASUS KGPE-D16 Tested-With: 1x Opteron 6262HE Tested-With: 4x Crucial 36KSF1G72PZ-1G6M1 (slots A2 / A1 / B2 / B1) Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 81e22a8..7ef2900 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -1687,6 +1687,11 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 (2) */ read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg); + /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ + for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) + current_read_dqs_delay[internal_lane] = 0x20; + write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); + for (lane = 0; lane < lane_count; lane++) { /* Initialize variables */ memset(dqs_results_array, 0, sizeof(dqs_results_array)); @@ -1711,11 +1716,6 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.3 (4 A) */ write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - /* Reset the read data timing registers to 1UI before calculating MaxRdLatency */ - for (internal_lane = 0; internal_lane < MAX_BYTE_LANES; internal_lane++) - current_read_dqs_delay[internal_lane] = 0x20; - write_dqs_read_data_timing_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - /* Calculate and program MaxRdLatency */ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); @@ -1769,6 +1769,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, /* Update hardware registers with final values */ write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); + TrainDQSRdWrPos_D_Fam15(pMCTstat, pDCTstat, dct, Receiver, Receiver + 2, lane, lane + 1); break; } prev = dqs_results_array[current_phy_phase_delay[lane]];

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: fix regression "always use mrccache"
by gerrit＠coreboot.org 29 Apr '16

29 Apr '16

the following patch was just integrated into master: commit 588ccaa9a7d94da4f5a5b3579eb9e3d06c9f4a51 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Apr 20 18:00:27 2016 +0200 nb/intel/sandybridge/raminit: fix regression "always use mrccache" Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/14439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/14439 for details. -gerrit

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14541 -gerrit commit e68616c9abf0b1955f7849f381f5414e5b347398 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 00:38:29 2016 -0500 nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h The existing Family 15h receiver enable training code stored temporary delay values in the wrong variables, leading to the requisite averaging of delays across nibbles not being applied. This in turn made x4 DIMMs less stable than they should have been. Store temporary nibble delay values in a dedicated array. Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 49 ++++++++++++++++------------ 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index c8c75e1..f0ee6af 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1194,6 +1194,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, uint16_t initial_seed; uint8_t train_both_nibbles; uint16_t current_total_delay[MAX_BYTE_LANES]; + uint16_t nibble0_current_total_delay[MAX_BYTE_LANES]; uint16_t dqs_ret_pass1_total_delay[MAX_BYTE_LANES]; uint16_t rank0_current_total_delay[MAX_BYTE_LANES]; uint16_t phase_recovery_delays[MAX_BYTE_LANES]; @@ -1419,19 +1420,11 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (phase_recovery_delays[lane] & 0x1f); current_total_delay[lane] |= ((seed_gross[lane] + ((phase_recovery_delays[lane] >> 5) & 0x1f) - seed_pre_gross[lane] + 1) << 5); - if (nibble == 0) { - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; - } else { + if (nibble == 1) { /* 2.10.5.8.2 (1) * Average the trained values of both nibbles on x4 DIMMs */ - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = (pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] + current_total_delay[lane]) / 2; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = (pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] + current_total_delay[lane]) / 2; + current_total_delay[lane] = (nibble0_current_total_delay[lane] + current_total_delay[lane]) / 2; } } @@ -1441,26 +1434,40 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - } - if (rank == 0) { - /* Back up the Rank 0 delays for later use */ - memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + if (nibble == 0) { + /* Back up the Nibble 0 delays for later use */ + memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + } } - if (rank == 1) { - /* 2.10.5.8.2 (8) - * Compute the average delay across both ranks and program the result into - * the DQS Receiver Enable delay registers - */ + if (_2Ranks) { + if (rank == 0) { + /* Back up the Rank 0 delays for later use */ + memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + } + if (rank == 1) { + /* 2.10.5.8.2 (8) + * Compute the average delay across both ranks and program the result into + * the DQS Receiver Enable delay registers + */ + for (lane = 0; lane < lane_count; lane++) { + current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; + if (lane == 8) + pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + else + pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + } + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + } + } else { + /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { - current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } }

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Patch set updated for coreboot: nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14542 -gerrit commit 216f57632172246188e34a0eea04c5d1556e4989 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 01:34:08 2016 -0500 nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4 Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index f0ee6af..77ae483 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1439,6 +1439,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Back up the Nibble 0 delays for later use */ memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); } + + /* Exit nibble training if current DIMM is not x4 */ + if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0) + break; } if (_2Ranks) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index c6ec905..ffc6fb2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -184,6 +184,10 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT } pDCTData->WLCriticalGrossDelayPrevPass = 0x0; + + /* Exit nibble training if current DIMM is not x4 */ + if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0) + break; } return 0;

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New patch to review for coreboot: nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14542 -gerrit commit 5ba38a02da2f18fe7360084014aa04a729d5b19a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 01:34:08 2016 -0500 nb/amd/mct_ddr3: Skip nibble training when current DIMM is not x4 Change-Id: I1f5b024606093dc81de3f3d69b7a43e20141b709 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 4 ++++ src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index f0ee6af..77ae483 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1439,6 +1439,10 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Back up the Nibble 0 delays for later use */ memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); } + + /* Exit nibble training if current DIMM is not x4 */ + if ((pDCTstat->Dimmx4Present & (1 << (dimm + Channel))) == 0) + break; } if (_2Ranks) { diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index c6ec905..ffc6fb2 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -184,6 +184,10 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT } pDCTData->WLCriticalGrossDelayPrevPass = 0x0; + + /* Exit nibble training if current DIMM is not x4 */ + if ((pDCTstat->Dimmx4Present & (1 << (dimm + dct))) == 0) + break; } return 0;

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Patch set updated for coreboot: nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14541 -gerrit commit 845756a0d27c3b1acc1078332e0e2e6649de8a05 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 00:38:29 2016 -0500 nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h The existing Family 51h receiver enable training code stored temporary delay values in the wrong variables, leading to the requisite averaging of delays across nibbles not being applied. This in turn made x4 DIMMs less stable than they should have been. Store temporary nibble delay values in a dedicated array. Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 49 ++++++++++++++++------------ 1 file changed, 28 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index c8c75e1..f0ee6af 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1194,6 +1194,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, uint16_t initial_seed; uint8_t train_both_nibbles; uint16_t current_total_delay[MAX_BYTE_LANES]; + uint16_t nibble0_current_total_delay[MAX_BYTE_LANES]; uint16_t dqs_ret_pass1_total_delay[MAX_BYTE_LANES]; uint16_t rank0_current_total_delay[MAX_BYTE_LANES]; uint16_t phase_recovery_delays[MAX_BYTE_LANES]; @@ -1419,19 +1420,11 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (phase_recovery_delays[lane] & 0x1f); current_total_delay[lane] |= ((seed_gross[lane] + ((phase_recovery_delays[lane] >> 5) & 0x1f) - seed_pre_gross[lane] + 1) << 5); - if (nibble == 0) { - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; - } else { + if (nibble == 1) { /* 2.10.5.8.2 (1) * Average the trained values of both nibbles on x4 DIMMs */ - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = (pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] + current_total_delay[lane]) / 2; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = (pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] + current_total_delay[lane]) / 2; + current_total_delay[lane] = (nibble0_current_total_delay[lane] + current_total_delay[lane]) / 2; } } @@ -1441,26 +1434,40 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - } - if (rank == 0) { - /* Back up the Rank 0 delays for later use */ - memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + if (nibble == 0) { + /* Back up the Nibble 0 delays for later use */ + memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + } } - if (rank == 1) { - /* 2.10.5.8.2 (8) - * Compute the average delay across both ranks and program the result into - * the DQS Receiver Enable delay registers - */ + if (_2Ranks) { + if (rank == 0) { + /* Back up the Rank 0 delays for later use */ + memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + } + if (rank == 1) { + /* 2.10.5.8.2 (8) + * Compute the average delay across both ranks and program the result into + * the DQS Receiver Enable delay registers + */ + for (lane = 0; lane < lane_count; lane++) { + current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; + if (lane == 8) + pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + else + pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + } + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + } + } else { + /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { - current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } }

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New patch to review for coreboot: nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h
by Timothy Pearson 29 Apr '16

29 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14541 -gerrit commit 52b2f2fe258558f2a8cd49d7ef4a54c3e7648bc6 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 29 00:38:29 2016 -0500 nb/amd/mct_ddr3: Fix x4 DIMM receiver enable training on Fam15h The existing Family 51h receiver enable training code stored temporary delay values in the wrong variables, leading to the requisite averaging of delays across nibbles not being applied. This in turn made x4 DIMMs less stable than they should have been. Store temporary nibble delay values in a dedicated array. Change-Id: Ic5da898af7d689db4110211f89b886ccdbb5f78f Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 47 +++++++++++++++------------- 1 file changed, 26 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index c8c75e1..90c612d 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -1194,6 +1194,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, uint16_t initial_seed; uint8_t train_both_nibbles; uint16_t current_total_delay[MAX_BYTE_LANES]; + uint16_t nibble0_current_total_delay[MAX_BYTE_LANES]; uint16_t dqs_ret_pass1_total_delay[MAX_BYTE_LANES]; uint16_t rank0_current_total_delay[MAX_BYTE_LANES]; uint16_t phase_recovery_delays[MAX_BYTE_LANES]; @@ -1419,19 +1420,11 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, for (lane = 0; lane < lane_count; lane++) { current_total_delay[lane] = (phase_recovery_delays[lane] & 0x1f); current_total_delay[lane] |= ((seed_gross[lane] + ((phase_recovery_delays[lane] >> 5) & 0x1f) - seed_pre_gross[lane] + 1) << 5); - if (nibble == 0) { - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; - } else { + if (nibble == 1) { /* 2.10.5.8.2 (1) * Average the trained values of both nibbles on x4 DIMMs */ - if (lane == 8) - pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = (pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] + current_total_delay[lane]) / 2; - else - pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = (pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] + current_total_delay[lane]) / 2; + current_total_delay[lane] = (nibble0_current_total_delay[lane] + current_total_delay[lane]) / 2; } } @@ -1441,26 +1434,38 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - } - if (rank == 0) { - /* Back up the Rank 0 delays for later use */ - memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + /* Back up the Nibble 0 delays for later use */ + memcpy(nibble0_current_total_delay, current_total_delay, sizeof(current_total_delay)); } - if (rank == 1) { - /* 2.10.5.8.2 (8) - * Compute the average delay across both ranks and program the result into - * the DQS Receiver Enable delay registers - */ + if (_2Ranks) { + if (rank == 0) { + /* Back up the Rank 0 delays for later use */ + memcpy(rank0_current_total_delay, current_total_delay, sizeof(current_total_delay)); + } + if (rank == 1) { + /* 2.10.5.8.2 (8) + * Compute the average delay across both ranks and program the result into + * the DQS Receiver Enable delay registers + */ + for (lane = 0; lane < lane_count; lane++) { + current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; + if (lane == 8) + pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; + else + pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; + } + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + } + } else { + /* Save the current delay for later use by other routines */ for (lane = 0; lane < lane_count; lane++) { - current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); } }

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Patch merged into coreboot/master: siemens/mc_bdx1: Add new mainboard.
by gerrit＠coreboot.org 29 Apr '16

29 Apr '16

the following patch was just integrated into master: commit fa6f861b574f27d5eb8df5e67dd8e2548779ecfc Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Apr 20 10:08:17 2016 +0200 siemens/mc_bdx1: Add new mainboard. Add new mainboard for MC BDX1 board which is based on Intel Camelback Mountain. This mainboard is an industry type board and has several Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC power supply and has its own form factor which does not match any standard. This commit adds the new mainboard and prepares the Kconfig environment so that this board can be selected and generated. Although the generated image can boot into Linux and DOS, not all functions are implemented yet. Forthcoming commits will add more functionality. Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/14516 Tested-by: build bot (Jenkins) Reviewed-by: York Yang <york.yang(a)intel.com> See https://review.coreboot.org/14516 for details. -gerrit

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