coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: fix regression "always use mrccache"
by Patrick Rudolph 28 Apr '16

28 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14439 -gerrit commit d9203f040b50aecd39f16fd2ddaa3e8c019b708a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Wed Apr 20 18:00:27 2016 +0200 nb/intel/sandybridge/raminit: fix regression "always use mrccache" Fix regression introduced by: Ib48fe8380446846df17d37b22968f7d4fd6b9b13 Don't run channel_test on S3 resume as it overrides memory that might be in use. Fixes MCE events reported by the GNU/Linux kernel that low memory has been modified. Reset on failed s3 resume. Change-Id: Ibadea286619c7906225f86a93aaa0b4caf26cabe Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 042898d..3c606e1 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -4038,7 +4038,7 @@ static void restore_timings(ramctr_timing * ctrl) } static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, - int me_uma_size) + int s3_resume, int me_uma_size) { int err; @@ -4148,9 +4148,11 @@ static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, write_controller_mr(ctrl); - err = channel_test(ctrl); - if (err) - return err; + if (!s3_resume) { + err = channel_test(ctrl); + if (err) + return err; + } return 0; } @@ -4228,9 +4230,14 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, printk(BIOS_DEBUG, "Trying stored timings.\n"); memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); - err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); if (err) { - /* no need to erase bad mrc cache here, it gets overritten on + if (s3resume) { + /* Failed S3 resume, reset to come up cleanly */ + outb(0x6, 0xcf9); + halt(); + } + /* no need to erase bad mrc cache here, it gets overwritten on * successful boot. */ printk(BIOS_ERR, "Stored timings are invalid !\n"); fast_boot = 0; @@ -4243,7 +4250,7 @@ void init_dram_ddr3(spd_raw_data *spds, int mobile, int min_tck, /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &ctrl); - err = try_init_dram_ddr3(&ctrl, fast_boot, me_uma_size); + err = try_init_dram_ddr3(&ctrl, fast_boot, s3resume, me_uma_size); } if (err) die("raminit failed");

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Patch set updated for coreboot: console/serialice: Add SerialICE
by Patrick Rudolph 28 Apr '16

28 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit e8ce8f4a3452c8a388c98612f619d71b3d4b28a0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520. Needs tests: * Ramstage * Serial cable * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/Kconfig | 32 +++ src/console/Makefile.inc | 2 + src/console/init.c | 3 + src/console/serialice.c | 440 ++++++++++++++++++++++++++++++++++++++++ src/include/console/serialice.h | 28 +++ src/include/console/uart.h | 2 + src/include/console/usb.h | 2 + 7 files changed, 509 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index f9bd661..7d739c6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,38 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + default n + depends on ARCH_X86 + depends on CONSOLE_SERIAL || CONSOLE_USB + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +if DEBUG_SERIALICE + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + depends on CONSOLE_SERIAL || USBDEBUG_IN_ROMSTAGE + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + +endif endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..e3015fe 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..66b751c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,8 @@ void console_init(void) console_hw_init(); + serialice_main(); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..035cc03 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,440 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/usb.h> +#include <console/uart.h> +#include <console/serialice.h> +#include <arch/io.h> +#include "serialice_priv.h" + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + __usb_tx_flush(); + __uart_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + __usb_tx_byte(byte); + __uart_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + val = __usb_rx_byte(); + if (val) { +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + + val = __uart_rx_byte(); + if (val) { +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +void serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } +} diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..8a28558 --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,28 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#if (ENV_RAMSTAGE && CONFIG_DEBUG_SERIALICE_RAMSTAGE) || \ + (ENV_ROMSTAGE && CONFIG_DEBUG_SERIALICE_ROMSTAGE) +void serialice_main(void); +#else +static inline void serialice_main(void) { } +#endif + +#endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..278e0e3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -59,10 +59,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} +static inline u8 __uart_rx_byte(void) { return 0; } #endif #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..2f7da49 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,10 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} +static inline u8 __usb_rx_byte(void) { return 0; } #endif /* */

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Patch set updated for coreboot: console/serialice: Add SerialICE
by Patrick Rudolph 28 Apr '16

28 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 092f7b4171501d5200b2aed66a29ee9cc4117f56 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520. Needs tests: * Ramstage * Serial cable * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/Kconfig | 32 +++ src/console/Makefile.inc | 2 + src/console/init.c | 3 + src/console/serialice.c | 443 ++++++++++++++++++++++++++++++++++++++++ src/include/console/serialice.h | 28 +++ src/include/console/uart.h | 2 + src/include/console/usb.h | 2 + 7 files changed, 512 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index f9bd661..7d739c6 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,38 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + default n + depends on ARCH_X86 + depends on CONSOLE_SERIAL || CONSOLE_USB + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +if DEBUG_SERIALICE + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + depends on CONSOLE_SERIAL || USBDEBUG_IN_ROMSTAGE + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + +endif endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..e3015fe 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(CONFIG_DEBUG_SERIALICE_RAMSTAGE) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(CONFIG_DEBUG_SERIALICE_ROMSTAGE) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..66b751c 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,8 @@ void console_init(void) console_hw_init(); + serialice_main(); + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..6981101 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,443 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/usb.h> +#include <console/uart.h> +#include <console/serialice.h> +#include <arch/io.h> +#include "serialice_priv.h" + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_flush(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_byte(byte); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + if (IS_ENABLED(CONFIG_CONSOLE_USB)) { + val = __usb_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + val = __uart_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +void serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } +} diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..8a28558 --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,28 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#if (ENV_RAMSTAGE && CONFIG_DEBUG_SERIALICE_RAMSTAGE) || \ + (ENV_ROMSTAGE && CONFIG_DEBUG_SERIALICE_ROMSTAGE) +void serialice_main(void); +#else +static inline void serialice_main(void) { } +#endif + +#endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..278e0e3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -59,10 +59,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} +static inline u8 __uart_rx_byte(void) { return 0; } #endif #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..2f7da49 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,10 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} +static inline u8 __usb_rx_byte(void) { return 0; } #endif /* */

1 0

New patch to review for coreboot: fsp_baytrail: Fix missing "$" when using Kconfig switch
by Werner Zeh 28 Apr '16

28 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14532 -gerrit commit 7f0fa67ad09b043832829a6fbf5918117f4a971c Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Apr 28 09:39:34 2016 +0200 fsp_baytrail: Fix missing "$" when using Kconfig switch To include gfx.c in ramstage, there is a Kconfig option (FSP_BAYTRAIL_GFX_INIT) which can be activated on demand. Unfortunately, the "$"-character is missing so that this switch is never active. Change-Id: I0c3c562b3caca53ac6510c2c5dc30e7f606f5ad0 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/soc/intel/fsp_baytrail/Makefile.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/fsp_baytrail/Makefile.inc b/src/soc/intel/fsp_baytrail/Makefile.inc index 92b5f98..6e16b42 100644 --- a/src/soc/intel/fsp_baytrail/Makefile.inc +++ b/src/soc/intel/fsp_baytrail/Makefile.inc @@ -57,7 +57,7 @@ ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smm.c ramstage-y += placeholders.c ramstage-y += i2c.c -ramstage-(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c +ramstage-$(CONFIG_FSP_BAYTRAIL_GFX_INIT) += gfx.c CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/include CPPFLAGS_common += -I$(src)/soc/intel/fsp_baytrail/fsp

1 0

Patch set updated for coreboot: siemens/mc_bdx1: Add new mainboard.
by Werner Zeh 28 Apr '16

28 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14516 -gerrit commit 72cc09f2b283e90ebef275c14efe6eedb35ad93e Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Apr 20 10:08:17 2016 +0200 siemens/mc_bdx1: Add new mainboard. Add new mainboard for MC BDX1 board which is based on Intel Camelback Mountain. This mainboard is an industry type board and has several Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC power supply and has its own form factor which does not match any standard. This commit adds the new mainboard and prepares the Kconfig environment so that this board can be selected and generated. Although the generated image can boot into Linux and DOS, not all functions are implemented yet. Forthcoming commits will add more functionality. Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/Kconfig | 52 ++++ src/mainboard/siemens/mc_bdx1/Kconfig.name | 2 + src/mainboard/siemens/mc_bdx1/Makefile.inc | 16 ++ src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl | 20 ++ src/mainboard/siemens/mc_bdx1/acpi/platform.asl | 56 +++++ src/mainboard/siemens/mc_bdx1/acpi_tables.c | 43 ++++ src/mainboard/siemens/mc_bdx1/board_info.txt | 5 + src/mainboard/siemens/mc_bdx1/cmos.layout | 128 ++++++++++ src/mainboard/siemens/mc_bdx1/devicetree.cb | 15 ++ src/mainboard/siemens/mc_bdx1/dsdt.asl | 293 +++++++++++++++++++++++ src/mainboard/siemens/mc_bdx1/fadt.c | 29 +++ src/mainboard/siemens/mc_bdx1/irqroute.c | 18 ++ src/mainboard/siemens/mc_bdx1/irqroute.h | 48 ++++ src/mainboard/siemens/mc_bdx1/mainboard.c | 44 ++++ src/mainboard/siemens/mc_bdx1/romstage.c | 45 ++++ 15 files changed, 814 insertions(+) diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig new file mode 100644 index 0000000..e33b14a --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -0,0 +1,52 @@ +if BOARD_SIEMENS_MC_BDX1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_FSP_BROADWELL_DE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select TSC_MONOTONIC_TIMER + select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT + select CBFS_AUTOGEN_ATTRIBUTES + +config MAINBOARD_DIR + string + default "siemens/mc_bdx1" + +config MAINBOARD_PART_NUMBER + string + default "MC BDX1" + +config IRQ_SLOT_COUNT + int + default 18 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x1000000 + +config CBFS_SIZE + hex + default 0x00D00000 + +config VIRTUAL_ROM_SIZE + hex + default 0x1000000 + +config CONSOLE_POST + bool + default y + +config INTEGRATED_UART + bool + default n + +config DRIVERS_UART_8250IO + def_bool y + +config FSP_PACKAGE_DEFAULT + bool "Configure defaults for the Intel FSP package" + default n + +endif # BOARD_SIEMENS_MC_BDX1 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig.name b/src/mainboard/siemens/mc_bdx1/Kconfig.name new file mode 100644 index 0000000..b37cee3 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIEMENS_MC_BDX1 + bool "MC BDX1" diff --git a/src/mainboard/siemens/mc_bdx1/Makefile.inc b/src/mainboard/siemens/mc_bdx1/Makefile.inc new file mode 100644 index 0000000..e7de261 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += irqroute.c \ No newline at end of file diff --git a/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl b/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl new file mode 100644 index 0000000..62944ef --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/siemens/mc_bdx1/acpi/platform.asl b/src/mainboard/siemens/mc_bdx1/acpi/platform.asl new file mode 100644 index 0000000..7ffae2e --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/acpi/platform.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/siemens/mc_bdx1/acpi_tables.c b/src/mainboard/siemens/mc_bdx1/acpi_tables.c new file mode 100644 index 0000000..0197def --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/acpi_tables.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/iomap.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_madt(unsigned long current) +{ + u32 i; + + current = acpi_create_madt_lapics(current); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, + IOXAPIC1_BASE_ADDRESS, 0); + set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, + IOXAPIC2_BASE_ADDRESS, 24); + set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); + + current = acpi_madt_irq_overrides(current); + + for (i = 0; i < 16; i++) + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); + + return current; +} diff --git a/src/mainboard/siemens/mc_bdx1/board_info.txt b/src/mainboard/siemens/mc_bdx1/board_info.txt new file mode 100644 index 0000000..15b66c1 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/board_info.txt @@ -0,0 +1,5 @@ +Board name: MC BDX1 +Category: misc +ROM protocol: SPI +ROM socketed: no +Release year: 2016 diff --git a/src/mainboard/siemens/mc_bdx1/cmos.layout b/src/mainboard/siemens/mc_bdx1/cmos.layout new file mode 100644 index 0000000..9ff9d1f --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/cmos.layout @@ -0,0 +1,128 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb new file mode 100644 index 0000000..30d99c2 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/devicetree.cb @@ -0,0 +1,15 @@ +chip soc/intel/fsp_broadwell_de + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 14.0 on end # xHCI Controller + device pci 19.0 on end # Gigabit LAN Controller + device pci 1d.0 on end # EHCI Controller + device pci 1f.0 on end # LPC Bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus Controller + device pci 1f.5 on end # SATA Controller + end +end diff --git a/src/mainboard/siemens/mc_bdx1/dsdt.asl b/src/mainboard/siemens/mc_bdx1/dsdt.asl new file mode 100644 index 0000000..9db2693 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/dsdt.asl @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include <acpi/southcluster.asl> + #include <acpi/pcie1.asl> + } + + Name (PRUN, Package() { + Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + }) + + Name (ARUN, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + + Package() { 0x0013FFFF, 0, 0, 16 }, + Package() { 0x0013FFFF, 1, 0, 17 }, + Package() { 0x0013FFFF, 2, 0, 18 }, + Package() { 0x0013FFFF, 3, 0, 19 }, + + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + + Package() { 0x0018FFFF, 0, 0, 16 }, + Package() { 0x0018FFFF, 1, 0, 17 }, + Package() { 0x0018FFFF, 2, 0, 18 }, + Package() { 0x0018FFFF, 3, 0, 19 }, + + Package() { 0x0019FFFF, 0, 0, 16 }, + Package() { 0x0019FFFF, 1, 0, 17 }, + Package() { 0x0019FFFF, 2, 0, 18 }, + Package() { 0x0019FFFF, 3, 0, 19 }, + + Package() { 0x001CFFFF, 0, 0, 16 }, + Package() { 0x001CFFFF, 1, 0, 17 }, + Package() { 0x001CFFFF, 2, 0, 18 }, + Package() { 0x001CFFFF, 3, 0, 19 }, + + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (PICM, Zero)) + { + Return (PRUN) + } + + Return (ARUN) + } + } + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/siemens/mc_bdx1/fadt.c b/src/mainboard/siemens/mc_bdx1/fadt.c new file mode 100644 index 0000000..b274531 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/fadt.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt, facs, dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.c b/src/mainboard/siemens/mc_bdx1/irqroute.c new file mode 100644 index 0000000..9b09f4b --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/irqroute.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../mc_bdx1/irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.h b/src/mainboard/siemens/mc_bdx1/irqroute.h new file mode 100644 index 0000000..c3911be --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/irqroute.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/irq.h> +#include <soc/pci_devs.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * ACPI/SCI: 9 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 5), \ + PIRQ_PIC(B, 6), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c new file mode 100644 index 0000000..58da036 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/siemens/mc_bdx1/romstage.c b/src/mainboard/siemens/mc_bdx1/romstage.c new file mode 100644 index 0000000..cf52c01 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/romstage.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <drivers/intel/fsp1_0/fsp_util.h> + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry(void) +{ + +} + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ +void late_mainboard_romstage_entry(void) +{ + +} + +/** + * /brief customize fsp parameters here if needed + */ +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + +}

1 0

Patch merged into coreboot/master: drivers/intel/i210: Use uint8_t and friends instead of u8
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit 608d991cf8032bbacf67961a15905621ec2034f3 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Apr 26 09:26:14 2016 +0200 drivers/intel/i210: Use uint8_t and friends instead of u8 Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/14515 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14515 for details. -gerrit

1 0

Patch set updated for coreboot: drivers/intel/i210: Use uint8_t and friends instead of u8
by Werner Zeh 28 Apr '16

28 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14515 -gerrit commit 7363bce113e5518acca9220650eaea2e99148b47 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Apr 26 09:26:14 2016 +0200 drivers/intel/i210: Use uint8_t and friends instead of u8 Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/i210/i210.c | 67 ++++++++++++++++--------------- src/mainboard/siemens/mc_tcu3/mainboard.c | 5 ++- src/vendorcode/siemens/hwilib/hwilib.h | 3 +- 3 files changed, 40 insertions(+), 35 deletions(-) diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index e821d48..c5e0c4e 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG. + * Copyright (C) 2014-2016 Siemens AG. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,13 +25,14 @@ /* We need one function we can call to get a MAC address to use */ /* This function can be coded somewhere else but must exist. */ -extern enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +extern enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]); /* This is a private function to wait for a bit mask in a given register */ /* To avoid endless loops, a time-out is implemented here. */ -static int wait_done(u32* reg, u32 mask) +static int wait_done(uint32_t* reg, uint32_t mask) { - u32 timeout = I210_POLL_TIMEOUT_US; + uint32_t timeout = I210_POLL_TIMEOUT_US; while (!(*reg & mask)) { udelay(1); @@ -50,17 +51,18 @@ static int wait_done(u32* reg, u32 mask) * @param *buffer Pointer to the buffer where to store read data * @return void I210_NO_ERROR or an error code */ -static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +static uint32_t read_flash(struct device *dev, uint32_t address, + uint32_t count, uint16_t *buffer) { - u32 bar; - u32 *eeprd; - u32 i; + uint32_t bar; + uint32_t *eeprd; + uint32_t i; /* Get the BAR to memory mapped space*/ bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eeprd = (u32*)(bar + I210_REG_EEREAD); + eeprd = (uint32_t*)(bar + I210_REG_EEREAD); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eeprd, I210_DONE)) return I210_NOT_READY; @@ -84,10 +86,10 @@ static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) * @param *checksum Pointer to the buffer where to store the checksum * @return void I210_NO_ERROR or an error code */ -static u32 compute_checksum(struct device *dev, u16 *checksum) +static uint32_t compute_checksum(struct device *dev, uint16_t *checksum) { - u16 eep_data[0x40]; - u32 i; + uint16_t eep_data[0x40]; + uint32_t i; /* First read back data to compute the checksum for */ if (read_flash(dev, 0, 0x3f, eep_data)) @@ -111,20 +113,21 @@ static u32 compute_checksum(struct device *dev, u16 *checksum) * @param *buffer Pointer to the buffer where data to write is stored in * @return void I210_NO_ERROR or an error code */ -static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +static uint32_t write_flash(struct device *dev, uint32_t address, + uint32_t count, uint16_t *buffer) { - u32 bar; - u32 *eepwr; - u32 *eectrl; - u16 checksum; - u32 i; + uint32_t bar; + uint32_t *eepwr; + uint32_t *eectrl; + uint16_t checksum; + uint32_t i; /* Get the BAR to memory mapped space */ bar = pci_read_config32(dev, 0x10); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eepwr = (u32*)(bar + I210_REG_EEWRITE); - eectrl = (u32*)(bar + I210_REG_EECTRL); + eepwr = (uint32_t*)(bar + I210_REG_EEWRITE); + eectrl = (uint32_t*)(bar + I210_REG_EECTRL); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eepwr, I210_DONE)) return I210_NOT_READY; @@ -145,8 +148,8 @@ static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) if (wait_done(eepwr, I210_DONE)) return I210_WRITE_ERROR; /* Up to now, desired data was written into shadowed RAM. We now need */ - /* to perform a flash cycle to bring the shadowed RAM into flash memory. */ - /* To start a flash cycle we need to set FLUPD-bit and wait for FLDONE. */ + /* to perform a flash cycle to bring the shadowed RAM into flash. */ + /* To start a flash cycle we need to set FLUPD and wait for FLDONE. */ *eectrl = *eectrl | I210_FLUPD; if (wait_done(eectrl, I210_FLUDONE)) return I210_FLASH_UPDATE_ERROR; @@ -158,16 +161,16 @@ static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) * @param *MACAdr Pointer to the buffer where to store read MAC address * @return void I210_NO_ERROR or an error code */ -static u32 read_mac_adr(struct device *dev, u8 *mac_adr) +static uint32_t read_mac_adr(struct device *dev, uint8_t *mac_adr) { - u16 adr[3]; + uint16_t adr[3]; if (!dev || !mac_adr) return I210_INVALID_PARAM; if (read_flash(dev, 0, 3, adr)) return I210_READ_ERROR; - /* Copy the address into destination. This is done because of */ - /* possible not matching alignment for destination to u16 boundary. */ - memcpy(mac_adr, (u8*)adr, 6); + /* Copy the address into destination. This is done because of possible */ + /* not matching alignment for destination to uint16_t boundary. */ + memcpy(mac_adr, (uint8_t*)adr, 6); return I210_SUCCESS; } @@ -176,13 +179,13 @@ static u32 read_mac_adr(struct device *dev, u8 *mac_adr) * @param *MACAdr Pointer to the buffer where the desired MAC address is * @return void I210_NO_ERROR or an error code */ -static u32 write_mac_adr(struct device *dev, u8 *mac_adr) +static uint32_t write_mac_adr(struct device *dev, uint8_t *mac_adr) { - u16 adr[3]; + uint16_t adr[3]; if (!dev || !mac_adr) return I210_INVALID_PARAM; /* Copy desired address into a local buffer to avoid alignment issues */ - memcpy((u8*)adr, mac_adr, 6); + memcpy((uint8_t*)adr, mac_adr, 6); return write_flash(dev, 0, 3, adr); } @@ -194,8 +197,8 @@ static u32 write_mac_adr(struct device *dev, u8 *mac_adr) */ static void init(struct device *dev) { - u8 cur_adr[6]; - u8 adr_to_set[6]; + uint8_t cur_adr[6]; + uint8_t adr_to_set[6]; enum cb_err status; /*Check first whether there is a valid MAC address available */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index e9c29a0..009c34d 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -39,10 +39,11 @@ * @param mac buffer where to store the MAC address * @return cb_err CB_ERR or CB_SUCCESS */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) +enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]) { uint8_t mac_adr[6]; - u32 i; + uint32_t i; /* Open main hwinfo block */ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index fb0798b..c66a99c 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -70,5 +70,6 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename); uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *data, uint32_t maxlen); /* This functions needs to be implemented for every mainboard that uses i210. */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]); #endif /* SIEMENS_HWI_LIB_H_ */

1 0

Patch merged into coreboot/master: mc_tcu3: Switch to hwilib instead of own hwinfo implementation
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit bf13d3f567795324a587af745c71e58ce680ab3f Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Apr 25 12:24:17 2016 +0200 mc_tcu3: Switch to hwilib instead of own hwinfo implementation Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo instead of having mainboard specific hwinfo code. This patch does not change the functional behavior in any way. Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/14506 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14506 for details. -gerrit

1 0

Patch merged into coreboot/master: vendorcode/siemens: Add hwilib for Siemens specific info struct
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit 223498fa16c8de69b2649c669d2fba43ecf364d8 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Apr 22 14:14:45 2016 +0200 vendorcode/siemens: Add hwilib for Siemens specific info struct Add a library which unifies access to Siemens specific hardware information data. This library is meant to be used with Siemens platforms and can be selected in Kconfig. The needed source of information has to be present in cbfs. This lib can be used in romstage and ramstage. Change-Id: I2c6e003b0c123b4cf6a84906c2b133b8c38c8b1a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/14505 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14505 for details. -gerrit

1 0

Patch set updated for coreboot: drivers/intel/i210: Use uint8_t and friends instead of u8
by Werner Zeh 28 Apr '16

28 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14515 -gerrit commit a4361b538cab5461b963b355e66addba327e1a5c Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Apr 26 09:26:14 2016 +0200 drivers/intel/i210: Use uint8_t and friends instead of u8 Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/i210/i210.c | 67 ++++++++++++++++--------------- src/mainboard/siemens/mc_tcu3/mainboard.c | 5 ++- src/vendorcode/siemens/hwilib/hwilib.h | 3 +- 3 files changed, 40 insertions(+), 35 deletions(-) diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index e821d48..c5e0c4e 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG. + * Copyright (C) 2014-2016 Siemens AG. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,13 +25,14 @@ /* We need one function we can call to get a MAC address to use */ /* This function can be coded somewhere else but must exist. */ -extern enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +extern enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]); /* This is a private function to wait for a bit mask in a given register */ /* To avoid endless loops, a time-out is implemented here. */ -static int wait_done(u32* reg, u32 mask) +static int wait_done(uint32_t* reg, uint32_t mask) { - u32 timeout = I210_POLL_TIMEOUT_US; + uint32_t timeout = I210_POLL_TIMEOUT_US; while (!(*reg & mask)) { udelay(1); @@ -50,17 +51,18 @@ static int wait_done(u32* reg, u32 mask) * @param *buffer Pointer to the buffer where to store read data * @return void I210_NO_ERROR or an error code */ -static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +static uint32_t read_flash(struct device *dev, uint32_t address, + uint32_t count, uint16_t *buffer) { - u32 bar; - u32 *eeprd; - u32 i; + uint32_t bar; + uint32_t *eeprd; + uint32_t i; /* Get the BAR to memory mapped space*/ bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eeprd = (u32*)(bar + I210_REG_EEREAD); + eeprd = (uint32_t*)(bar + I210_REG_EEREAD); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eeprd, I210_DONE)) return I210_NOT_READY; @@ -84,10 +86,10 @@ static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) * @param *checksum Pointer to the buffer where to store the checksum * @return void I210_NO_ERROR or an error code */ -static u32 compute_checksum(struct device *dev, u16 *checksum) +static uint32_t compute_checksum(struct device *dev, uint16_t *checksum) { - u16 eep_data[0x40]; - u32 i; + uint16_t eep_data[0x40]; + uint32_t i; /* First read back data to compute the checksum for */ if (read_flash(dev, 0, 0x3f, eep_data)) @@ -111,20 +113,21 @@ static u32 compute_checksum(struct device *dev, u16 *checksum) * @param *buffer Pointer to the buffer where data to write is stored in * @return void I210_NO_ERROR or an error code */ -static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +static uint32_t write_flash(struct device *dev, uint32_t address, + uint32_t count, uint16_t *buffer) { - u32 bar; - u32 *eepwr; - u32 *eectrl; - u16 checksum; - u32 i; + uint32_t bar; + uint32_t *eepwr; + uint32_t *eectrl; + uint16_t checksum; + uint32_t i; /* Get the BAR to memory mapped space */ bar = pci_read_config32(dev, 0x10); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eepwr = (u32*)(bar + I210_REG_EEWRITE); - eectrl = (u32*)(bar + I210_REG_EECTRL); + eepwr = (uint32_t*)(bar + I210_REG_EEWRITE); + eectrl = (uint32_t*)(bar + I210_REG_EECTRL); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eepwr, I210_DONE)) return I210_NOT_READY; @@ -145,8 +148,8 @@ static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) if (wait_done(eepwr, I210_DONE)) return I210_WRITE_ERROR; /* Up to now, desired data was written into shadowed RAM. We now need */ - /* to perform a flash cycle to bring the shadowed RAM into flash memory. */ - /* To start a flash cycle we need to set FLUPD-bit and wait for FLDONE. */ + /* to perform a flash cycle to bring the shadowed RAM into flash. */ + /* To start a flash cycle we need to set FLUPD and wait for FLDONE. */ *eectrl = *eectrl | I210_FLUPD; if (wait_done(eectrl, I210_FLUDONE)) return I210_FLASH_UPDATE_ERROR; @@ -158,16 +161,16 @@ static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) * @param *MACAdr Pointer to the buffer where to store read MAC address * @return void I210_NO_ERROR or an error code */ -static u32 read_mac_adr(struct device *dev, u8 *mac_adr) +static uint32_t read_mac_adr(struct device *dev, uint8_t *mac_adr) { - u16 adr[3]; + uint16_t adr[3]; if (!dev || !mac_adr) return I210_INVALID_PARAM; if (read_flash(dev, 0, 3, adr)) return I210_READ_ERROR; - /* Copy the address into destination. This is done because of */ - /* possible not matching alignment for destination to u16 boundary. */ - memcpy(mac_adr, (u8*)adr, 6); + /* Copy the address into destination. This is done because of possible */ + /* not matching alignment for destination to uint16_t boundary. */ + memcpy(mac_adr, (uint8_t*)adr, 6); return I210_SUCCESS; } @@ -176,13 +179,13 @@ static u32 read_mac_adr(struct device *dev, u8 *mac_adr) * @param *MACAdr Pointer to the buffer where the desired MAC address is * @return void I210_NO_ERROR or an error code */ -static u32 write_mac_adr(struct device *dev, u8 *mac_adr) +static uint32_t write_mac_adr(struct device *dev, uint8_t *mac_adr) { - u16 adr[3]; + uint16_t adr[3]; if (!dev || !mac_adr) return I210_INVALID_PARAM; /* Copy desired address into a local buffer to avoid alignment issues */ - memcpy((u8*)adr, mac_adr, 6); + memcpy((uint8_t*)adr, mac_adr, 6); return write_flash(dev, 0, 3, adr); } @@ -194,8 +197,8 @@ static u32 write_mac_adr(struct device *dev, u8 *mac_adr) */ static void init(struct device *dev) { - u8 cur_adr[6]; - u8 adr_to_set[6]; + uint8_t cur_adr[6]; + uint8_t adr_to_set[6]; enum cb_err status; /*Check first whether there is a valid MAC address available */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index e9c29a0..009c34d 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -39,10 +39,11 @@ * @param mac buffer where to store the MAC address * @return cb_err CB_ERR or CB_SUCCESS */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) +enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]) { uint8_t mac_adr[6]; - u32 i; + uint32_t i; /* Open main hwinfo block */ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index fb0798b..c66a99c 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -70,5 +70,6 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename); uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *data, uint32_t maxlen); /* This functions needs to be implemented for every mainboard that uses i210. */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]); #endif /* SIEMENS_HWI_LIB_H_ */

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coreboot-gerrit April 2016