coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Add GPIO devices
by Aaron Durbin 28 Apr '16

28 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14478 -gerrit commit a7994a87523dfb70bcae709788e3091071a1b455 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Mon Feb 1 16:41:59 2016 -0800 soc/intel/apollolake: Add GPIO devices Add GPIO controller in ACPI device description. GPIO controller driver is probed in kernel and all the pins in the banks are showing respective values. Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 144 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/soc_int.asl | 1 + src/soc/intel/apollolake/acpi/southbridge.asl | 3 + 3 files changed, 148 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl new file mode 100644 index 0000000..4bf0442 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> + +scope (\_SB) { + + Device (GPO0) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTH, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO1) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO2) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_WEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO3) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_SOUTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } +} diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 7db23ee..c7259d0 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -24,6 +24,7 @@ #define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ #define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ #define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 16 #define NPK_INT 16 #define PIRQA_INT 16 #define PIRQB_INT 17 diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 46d7013..0584439 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,3 +20,6 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl"

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Patch set updated for coreboot: soc/intel/apollolake: Add cache for BIOS ROM
by Aaron Durbin 28 Apr '16

28 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14480 -gerrit commit 88270210003a380a9be37b0387b111ad3a37c94d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sat Apr 23 12:31:01 2016 -0700 soc/intel/apollolake: Add cache for BIOS ROM Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/cpu/x86/mtrr/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/bootblock.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 9b7207b..e6e9c50 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,2 +1,3 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c +bootblock-y += earlymtrr.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index bb3b9c1..2456455 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -16,7 +16,9 @@ */ #include <arch/cpu.h> #include <bootblock_common.h> +#include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <lib.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/gpio.h> @@ -76,6 +78,24 @@ void asmlinkage bootblock_c_entry(void) main(); } +static void cache_bios_region(void) +{ + int mtrr; + uint32_t rom_size, alignment; + + mtrr = get_free_var_mtrr(); + + if (mtrr==-1) + return; + + /* Only the IFD BIOS region is memory mapped (at top of 4G) */ + rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START; + /* Round to power of two */ + alignment = 1 << (log2_ceil(rom_size)); + rom_size = ALIGN_UP(rom_size, alignment); + set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); +} + void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ @@ -88,4 +108,5 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) early_lpc_enable(); + cache_bios_region(); }

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Patch merged into coreboot/master: soc/intel/apollolake: Enable LPC bus interface
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit e976bd44692d2adb320a1256f1b6bfaa6469108a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14469 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14469 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Enable LPC bus interface
by Aaron Durbin 28 Apr '16

28 Apr '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14469 -gerrit commit 18baf66fb8aa4195d8da86e5cc932852718906b0 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 5 11:27:44 2016 -0800 soc/intel/apollolake: Enable LPC bus interface This adds early LPC setup in bootblock (for Chrome EC) as well as late (ramstage) IO decode/sirq enable. Change-Id: Ic270e66dbf07240229d4783f80e2ec02007c36c2 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/bootblock/bootblock.c | 29 +++++++++++++++++ src/soc/intel/apollolake/chip.h | 9 ++++++ src/soc/intel/apollolake/include/soc/lpc.h | 40 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/pci_devs.h | 3 ++ src/soc/intel/apollolake/lpc.c | 43 ++++++++++++++++++++++++- 5 files changed, 123 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index be07776..bb3b9c1 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -20,6 +20,7 @@ #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/gpio.h> +#include <soc/lpc.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/uart.h> @@ -28,12 +29,36 @@ static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; +static const struct pad_config lpc_gpio_configs[] = { + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, UP_20K, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, UP_20K, DEEP, NF1) +}; + static void tpm_enable(void) { /* Configure gpios */ gpio_configure_pads(tpm_spi_configs, ARRAY_SIZE(tpm_spi_configs)); } +static void early_lpc_enable(void) +{ + /* Enable requested fixed IO decode ranges */ + pci_write_config16(LPC_DEV, LPC_EN, LPC_EN_MC1 | LPC_EN_KB | LPC_EN_LGAME); + + /* Enable generic IO decode ranges for 0x800-0x9ff */ + /* FIXME: remove range hardcoding and/or calculate based on EC definitions */ + pci_write_config32(LPC_DEV, LPC_GEN1_DEC, ((0xff & ~3 ) << 8) | 0x800 | 1); + pci_write_config32(LPC_DEV, LPC_GEN2_DEC, ((0xff & ~3 ) << 8) | 0x900 | 1); + + /* GPIO pins need to be configured to specific native function */ + gpio_configure_pads(lpc_gpio_configs, ARRAY_SIZE(lpc_gpio_configs)); +} + void asmlinkage bootblock_c_entry(void) { device_t dev = NB_DEV_ROOT; @@ -59,4 +84,8 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_LPC_TPM)) tpm_enable(); + + if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) + early_lpc_enable(); + } diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 9d2bc46..32d93de 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -32,6 +32,15 @@ struct soc_intel_apollolake_config { uint8_t pcie_rp3_clkreq_pin; uint8_t pcie_rp4_clkreq_pin; uint8_t pcie_rp5_clkreq_pin; + + /* Generic IO decode ranges */ + uint32_t gen1_dec; + uint32_t gen2_dec; + uint32_t gen3_dec; + uint32_t gen4_dec; + + /* LPC port ranges */ + uint16_t lpc_dec; }; #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/lpc.h b/src/soc/intel/apollolake/include/soc/lpc.h new file mode 100644 index 0000000..2125f4a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/lpc.h @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_LPC_H +#define _SOC_APOLLOLAKE_LPC_H + +/* PCI Configuration Space (D31:F0): LPC */ +#define SERIRQ_CNTL 0x64 /* Serial IRQ Control Register */ +#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */ +#define LPC_EN 0x82 /* LPC IF Enables Register */ +#define LPC_EN_COMA (1 << 0) /* COM port A */ +#define LPC_EN_COMB (1 << 1) /* COM port B */ +#define LPC_EN_PARP (1 << 2) /* Parallel port */ +#define LPC_EN_FLP (1 << 3) /* Floppy */ +#define LPC_EN_LGAME (1 << 8) /* Low Gameport, 0x200-0x207 */ +#define LPC_EN_HGAME (1 << 9) /* High Gameport, 0x208-0x20f */ +#define LPC_EN_KB (1 << 10) /* Keyboard, 0x60, 0x64 */ +#define LPC_EN_MC1 (1 << 11) /* Microcontroller #1, 0x62, 0x66 */ +#define LPC_EN_MC2 (1 << 13) /* Microcontroller #2, 0x4e, 0x4f */ +#define LPC_EN_SIO (1 << 12) /* Super IO, 0x2e, 0x2f */ + +#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */ +#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */ +#define LPC_GEN3_DEC 0x8C /* LPC IF Generic Decode Range 3 */ +#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ + +#endif //_SOC_APOLLOLAKE_LPC_H diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index 7b8caaf..ae80a04 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -48,8 +48,11 @@ #define LPSS_DEV_UART2 _LPSS_PCI_DEV(UART, 2) #define LPSS_DEV_UART3 _LPSS_PCI_DEV(UART, 3) +#define LPC_SLOT 0x1f + #define P2SB_DEV PCI_DEV(0, 0xd, 0) #define PMC_DEV PCI_DEV(0, 0xd, 1) #define SPI_DEV PCI_DEV(0, 0xd, 2) +#define LPC_DEV PCI_DEV(0, LPC_SLOT, 0) #endif diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 902ada2..6e366e0 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2015-2016 Intel Corp. * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) * * This program is free software; you can redistribute it and/or modify @@ -20,6 +20,46 @@ #include <device/pci_ids.h> #include <soc/acpi.h> #include <soc/pci_ids.h> +#include <reg_script.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/lpc.h> +#include "chip.h" + +static const struct reg_script lpc_serirq_enable[] = { + /* Setup SERIRQ, enable continuous mode */ + REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)), +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) + REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0), +#endif + REG_SCRIPT_END +}; + +static void enable_lpc_decode(struct device *lpc) +{ + const struct soc_intel_apollolake_config *config; + + if (!lpc || !lpc->chip_info) + return; + + config = lpc->chip_info; + + /* Enable requested fixed IO decode ranges */ + pci_write_config16(lpc, LPC_EN, config->lpc_dec); + + /* Enable generic IO decode ranges */ + pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec); + pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec); + pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec); + pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec); +} + + +static void lpc_init(struct device *dev) +{ + enable_lpc_decode(dev); + reg_script_run_on_dev(dev, lpc_serirq_enable); +} + static void soc_lpc_add_io_resources(device_t dev) { @@ -46,6 +86,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .init = &lpc_init }; static const struct pci_driver soc_lpc __pci_driver = {

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Patch merged into coreboot/master: soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit f748f83ecb389552e7afe10ce8837b5173534b96 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sat Apr 23 13:15:51 2016 -0700 soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage Use postcar infrastructure to enable caching of area where ramstage runs. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14095 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14095 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Fix northbridge _crs scope
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit 2b9a5f5688db5a19a2511a19b91025440d9c138f Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:19:44 2016 -0700 soc/intel/apollolake: Fix northbridge _crs scope Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Reviewed-on: https://review.coreboot.org/14477 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14477 for details. -gerrit

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Patch merged into coreboot/master: mainboard/amenia: Enable Chrome EC Interface/Keyboard
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit cbf1a0fec8b84dc936a35428b835501ad0f46a30 Author: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Date: Mon Feb 8 09:45:37 2016 -0800 mainboard/amenia: Enable Chrome EC Interface/Keyboard Enabled LPC channel between host and EC. Superio.asl will enable proper probing of onboard keyboard. Change-Id: I57014fc90b345661853280ae3402f86e56af5fb9 Signed-off-by: Divya Sasidharan <divya.s.sasidharan(a)intel.com> Signed-off-by: Freddy Paul <freddy.paul(a)intel.com> Reviewed-on: https://review.coreboot.org/14468 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14468 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Configure a GPIO for TPM in bootblock
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit 4520c5e757cf280b7029a99adff60baed52493ce Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Mon Apr 18 13:36:19 2016 -0700 soc/intel/apollolake: Configure a GPIO for TPM in bootblock One of devices connected to FAST SPI bus is TPM. SoC uses dedicated line for chip select for TPM function. If TPM is used, that line needs to be configured to a specific native funciton. Change-Id: Ib5bf4c759adf9656f7b34540d4fc924945d27a97 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14467 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14467 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit 1ba068550d70549580838ba675c8a6543c1d175d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 14:59:12 2016 -0700 soc/intel/apollolake: Avoid marking 0xe0000-0xfffff region usable coreboot writes RDSP at 0xf0000. Since depthcharge wipes usable memory regions before starting, kernel can't find RDSP. Change-Id: I584bd5d24248cf38f46342615cf3b0252a821b2a Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14466 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14466 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Actually include ACPI PCI IRQ definitions
by gerrit＠coreboot.org 28 Apr '16

28 Apr '16

the following patch was just integrated into master: commit d047ab590e525ae72aea117953250b25f71a1e60 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Apr 21 14:53:33 2016 -0700 soc/intel/apollolake: Actually include ACPI PCI IRQ definitions Without ACPI PCI IRQ definitions kernel is left only with informaiton available in PCI config space, which is not sufficient. Change-Id: I3854781049851b5aa5b2dbf3257ece2fee76c3e2 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14465 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/14465 for details. -gerrit

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2019

2018

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2016

2015

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2013

coreboot-gerrit April 2016