coreboot-gerrit April 2016

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Patch set updated for coreboot: AGESA boards: Split dispatcher to romstage and ramstage
by Kyösti Mälkki 27 Apr '16

27 Apr '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14417 -gerrit commit 9048b6db96d47fa53c1f00e4170b7722d4b4c236 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:18:02 2016 +0300 AGESA boards: Split dispatcher to romstage and ramstage The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/amd/dinar/buildOpts.c | 17 -- src/mainboard/amd/inagua/buildOpts.c | 15 -- src/mainboard/amd/olivehill/buildOpts.c | 12 - src/mainboard/amd/parmer/buildOpts.c | 12 - src/mainboard/amd/persimmon/buildOpts.c | 15 -- src/mainboard/amd/south_station/buildOpts.c | 15 -- src/mainboard/amd/thatcher/buildOpts.c | 12 - src/mainboard/amd/torpedo/buildOpts.c | 16 -- src/mainboard/amd/union_station/buildOpts.c | 15 -- src/mainboard/asrock/e350m1/buildOpts.c | 16 -- src/mainboard/asrock/imb-a180/buildOpts.c | 12 - src/mainboard/asus/f2a85-m/buildOpts.c | 12 - src/mainboard/asus/f2a85-m_le/buildOpts.c | 12 - src/mainboard/bap/ode_e20XX/buildOpts.c | 13 -- src/mainboard/biostar/am1ml/buildOpts.c | 12 - src/mainboard/gizmosphere/gizmo/buildOpts.c | 15 -- src/mainboard/gizmosphere/gizmo2/buildOpts.c | 13 -- src/mainboard/hp/abm/buildOpts.c | 12 - src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c | 12 - src/mainboard/jetway/nf81-t56n-lf/buildOpts.c | 15 -- src/mainboard/lenovo/g505s/buildOpts.c | 12 - src/mainboard/lippert/frontrunner-af/buildOpts.c | 15 -- src/mainboard/lippert/toucan-af/buildOpts.c | 15 -- src/mainboard/pcengines/apu1/buildOpts.c | 15 -- src/mainboard/supermicro/h8qgi/buildOpts.c | 12 - src/mainboard/supermicro/h8scm/buildOpts.c | 12 - src/mainboard/tyan/s8226/buildOpts.c | 12 - src/vendorcode/amd/agesa/Makefile.inc | 5 + src/vendorcode/amd/agesa/common/agesa-entry-cfg.h | 86 +++++++ src/vendorcode/amd/agesa/common/agesa-entry.c | 177 +++++++++++++++ .../amd/agesa/f10/Include/OptionDmiInstall.h | 2 - .../amd/agesa/f10/Include/OptionHtAssistInstall.h | 2 - .../amd/agesa/f12/Include/OptionDmiInstall.h | 2 - .../agesa/f12/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f12/Include/OptionPstateInstall.h | 2 +- .../amd/agesa/f12/Include/PlatformInstall.h | 246 +------------------- .../amd/agesa/f14/Include/OptionDmiInstall.h | 2 - .../amd/agesa/f14/Include/OptionHtAssistInstall.h | 2 - .../amd/agesa/f14/Include/PlatformInstall.h | 248 +------------------- .../amd/agesa/f15/Include/OptionDmiInstall.h | 2 - .../agesa/f15/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f15/Include/PlatformInstall.h | 247 +------------------- .../amd/agesa/f15tn/Include/OptionDmiInstall.h | 2 - .../agesa/f15tn/Include/OptionL3FeaturesInstall.h | 2 - .../amd/agesa/f15tn/Include/PlatformInstall.h | 247 +------------------- .../amd/agesa/f16kb/Include/OptionDmiInstall.h | 2 - .../agesa/f16kb/Include/OptionL3FeaturesInstall.h | 2 - .../f16kb/Include/OptionPrefetchModeInstall.h | 2 - .../amd/agesa/f16kb/Include/PlatformInstall.h | 251 +-------------------- 49 files changed, 279 insertions(+), 1622 deletions(-) diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index f69f005..0b08cc6 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -26,7 +26,6 @@ */ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE //#define OPTION_HW_DQS_REC_EN_TRAINING TRUE @@ -153,24 +152,9 @@ #define BLDCFG_PSTATE_HPC_MODE FALSE #define BLDCFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST &MaranelloOverrideDevCap -/* - * Agesa entry points used in this implementation. - */ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE -#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE /***************************************************************************** @@ -395,7 +379,6 @@ CONST DEVICE_CAP_OVERRIDE ROMDATA MaranelloOverrideDevCap[2] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterfaceStub.h" diff --git a/src/mainboard/amd/inagua/buildOpts.c b/src/mainboard/amd/inagua/buildOpts.c index 57590a2..980fb3e 100644 --- a/src/mainboard/amd/inagua/buildOpts.c +++ b/src/mainboard/amd/inagua/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/olivehill/buildOpts.c b/src/mainboard/amd/olivehill/buildOpts.c index 18e403f..d558694 100644 --- a/src/mainboard/amd/olivehill/buildOpts.c +++ b/src/mainboard/amd/olivehill/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 41b3e39..e5637d0 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -172,17 +172,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/persimmon/buildOpts.c b/src/mainboard/amd/persimmon/buildOpts.c index 23e2706..915303c 100644 --- a/src/mainboard/amd/persimmon/buildOpts.c +++ b/src/mainboard/amd/persimmon/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/south_station/buildOpts.c b/src/mainboard/amd/south_station/buildOpts.c index ad4047a..ab3efec 100644 --- a/src/mainboard/amd/south_station/buildOpts.c +++ b/src/mainboard/amd/south_station/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 94d842a..69b8a87 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -172,17 +172,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -252,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA TrinityApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/torpedo/buildOpts.c b/src/mainboard/amd/torpedo/buildOpts.c index b42d9a1..16817c2 100644 --- a/src/mainboard/amd/torpedo/buildOpts.c +++ b/src/mainboard/amd/torpedo/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -83,20 +82,6 @@ //For revision C single-link processors #define BLDCFG_SUPPORT_ACPI_PSTATES_PSD_INDPX TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /***************************************************************************** * Define the RELEASE VERSION string @@ -230,7 +215,6 @@ CONST AP_MTRR_SETTINGS ROMDATA LlanoApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/amd/union_station/buildOpts.c b/src/mainboard/amd/union_station/buildOpts.c index ad4047a..ab3efec 100644 --- a/src/mainboard/amd/union_station/buildOpts.c +++ b/src/mainboard/amd/union_station/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/asrock/e350m1/buildOpts.c b/src/mainboard/asrock/e350m1/buildOpts.c index 140ece4..83049b6 100644 --- a/src/mainboard/asrock/e350m1/buildOpts.c +++ b/src/mainboard/asrock/e350m1/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -103,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE /* * Agesa configuration values selection. @@ -246,7 +231,6 @@ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/asrock/imb-a180/buildOpts.c b/src/mainboard/asrock/imb-a180/buildOpts.c index 742646c..ea47cec 100644 --- a/src/mainboard/asrock/imb-a180/buildOpts.c +++ b/src/mainboard/asrock/imb-a180/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 83f96f9..755505b 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -187,17 +186,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/asus/f2a85-m_le/buildOpts.c b/src/mainboard/asus/f2a85-m_le/buildOpts.c index c6810f1..8b01f24 100644 --- a/src/mainboard/asus/f2a85-m_le/buildOpts.c +++ b/src/mainboard/asus/f2a85-m_le/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -187,17 +186,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/bap/ode_e20XX/buildOpts.c b/src/mainboard/bap/ode_e20XX/buildOpts.c index 8162d42..9a02b43 100644 --- a/src/mainboard/bap/ode_e20XX/buildOpts.c +++ b/src/mainboard/bap/ode_e20XX/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -//#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -172,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/biostar/am1ml/buildOpts.c b/src/mainboard/biostar/am1ml/buildOpts.c index 075fe57..0e98517 100644 --- a/src/mainboard/biostar/am1ml/buildOpts.c +++ b/src/mainboard/biostar/am1ml/buildOpts.c @@ -171,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -251,7 +240,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/gizmosphere/gizmo/buildOpts.c b/src/mainboard/gizmosphere/gizmo/buildOpts.c index 8279802..9b62536 100644 --- a/src/mainboard/gizmosphere/gizmo/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo/buildOpts.c @@ -103,20 +103,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -220,7 +206,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/gizmosphere/gizmo2/buildOpts.c b/src/mainboard/gizmosphere/gizmo2/buildOpts.c index 8162d42..9a02b43 100644 --- a/src/mainboard/gizmosphere/gizmo2/buildOpts.c +++ b/src/mainboard/gizmosphere/gizmo2/buildOpts.c @@ -27,7 +27,6 @@ #include <stdlib.h> #include "AGESA.h" -//#include "CommonReturns.h" #include "Filecode.h" #define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE @@ -172,17 +171,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -253,7 +241,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/hp/abm/buildOpts.c b/src/mainboard/hp/abm/buildOpts.c index 96d59db..05889cb 100644 --- a/src/mainboard/hp/abm/buildOpts.c +++ b/src/mainboard/hp/abm/buildOpts.c @@ -176,17 +176,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ @@ -256,7 +245,6 @@ CONST AP_MTRR_SETTINGS ROMDATA KabiniApMtrrSettingsList[] = #include "CreateStruct.h" #include "cpuFeatures.h" #include "Table.h" -#include "CommonReturns.h" #include "cpuEarlyInit.h" #include "cpuLateInit.h" #include "GnbInterface.h" diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index 8d02f03..23457d6 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -33,7 +33,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -188,17 +187,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c index 73673ef..48b9118 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c +++ b/src/mainboard/jetway/nf81-t56n-lf/buildOpts.c @@ -31,7 +31,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f14/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f14/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f14/Proc/CPU/heapManager.h> @@ -115,20 +114,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * AGESA entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 7b491d4..19ea01e 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -33,7 +33,6 @@ /* Include the files that instantiate the configuration definitions. */ #include <vendorcode/amd/agesa/f15tn/Include/AdvancedApi.h> -#include <vendorcode/amd/agesa/f15tn/Include/CommonReturns.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatures.h> #include <vendorcode/amd/agesa/f15tn/Proc/CPU/heapManager.h> @@ -188,17 +187,6 @@ /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE //TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* * Customized OEM build configurations for FCH component */ diff --git a/src/mainboard/lippert/frontrunner-af/buildOpts.c b/src/mainboard/lippert/frontrunner-af/buildOpts.c index 3211966..e054e58 100644 --- a/src/mainboard/lippert/frontrunner-af/buildOpts.c +++ b/src/mainboard/lippert/frontrunner-af/buildOpts.c @@ -102,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -219,7 +205,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/lippert/toucan-af/buildOpts.c b/src/mainboard/lippert/toucan-af/buildOpts.c index 3211966..e054e58 100644 --- a/src/mainboard/lippert/toucan-af/buildOpts.c +++ b/src/mainboard/lippert/toucan-af/buildOpts.c @@ -102,20 +102,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -219,7 +205,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/pcengines/apu1/buildOpts.c b/src/mainboard/pcengines/apu1/buildOpts.c index 50cf4cf..52b8f52 100644 --- a/src/mainboard/pcengines/apu1/buildOpts.c +++ b/src/mainboard/pcengines/apu1/buildOpts.c @@ -101,20 +101,6 @@ #define BLDOPT_REMOVE_GFX_RECOVERY TRUE #define BLDOPT_REMOVE_EARLY_SAMPLES TRUE -/* - * Agesa entry points used in this implementation. - */ -#define AGESA_ENTRY_INIT_RESET TRUE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #define BLDCFG_PCI_MMIO_BASE CONFIG_MMCONF_BASE_ADDRESS #define BLDCFG_PCI_MMIO_SIZE CONFIG_MMCONF_BUS_NUMBER @@ -218,7 +204,6 @@ * needed by the system. */ #include "AGESA.h" -#include "CommonReturns.h" /* The fixed MTRR values to be set after memory initialization. */ CONST AP_MTRR_SETTINGS ROMDATA OntarioApMtrrSettingsList[] = diff --git a/src/mainboard/supermicro/h8qgi/buildOpts.c b/src/mainboard/supermicro/h8qgi/buildOpts.c index f6e654a..cbc7bd6 100644 --- a/src/mainboard/supermicro/h8qgi/buildOpts.c +++ b/src/mainboard/supermicro/h8qgi/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -426,17 +425,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8qgi_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* #if CONFIG_CPU_AMD_AGESA_FAMILY15 diff --git a/src/mainboard/supermicro/h8scm/buildOpts.c b/src/mainboard/supermicro/h8scm/buildOpts.c index 1403999..2f96f78 100644 --- a/src/mainboard/supermicro/h8scm/buildOpts.c +++ b/src/mainboard/supermicro/h8scm/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -339,17 +338,6 @@ CONST AP_MTRR_SETTINGS ROMDATA h8scm_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE #include "SanMarinoInstall.h" diff --git a/src/mainboard/tyan/s8226/buildOpts.c b/src/mainboard/tyan/s8226/buildOpts.c index 4a3d808..cdefa03 100644 --- a/src/mainboard/tyan/s8226/buildOpts.c +++ b/src/mainboard/tyan/s8226/buildOpts.c @@ -16,7 +16,6 @@ #include <stdlib.h> #include "AGESA.h" -#include "CommonReturns.h" #include "AdvancedApi.h" #include <PlatformMemoryConfiguration.h> #include "Filecode.h" @@ -426,17 +425,6 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] = /* Process the options... * This file include MUST occur AFTER the user option selection settings */ -#define AGESA_ENTRY_INIT_RESET TRUE//FALSE -#define AGESA_ENTRY_INIT_RECOVERY FALSE -#define AGESA_ENTRY_INIT_EARLY TRUE -#define AGESA_ENTRY_INIT_POST TRUE -#define AGESA_ENTRY_INIT_ENV TRUE -#define AGESA_ENTRY_INIT_MID TRUE -#define AGESA_ENTRY_INIT_LATE TRUE -#define AGESA_ENTRY_INIT_S3SAVE TRUE -#define AGESA_ENTRY_INIT_RESUME TRUE -#define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -#define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE /* #if CONFIG_CPU_AMD_AGESA_FAMILY15 diff --git a/src/vendorcode/amd/agesa/Makefile.inc b/src/vendorcode/amd/agesa/Makefile.inc index 02d9063..4a304be 100644 --- a/src/vendorcode/amd/agesa/Makefile.inc +++ b/src/vendorcode/amd/agesa/Makefile.inc @@ -5,3 +5,8 @@ subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15) += f15 subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) += f15tn subdirs-$(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) += f16kb + +ifeq ($(CONFIG_CPU_AMD_AGESA),y) +romstage-y += common/agesa-entry.c +ramstage-y += common/agesa-entry.c +endif diff --git a/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h new file mode 100644 index 0000000..e882f2e --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry-cfg.h @@ -0,0 +1,86 @@ +#ifndef AGESA_ENTRY_CFG_H +#define AGESA_ENTRY_CFG_H + + +#if defined(__PRE_RAM__) + +#define AGESA_ENTRY_INIT_RESET TRUE +#define AGESA_ENTRY_INIT_EARLY TRUE +#define AGESA_ENTRY_INIT_POST TRUE + +/* Not implemented in coreboot romstage. */ +#define AGESA_ENTRY_INIT_RECOVERY FALSE + +#define AGESA_ENTRY_INIT_RESUME IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +#define AGESA_ENTRY_INIT_LATE_RESTORE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + +/* Move to ramstage? */ +#define AGESA_ENTRY_INIT_ENV TRUE + +#else + +#define AGESA_ENTRY_INIT_MID TRUE +#define AGESA_ENTRY_INIT_LATE TRUE +#define AGESA_ENTRY_INIT_S3SAVE IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) + +#endif + +/* Not required. */ +#define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE + +/* Required for any multi-core. */ +#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE + + +/* Defaults below. */ + +/* Process user desired AGESA entry points */ +#ifndef AGESA_ENTRY_INIT_RESET + #define AGESA_ENTRY_INIT_RESET FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RECOVERY + #define AGESA_ENTRY_INIT_RECOVERY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_EARLY + #define AGESA_ENTRY_INIT_EARLY FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_POST + #define AGESA_ENTRY_INIT_POST FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_ENV + #define AGESA_ENTRY_INIT_ENV FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_MID + #define AGESA_ENTRY_INIT_MID FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE + #define AGESA_ENTRY_INIT_LATE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_S3SAVE + #define AGESA_ENTRY_INIT_S3SAVE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_RESUME + #define AGESA_ENTRY_INIT_RESUME FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_LATE_RESTORE + #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE +#endif + +#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES + #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE +#endif + +#ifndef AGESA_ENTRY_LATE_RUN_AP_TASK + #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE +#endif + +#endif /* AGESA_ENTRY_CFG_H */ diff --git a/src/vendorcode/amd/agesa/common/agesa-entry.c b/src/vendorcode/amd/agesa/common/agesa-entry.c new file mode 100644 index 0000000..e722fc1 --- /dev/null +++ b/src/vendorcode/amd/agesa/common/agesa-entry.c @@ -0,0 +1,177 @@ +#include <Porting.h> +#include <AMD.h> +#include <AGESA.h> + +#include "CommonReturns.h" + +#include <heapManager.h> +#include <CreateStruct.h> + +#include <Options.h> + +#include <agesa-entry-cfg.h> + +CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = +{ + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, + sizeof (AMD_RESET_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResetConstructor, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_RESET_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, + sizeof (AMD_RECOVERY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, + sizeof (AMD_EARLY_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_EARLY_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, + sizeof (AMD_ENV_PARAMS), + (PF_AGESA_FUNCTION) AmdInitEnvInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_ENV_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, + sizeof (AMD_LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdInitLateInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, + AMD_INIT_LATE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, + sizeof (AMD_MID_PARAMS), + (PF_AGESA_FUNCTION) AmdInitMidInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_INIT_MID_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, + sizeof (AMD_POST_PARAMS), + (PF_AGESA_FUNCTION) AmdInitPostInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, + AMD_INIT_POST_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, + sizeof (AMD_RESUME_PARAMS), + (PF_AGESA_FUNCTION) AmdInitResumeInitializer, + (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, + AMD_INIT_RESUME_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, + sizeof (AMD_S3LATE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_S3_LATE_RESTORE_HANDLE + }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, + sizeof (AMD_S3SAVE_PARAMS), + (PF_AGESA_FUNCTION) AmdS3SaveInitializer, + (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, + AMD_S3_SAVE_HANDLE + }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, + sizeof (AP_EXE_PARAMS), + (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, + (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, + AMD_LATE_RUN_AP_TASK_HANDLE + }, + #endif + { 0, 0, NULL } +}; + +CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); + +CONST DISPATCH_TABLE ROMDATA DispatchTable[] = +{ + { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, + { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, + + #if AGESA_ENTRY_INIT_RESET == TRUE + { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, + #endif + + #if AGESA_ENTRY_INIT_RECOVERY == TRUE + { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, + #endif + + #if AGESA_ENTRY_INIT_EARLY == TRUE + { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, + #endif + + #if AGESA_ENTRY_INIT_POST == TRUE + { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, + #endif + + #if AGESA_ENTRY_INIT_ENV == TRUE + { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, + #endif + + #if AGESA_ENTRY_INIT_MID == TRUE + { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, + #endif + + #if AGESA_ENTRY_INIT_LATE == TRUE + { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, + #endif + + #if AGESA_ENTRY_INIT_S3SAVE == TRUE + { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, + #endif + + #if AGESA_ENTRY_INIT_RESUME == TRUE + { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, + #endif + + #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE + { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, + #endif + + #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE + { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, + { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, + { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, + { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, + { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, + { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, + #endif + + #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE + { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, + #endif + { 0, NULL } +}; diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h index 2ad7792..232d407 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionDmiInstall.h @@ -60,8 +60,6 @@ #define USER_DMI_OPTION &GetDmiInfoMain #define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #ifdef OPTION_FAMILY10H diff --git a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h index c084924..a7149f0 100644 --- a/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h +++ b/src/vendorcode/amd/agesa/f10/Include/OptionHtAssistInstall.h @@ -79,8 +79,6 @@ &HtAssistFamilyServiceArray[0] }; - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef HT_ASSIST_AP_DISABLE_CACHE #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef HT_ASSIST_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h index 410d3cb..ead4fce 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionDmiInstall.h @@ -63,8 +63,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h index f3ef633..7f3ac07 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionL3FeaturesInstall.h @@ -82,8 +82,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h index d52adfb..7d6433d 100644 --- a/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/OptionPstateInstall.h @@ -129,7 +129,7 @@ #if AGESA_ENTRY_INIT_LATE == TRUE #define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables #else - OPTION_ACPI_FEATURE CreateAcpiTablesStub; +// OPTION_ACPI_FEATURE CreateAcpiTablesStub; #define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub #endif #if AGESA_ENTRY_INIT_POST == TRUE diff --git a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h index 14dd179..2b99660 100644 --- a/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f12/Include/PlatformInstall.h @@ -52,30 +52,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature @@ -91,61 +67,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2268,6 +2189,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2484,171 +2407,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h index 31111e3..eb4bc91 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionDmiInstall.h @@ -66,8 +66,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h index d98300f..175482b 100644 --- a/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/OptionHtAssistInstall.h @@ -97,8 +97,6 @@ &HtAssistFamilyServiceArray[0] }; - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef HT_ASSIST_AP_DISABLE_CACHE #define HT_ASSIST_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef HT_ASSIST_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h index 8641589..9a8bd68 100644 --- a/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f14/Include/PlatformInstall.h @@ -51,31 +51,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -90,62 +65,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -2149,12 +2068,13 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; #define OPTFCN_PSTATE_LEVELING CommonReturnAgesaSuccess #endif - /***************************************************************************** * * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2329,170 +2249,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h index a6d48b3..b09a58f 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionDmiInstall.h @@ -64,8 +64,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h index 5804f1d..4a73c40 100644 --- a/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/OptionL3FeaturesInstall.h @@ -94,8 +94,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h index 38ec4ad..0e6f1c8 100644 --- a/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15/Include/PlatformInstall.h @@ -49,31 +49,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -88,61 +63,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2249,6 +2169,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2499,171 +2421,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h index fb1b54d..541cee9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionDmiInstall.h @@ -63,8 +63,6 @@ // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #else #define CPU_DMI_AP_GET_TYPE4_TYPE7 diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h index 5d188e2..203b9e2 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionL3FeaturesInstall.h @@ -82,8 +82,6 @@ #endif #endif - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h index eca567b..af5c8b7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/PlatformInstall.h @@ -48,31 +48,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -87,61 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - /* Process solution defined socket / family installations * @@ -2618,6 +2538,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2883,171 +2805,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h index ce8ef06..e0b09b3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionDmiInstall.h @@ -75,8 +75,6 @@ OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub; // This additional check keeps AP launch routines from being unnecessarily included // in single socket systems. #if OPTION_MULTISOCKET == TRUE - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef CPU_DMI_AP_GET_TYPE4_TYPE7 #define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info}, #endif diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h index 8d34603..3323fea 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionL3FeaturesInstall.h @@ -57,8 +57,6 @@ #if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE || OPTION_NBR_CACHE == TRUE) #if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef L3_FEAT_AP_DISABLE_CACHE #define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches}, #undef L3_FEAT_AP_ENABLE_CACHE diff --git a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h index aa510aa..711b1a3 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/OptionPrefetchModeInstall.h @@ -57,8 +57,6 @@ #if OPTION_PREFETCH_MODE == TRUE #if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE) - #undef AGESA_ENTRY_LATE_RUN_AP_TASK - #define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE #undef CPU_PREFETCH_MODE_AP_TASK #define CPU_PREFETCH_MODE_AP_TASK {AP_LATE_TASK_CPU_PREFETCH_MODE, (IMAGE_ENTRY) CpuPrefetchModeApTask}, diff --git a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h index 1295888..afe15b6 100644 --- a/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Include/PlatformInstall.h @@ -48,31 +48,6 @@ * ****************************************************************************/ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. Turn these on in your option c file, not - * here. - */ -// #define AGESA_ENTRY_INIT_RESET TRUE -// #define AGESA_ENTRY_INIT_RECOVERY TRUE -// #define AGESA_ENTRY_INIT_EARLY TRUE -// #define AGESA_ENTRY_INIT_POST TRUE -// #define AGESA_ENTRY_INIT_ENV TRUE -// #define AGESA_ENTRY_INIT_MID TRUE -// #define AGESA_ENTRY_INIT_LATE TRUE -// #define AGESA_ENTRY_INIT_S3SAVE TRUE -// #define AGESA_ENTRY_INIT_RESUME TRUE -// #define AGESA_ENTRY_INIT_LATE_RESTORE TRUE -// #define AGESA_ENTRY_INIT_GENERAL_SERVICES TRUE - -/* Defaults for private/internal build control settings */ -/* Available options for image builds. - * - * As part of the image build for each image, define the options below to select the - * AGESA entry points included in that image. - */ - VOLATILE AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , @@ -87,62 +62,6 @@ VOLATILE AMD_MODULE_HEADER mCpuModuleID = { NULL }; -/* Process user desired AGESA entry points */ -#ifndef AGESA_ENTRY_INIT_RESET - #define AGESA_ENTRY_INIT_RESET FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RECOVERY - #define AGESA_ENTRY_INIT_RECOVERY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_EARLY - #define AGESA_ENTRY_INIT_EARLY FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_POST - #define AGESA_ENTRY_INIT_POST FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_ENV - #define AGESA_ENTRY_INIT_ENV FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_MID - #define AGESA_ENTRY_INIT_MID FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE - #define AGESA_ENTRY_INIT_LATE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_S3SAVE - #define AGESA_ENTRY_INIT_S3SAVE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_RESUME - #define AGESA_ENTRY_INIT_RESUME FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_LATE_RESTORE - #define AGESA_ENTRY_INIT_LATE_RESTORE FALSE -#endif - -#ifndef AGESA_ENTRY_INIT_GENERAL_SERVICES - #define AGESA_ENTRY_INIT_GENERAL_SERVICES FALSE -#endif - -/* Default the late AP entry point to off. It can be enabled - by any family that may need the late AP functionality, or - by any feature code that may need it. The IBVs no longer - have control over this entry point. */ -#ifdef AGESA_ENTRY_LATE_RUN_AP_TASK - #undef AGESA_ENTRY_LATE_RUN_AP_TASK -#endif -#define AGESA_ENTRY_LATE_RUN_AP_TASK FALSE - - - /* Process solution defined socket / family installations * * As part of the release package for each image, define the options below to select the @@ -1727,6 +1646,8 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * Include the structure definitions for the defaults table structures * ****************************************************************************/ +#include <CommonReturns.h> +#include <agesa-entry-cfg.h> #include "Options.h" #include "OptionCpuFamiliesInstall.h" #include "OptionsHt.h" @@ -2008,174 +1929,6 @@ BUILD_OPT_CFG UserOptions = { 0, //reserved... }; -CONST FUNCTION_PARAMS_INFO ROMDATA FuncParamsInfo[] = -{ - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, - sizeof (AMD_RESET_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResetConstructor, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_RESET_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, - sizeof (AMD_RECOVERY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitRecoveryInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, - sizeof (AMD_EARLY_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEarlyInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_EARLY_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, - sizeof (AMD_ENV_PARAMS), - (PF_AGESA_FUNCTION) AmdInitEnvInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_ENV_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, - sizeof (AMD_LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdInitLateInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitLateDestructor, - AMD_INIT_LATE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, - sizeof (AMD_MID_PARAMS), - (PF_AGESA_FUNCTION) AmdInitMidInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_INIT_MID_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, - sizeof (AMD_POST_PARAMS), - (PF_AGESA_FUNCTION) AmdInitPostInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitPostDestructor, - AMD_INIT_POST_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, - sizeof (AMD_RESUME_PARAMS), - (PF_AGESA_FUNCTION) AmdInitResumeInitializer, - (PF_AGESA_DESTRUCTOR) AmdInitResumeDestructor, - AMD_INIT_RESUME_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, - sizeof (AMD_S3LATE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3LateRestoreInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_S3_LATE_RESTORE_HANDLE - }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, - sizeof (AMD_S3SAVE_PARAMS), - (PF_AGESA_FUNCTION) AmdS3SaveInitializer, - (PF_AGESA_DESTRUCTOR) AmdS3SaveDestructor, - AMD_S3_SAVE_HANDLE - }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, - sizeof (AP_EXE_PARAMS), - (PF_AGESA_FUNCTION) AmdLateRunApTaskInitializer, - (PF_AGESA_DESTRUCTOR) CommonReturnAgesaSuccess, - AMD_LATE_RUN_AP_TASK_HANDLE - }, - #endif - { 0, 0, NULL, NULL, 0 } -}; - -CONST UINTN InitializerCount = ((sizeof (FuncParamsInfo)) / (sizeof (FuncParamsInfo[0]))); - -CONST DISPATCH_TABLE ROMDATA DispatchTable[] = -{ - { AMD_CREATE_STRUCT, (IMAGE_ENTRY)AmdCreateStruct }, - { AMD_RELEASE_STRUCT, (IMAGE_ENTRY)AmdReleaseStruct }, - - #if AGESA_ENTRY_INIT_RESET == TRUE - { AMD_INIT_RESET, (IMAGE_ENTRY)AmdInitReset }, - #endif - - #if AGESA_ENTRY_INIT_RECOVERY == TRUE - { AMD_INIT_RECOVERY, (IMAGE_ENTRY)AmdInitRecovery }, - #endif - - #if AGESA_ENTRY_INIT_EARLY == TRUE - { AMD_INIT_EARLY, (IMAGE_ENTRY)AmdInitEarly }, - #endif - - #if AGESA_ENTRY_INIT_POST == TRUE - { AMD_INIT_POST, (IMAGE_ENTRY)AmdInitPost }, - #if OPTION_DATA_EYE == TRUE - { AMD_GET_2D_DATA_EYE, (IMAGE_ENTRY)AmdGet2DDataEye }, - #endif - #endif - - #if AGESA_ENTRY_INIT_ENV == TRUE - { AMD_INIT_ENV, (IMAGE_ENTRY)AmdInitEnv }, - #endif - - #if AGESA_ENTRY_INIT_MID == TRUE - { AMD_INIT_MID, (IMAGE_ENTRY)AmdInitMid }, - #endif - - #if AGESA_ENTRY_INIT_LATE == TRUE - { AMD_INIT_LATE, (IMAGE_ENTRY)AmdInitLate }, - #endif - - #if AGESA_ENTRY_INIT_S3SAVE == TRUE - { AMD_S3_SAVE, (IMAGE_ENTRY)AmdS3Save }, - #endif - - #if AGESA_ENTRY_INIT_RESUME == TRUE - { AMD_INIT_RESUME, (IMAGE_ENTRY)AmdInitResume }, - #endif - - #if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE - { AMD_S3LATE_RESTORE, (IMAGE_ENTRY)AmdS3LateRestore }, - #endif - - #if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE - { AMD_GET_APIC_ID, (IMAGE_ENTRY)AmdGetApicId }, - { AMD_GET_PCI_ADDRESS, (IMAGE_ENTRY)AmdGetPciAddress }, - { AMD_IDENTIFY_CORE, (IMAGE_ENTRY)AmdIdentifyCore }, - { AMD_READ_EVENT_LOG, (IMAGE_ENTRY)AmdReadEventLog }, - { AMD_IDENTIFY_DIMMS, (IMAGE_ENTRY)AmdIdentifyDimm }, - { AMD_GET_EXECACHE_SIZE, (IMAGE_ENTRY)AmdGetAvailableExeCacheSize }, - #endif - - #if AGESA_ENTRY_LATE_RUN_AP_TASK == TRUE - { AMD_LATE_RUN_AP_TASK, (IMAGE_ENTRY)AmdLateRunApTask }, - #endif - { 0, NULL } -}; - CONST DISPATCH_TABLE ROMDATA ApDispatchTable[] = { IDS_LATE_RUN_AP_TASK

1 0

Patch set updated for coreboot: AGESA: Rewrite agesawrapper [NOTFORMERGE]
by Kyösti Mälkki 27 Apr '16

27 Apr '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14418 -gerrit commit fb03f923138efb65b5aea256b1f6871433479546 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Apr 19 15:51:24 2016 +0300 AGESA: Rewrite agesawrapper [NOTFORMERGE] Change-Id: Ic111291a2c0f1f171d2330c9ddaf6061a648bc86 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/northbridge/amd/agesa/agesawrapper.c | 254 ++++++++++++------------------- 1 file changed, 94 insertions(+), 160 deletions(-) diff --git a/src/northbridge/amd/agesa/agesawrapper.c b/src/northbridge/amd/agesa/agesawrapper.c index a72e239..19b7e33 100644 --- a/src/northbridge/amd/agesa/agesawrapper.c +++ b/src/northbridge/amd/agesa/agesawrapper.c @@ -25,60 +25,74 @@ static const struct OEM_HOOK *OemHook = &OemCustomize; + +static void prepare_AmdParams(AMD_INTERFACE_PARAMS *p, int f) +{ + memset(p, 0, sizeof(AMD_INTERFACE_PARAMS)); + p->StdHeader.CalloutPtr = GetBiosCallout; + p->AgesaFunctionName = f; + + p->AllocationMethod = 0; /* Only byHost makes difference. */ +} + +static void * empty_AmdParams(AMD_INTERFACE_PARAMS *p, int f) +{ + prepare_AmdParams(p, f); + + AmdCreateStruct(p); + return (void *) p->NewStructPtr; +} + +static void free_AmdParams(AMD_INTERFACE_PARAMS *p) +{ + AmdReleaseStruct(p); +} + #if defined(__PRE_RAM__) +static void * local_AmdParams(AMD_INTERFACE_PARAMS *p, int f, void *buf, size_t len) +{ + prepare_AmdParams(p, f); + + memset(buf, 0, len); + p->NewStructPtr = buf; + p->NewStructSize = len; + p->AllocationMethod = ByHost; + + AmdCreateStruct(p); + return (void *) p->NewStructPtr; +} + AGESA_STATUS agesawrapper_amdinitreset(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESET_PARAMS AmdResetParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - memset(&AmdResetParams, 0, sizeof(AMD_RESET_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESET; - AmdParamStruct.AllocationMethod = ByHost; - AmdParamStruct.NewStructSize = sizeof(AMD_RESET_PARAMS); - AmdParamStruct.NewStructPtr = &AmdResetParams; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); - AmdResetParams.HtConfig.Depth = 0; - - status = AmdInitReset((AMD_RESET_PARAMS *) AmdParamStruct.NewStructPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; + AMD_RESET_PARAMS tmp; + + AMD_RESET_PARAMS *AmdResetParams = local_AmdParams(&aip, + AMD_INIT_RESET, &tmp, sizeof(tmp)); + + AmdResetParams->HtConfig.Depth = 0; + + status = AmdInitReset(AmdResetParams); + AGESA_EVENTLOG(status, &aip.StdHeader); return status; } AGESA_STATUS agesawrapper_amdinitearly(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_EARLY_PARAMS *AmdEarlyParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_EARLY; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; /* OEM Should Customize the defaults through this hook. */ - AmdEarlyParamsPtr = (AMD_EARLY_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_EARLY_PARAMS *AmdEarlyParams = empty_AmdParams(&aip, AMD_INIT_EARLY); if (OemHook->InitEarly) - OemHook->InitEarly(AmdEarlyParamsPtr); + OemHook->InitEarly(AmdEarlyParams); - status = AmdInitEarly(AmdEarlyParamsPtr); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); + status = AmdInitEarly(AmdEarlyParams); + AGESA_EVENTLOG(status, &aip.StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); return status; } @@ -86,29 +100,17 @@ AGESA_STATUS agesawrapper_amdinitearly(void) AGESA_STATUS agesawrapper_amdinitpost(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_POST_PARAMS *PostParams; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_POST; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; /* OEM Should Customize the defaults through this hook. */ - PostParams = (AMD_POST_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_POST_PARAMS *PostParams = empty_AmdParams(&aip, AMD_INIT_POST); if (OemHook->InitPost) OemHook->InitPost(PostParams); status = AmdInitPost(PostParams); AGESA_EVENTLOG(status, &PostParams->StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); /* Initialize heap space */ EmptyHeap(); @@ -119,29 +121,18 @@ AGESA_STATUS agesawrapper_amdinitpost(void) AGESA_STATUS agesawrapper_amdinitresume(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_RESUME_PARAMS *AmdResumeParamsPtr; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_RESUME; - AmdParamStruct.AllocationMethod = PreMemHeap; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; - AmdResumeParamsPtr = (AMD_RESUME_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_RESUME_PARAMS *AmdResumeParams = empty_AmdParams(&aip, AMD_INIT_RESUME); - AmdResumeParamsPtr->S3DataBlock.NvStorageSize = 0; - AmdResumeParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemInitResume(AmdResumeParamsPtr); + AmdResumeParams->S3DataBlock.NvStorageSize = 0; + AmdResumeParams->S3DataBlock.VolatileStorageSize = 0; + OemInitResume(AmdResumeParams); - status = AmdInitResume(AmdResumeParamsPtr); + status = AmdInitResume(AmdResumeParams); + AGESA_EVENTLOG(status, &aip.StdHeader); - AGESA_EVENTLOG(status, &AmdParamStruct.StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); return status; } @@ -149,55 +140,34 @@ AGESA_STATUS agesawrapper_amdinitresume(void) AGESA_STATUS agesawrapper_amdinitenv(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_ENV_PARAMS *EnvParam; + AMD_INTERFACE_PARAMS aip; - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_ENV; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - AmdCreateStruct(&AmdParamStruct); - EnvParam = (AMD_ENV_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_ENV_PARAMS *EnvParam = empty_AmdParams(&aip, AMD_INIT_ENV); status = AmdInitEnv(EnvParam); AGESA_EVENTLOG(status, &EnvParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); + free_AmdParams(&aip); return status; } AGESA_STATUS agesawrapper_amds3laterestore(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - AMD_S3LATE_PARAMS AmdS3LateParams; - AMD_S3LATE_PARAMS *AmdS3LateParamsPtr; - - memset(&AmdS3LateParams, 0, sizeof(AMD_S3LATE_PARAMS)); - - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.AllocationMethod = ByHost; - AmdInterfaceParams.AgesaFunctionName = AMD_S3LATE_RESTORE; - AmdInterfaceParams.NewStructPtr = &AmdS3LateParams; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdS3LateParamsPtr = &AmdS3LateParams; - AmdInterfaceParams.NewStructSize = sizeof(AMD_S3LATE_PARAMS); + AMD_INTERFACE_PARAMS aip; + AMD_S3LATE_PARAMS tmp; - AmdCreateStruct(&AmdInterfaceParams); + AMD_S3LATE_PARAMS *AmdS3LateParams = local_AmdParams(&aip, + AMD_S3LATE_RESTORE, &tmp, sizeof(tmp)); -#if 0 - /* TODO: What to do with NvStorage here? */ - AmdS3LateParamsPtr->S3DataBlock.NvStorageSize = 0; +#if 0 /* TODO: What to do with NvStorage here? */ + AmdS3LateParams->S3DataBlock.NvStorageSize = 0; #endif - AmdS3LateParamsPtr->S3DataBlock.VolatileStorageSize = 0; - OemS3LateRestore(AmdS3LateParamsPtr); + AmdS3LateParams->S3DataBlock.VolatileStorageSize = 0; + OemS3LateRestore(AmdS3LateParams); - status = AmdS3LateRestore(AmdS3LateParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); + status = AmdS3LateRestore(AmdS3LateParams); + AGESA_EVENTLOG(status, &aip.StdHeader); ASSERT(status == AGESA_SUCCESS); return status; @@ -208,28 +178,20 @@ AGESA_STATUS agesawrapper_amds3laterestore(void) AGESA_STATUS agesawrapper_amdinitmid(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; - AMD_MID_PARAMS *MidParam; - - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); - - AmdParamStruct.AgesaFunctionName = AMD_INIT_MID; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - - AmdCreateStruct(&AmdParamStruct); + AMD_INTERFACE_PARAMS aip; /* OEM Should Customize the defaults through this hook. */ - MidParam = (AMD_MID_PARAMS *) AmdParamStruct.NewStructPtr; + AMD_MID_PARAMS *MidParam = empty_AmdParams(&aip, AMD_INIT_MID); if (OemHook->InitMid) OemHook->InitMid(MidParam); status = AmdInitMid(MidParam); AGESA_EVENTLOG(status, &MidParam->StdHeader); - AmdReleaseStruct(&AmdParamStruct); +#if 0 /* TODO: Why not? */ + ASSERT(status == AGESA_SUCCESS); +#endif + + free_AmdParams(&aip); return status; } @@ -237,30 +199,19 @@ AGESA_STATUS agesawrapper_amdinitmid(void) AGESA_STATUS agesawrapper_amdS3Save(void) { AGESA_STATUS status; - AMD_S3SAVE_PARAMS *AmdS3SaveParamsPtr; - AMD_INTERFACE_PARAMS AmdInterfaceParams; - - memset(&AmdInterfaceParams, 0, sizeof(AMD_INTERFACE_PARAMS)); + AMD_INTERFACE_PARAMS aip; - AmdInterfaceParams.StdHeader.ImageBasePtr = 0; - AmdInterfaceParams.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; - AmdInterfaceParams.StdHeader.CalloutPtr = &GetBiosCallout; - AmdInterfaceParams.AllocationMethod = PostMemDram; - AmdInterfaceParams.AgesaFunctionName = AMD_S3_SAVE; - AmdInterfaceParams.StdHeader.AltImageBasePtr = 0; - AmdInterfaceParams.StdHeader.Func = 0; - AmdCreateStruct(&AmdInterfaceParams); + AMD_S3SAVE_PARAMS *AmdS3SaveParams = empty_AmdParams(&aip, AMD_S3_SAVE); - AmdS3SaveParamsPtr = (AMD_S3SAVE_PARAMS *) AmdInterfaceParams.NewStructPtr; - AmdS3SaveParamsPtr->StdHeader = AmdInterfaceParams.StdHeader; + AmdS3SaveParams->StdHeader = aip.StdHeader; - status = AmdS3Save(AmdS3SaveParamsPtr); - AGESA_EVENTLOG(status, &AmdInterfaceParams.StdHeader); + status = AmdS3Save(AmdS3SaveParams); + AGESA_EVENTLOG(status, &aip.StdHeader); ASSERT(status == AGESA_SUCCESS); - OemS3Save(AmdS3SaveParamsPtr); + OemS3Save(AmdS3SaveParams); - AmdReleaseStruct(&AmdInterfaceParams); + free_AmdParams(&aip); return status; } @@ -271,29 +222,15 @@ static AMD_LATE_PARAMS *AmdLateParams = NULL; AGESA_STATUS agesawrapper_amdinitlate(void) { AGESA_STATUS status; - AMD_INTERFACE_PARAMS AmdParamStruct; + AMD_INTERFACE_PARAMS aip; - memset(&AmdParamStruct, 0, sizeof(AMD_INTERFACE_PARAMS)); + AmdLateParams = empty_AmdParams(&aip, AMD_INIT_LATE); - AmdParamStruct.AgesaFunctionName = AMD_INIT_LATE; - AmdParamStruct.AllocationMethod = PostMemDram; - AmdParamStruct.StdHeader.AltImageBasePtr = 0; - AmdParamStruct.StdHeader.CalloutPtr = &GetBiosCallout; - AmdParamStruct.StdHeader.Func = 0; - AmdParamStruct.StdHeader.ImageBasePtr = 0; - -#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_TN) || IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15_RL) || \ - IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY16_KB) - AmdParamStruct.StdHeader.HeapStatus = HEAP_SYSTEM_MEM; -#endif - - AmdCreateStruct(&AmdParamStruct); - AmdLateParams = (AMD_LATE_PARAMS *) AmdParamStruct.NewStructPtr; status = AmdInitLate(AmdLateParams); AGESA_EVENTLOG(status, &AmdLateParams->StdHeader); ASSERT(status == AGESA_SUCCESS); - /* No AmdReleaseStruct(&AmdParamStruct), we need AmdLateParams later. */ + /* No free_AmdParams(&aip), we need AmdLateParams later. */ return status; } @@ -336,11 +273,8 @@ AGESA_STATUS agesawrapper_amdlaterunaptask(UINT32 Func, UINT32 Data, VOID * Conf AP_EXE_PARAMS ApExeParams; memset(&ApExeParams, 0, sizeof(AP_EXE_PARAMS)); - - ApExeParams.StdHeader.AltImageBasePtr = 0; ApExeParams.StdHeader.CalloutPtr = &GetBiosCallout; - ApExeParams.StdHeader.Func = 0; - ApExeParams.StdHeader.ImageBasePtr = 0; + ApExeParams.FunctionNumber = Func; ApExeParams.RelatedDataBlock = ConfigPtr;

1 0

Patch set updated for coreboot: board_status: Allow for parsing longopts
by David Hendricks 27 Apr '16

27 Apr '16

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14523 -gerrit commit b307f755b38bfcd7b1d39b716d6f5d0aabea18ef Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 26 14:07:42 2016 -0700 board_status: Allow for parsing longopts This converts the argument parsing to allow us to add longopts so that we can keep the shortopts to relatively generic script behavior. Longopts can be used for tweaking specific behaviors. For example, we might wish to change SSH port, timeout, and authentication parameters with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc. This is virtuall untested, it would be nice if someone else can hijack this patch to test and clean it up where necessary. Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/board_status/board_status.sh | 42 +++++++++++++++++++++++++++------------ 1 file changed, 29 insertions(+), 13 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index b315be1..0bb0864 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -188,31 +188,47 @@ Options " } -while getopts "Chi:r:s:S:u" opt; do - case "$opt" in - h) +# TODO: add longopts in the quotes after -l +ARGS=$(getopt -o Chi:r:s:S:u -l "" -n "$0" -- "$@"); +if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi +eval set -- "$ARGS" +while true ; do + case "$1" in + -h) show_help exit $EXIT_SUCCESS ;; - C) + -C) CLOBBER_OUTPUT=1 ;; - i) - COREBOOT_IMAGE="$OPTARG" + -i) + shift + COREBOOT_IMAGE="$1" ;; - r) - REMOTE_HOST="$OPTARG" + -r) + shift + REMOTE_HOST="$1" ;; - s) - SERIAL_DEVICE="$OPTARG" + -s) + shift + SERIAL_DEVICE="$1" ;; - S) - SERIAL_PORT_SPEED="$OPTARG" + -S) + shift + SERIAL_PORT_SPEED="$1" ;; - u) + -u) UPLOAD_RESULTS=1 ;; + --) + shift + break + ;; + *) + echo "error processing options" + exit $EXIT_FAILURE esac + shift done grep -rH 'coreboot.org' .git/config >/dev/null 2>&1

1 0

New patch to review for coreboot: payloads/nvramcui: Make the makefile non-executable
by Jonathan Neuschäfer 27 Apr '16

27 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14526 -gerrit commit 858fa2404ecf7a571142824d8611b26e960fb3b4 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Apr 27 04:13:33 2016 +0200 payloads/nvramcui: Make the makefile non-executable Change-Id: Id584cbf02c9d3ecb89fcf2a3190f0a73816954a8 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- payloads/nvramcui/Makefile | 0 1 file changed, 0 insertions(+), 0 deletions(-) diff --git a/payloads/nvramcui/Makefile b/payloads/nvramcui/Makefile old mode 100755 new mode 100644

1 0

New patch to review for coreboot: mb/emulation/*/board_info.txt: Update QEMU URL
by Jonathan Neuschäfer 27 Apr '16

27 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14525 -gerrit commit 0513f2af5d728c71ec8613513cd3c5a8c525571e Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Apr 27 04:13:33 2016 +0200 mb/emulation/*/board_info.txt: Update QEMU URL Change-Id: If4d57c7898c0de20035533dccd4554f45a71d5d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/qemu-armv7/board_info.txt | 2 +- src/mainboard/emulation/qemu-i440fx/board_info.txt | 2 +- src/mainboard/emulation/qemu-q35/board_info.txt | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/emulation/qemu-armv7/board_info.txt b/src/mainboard/emulation/qemu-armv7/board_info.txt index 1bb78e9..5b94afd 100644 --- a/src/mainboard/emulation/qemu-armv7/board_info.txt +++ b/src/mainboard/emulation/qemu-armv7/board_info.txt @@ -1,3 +1,3 @@ Board name: QEMU armv7 (vexpress-a9) Category: emulation -Board URL: http://fabrice.bellard.free.fr/qemu/ +Board URL: http://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-i440fx/board_info.txt b/src/mainboard/emulation/qemu-i440fx/board_info.txt index 6938d86..77cdcf5 100644 --- a/src/mainboard/emulation/qemu-i440fx/board_info.txt +++ b/src/mainboard/emulation/qemu-i440fx/board_info.txt @@ -1,2 +1,2 @@ Category: emulation -Board URL: http://fabrice.bellard.free.fr/qemu/ +Board URL: http://wiki.qemu.org/Main_Page diff --git a/src/mainboard/emulation/qemu-q35/board_info.txt b/src/mainboard/emulation/qemu-q35/board_info.txt index 6938d86..77cdcf5 100644 --- a/src/mainboard/emulation/qemu-q35/board_info.txt +++ b/src/mainboard/emulation/qemu-q35/board_info.txt @@ -1,2 +1,2 @@ Category: emulation -Board URL: http://fabrice.bellard.free.fr/qemu/ +Board URL: http://wiki.qemu.org/Main_Page

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Andrey Petrov 27 Apr '16

27 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 0d404d50e899686f59d409581d330b2630d34f37 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 40 ++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 3 + src/soc/intel/apollolake/acpi.c | 89 +++++++++++- src/soc/intel/apollolake/include/soc/acpi.h | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 10 ++ src/soc/intel/common/gma.h | 182 +++++++++++++++++++++++++ 6 files changed, 324 insertions(+), 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..e52a5f4 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -54,6 +54,46 @@ static const struct fsp_framebuffer { [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; +/* Reading VBT table from flash */ +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) +{ + size_t vbt_size; + union { + const optionrom_vbt_t *data; + uint32_t *signature; + } vbt; + + /* Locate the vbt file in cbfs */ + vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, + &vbt_size); + if (!vbt.data) { + printk(BIOS_INFO, + "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); + return NULL; + } + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return NULL; + } + *vbt_len = vbt_size; + printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n", + vbt.data, *vbt_len); + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + printk(BIOS_DEBUG, "VBT Data:\n"); + hexdump(vbt.data, *vbt_len); + printk(BIOS_DEBUG, "\n"); +#endif + + /* Return the pointer to the vbt file data */ + return vbt.data; +} + + enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { size_t size; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..fe0e359 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,9 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> + +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a5d1dfa..bdbdfe9 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,12 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +41,78 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } + +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); +} + + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (u32)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,7 +204,16 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); + current = acpi_write_hpet(device, current, rsdp); + + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); + } static void acpi_create_gnvs(struct global_nvs_t *gnvs) diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 3605cc3..1f5663f 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_ACPI_H_ #include <arch/acpi.h> +#include <soc/nvs.h> void soc_fill_common_fadt(acpi_fadt_t * fadt); diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 148640f..458c24e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -41,4 +41,14 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + +/* System Agent Devices */ +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD) + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..1079bc8 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds
by Andrey Petrov 27 Apr '16

27 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14471 -gerrit commit b0e71a8f39d88c60da75257550a1fd97951a119c Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Tue Apr 19 18:04:21 2016 -0700 soc/intel/apollolake: Add handling of GNVS ACPI entry fo CHROMES builds Add chromeos required GNVS feature. The GNVS table stays in both CBMEM and ACPI DSDT tables. Change-Id: I4db0eb18d2de62917a94704318a7896c04e4777f Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/acpi.c | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/acpi/globalnvs.asl | 35 +++++++++++++++++++++++++++ src/soc/intel/apollolake/chip.c | 6 +++++ src/soc/intel/apollolake/include/soc/acpi.h | 2 ++ src/soc/intel/apollolake/include/soc/nvs.h | 37 +++++++++++++++++++++++++++++ src/soc/intel/apollolake/lpc.c | 1 + 6 files changed, 110 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index 7d28313..a5d1dfa 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -16,12 +16,15 @@ */ #include <arch/acpi.h> +#include <arch/acpigen.h> #include <arch/ioapic.h> #include <arch/smp/mpspec.h> +#include <cbmem.h> #include <cpu/x86/smm.h> #include <soc/acpi.h> #include <soc/iomap.h> #include <soc/pm.h> +#include <soc/nvs.h> unsigned long acpi_fill_mcfg(unsigned long current) { @@ -125,3 +128,29 @@ unsigned long southbridge_write_acpi_tables(device_t device, { return acpi_write_hpet(device, current, rsdp); } + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if (IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&gnvs->chromeos); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} + +void southbridge_inject_dsdt(device_t device) +{ + struct global_nvs_t *gnvs; + + gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); + + if (gnvs) { + acpi_create_gnvs(gnvs); + acpi_save_gnvs((uintptr_t)gnvs); + + /* Add it to DSDT. */ + acpigen_write_scope("\\"); + acpigen_write_name_dword("NVSA", (uintptr_t)gnvs); + acpigen_pop_len(); + } +} diff --git a/src/soc/intel/apollolake/acpi/globalnvs.asl b/src/soc/intel/apollolake/acpi/globalnvs.asl new file mode 100644 index 0000000..2ef5031 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/globalnvs.asl @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the GNVS structure below must match the layout in + * soc/intel/apollolake/include/soc/nvs.h !!! + * + */ + +External (NVSA) + +OperationRegion (GNVS, SystemMemory, NVSA, 0x1000) +Field (GNVS, ByteAcc, NoLock, Preserve) +{ + /* Nothing here yet, folks */ + Offset (0x00), + + /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ + Offset (0x100), + #include <vendorcode/google/chromeos/acpi/gnvs.asl> +} diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d2a1e0d..6e0a90f 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -17,6 +17,7 @@ */ #include <bootstate.h> +#include <cbmem.h> #include <console/console.h> #include <cpu/cpu.h> #include <device/device.h> @@ -26,6 +27,7 @@ #include <memrange.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/nvs.h> #include <soc/pci_devs.h> #include "chip.h" @@ -65,11 +67,15 @@ static void enable_dev(device_t dev) static void soc_init(void *data) { struct range_entry range; + struct global_nvs_t *gnvs; /* TODO: tigten this resource range */ /* TODO: fix for S3 resume, as this would corrupt OS memory */ range_entry_init(&range, 0x200000, 4ULL*GiB, 0); fsp_silicon_init(&range); + + /* Allocate ACPI NVS in CBMEM */ + gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs)); } void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd) diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 2d20805..3605cc3 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -25,4 +25,6 @@ void soc_fill_common_fadt(acpi_fadt_t * fadt); unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp); +void southbridge_inject_dsdt(device_t device); + #endif /* _SOC_APOLLOLAKE_ACPI_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/nvs.h b/src/soc/intel/apollolake/include/soc/nvs.h new file mode 100644 index 0000000..8b3a3af --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/nvs.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * NOTE: The layout of the global_nvs_t structure below must match the layout + * in soc/intel/apollolake/acpi/globalnvs.asl !!! + * + */ + +#ifndef _SOC_APOLLOLAKE_NVS_H_ +#define _SOC_APOLLOLAKE_NVS_H_ + +#include <vendorcode/google/chromeos/gnvs.h> + +struct global_nvs_t { + /* Miscellaneous */ + uint8_t unused[256]; + + /* ChromeOS specific (0x100 - 0xfff) */ + chromeos_acpi_t chromeos; +} __attribute__((packed)); + +#endif /* _SOC_APOLLOLAKE_NVS_H_ */ diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index 6e366e0..06ca0db 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -86,6 +86,7 @@ static struct device_operations device_ops = { .set_resources = &pci_dev_set_resources, .enable_resources = &pci_dev_enable_resources, .write_acpi_tables = southbridge_write_acpi_tables, + .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .init = &lpc_init };

1 0

New patch to review for coreboot: nb/intel/gm45: Fix native text mode initialization
by Nick High 26 Apr '16

26 Apr '16

Nick High (nhigh(a)openmailbox.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14524 -gerrit commit 7615ee64ae34f33df008a10945428a66be2ac732 Author: Nick High <nhigh(a)openmailbox.org> Date: Tue Apr 26 17:22:05 2016 -0400 nb/intel/gm45: Fix native text mode initialization The LVDS port is configured to accept data from pipe A, but the panel fitter and VGA were attached to pipe B. Change-Id: I2356f264580d8b021952c217de3477291d866f98 Signed-off-by: Nick High <nhigh(a)openmailbox.org> --- src/northbridge/intel/gm45/gma.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 299cb25..41a1aff 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -340,7 +340,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPESRC(0), (639 << 16) | 399); write32(mmio + PF_CTL(0), PF_ENABLE | PF_FILTER_MED_3x3); write32(mmio + PF_WIN_SZ(0), vactive | (hactive << 16)); - write32(mmio + PFIT_CONTROL, 0xa0000000); + write32(mmio + PFIT_CONTROL, 0x80000000); } mdelay(1); @@ -362,12 +362,12 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info, write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); if (IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)) { - write32(mmio + VGACNTRL, 0x22c4008e | VGA_DISP_DISABLE); + write32(mmio + VGACNTRL, 0x20008e | VGA_DISP_DISABLE); write32(mmio + DSPCNTR(0), DISPLAY_PLANE_ENABLE | DISPPLANE_BGRX888); mdelay(1); } else { - write32(mmio + VGACNTRL, 0x22c4008e); + write32(mmio + VGACNTRL, 0x20008e); } write32(mmio + TRANS_HTOTAL(0),

1 0

Patch set updated for coreboot: board_status: Allow for parsing longopts
by David Hendricks 26 Apr '16

26 Apr '16

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14523 -gerrit commit df71ca282339b97bfab99b0b130aaeb4e879328c Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 26 14:07:42 2016 -0700 board_status: Allow for parsing longopts This converts the argument parsing to allow us to add longopts so that we can keep the shortopts to relatively generic script behavior. Longopts can be used for tweaking specific behaviors. For example, we might wish to change SSH port, timeout, and authentication parameters with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc. This is virtually untested. It would be nice if someone else can hijack this patch to test and clean it up where necessary. Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/board_status/board_status.sh | 41 ++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index b315be1..4807ce7 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -188,30 +188,45 @@ Options " } -while getopts "Chi:r:s:S:u" opt; do - case "$opt" in - h) +# TODO: add longopts in the quotes after -l +ARGS=$(getopt -o Chi:r:s:S:u -l "" -n "$0" -- "$@"); +if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi +eval set -- "$ARGS" +while true ; do + case "$1" in + -h) show_help exit $EXIT_SUCCESS ;; - C) + -C) CLOBBER_OUTPUT=1 ;; - i) - COREBOOT_IMAGE="$OPTARG" + -i) + shift + COREBOOT_IMAGE="$1" ;; - r) - REMOTE_HOST="$OPTARG" + -r) + shift + REMOTE_HOST="$1" ;; - s) - SERIAL_DEVICE="$OPTARG" + -s) + shift + SERIAL_DEVICE="$1" ;; - S) - SERIAL_PORT_SPEED="$OPTARG" + -S) + shift + SERIAL_PORT_SPEED="$1" ;; - u) + -u) UPLOAD_RESULTS=1 ;; + --) + shift + break + ;; + *) + echo "error processing options" + exit $EXIT_FAILURE esac done

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New patch to review for coreboot: board_status: Allow for parsing longopts
by David Hendricks 26 Apr '16

26 Apr '16

David Hendricks (dhendrix(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14523 -gerrit commit 0262bd8f6de1d98d203573a45643608b79d59f12 Author: David Hendricks <dhendrix(a)chromium.org> Date: Tue Apr 26 14:07:42 2016 -0700 board_status: Allow for parsing longopts This converts the argument parsing to allow us to add longopts so that we can keep the shortopts to relatively generic script behavior. Longopts can be used for tweaking specific behaviors. For example, we might wish to change SSH port, timeout, and authentication parameters with "--ssh-port", "--ssh-timeout", "--ssh-identity", etc. This is virtuall untested, it would be nice if someone else can hijack this patch to test and clean it up where necessary. Change-Id: Idee5579079dbbb7296ad98f5d6025b01aab55452 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> --- util/board_status/board_status.sh | 41 ++++++++++++++++++++++++++------------- 1 file changed, 28 insertions(+), 13 deletions(-) diff --git a/util/board_status/board_status.sh b/util/board_status/board_status.sh index b315be1..4807ce7 100755 --- a/util/board_status/board_status.sh +++ b/util/board_status/board_status.sh @@ -188,30 +188,45 @@ Options " } -while getopts "Chi:r:s:S:u" opt; do - case "$opt" in - h) +# TODO: add longopts in the quotes after -l +ARGS=$(getopt -o Chi:r:s:S:u -l "" -n "$0" -- "$@"); +if [ $? != 0 ] ; then echo "Terminating..." >&2 ; exit 1 ; fi +eval set -- "$ARGS" +while true ; do + case "$1" in + -h) show_help exit $EXIT_SUCCESS ;; - C) + -C) CLOBBER_OUTPUT=1 ;; - i) - COREBOOT_IMAGE="$OPTARG" + -i) + shift + COREBOOT_IMAGE="$1" ;; - r) - REMOTE_HOST="$OPTARG" + -r) + shift + REMOTE_HOST="$1" ;; - s) - SERIAL_DEVICE="$OPTARG" + -s) + shift + SERIAL_DEVICE="$1" ;; - S) - SERIAL_PORT_SPEED="$OPTARG" + -S) + shift + SERIAL_PORT_SPEED="$1" ;; - u) + -u) UPLOAD_RESULTS=1 ;; + --) + shift + break + ;; + *) + echo "error processing options" + exit $EXIT_FAILURE esac done

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coreboot-gerrit April 2016