coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Fix northbridge _crs scope
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14477 -gerrit commit f39469a31316f52d48d34e392dec636173faf437 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:19:44 2016 -0700 soc/intel/apollolake: Fix northbridge _crs scope Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 167 +++++++++++++------------- 1 file changed, 84 insertions(+), 83 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 8415ffe..a73a8a9 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -36,97 +36,98 @@ Device (MCHC) Offset(0xBC), TLUD, 32, /* Top of Low Useable DRAM */ } - Name (MCRS, ResourceTemplate() - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,,) - - /* Data and GFX stolen memory */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, - 0x04200000,,, STOM) - - /* - * PCI MMIO Region (TOLUD - PCI extended base MMCONF) - * This assumes that MMCONF is placed after PCI config space, - * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. - */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - }) - - /* Current Resource Settings */ - Method (_CRS, 0, Serialized) - { +} +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, ^PM01._MIN, PMIN) - CreateDwordField (MCRS, ^PM01._MAX, PMAX) - CreateDwordField (MCRS, ^PM01._LEN, PLEN) + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) - /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^TLUD, 0xFFF00000, PMIN) - /* Read MMCONF base */ - And(^MCNF, 0xF0000000, PMAX) + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) - /* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) - /* Find GFX resource area in GCRS */ - CreateDwordField(MCRS, ^STOM._MIN, GMIN) - CreateDwordField(MCRS, ^STOM._MAX, GMAX) - CreateDwordField(MCRS, ^STOM._LEN, GLEN) + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN) - /* Read BGSM */ - And(^BGSM, 0xFFF00000, GMIN) + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) - /* Read TOLUD */ - And(^TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN) - Store (^TUUD, Local0) + Store (^MCHC.TUUD, Local0) - If (LLessEqual (Local0, 0x1000000000)) - { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) + If (LLessEqual (Local0, 0x1000000000)) + { + Store (0, MMIN) + Store (0, MLEN) } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) } +

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Patch set updated for coreboot: soc/intel/apollolake: Add GPIO devices
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14478 -gerrit commit bcd7b946168dbaf2d24339a925a98ea4fcce75db Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Mon Feb 1 16:41:59 2016 -0800 soc/intel/apollolake: Add GPIO devices Add GPIO controller in ACPI device description. GPIO controller driver is probed in kernel and all the pins in the banks are showing respective values. Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 144 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/soc_int.asl | 1 + src/soc/intel/apollolake/acpi/southbridge.asl | 3 + 3 files changed, 148 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl new file mode 100644 index 0000000..4bf0442 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> + +scope (\_SB) { + + Device (GPO0) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTH, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO1) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO2) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_WEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO3) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_SOUTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } +} diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 7db23ee..c7259d0 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -24,6 +24,7 @@ #define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ #define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ #define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 16 #define NPK_INT 16 #define PIRQA_INT 16 #define PIRQB_INT 17 diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 46d7013..0584439 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,3 +20,6 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl"

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Patch set updated for coreboot: soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095 -gerrit commit a83016fa3656075b46e0a144633fa237a1f4e493 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sat Apr 23 13:15:51 2016 -0700 soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage Use postcar infrastructure to enable caching of area where ramstage runs. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 640026a..9dcb26a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,12 +16,14 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <fsp/api.h> #include <fsp/util.h> @@ -81,6 +83,7 @@ asmlinkage void car_stage_entry(void) struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; + uintptr_t top_of_ram; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -122,6 +125,16 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

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Patch set updated for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 81658425a7867cd9d7c43fdb0c58675d02666dd4 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 40 ++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 3 + src/soc/intel/apollolake/acpi.c | 105 ++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 10 ++ src/soc/intel/common/gma.h | 182 +++++++++++++++++++++++++ 6 files changed, 332 insertions(+), 9 deletions(-) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..e52a5f4 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -54,6 +54,46 @@ static const struct fsp_framebuffer { [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; +/* Reading VBT table from flash */ +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) +{ + size_t vbt_size; + union { + const optionrom_vbt_t *data; + uint32_t *signature; + } vbt; + + /* Locate the vbt file in cbfs */ + vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, + &vbt_size); + if (!vbt.data) { + printk(BIOS_INFO, + "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); + return NULL; + } + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return NULL; + } + *vbt_len = vbt_size; + printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n", + vbt.data, *vbt_len); + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + printk(BIOS_DEBUG, "VBT Data:\n"); + hexdump(vbt.data, *vbt_len); + printk(BIOS_DEBUG, "\n"); +#endif + + /* Return the pointer to the vbt file data */ + return vbt.data; +} + + enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { size_t size; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..fe0e359 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,9 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> + +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a300417..cd7937b 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,22 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> + + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +51,78 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } + +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); +} + + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (u32)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,16 +214,15 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); -} + current = acpi_write_hpet(device, current, rsdp); -static void acpi_create_gnvs(struct global_nvs_t *gnvs) -{ - if(IS_ENABLED(CONFIG_CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); } void southbridge_inject_dsdt(device_t device) diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 3605cc3..1f5663f 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_ACPI_H_ #include <arch/acpi.h> +#include <soc/nvs.h> void soc_fill_common_fadt(acpi_fadt_t * fadt); diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 148640f..458c24e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -41,4 +41,14 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + +/* System Agent Devices */ +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD) + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..1079bc8 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

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Patch set updated for coreboot: soc/intel/apollolake: Add cache for BIOS ROM
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14480 -gerrit commit 1aee866b279ddaca3335a781cd27b9085b62f945 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sat Apr 23 12:31:01 2016 -0700 soc/intel/apollolake: Add cache for BIOS ROM Enable caching of BIOS region with variable MTRR. This is most useful if enabled early such as in bootblock. Change-Id: I39f33ca43f06fce26d1d48e706c97f097e3c10f1 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/cpu/x86/mtrr/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/bootblock.c | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 9b7207b..e6e9c50 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1,2 +1,3 @@ ramstage-y += mtrr.c romstage-y += earlymtrr.c +bootblock-y += earlymtrr.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 78ce65f..ff84ae2 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -16,7 +16,9 @@ */ #include <arch/cpu.h> #include <bootblock_common.h> +#include <cpu/x86/mtrr.h> #include <device/pci.h> +#include <lib.h> #include <soc/bootblock.h> #include <soc/cpu.h> #include <soc/gpio.h> @@ -75,6 +77,24 @@ void asmlinkage bootblock_c_entry(void) main(); } +static void cache_bios_region(void) +{ + int mtrr; + uint32_t rom_size, alignment; + + mtrr = get_free_var_mtrr(); + + if (mtrr==-1) + return; + + /* Only the IFD BIOS region is memory mapped (at top of 4G) */ + rom_size = CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START; + /* Round to power of two */ + alignment = 1 << (log2_ceil(rom_size)); + rom_size = ALIGN_UP(rom_size, alignment); + set_var_mtrr(mtrr, 4ULL*GiB - rom_size, rom_size, MTRR_TYPE_WRPROT); +} + void bootblock_soc_early_init(void) { /* Prepare UART for serial console. */ @@ -87,4 +107,5 @@ void bootblock_soc_early_init(void) if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)) early_lpc_enable(); + cache_bios_region(); }

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add GPIO devices
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14478 -gerrit commit d97654439f8b43679fc7f06f964af6095396662f Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Mon Feb 1 16:41:59 2016 -0800 soc/intel/apollolake: Add GPIO devices Add GPIO controller in ACPI device description. GPIO controller driver is probed in kernel and all the pins in the banks are showing respective values. Change-Id: I0512cfec872113b15fd204ec3b95efeac87f694a Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy(a)intel.com> --- src/soc/intel/apollolake/acpi/gpio.asl | 144 ++++++++++++++++++++++++++ src/soc/intel/apollolake/acpi/soc_int.asl | 1 + src/soc/intel/apollolake/acpi/southbridge.asl | 3 + 3 files changed, 148 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/gpio.asl b/src/soc/intel/apollolake/acpi/gpio.asl new file mode 100644 index 0000000..73e193e --- /dev/null +++ b/src/soc/intel/apollolake/acpi/gpio.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <soc/gpio_defs.h> + +scope (\_SB) { + + Device (GPO0) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - North" ) + Name (_UID, 1) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTH, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO1) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Northwest" ) + Name (_UID, 2) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_NORTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO2) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - West" ) + Name (_UID, 3) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_WEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } + + Device (GPO3) + { + Name (_ADR, 0) + Name (_HID, "INT3452") + Name (_CID, "INT3452") + Name (_DDN, "General Purpose Input/Output (GPIO) Controller - Southwest" ) + Name (_UID, 4) + + Name (RBUF, ResourceTemplate () + { + Memory32Fixed (ReadWrite, 0, 0x4000, RMEM) + Interrupt (ResourceConsumer, Level, ActiveLow, Shared, , , ) + { + GPIO_BANK_INT + } + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateDwordField (^RBUF, ^RMEM._BAS, RBAS) + ShiftLeft (GPIO_SOUTHWEST, 16, Local0) + Or (CONFIG_IOSF_BASE_ADDRESS, Local0, RBAS) + Return (^RBUF) + } + + Method (_STA, 0x0, NotSerialized) + { + Return(0xf) + } + } +} diff --git a/src/soc/intel/apollolake/acpi/soc_int.asl b/src/soc/intel/apollolake/acpi/soc_int.asl index 7db23ee..c7259d0 100644 --- a/src/soc/intel/apollolake/acpi/soc_int.asl +++ b/src/soc/intel/apollolake/acpi/soc_int.asl @@ -24,6 +24,7 @@ #define UART2_INT 6 /* Need to be shared by PMC and SCC only*/ #define UART3_INT 7 /* Need to be shared by PMC and SCC only*/ #define XDCI_INT 13 /* Need to be shared by PMC and SCC only*/ +#define GPIO_BANK_INT 16 #define NPK_INT 16 #define PIRQA_INT 16 #define PIRQB_INT 17 diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index 46d7013..0584439 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,3 +20,6 @@ /* PCI IRQ assignment */ #include "pci_irqs.asl" + +/* GPIO controller */ +#include "gpio.asl"

1 0

Patch set updated for coreboot: soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095 -gerrit commit 3a05d06de4ebff3a7b6780438938c2ca7c4b094c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sat Apr 23 13:15:51 2016 -0700 soc/intel/apollolake: Enable RAM cache for cbmem region in ramstage Use postcar infrastructure to enable caching of area where ramstage runs. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 640026a..9dcb26a 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -16,12 +16,14 @@ * GNU General Public License for more details. */ +#include <assert.h> #include <arch/cpu.h> #include <arch/io.h> #include <arch/symbols.h> #include <cbfs.h> #include <cbmem.h> #include <console/console.h> +#include <cpu/x86/mtrr.h> #include <device/pci_def.h> #include <fsp/api.h> #include <fsp/util.h> @@ -81,6 +83,7 @@ asmlinkage void car_stage_entry(void) struct range_entry fsp_mem, reg_car; struct postcar_frame pcf; size_t mrc_data_size; + uintptr_t top_of_ram; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -122,6 +125,16 @@ asmlinkage void car_stage_entry(void) if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); + /* + * We need to make sure ramstage will be run cached. At this point exact + * location of ramstage in cbmem is not known. Instruct postcar to cache + * 16 megs under cbmem top which is a safe bet to cover ramstage. + */ + top_of_ram = (uintptr_t) cbmem_top(); + /* cbmem_top() needs to be at least 16 MiB aligned */ + assert(ALIGN_DOWN(top_of_ram, 16*MiB) == top_of_ram); + postcar_frame_add_mtrr(&pcf, top_of_ram - 16*MiB, 16*MiB, MTRR_TYPE_WRBACK); + run_postcar_phase(&pcf); }

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New patch to review for coreboot: payloads: Add a stable version of Memtest86+ for reproducibility
by Martin Roth 26 Apr '16

26 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14520 -gerrit commit 4750ee1e2b43f8ebe04e3f43cb09a89f1f8d4500 Author: Martin Roth <martinroth(a)google.com> Date: Tue Apr 26 09:51:41 2016 -0600 payloads: Add a stable version of Memtest86+ for reproducibility Memtest86+ was pulling origin/master which will change over time. This adds a commit-id as a stable version to allow it to be reproducible. The other secondary payloads, coreinfo and nvramcui, do not need this because they are part of the coreboot repo and not fetched from an external source. Change-Id: I20c516010f76cf03342bd8883d0ee7ac5f8bc7e4 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/Kconfig | 21 +++++++++++++++++++++ payloads/external/Makefile.inc | 2 ++ payloads/external/Memtest86Plus/Makefile | 8 +++++--- 3 files changed, 28 insertions(+), 3 deletions(-) diff --git a/payloads/Kconfig b/payloads/Kconfig index 00d5d88..6c178d4 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -77,6 +77,27 @@ config MEMTEST_SECONDARY_PAYLOAD Memtest86+ can be loaded as a secondary payload under SeaBIOS, GRUB, or any other payload that can load additional payloads. +choice + prompt "Memtest86+ version" + default MEMTEST_STABLE + depends on MEMTEST_SECONDARY_PAYLOAD + +config MEMTEST_STABLE + bool "Stable" + help + Stable Memtest86+ version. + + For reproducible builds, this option must be selected. +config MEMTEST_MASTER + bool "Master" + help + Newest Memtest86+ version. + + This option will fetch the newest version of the Memtest86+ code, + updating as new changes are committed. This makes the build + non-reproducible, as it can fetch different code each time. +endchoice + config NVRAMCUI_SECONDARY_PAYLOAD bool "Load nvramcui as a secondary payload" default n diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 26a5613..5ae9f7e 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -122,6 +122,8 @@ payloads/external/Memtest86Plus/memtest86plus/memtest: $(top)/$(DOTCONFIG) LD="$(LD_x86_32)" \ OBJCOPY="$(OBJCOPY_x86_32)" \ AS="$(AS_x86_32)" \ + CONFIG_MEMTEST_MASTER=$(CONFIG_MEMTEST_MASTER) \ + CONFIG_MEMTEST_STABLE=$(CONFIG_MEMTEST_STABLE) \ $(MEMTEST_SERIAL_OPTIONS) \ MFLAGS= MAKEFLAGS= diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index f77fa38..90ea5e8 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -13,8 +13,10 @@ ## GNU General Public License for more details. ## -TAG-y=origin/master -NAME-y=MASTER +TAG-$(CONFIG_MEMTEST_MASTER)=origin/master +NAME-$(CONFIG_MEMTEST_MASTER)=Master +TAG-$(CONFIG_MEMTEST_STABLE)=ca352c9a6bd8c1bba16ea22cbfc7028d97bacec9 +NAME-$(CONFIG_MEMTEST_STABLE)=Stable project_name=Memtest86+ project_dir=$(CURDIR)/memtest86plus @@ -33,7 +35,7 @@ fetch: $(project_dir) git fetch; fi checkout: fetch - echo " Checking out $(project_name) revision $(NAME-y)" + echo " Checking out $(project_name) revision $(NAME-y) ($(TAG-y))" cd $(project_dir); \ git checkout master; \ git branch -D coreboot 2>/dev/null; \

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Patch set updated for coreboot: Memtest86Plus/Makefile: Update to common payload makefile format
by Martin Roth 26 Apr '16

26 Apr '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14152 -gerrit commit 4f498067f77a3338d907df5ba06ed02195b45b23 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:00:37 2016 -0600 Memtest86Plus/Makefile: Update to common payload makefile format This series of patches attempts to update all of the external payload makefiles to be as similar as possible. - Add .git to the git repo URL to show that it's a git repo. - Use the common checkout, fetch, and clone ($(project dir)) targets - Add TAG-y and NAME-y variables - just with origin/master for now. Stable will be added shortly. - Make sure all phony targets are in .PHONY Change-Id: If83c100841d5f91a9fab7ac44ba20ec2271c0594 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Memtest86Plus/Makefile | 24 +++++++++++++++++------- 1 file changed, 17 insertions(+), 7 deletions(-) diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index db8a51d..f77fa38 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -13,9 +13,12 @@ ## GNU General Public License for more details. ## +TAG-y=origin/master +NAME-y=MASTER + project_name=Memtest86+ project_dir=$(CURDIR)/memtest86plus -project_git_repo=https://review.coreboot.org/memtest86plus +project_git_repo=https://review.coreboot.org/memtest86plus.git all: build @@ -24,13 +27,20 @@ $(project_dir): git clone $(project_git_repo) $(project_dir) fetch: $(project_dir) + -cd $(project_dir); git show $(TAG-y) >/dev/null 2>&1 ; \ + if [ $$? -ne 0 ] || [ "$(TAG-y)" = "origin/master" ]; then \ + echo " Fetching new commits from the $(project_name) git repo"; \ + git fetch; fi + +checkout: fetch + echo " Checking out $(project_name) revision $(NAME-y)" cd $(project_dir); \ - test -e '.git' && \ - git fetch && \ - git checkout origin/master + git checkout master; \ + git branch -D coreboot 2>/dev/null; \ + git checkout -b coreboot $(TAG-y) -build: fetch - echo " MAKE $(project_name)" +build: checkout + echo " MAKE $(project_name) $(NAME-y)" $(MAKE) -C $(project_dir) all clean: @@ -42,4 +52,4 @@ distclean: print-repo-info: echo "$(project_git_repo) $(project_dir)" -.PHONY: all build fetch clean distclean print-repo-info +.PHONY: all build checkout clean distclean fetch print-repo-info

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New patch to review for coreboot: soc/intel/apollolake: Add opregion code to pass vbt in kernel.
by Andrey Petrov 26 Apr '16

26 Apr '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14519 -gerrit commit 6082d03cca94ea44cf3230a6cc3e568389b31622 Author: Abhay Kumar <abhay.kumar(a)intel.com> Date: Tue Mar 15 16:16:44 2016 -0700 soc/intel/apollolake: Add opregion code to pass vbt in kernel. Change-Id: I47d01a56d242f0d3fcdb0fc5146500210ea6f48c Signed-off-by: Abhay Kumar <abhay.kumar(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 40 ++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 3 + src/soc/intel/apollolake/acpi.c | 105 ++++++++++++-- src/soc/intel/apollolake/include/soc/acpi.h | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 10 ++ src/soc/intel/common/gma.h | 182 +++++++++++++++++++++++++ 6 files changed, 332 insertions(+), 9 deletions(-) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c index 1480179..e52a5f4 100644 --- a/src/drivers/intel/fsp2_0/graphics.c +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -54,6 +54,46 @@ static const struct fsp_framebuffer { [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, }; +/* Reading VBT table from flash */ +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len) +{ + size_t vbt_size; + union { + const optionrom_vbt_t *data; + uint32_t *signature; + } vbt; + + /* Locate the vbt file in cbfs */ + vbt.data = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, + &vbt_size); + if (!vbt.data) { + printk(BIOS_INFO, + "FSP_INFO: VBT data file (vbt.bin) not found in CBFS"); + return NULL; + } + + /* Validate the vbt file */ + if (*vbt.signature != VBT_SIGNATURE) { + printk(BIOS_WARNING, + "FSP_WARNING: Invalid signature in VBT data file (vbt.bin)!\n"); + return NULL; + } + *vbt_len = vbt_size; + printk(BIOS_DEBUG, "FSP_INFO: VBT found at %p, 0x%08x bytes\n", + vbt.data, *vbt_len); + +#if IS_ENABLED(CONFIG_DISPLAY_VBT) + /* Display the vbt file contents */ + printk(BIOS_DEBUG, "VBT Data:\n"); + hexdump(vbt.data, *vbt_len); + printk(BIOS_DEBUG, "\n"); +#endif + + /* Return the pointer to the vbt file data */ + return vbt.data; +} + + enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) { size_t size; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index d9d9539..fe0e359 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -16,6 +16,9 @@ #include <boot/coreboot_tables.h> #include <fsp/info_header.h> #include <memrange.h> +#include <soc/intel/common/gma.h> + +const optionrom_vbt_t *fsp_get_vbt(uint32_t *vbt_len); /* * Hand-off-block handling functions that depend on CBMEM, and thus can only diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index a300417..cd7937b 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -25,6 +25,22 @@ #include <soc/iomap.h> #include <soc/pm.h> #include <soc/nvs.h> +#include <vendorcode/google/chromeos/gnvs.h> +#include <fsp/util.h> +#include <soc/pci_ids.h> +#include <string.h> +#include <fsp/util.h> +#include <device/pci.h> + + +static void acpi_create_gnvs(struct global_nvs_t *gnvs) +{ + if(IS_ENABLED(CONFIG_CHROMEOS)) { + /* Initialize Verified Boot data */ + chromeos_init_vboot(&(gnvs->chromeos)); + gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; + } +} unsigned long acpi_fill_mcfg(unsigned long current) { @@ -35,6 +51,78 @@ unsigned long acpi_fill_mcfg(unsigned long current) return current; } + +/* Reading VBT table from flash */ +static void get_fsp_vbt(igd_opregion_t *opregion) +{ + const optionrom_vbt_t *vbt; + uint32_t vbt_len; + + vbt = fsp_get_vbt(&vbt_len); + if (!vbt) + die("vbt data not found"); + memcpy(opregion->header.vbios_version, vbt->coreblock_biosbuild, 4); + memcpy(opregion->vbt.gvd1, vbt, vbt->hdr_vbt_size < + sizeof(opregion->vbt.gvd1) ? vbt->hdr_vbt_size : + sizeof(opregion->vbt.gvd1)); +} + + +static int init_igd_opregion(igd_opregion_t *opregion) +{ + device_t igd; + u16 reg16; + + memset(opregion, 0, sizeof(igd_opregion_t)); + + /* FIXME if IGD is disabled, we should exit here. */ + + memcpy(&opregion->header.signature, IGD_OPREGION_SIGNATURE, + sizeof(IGD_OPREGION_SIGNATURE)); + + /* 8kb */ + opregion->header.size = sizeof(igd_opregion_t) / 1024; + opregion->header.version = IGD_OPREGION_VERSION; + + /* FIXME We just assume we're mobile for now */ + opregion->header.mailboxes = MAILBOXES_MOBILE; + + /* TODO Initialize Mailbox 1 */ + + /* TODO Initialize Mailbox 3 */ + opregion->mailbox3.bclp = IGD_BACKLIGHT_BRIGHTNESS; + opregion->mailbox3.pfit = IGD_FIELD_VALID | IGD_PFIT_STRETCH; + opregion->mailbox3.pcft = 0; /* should be (IMON << 1) & 0x3e */ + opregion->mailbox3.cblv = IGD_FIELD_VALID | IGD_INITIAL_BRIGHTNESS; + opregion->mailbox3.bclm[0] = IGD_WORD_FIELD_VALID + 0x0000; + opregion->mailbox3.bclm[1] = IGD_WORD_FIELD_VALID + 0x0a19; + opregion->mailbox3.bclm[2] = IGD_WORD_FIELD_VALID + 0x1433; + opregion->mailbox3.bclm[3] = IGD_WORD_FIELD_VALID + 0x1e4c; + opregion->mailbox3.bclm[4] = IGD_WORD_FIELD_VALID + 0x2866; + opregion->mailbox3.bclm[5] = IGD_WORD_FIELD_VALID + 0x327f; + opregion->mailbox3.bclm[6] = IGD_WORD_FIELD_VALID + 0x3c99; + opregion->mailbox3.bclm[7] = IGD_WORD_FIELD_VALID + 0x46b2; + opregion->mailbox3.bclm[8] = IGD_WORD_FIELD_VALID + 0x50cc; + opregion->mailbox3.bclm[9] = IGD_WORD_FIELD_VALID + 0x5ae5; + opregion->mailbox3.bclm[10] = IGD_WORD_FIELD_VALID + 0x64ff; + + get_fsp_vbt(opregion); + + /* + * TODO This needs to happen in S3 resume, too. + * Maybe it should move to the finalize handler + */ + igd = dev_find_slot(0, PCI_DEVFN(GFX_DEV, GFX_FUNC)); + + pci_write_config32(igd, ASLS, (u32)opregion); + reg16 = pci_read_config16(igd, SWSCI); + reg16 &= ~(1 << 0); + reg16 |= (1 << 15); + pci_write_config16(igd, SWSCI, reg16); + + return 0; +} + static int acpi_sci_irq(void) { int sci_irq = 9; @@ -126,16 +214,15 @@ unsigned long southbridge_write_acpi_tables(device_t device, unsigned long current, struct acpi_rsdp *rsdp) { - return acpi_write_hpet(device, current, rsdp); -} + current = acpi_write_hpet(device, current, rsdp); -static void acpi_create_gnvs(struct global_nvs_t *gnvs) -{ - if(IS_ENABLED(CONFIG_CHROMEOS)) { - /* Initialize Verified Boot data */ - chromeos_init_vboot(&(gnvs->chromeos)); - gnvs->chromeos.vbt2 = ACTIVE_ECFW_RO; - } + igd_opregion_t *opregion; + printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n"); + opregion = (igd_opregion_t *)current; + init_igd_opregion(opregion); + current += sizeof(igd_opregion_t); + + return acpi_align_current(current); } void southbridge_inject_dsdt(device_t device) diff --git a/src/soc/intel/apollolake/include/soc/acpi.h b/src/soc/intel/apollolake/include/soc/acpi.h index 3605cc3..1f5663f 100644 --- a/src/soc/intel/apollolake/include/soc/acpi.h +++ b/src/soc/intel/apollolake/include/soc/acpi.h @@ -19,6 +19,7 @@ #define _SOC_APOLLOLAKE_ACPI_H_ #include <arch/acpi.h> +#include <soc/nvs.h> void soc_fill_common_fadt(acpi_fadt_t * fadt); diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 148640f..458c24e 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -41,4 +41,14 @@ #define PCI_DEVICE_ID_APOLLOLAKE_SPI2 0x5ac6 /* 00:19.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_LPC 0x5ae8 /* 00:1f.0 */ +/* Graphics and Display */ +#define GFX_DEV 0x2 +#define GFX_FUNC 0 +#define GFX_DEVID 0x5a84 + +/* System Agent Devices */ +#define SA_DEV_SLOT_IGD 0x02 +#define SA_DEVFN_IGD _SA_DEVFN(IGD) +#define SA_DEV_IGD _SA_DEV(IGD) + #endif /* _SOC_APOLLOLAKE_PCI_IDS_H_ */ diff --git a/src/soc/intel/common/gma.h b/src/soc/intel/common/gma.h new file mode 100644 index 0000000..1079bc8 --- /dev/null +++ b/src/soc/intel/common/gma.h @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Chromium OS Authors + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#ifndef _GMA_H_ +#define _GMA_H_ + +#include <types.h> + +/* IGD PCI Configuration register */ +#define ASLS 0xfc /* OpRegion Base */ +#define SWSCI 0xe8 /* SWSCI Register */ +#define GSSCIE (1 << 0) /* SCI Event trigger */ +#define SMISCISEL (1 << 15) /* Select SMI or SCI event source */ + +/* mailbox 0: header */ +typedef struct { + u8 signature[16]; + u32 size; + u32 version; + u8 sbios_version[32]; + u8 vbios_version[16]; + u8 driver_version[16]; + u32 mailboxes; + u8 reserved[164]; +} __attribute__((packed)) opregion_header_t; + +#define IGD_OPREGION_SIGNATURE "IntelGraphicsMem" +#define IGD_OPREGION_VERSION 2 + +#define IGD_MBOX1 (1 << 0) +#define IGD_MBOX2 (1 << 1) +#define IGD_MBOX3 (1 << 2) +#define IGD_MBOX4 (1 << 3) +#define IGD_MBOX5 (1 << 4) + +#define MAILBOXES_MOBILE (IGD_MBOX1 | IGD_MBOX2 | IGD_MBOX3 | \ + IGD_MBOX4 | IGD_MBOX5) +#define MAILBOXES_DESKTOP (IGD_MBOX2 | IGD_MBOX4) + +#define SBIOS_VERSION_SIZE 32 + +/* mailbox 1: public acpi methods */ +typedef struct { + u32 drdy; + u32 csts; + u32 cevt; + u8 reserved1[20]; + u32 didl[8]; + u32 cpdl[8]; + u32 cadl[8]; + u32 nadl[8]; + u32 aslp; + u32 tidx; + u32 chpd; + u32 clid; + u32 cdck; + u32 sxsw; + u32 evts; + u32 cnot; + u32 nrdy; + u8 reserved2[60]; +} __attribute__((packed)) opregion_mailbox1_t; + +/* mailbox 2: software sci interface */ +typedef struct { + u32 scic; + u32 parm; + u32 dslp; + u8 reserved[244]; +} __attribute__((packed)) opregion_mailbox2_t; + +/* mailbox 3: power conservation */ +typedef struct { + u32 ardy; + u32 aslc; + u32 tche; + u32 alsi; + u32 bclp; + u32 pfit; + u32 cblv; + u16 bclm[20]; + u32 cpfm; + u32 epfm; + u8 plut[74]; + u32 pfmb; + u32 ccdv; + u32 pcft; + u8 reserved[94]; +} __attribute__((packed)) opregion_mailbox3_t; + +#define IGD_BACKLIGHT_BRIGHTNESS 0xff +#define IGD_INITIAL_BRIGHTNESS 0x64 + +#define IGD_FIELD_VALID (1 << 31) +#define IGD_WORD_FIELD_VALID (1 << 15) +#define IGD_PFIT_STRETCH 6 + +/* mailbox 4: vbt */ +typedef struct { + u8 gvd1[7168]; +} __attribute__((packed)) opregion_vbt_t; + +/* IGD OpRegion */ +typedef struct { + opregion_header_t header; + opregion_mailbox1_t mailbox1; + opregion_mailbox2_t mailbox2; + opregion_mailbox3_t mailbox3; + opregion_vbt_t vbt; +} __attribute__((packed)) igd_opregion_t; + +/* Intel Video BIOS (Option ROM) */ +typedef struct { + u16 signature; + u8 size; + u8 reserved[21]; + u16 pcir_offset; + u16 vbt_offset; +} __attribute__((packed)) optionrom_header_t; + +#define OPROM_SIGNATURE 0xaa55 + +typedef struct { + u32 signature; + u16 vendor; + u16 device; + u16 reserved1; + u16 length; + u8 revision; + u8 classcode[3]; + u16 imagelength; + u16 coderevision; + u8 codetype; + u8 indicator; + u16 reserved2; +} __attribute__((packed)) optionrom_pcir_t; + +typedef struct { + u8 hdr_signature[20]; + u16 hdr_version; + u16 hdr_size; + u16 hdr_vbt_size; + u8 hdr_vbt_checksum; + u8 hdr_reserved; + u32 hdr_vbt_datablock; + u32 hdr_aim[4]; + u8 datahdr_signature[16]; + u16 datahdr_version; + u16 datahdr_size; + u16 datahdr_datablocksize; + u8 coreblock_id; + u16 coreblock_size; + u16 coreblock_biossize; + u8 coreblock_biostype; + u8 coreblock_releasestatus; + u8 coreblock_hwsupported; + u8 coreblock_integratedhw; + u8 coreblock_biosbuild[4]; + u8 coreblock_biossignon[155]; +} __attribute__((packed)) optionrom_vbt_t; + +#define VBT_SIGNATURE 0x54425624 + +#endif /* _GMA_H_ */ +

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coreboot-gerrit April 2016