coreboot-gerrit April 2016

coreboot-gerrit@coreboot.org

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1270 discussions

New patch to review for coreboot: Add board URLs for the RISC-V boards
by Jonathan Neuschäfer 26 Apr '16

26 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14518 -gerrit commit 2b92a5cd539a8c3a40cf1d2062f33a6d1af5bc99 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Apr 26 16:40:55 2016 +0200 Add board URLs for the RISC-V boards Change-Id: Ifdf40986c2407d8c5b0097654b42e056f4498d39 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/qemu-riscv/board_info.txt | 1 + src/mainboard/emulation/spike-riscv/board_info.txt | 1 + 2 files changed, 2 insertions(+) diff --git a/src/mainboard/emulation/qemu-riscv/board_info.txt b/src/mainboard/emulation/qemu-riscv/board_info.txt index 811e8e0..4d8dcaa 100644 --- a/src/mainboard/emulation/qemu-riscv/board_info.txt +++ b/src/mainboard/emulation/qemu-riscv/board_info.txt @@ -1,2 +1,3 @@ Board name: QEMU RISCV Category: emulation +Board URL: https://github.com/riscv/riscv-qemu diff --git a/src/mainboard/emulation/spike-riscv/board_info.txt b/src/mainboard/emulation/spike-riscv/board_info.txt index a1d11f9..37a0ae9 100644 --- a/src/mainboard/emulation/spike-riscv/board_info.txt +++ b/src/mainboard/emulation/spike-riscv/board_info.txt @@ -1,2 +1,3 @@ Board name: Spike RISCV Category: emulation +Board URL: https://github.com/riscv/riscv-isa-sim

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New patch to review for coreboot: Fix "Spike RISCV" board name
by Jonathan Neuschäfer 26 Apr '16

26 Apr '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14517 -gerrit commit 76b98ec78d82e36dda4bcf5a5fde0d81821c96ed Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Tue Apr 26 16:40:55 2016 +0200 Fix "Spike RISCV" board name Change-Id: If0f835e69862a78433e7c1a34efa4706cc27b214 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/spike-riscv/board_info.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/emulation/spike-riscv/board_info.txt b/src/mainboard/emulation/spike-riscv/board_info.txt index 811e8e0..a1d11f9 100644 --- a/src/mainboard/emulation/spike-riscv/board_info.txt +++ b/src/mainboard/emulation/spike-riscv/board_info.txt @@ -1,2 +1,2 @@ -Board name: QEMU RISCV +Board name: Spike RISCV Category: emulation

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Patch merged into coreboot/master: mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage
by gerrit＠coreboot.org 26 Apr '16

26 Apr '16

the following patch was just integrated into master: commit 99e27ceb6d913a7a882cc6e7277b881df38dc9ad Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 24 20:33:29 2016 -0500 mainboard/kgpe-d16|kcma-d8: Update memory test to include second PRNG stage The existing memory test routine was insufficient to detect certain types of bus instability related to multiple incompatible RDIMMs on one channel. Add a PRNG second stage test to the memory test routine. This second stage test reliably detects faults in memory setup for RDIMM configurations that also fail under the proprietary BIOS. Change-Id: I44721447ce4c2b728d4a8f328ad1a3eb8f324d3d Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14502 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14502 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines
by gerrit＠coreboot.org 26 Apr '16

26 Apr '16

the following patch was just integrated into master: commit 0739b9fe85142051bb121c74ce9436ed030e7347 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 24 20:27:28 2016 -0500 nb/amd/mct_ddr3: Report correct DIMM in MRS setup routines The wrong DIMM number was used in the initial non-target MRS setup routines. This had no functional impact other than to print the wrong DIMM number in the DDR3 verbose debug output. Change-Id: I480118ed00e1786a06e641a56f0fb19cd87f92eb Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14501 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14501 for details. -gerrit

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup
by gerrit＠coreboot.org 26 Apr '16

26 Apr '16

the following patch was just integrated into master: commit 3242bcfa0feb50160dc0e6059216a5c1a0626031 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 24 20:22:28 2016 -0500 nb/amd/mct_ddr3: Fix a number of minor errors in RDIMM setup The existing RDIMM RC control word send routines were a hodgepodge of various AGESA chunks with different ways of handling the same task. Unify the control word chip select setup, use precise timing routines on Family 15h, fix a couple of incorrect masks, and add additional debugging statements. It is believed that this patch is cosmetic and does not significantly alter existing functionality. Change-Id: Ie4ec7b6a7be7fce09e89f9eec146cc98b15b6160 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14500 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14500 for details. -gerrit

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New patch to review for coreboot: siemens/mc_bdx1: Add new mainboard.
by Werner Zeh 26 Apr '16

26 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14516 -gerrit commit e821d45a1a20e1dab89f2d191836768cc174eb3a Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Apr 20 10:08:17 2016 +0200 siemens/mc_bdx1: Add new mainboard. Add new mainboard for MC BDX1 board which is based on Intel Camelback Mountain. This mainboard is an industry type board and has several Ethernet interfaces among with two USB3.0 connectors. It uses 24V DC power supply and has its own form factor which do not match any standard. This commit adds the new mainboard and prepares the Kconfig envirnoment so that this board can be selected and generated. Although the generated image can boot into Linux and DOS, not all functions are implemented yet. Forthcoming commits will add more functionality. Change-Id: I29011cfd3b0d13bcf163223f657e02f69978e39a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_bdx1/Kconfig | 52 ++++ src/mainboard/siemens/mc_bdx1/Kconfig.name | 2 + src/mainboard/siemens/mc_bdx1/Makefile.inc | 16 ++ src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl | 20 ++ src/mainboard/siemens/mc_bdx1/acpi/platform.asl | 56 +++++ src/mainboard/siemens/mc_bdx1/acpi_tables.c | 43 ++++ src/mainboard/siemens/mc_bdx1/board_info.txt | 5 + src/mainboard/siemens/mc_bdx1/cmos.layout | 128 ++++++++++ src/mainboard/siemens/mc_bdx1/devicetree.cb | 15 ++ src/mainboard/siemens/mc_bdx1/dsdt.asl | 293 +++++++++++++++++++++++ src/mainboard/siemens/mc_bdx1/fadt.c | 29 +++ src/mainboard/siemens/mc_bdx1/irqroute.c | 18 ++ src/mainboard/siemens/mc_bdx1/irqroute.h | 48 ++++ src/mainboard/siemens/mc_bdx1/mainboard.c | 44 ++++ src/mainboard/siemens/mc_bdx1/romstage.c | 45 ++++ 15 files changed, 814 insertions(+) diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig new file mode 100644 index 0000000..e33b14a --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -0,0 +1,52 @@ +if BOARD_SIEMENS_MC_BDX1 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_FSP_BROADWELL_DE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select TSC_MONOTONIC_TIMER + select HAVE_FSP_BIN if FSP_PACKAGE_DEFAULT + select CBFS_AUTOGEN_ATTRIBUTES + +config MAINBOARD_DIR + string + default "siemens/mc_bdx1" + +config MAINBOARD_PART_NUMBER + string + default "MC BDX1" + +config IRQ_SLOT_COUNT + int + default 18 + +config CACHE_ROM_SIZE_OVERRIDE + hex + default 0x1000000 + +config CBFS_SIZE + hex + default 0x00D00000 + +config VIRTUAL_ROM_SIZE + hex + default 0x1000000 + +config CONSOLE_POST + bool + default y + +config INTEGRATED_UART + bool + default n + +config DRIVERS_UART_8250IO + def_bool y + +config FSP_PACKAGE_DEFAULT + bool "Configure defaults for the Intel FSP package" + default n + +endif # BOARD_SIEMENS_MC_BDX1 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig.name b/src/mainboard/siemens/mc_bdx1/Kconfig.name new file mode 100644 index 0000000..b37cee3 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_SIEMENS_MC_BDX1 + bool "MC BDX1" diff --git a/src/mainboard/siemens/mc_bdx1/Makefile.inc b/src/mainboard/siemens/mc_bdx1/Makefile.inc new file mode 100644 index 0000000..e7de261 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2012 Google Inc. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-y += irqroute.c \ No newline at end of file diff --git a/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl b/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl new file mode 100644 index 0000000..62944ef --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/acpi/mainboard.asl @@ -0,0 +1,20 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PWRB) +{ + Name(_HID, EisaId("PNP0C0C")) +} diff --git a/src/mainboard/siemens/mc_bdx1/acpi/platform.asl b/src/mainboard/siemens/mc_bdx1/acpi/platform.asl new file mode 100644 index 0000000..7ffae2e --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/acpi/platform.asl @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* The APM port can be used for generating software SMIs */ + +OperationRegion (APMP, SystemIO, 0xb2, 2) +Field (APMP, ByteAcc, NoLock, Preserve) +{ + APMC, 8, // APM command + APMS, 8 // APM status +} + +/* Port 80 POST */ + +OperationRegion (POST, SystemIO, 0x80, 1) +Field (POST, ByteAcc, Lock, Preserve) +{ + DBG0, 8 +} + +Name(\APC1, Zero) // IIO IOAPIC + +Name(\PICM, Zero) // IOAPIC/8259 + +Method(_PIC, 1) +{ + Store(Arg0, PICM) +} + +/* The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0 + */ + +Method(_PTS,1) +{ +} + +/* The _WAK method is called on system wakeup */ + +Method(_WAK,1) +{ + Return(Package(){0,0}) +} diff --git a/src/mainboard/siemens/mc_bdx1/acpi_tables.c b/src/mainboard/siemens/mc_bdx1/acpi_tables.c new file mode 100644 index 0000000..0197def --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/acpi_tables.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/ioapic.h> +#include <soc/acpi.h> +#include <soc/iomap.h> + +extern const unsigned char AmlCode[]; + +unsigned long acpi_fill_madt(unsigned long current) +{ + u32 i; + + current = acpi_create_madt_lapics(current); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 8, + IOXAPIC1_BASE_ADDRESS, 0); + set_ioapic_id((u8 *)IOXAPIC1_BASE_ADDRESS, 8); + + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, 9, + IOXAPIC2_BASE_ADDRESS, 24); + set_ioapic_id((u8 *)IOXAPIC2_BASE_ADDRESS, 9); + + current = acpi_madt_irq_overrides(current); + + for (i = 0; i < 16; i++) + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, i, 0xD, 1); + + return current; +} diff --git a/src/mainboard/siemens/mc_bdx1/board_info.txt b/src/mainboard/siemens/mc_bdx1/board_info.txt new file mode 100644 index 0000000..15b66c1 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/board_info.txt @@ -0,0 +1,5 @@ +Board name: MC BDX1 +Category: misc +ROM protocol: SPI +ROM socketed: no +Release year: 2016 diff --git a/src/mainboard/siemens/mc_bdx1/cmos.layout b/src/mainboard/siemens/mc_bdx1/cmos.layout new file mode 100644 index 0000000..9ff9d1f --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/cmos.layout @@ -0,0 +1,128 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007-2008 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# ----------------------------------------------------------------- +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +# ----------------------------------------------------------------- +# Status Register A +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +# ----------------------------------------------------------------- +# Status Register B +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +385 1 e 4 last_boot +388 4 r 0 reboot_bits +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +392 3 e 5 baud_rate +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +#411 5 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb new file mode 100644 index 0000000..30d99c2 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/devicetree.cb @@ -0,0 +1,15 @@ +chip soc/intel/fsp_broadwell_de + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + device pci 00.0 on end # SoC router + device pci 14.0 on end # xHCI Controller + device pci 19.0 on end # Gigabit LAN Controller + device pci 1d.0 on end # EHCI Controller + device pci 1f.0 on end # LPC Bridge + device pci 1f.2 on end # SATA Controller + device pci 1f.3 on end # SMBus Controller + device pci 1f.5 on end # SATA Controller + end +end diff --git a/src/mainboard/siemens/mc_bdx1/dsdt.asl b/src/mainboard/siemens/mc_bdx1/dsdt.asl new file mode 100644 index 0000000..9db2693 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/dsdt.asl @@ -0,0 +1,293 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + #include "acpi/platform.asl" + + Name(_S0, Package() { 0x00, 0x00, 0x00, 0x00 }) + Name(_S5, Package() { 0x07, 0x00, 0x00, 0x00 }) + + Scope (\_SB) + { + Device (PCI0) + { + #include <acpi/southcluster.asl> + #include <acpi/pcie1.asl> + } + + Name (PRUN, Package() { + Package() { 0x0008FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0008FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0008FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0008FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0009FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0009FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0009FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0009FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000AFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000AFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000AFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000AFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000BFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000BFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000BFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000BFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x000FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x000FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x000FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x000FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0010FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0010FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0010FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0010FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0011FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0011FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0011FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0011FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0012FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0012FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0012FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0012FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0013FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0013FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0013FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0013FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0014FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0014FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0014FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0014FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0016FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0016FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0016FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0016FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0017FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0017FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0017FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0017FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0018FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0018FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0018FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0018FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x0019FFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x0019FFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x0019FFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x0019FFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001CFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001CFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001CFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001CFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001DFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001DFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001DFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001DFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001EFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001EFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001EFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001EFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + + Package() { 0x001FFFFF, 0, \_SB.PCI0.LPC0.LNKA, 0 }, + Package() { 0x001FFFFF, 1, \_SB.PCI0.LPC0.LNKB, 0 }, + Package() { 0x001FFFFF, 2, \_SB.PCI0.LPC0.LNKC, 0 }, + Package() { 0x001FFFFF, 3, \_SB.PCI0.LPC0.LNKD, 0 }, + }) + + Name (ARUN, Package() { + Package() { 0x0008FFFF, 0, 0, 16 }, + Package() { 0x0008FFFF, 1, 0, 17 }, + Package() { 0x0008FFFF, 2, 0, 18 }, + Package() { 0x0008FFFF, 3, 0, 19 }, + + Package() { 0x0009FFFF, 0, 0, 16 }, + Package() { 0x0009FFFF, 1, 0, 17 }, + Package() { 0x0009FFFF, 2, 0, 18 }, + Package() { 0x0009FFFF, 3, 0, 19 }, + + Package() { 0x000AFFFF, 0, 0, 16 }, + Package() { 0x000AFFFF, 1, 0, 17 }, + Package() { 0x000AFFFF, 2, 0, 18 }, + Package() { 0x000AFFFF, 3, 0, 19 }, + + Package() { 0x000BFFFF, 0, 0, 16 }, + Package() { 0x000BFFFF, 1, 0, 17 }, + Package() { 0x000BFFFF, 2, 0, 18 }, + Package() { 0x000BFFFF, 3, 0, 19 }, + + Package() { 0x000CFFFF, 0, 0, 16 }, + Package() { 0x000CFFFF, 1, 0, 17 }, + Package() { 0x000CFFFF, 2, 0, 18 }, + Package() { 0x000CFFFF, 3, 0, 19 }, + + Package() { 0x000DFFFF, 0, 0, 16 }, + Package() { 0x000DFFFF, 1, 0, 17 }, + Package() { 0x000DFFFF, 2, 0, 18 }, + Package() { 0x000DFFFF, 3, 0, 19 }, + + Package() { 0x000EFFFF, 0, 0, 16 }, + Package() { 0x000EFFFF, 1, 0, 17 }, + Package() { 0x000EFFFF, 2, 0, 18 }, + Package() { 0x000EFFFF, 3, 0, 19 }, + + Package() { 0x000FFFFF, 0, 0, 16 }, + Package() { 0x000FFFFF, 1, 0, 17 }, + Package() { 0x000FFFFF, 2, 0, 18 }, + Package() { 0x000FFFFF, 3, 0, 19 }, + + Package() { 0x0010FFFF, 0, 0, 16 }, + Package() { 0x0010FFFF, 1, 0, 17 }, + Package() { 0x0010FFFF, 2, 0, 18 }, + Package() { 0x0010FFFF, 3, 0, 19 }, + + Package() { 0x0011FFFF, 0, 0, 16 }, + Package() { 0x0011FFFF, 1, 0, 17 }, + Package() { 0x0011FFFF, 2, 0, 18 }, + Package() { 0x0011FFFF, 3, 0, 19 }, + + Package() { 0x0012FFFF, 0, 0, 16 }, + Package() { 0x0012FFFF, 1, 0, 17 }, + Package() { 0x0012FFFF, 2, 0, 18 }, + Package() { 0x0012FFFF, 3, 0, 19 }, + + Package() { 0x0013FFFF, 0, 0, 16 }, + Package() { 0x0013FFFF, 1, 0, 17 }, + Package() { 0x0013FFFF, 2, 0, 18 }, + Package() { 0x0013FFFF, 3, 0, 19 }, + + Package() { 0x0014FFFF, 0, 0, 16 }, + Package() { 0x0014FFFF, 1, 0, 17 }, + Package() { 0x0014FFFF, 2, 0, 18 }, + Package() { 0x0014FFFF, 3, 0, 19 }, + + Package() { 0x0016FFFF, 0, 0, 16 }, + Package() { 0x0016FFFF, 1, 0, 17 }, + Package() { 0x0016FFFF, 2, 0, 18 }, + Package() { 0x0016FFFF, 3, 0, 19 }, + + Package() { 0x0017FFFF, 0, 0, 16 }, + Package() { 0x0017FFFF, 1, 0, 17 }, + Package() { 0x0017FFFF, 2, 0, 18 }, + Package() { 0x0017FFFF, 3, 0, 19 }, + + Package() { 0x0018FFFF, 0, 0, 16 }, + Package() { 0x0018FFFF, 1, 0, 17 }, + Package() { 0x0018FFFF, 2, 0, 18 }, + Package() { 0x0018FFFF, 3, 0, 19 }, + + Package() { 0x0019FFFF, 0, 0, 16 }, + Package() { 0x0019FFFF, 1, 0, 17 }, + Package() { 0x0019FFFF, 2, 0, 18 }, + Package() { 0x0019FFFF, 3, 0, 19 }, + + Package() { 0x001CFFFF, 0, 0, 16 }, + Package() { 0x001CFFFF, 1, 0, 17 }, + Package() { 0x001CFFFF, 2, 0, 18 }, + Package() { 0x001CFFFF, 3, 0, 19 }, + + Package() { 0x001DFFFF, 0, 0, 16 }, + Package() { 0x001DFFFF, 1, 0, 17 }, + Package() { 0x001DFFFF, 2, 0, 18 }, + Package() { 0x001DFFFF, 3, 0, 19 }, + + Package() { 0x001EFFFF, 0, 0, 16 }, + Package() { 0x001EFFFF, 1, 0, 17 }, + Package() { 0x001EFFFF, 2, 0, 18 }, + Package() { 0x001EFFFF, 3, 0, 19 }, + + Package() { 0x001FFFFF, 0, 0, 16 }, + Package() { 0x001FFFFF, 1, 0, 17 }, + Package() { 0x001FFFFF, 2, 0, 18 }, + Package() { 0x001FFFFF, 3, 0, 19 }, + }) + + Device (UNC0) + { + Name (_HID, EisaId ("PNP0A03")) + Name (_UID, 0x3F) + Method (_BBN, 0, NotSerialized) + { + Return (0xff) + } + + Name (_ADR, 0x00) + Method (_STA, 0, NotSerialized) + { + Return (0xf) + } + + Name (_CRS, ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x00FF, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + + Method (_PRT, 0, NotSerialized) + { + If (LEqual (PICM, Zero)) + { + Return (PRUN) + } + + Return (ARUN) + } + } + } + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/siemens/mc_bdx1/fadt.c b/src/mainboard/siemens/mc_bdx1/fadt.c new file mode 100644 index 0000000..b274531 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/fadt.c @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + acpi_fill_in_fadt(fadt, facs, dsdt); + + /* Platform specific customizations go here */ + + header->checksum = 0; + header->checksum = + acpi_checksum((void *) fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.c b/src/mainboard/siemens/mc_bdx1/irqroute.c new file mode 100644 index 0000000..9b09f4b --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/irqroute.c @@ -0,0 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "../mc_bdx1/irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/siemens/mc_bdx1/irqroute.h b/src/mainboard/siemens/mc_bdx1/irqroute.h new file mode 100644 index 0000000..c3911be --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/irqroute.h @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef IRQROUTE_H +#define IRQROUTE_H + +#include <soc/irq.h> +#include <soc/pci_devs.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(ME_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(GBE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI2_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI1_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * ACPI/SCI: 9 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 5), \ + PIRQ_PIC(B, 6), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) + +#endif /* IRQROUTE_H */ diff --git a/src/mainboard/siemens/mc_bdx1/mainboard.c b/src/mainboard/siemens/mc_bdx1/mainboard.c new file mode 100644 index 0000000..58da036 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/mainboard.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <console/console.h> +#if CONFIG_VGA_ROM_RUN +#include <x86emu/x86emu.h> +#endif +#include <pc80/mc146818rtc.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <arch/interrupt.h> +#include <boot/coreboot_tables.h> + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(device_t dev) +{ + +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/siemens/mc_bdx1/romstage.c b/src/mainboard/siemens/mc_bdx1/romstage.c new file mode 100644 index 0000000..cf52c01 --- /dev/null +++ b/src/mainboard/siemens/mc_bdx1/romstage.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stddef.h> +#include <soc/romstage.h> +#include <drivers/intel/fsp1_0/fsp_util.h> + +/** + * /brief mainboard call for setup that needs to be done before fsp init + * + */ +void early_mainboard_romstage_entry(void) +{ + +} + +/** + * /brief mainboard call for setup that needs to be done after fsp init + * + */ +void late_mainboard_romstage_entry(void) +{ + +} + +/** + * /brief customize fsp parameters here if needed + */ +void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) +{ + +}

1 0

New patch to review for coreboot: drivers/intel/i210: Use uint8_t and friends instead of u8
by Werner Zeh 26 Apr '16

26 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14515 -gerrit commit 195b661a5bd8448f6523b850d16d8dee840f5c0f Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Tue Apr 26 09:26:14 2016 +0200 drivers/intel/i210: Use uint8_t and friends instead of u8 Switch all types to uint8_t and the like instead of u8. Change-Id: Ia12c4ee9e21e2d3166c2f895c819357fa2ed9a94 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/drivers/intel/i210/i210.c | 67 ++++++++++++++++--------------- src/mainboard/siemens/mc_tcu3/mainboard.c | 5 ++- src/vendorcode/siemens/hwilib/hwilib.h | 3 +- 3 files changed, 40 insertions(+), 35 deletions(-) diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index e821d48..0125a1d 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2014 Siemens AG. + * Copyright (C) 2016 Siemens AG. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -25,13 +25,14 @@ /* We need one function we can call to get a MAC address to use */ /* This function can be coded somewhere else but must exist. */ -extern enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +extern enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]); /* This is a private function to wait for a bit mask in a given register */ /* To avoid endless loops, a time-out is implemented here. */ -static int wait_done(u32* reg, u32 mask) +static int wait_done(uint32_t* reg, uint32_t mask) { - u32 timeout = I210_POLL_TIMEOUT_US; + uint32_t timeout = I210_POLL_TIMEOUT_US; while (!(*reg & mask)) { udelay(1); @@ -50,17 +51,18 @@ static int wait_done(u32* reg, u32 mask) * @param *buffer Pointer to the buffer where to store read data * @return void I210_NO_ERROR or an error code */ -static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +static uint32_t read_flash(struct device *dev, uint32_t address, + uint32_t count, uint16_t *buffer) { - u32 bar; - u32 *eeprd; - u32 i; + uint32_t bar; + uint32_t *eeprd; + uint32_t i; /* Get the BAR to memory mapped space*/ bar = pci_read_config32(dev, PCI_BASE_ADDRESS_0); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eeprd = (u32*)(bar + I210_REG_EEREAD); + eeprd = (uint32_t*)(bar + I210_REG_EEREAD); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eeprd, I210_DONE)) return I210_NOT_READY; @@ -84,10 +86,10 @@ static u32 read_flash(struct device *dev, u32 address, u32 count, u16 *buffer) * @param *checksum Pointer to the buffer where to store the checksum * @return void I210_NO_ERROR or an error code */ -static u32 compute_checksum(struct device *dev, u16 *checksum) +static uint32_t compute_checksum(struct device *dev, uint16_t *checksum) { - u16 eep_data[0x40]; - u32 i; + uint16_t eep_data[0x40]; + uint32_t i; /* First read back data to compute the checksum for */ if (read_flash(dev, 0, 0x3f, eep_data)) @@ -111,20 +113,21 @@ static u32 compute_checksum(struct device *dev, u16 *checksum) * @param *buffer Pointer to the buffer where data to write is stored in * @return void I210_NO_ERROR or an error code */ -static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) +static uint32_t write_flash(struct device *dev, uint32_t address, + uint32_t count, uint16_t *buffer) { - u32 bar; - u32 *eepwr; - u32 *eectrl; - u16 checksum; - u32 i; + uint32_t bar; + uint32_t *eepwr; + uint32_t *eectrl; + uint16_t checksum; + uint32_t i; /* Get the BAR to memory mapped space */ bar = pci_read_config32(dev, 0x10); if ((!bar) || ((address + count) > 0x40)) return I210_INVALID_PARAM; - eepwr = (u32*)(bar + I210_REG_EEWRITE); - eectrl = (u32*)(bar + I210_REG_EECTRL); + eepwr = (uint32_t*)(bar + I210_REG_EEWRITE); + eectrl = (uint32_t*)(bar + I210_REG_EECTRL); /* Prior to start ensure flash interface is ready by checking DONE-bit */ if (wait_done(eepwr, I210_DONE)) return I210_NOT_READY; @@ -145,8 +148,8 @@ static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) if (wait_done(eepwr, I210_DONE)) return I210_WRITE_ERROR; /* Up to now, desired data was written into shadowed RAM. We now need */ - /* to perform a flash cycle to bring the shadowed RAM into flash memory. */ - /* To start a flash cycle we need to set FLUPD-bit and wait for FLDONE. */ + /* to perform a flash cycle to bring the shadowed RAM into flash. */ + /* To start a flash cycle we need to set FLUPD and wait for FLDONE. */ *eectrl = *eectrl | I210_FLUPD; if (wait_done(eectrl, I210_FLUDONE)) return I210_FLASH_UPDATE_ERROR; @@ -158,16 +161,16 @@ static u32 write_flash(struct device *dev, u32 address, u32 count, u16 *buffer) * @param *MACAdr Pointer to the buffer where to store read MAC address * @return void I210_NO_ERROR or an error code */ -static u32 read_mac_adr(struct device *dev, u8 *mac_adr) +static uint32_t read_mac_adr(struct device *dev, uint8_t *mac_adr) { - u16 adr[3]; + uint16_t adr[3]; if (!dev || !mac_adr) return I210_INVALID_PARAM; if (read_flash(dev, 0, 3, adr)) return I210_READ_ERROR; - /* Copy the address into destination. This is done because of */ - /* possible not matching alignment for destination to u16 boundary. */ - memcpy(mac_adr, (u8*)adr, 6); + /* Copy the address into destination. This is done because of possible */ + /* not matching alignment for destination to uint16_t boundary. */ + memcpy(mac_adr, (uint8_t*)adr, 6); return I210_SUCCESS; } @@ -176,13 +179,13 @@ static u32 read_mac_adr(struct device *dev, u8 *mac_adr) * @param *MACAdr Pointer to the buffer where the desired MAC address is * @return void I210_NO_ERROR or an error code */ -static u32 write_mac_adr(struct device *dev, u8 *mac_adr) +static uint32_t write_mac_adr(struct device *dev, uint8_t *mac_adr) { - u16 adr[3]; + uint16_t adr[3]; if (!dev || !mac_adr) return I210_INVALID_PARAM; /* Copy desired address into a local buffer to avoid alignment issues */ - memcpy((u8*)adr, mac_adr, 6); + memcpy((uint8_t*)adr, mac_adr, 6); return write_flash(dev, 0, 3, adr); } @@ -194,8 +197,8 @@ static u32 write_mac_adr(struct device *dev, u8 *mac_adr) */ static void init(struct device *dev) { - u8 cur_adr[6]; - u8 adr_to_set[6]; + uint8_t cur_adr[6]; + uint8_t adr_to_set[6]; enum cb_err status; /*Check first whether there is a valid MAC address available */ diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index e9c29a0..009c34d 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -39,10 +39,11 @@ * @param mac buffer where to store the MAC address * @return cb_err CB_ERR or CB_SUCCESS */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) +enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]) { uint8_t mac_adr[6]; - u32 i; + uint32_t i; /* Open main hwinfo block */ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h index 72dabcc..7cda553 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.h +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -68,5 +68,6 @@ enum cb_err hwilib_find_blocks (const char *hwi_filename); uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *data, uint32_t maxlen); /* This functions needs to be implemented for every mainboard that uses i210. */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +enum cb_err mainboard_get_mac_address(uint16_t bus, uint8_t devfn, + uint8_t mac[6]); #endif /* SIEMENS_HWI_LIB_H_ */

1 0

Patch set updated for coreboot: mc_tcu3: Switch to hwilib instead of own hwinfo implementation
by Werner Zeh 26 Apr '16

26 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14506 -gerrit commit 5320bbb63c4ae4c882fc1fb7bbf3cd6ec00e741b Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Apr 25 12:24:17 2016 +0200 mc_tcu3: Switch to hwilib instead of own hwinfo implementation Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo instead of having mainboard specific hwinfo code. This patch do not change the functional behavior in any way. Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 + src/mainboard/siemens/mc_tcu3/Makefile.inc | 3 - src/mainboard/siemens/mc_tcu3/lcd_panel.c | 26 ++--- src/mainboard/siemens/mc_tcu3/mainboard.c | 40 ++++++- src/mainboard/siemens/mc_tcu3/modhwinfo.c | 144 ------------------------- src/mainboard/siemens/mc_tcu3/modhwinfo.h | 166 ----------------------------- src/mainboard/siemens/mc_tcu3/ptn3460.c | 49 ++++++--- src/mainboard/siemens/mc_tcu3/ptn3460.h | 3 +- src/mainboard/siemens/mc_tcu3/romstage.c | 65 ++++++----- 9 files changed, 120 insertions(+), 377 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index d7ff867..5ff233d 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES select FSP_BAYTRAIL_GFX_INIT + select USE_SIEMENS_HWILIB config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc index 12be6a7..2922eef 100644 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -13,11 +13,8 @@ ## GNU General Public License for more details. ## -romstage-y += modhwinfo.c - ramstage-y += gpio.c ramstage-y += irqroute.c -ramstage-y += modhwinfo.c ramstage-y += lcd_panel.c ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.c b/src/mainboard/siemens/mc_tcu3/lcd_panel.c index 91159f9..214773a 100644 --- a/src/mainboard/siemens/mc_tcu3/lcd_panel.c +++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.c @@ -15,11 +15,11 @@ #include <cbfs.h> #include <console/console.h> #include <string.h> -#include "modhwinfo.h" #include "soc/gpio.h" #include "lcd_panel.h" #include "ptn3460.h" + /** \brief Reads GPIOs used for LCD panel encoding and returns the 4 bit value * @param no parameters * @return LCD panel type encoded in 4 bits @@ -42,10 +42,8 @@ u8 get_lcd_panel_type(void) */ int setup_lcd_panel(void) { - u8 lcd_type; + u8 lcd_type; int status; - struct edidinfo *eib = NULL; - struct shortinfo *sib = NULL; char blockname[33]; lcd_type = get_lcd_panel_type(); @@ -71,20 +69,12 @@ int setup_lcd_panel(void) status = 1; break; } - - /* Now that we have the panel type, get the matching block and setup */ - /* the DP2LVDS converter accordingly */ - eib = get_edidinfo(blockname); - sib = get_shortinfo(blockname); - - if ((!eib) || (!sib)) { - printk(BIOS_ERR, "LCD: Info block named \"%s\" not found!\n", blockname); - status = 1; - } else { - printk(BIOS_INFO, "LCD: Found SIB at 0x%x, EIB at 0x%x\n", - (int)sib, (int)eib); - status = ptn3460_init(lcd_type, eib, sib); + /* Now that we have the panel type, setup the DP2LVDS converter */ + status = ptn3460_init(blockname); + if (status) + printk(BIOS_ERR, "LCD: Setup PTN with status 0x%x\n", status); + else printk(BIOS_INFO, "LCD: Setup PTN with status 0x%x\n", status); - } + return status; } diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 8a966dc..e9c29a0 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -29,9 +29,47 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> - +#include <hwilib.h> #include "lcd_panel.h" + +/** \brief This function will search for a MAC address which can be assigned + * to a MACPHY. + * @param pci_bdf Bus, device and function of the given PCI-device + * @param mac buffer where to store the MAC address + * @return cb_err CB_ERR or CB_SUCCESS + */ +enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) +{ + uint8_t mac_adr[6]; + u32 i; + + /* Open main hwinfo block */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return CB_ERR; + /* Get first MAC address from hwinfo. */ + if (hwilib_get_field(Mac1, mac_adr, sizeof(mac_adr)) != sizeof(mac_adr)) + return CB_ERR; + /* Ensure the first MAC-Address is not completely 0x00 or 0xff */ + for (i = 0; i < 6; i++) { + if (mac_adr[i] != 0xFF) + break; + } + if (i == 6){ + return CB_ERR; + } + for (i = 0; i < 6; i++) { + if (mac_adr[i] != 0x00) + break; + } + if (i == 6){ + return CB_ERR; + } else { + memcpy(mac, mac_adr, 6); + return CB_SUCCESS; + } +} + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.c b/src/mainboard/siemens/mc_tcu3/modhwinfo.c deleted file mode 100644 index ac7404b..0000000 --- a/src/mainboard/siemens/mc_tcu3/modhwinfo.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Siemens AG. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "modhwinfo.h" -#include "lcd_panel.h" -#include <cbfs.h> -#include <string.h> - -/** \brief This function will find the first linked info block. - * @param *filename Filename in cbfs - * @param *file_offset Pointer to the offset of the cbfs file contents - * @return u8* Pointer to the found block - */ -u8* get_first_linked_block(char *filename, u8 **file_offset) -{ - u8* block_ptr = NULL; - - block_ptr = cbfs_boot_map_with_leak(filename, 0x50, NULL); - if (!block_ptr) - return NULL; - if (!strncmp((char*)block_ptr, "H1W2M3I4", LEN_MAGIC_NUM)) { - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET)) == LEN_MAIN_HWINFO) && - (*((s32*)(block_ptr + NEXT_OFFSET_HWINFO)) != 0x00)) { - *file_offset = block_ptr; - return *((s32*)(block_ptr + NEXT_OFFSET_HWINFO)) + block_ptr; - } else - return NULL; - } else if (!strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM)) { - *file_offset = block_ptr; - return block_ptr; - } else - return NULL; -} - -/** \brief This function will find the main info block - * @param *filename Filename in cbfs - * @return *hwinfo Pointer to the data of the main info block - */ -struct hwinfo* get_hwinfo(char *filename) -{ - struct hwinfo* main_hwinfo; - - main_hwinfo = cbfs_boot_map_with_leak(filename, 0x50, NULL); - if ((main_hwinfo) && - (!strncmp(main_hwinfo->magicNumber, "H1W2M3I4", LEN_MAGIC_NUM)) && - (main_hwinfo->length == LEN_MAIN_HWINFO)) - return main_hwinfo; - else - return NULL; -} - -/** \brief This function will find the short info block - * @param *filename Filename in cbfs - * @return *shortinfo Pointer to the data of the short info block - */ -struct shortinfo* get_shortinfo(char *filename) -{ - u8 *block_ptr = NULL; - u8 *file_offset = NULL; - - block_ptr = get_first_linked_block(filename, &file_offset); - if ((block_ptr == NULL) || - (strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM))) - return NULL; - - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_SHORT_INFO) - return (struct shortinfo *)block_ptr; - - block_ptr = (file_offset + *((s32*)(block_ptr + NEXT_OFFSET_EDID))); - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_SHORT_INFO) - return (struct shortinfo *)block_ptr; - else - return NULL; -} - -/** \brief This function will find the edid info block - * @param *filename Filename in cbfs - * @return *edidinfo Pointer to the data of the edid info block - */ -struct edidinfo* get_edidinfo(char *filename) -{ - u8 *block_ptr = NULL; - u8 *file_offset = NULL; - - block_ptr = get_first_linked_block(filename, &file_offset); - if ((block_ptr == NULL) || - (strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM))) - return NULL; - - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_EDID_INFO) - return (struct edidinfo *)block_ptr; - - block_ptr = (file_offset + *((s32*)(block_ptr + NEXT_OFFSET_SIB))); - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_EDID_INFO) - return (struct edidinfo *)block_ptr; - else - return NULL; -} - -/** \brief This function will search for a MAC address which can be assigned - * to a MACPHY. - * @param pci_bdf Bus, device and function of the given PCI-device - * @param mac buffer where to store the MAC address - * @return cb_err CB_ERR or CB_SUCCESS - */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) -{ - struct hwinfo* main_hwinfo; - u32 i; - - main_hwinfo = get_hwinfo((char*)"hwinfo.hex"); - if (!main_hwinfo) - return CB_ERR; - /* Ensure the first MAC-Address is not completely 0x00 or 0xff */ - for (i = 0; i < 6; i++) { - if (main_hwinfo->macAddress1[i] != 0xFF) - break; - } - if (i == 6){ - return CB_ERR; - } - for (i = 0; i < 6; i++) { - if (main_hwinfo->macAddress1[i] != 0x00) - break; - } - if (i == 6){ - return CB_ERR; - } else { - memcpy(mac, main_hwinfo->macAddress1, 6); - return CB_SUCCESS; - } -} diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.h b/src/mainboard/siemens/mc_tcu3/modhwinfo.h deleted file mode 100644 index 6bf891c..0000000 --- a/src/mainboard/siemens/mc_tcu3/modhwinfo.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MODHWINFO_H_ -#define _MODHWINFO_H_ - -#include <types.h> - -#define LEN_MAGIC_NUM 8 -#define LEN_MLFB 20 -#define LEN_SERIAL_NUM 16 -#define LEN_HW_REVISION 2 -#define LEN_MAC_ADDRESS 6 -#define LEN_SPD 128 -#define NUMBER_OF_MAC_ADDR 4 -#define LEN_EDID 128 -#define LEN_MAIN_HWINFO 509 -#define LEN_SHORT_INFO 289 -#define LEN_EDID_INFO 181 -#define NEXT_OFFSET_HWINFO 476 -#define NEXT_OFFSET_SIB 260 -#define NEXT_OFFSET_EDID 176 -#define HWI_LEN_OFFSET 12 - -/* Define some masks and values */ -#define SIB_HWINIT_IDX 0x0e -#define SIB_COLOR_6BIT 0x00 -#define SIB_COLOR_8BIT 0x01 -#define SIB_COLOR_10BIT 0x02 -#define SIB_DISP_CON_IDX 0x16 -#define SIB_LVDS_SINGLE_LANE 0x00 -#define SIB_LVDS_DUAL_LANE 0x05 - -struct PhysDevStruc { - u8 bustype; - u8 devfn; - u16 bus; -} __attribute__ ((packed)); - - -struct hwinfo { -// Offset 0x0 - char magicNumber[LEN_MAGIC_NUM]; -// Offset 0x08 - u8 versionID[4]; -// Offset 0x0c - u16 length; -// Offset 0x0e - char BGR_Name[128]; -//Offset 0x8e - char MLFB[LEN_MLFB]; -// Offset 0xa2 - u8 uniqueNumber[16]; -// Offset 0xb2 - u8 fill_1[12]; -// Offset 0xbe - u8 hwRevision[LEN_HW_REVISION]; -//Offset 0xc0 - u8 macAddress1[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr1; - u8 fill_2; -//Offset 0xc8 - u8 macAddress2[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr2; - u8 fill_3; -//Offset 0xd0 - u8 macAddress3[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr3; - u8 fill_4; -//Offset 0xd8 - u8 macAddress4[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr4; - u8 fill_5; -// Offset 0xe0 - u8 SPD[LEN_SPD]; -// Offset 0x160 - u8 fill_6[88]; -// Offset 0x1b8 - u32 featureFlags; -// Offset 0x1bc - u8 fill_7[4]; -// Offset 0x1c0 - u32 biosFlags; -// Offset 0x1c4 - u8 fill_8[8]; -//Offset 0x1cc - struct PhysDevStruc etherDev[NUMBER_OF_MAC_ADDR]; -// Offset 0x1dc - s32 nextInfoOffset; -// Offset 0x1e0 - u8 fill_9[4]; -// Offset 0x1e4 - u32 portRTC; -// Offset 0x1e8 - u8 typeRTC; -// Offset 0x1e9 - u8 fill_10[20]; -} __attribute__ ((packed)); - -struct shortinfo { -// Offset 0x0 - char magicNumber[LEN_MAGIC_NUM]; -// Offset 0x08 - u8 versionID[4]; -// Offset 0x0c - u16 length; -// Offset 0x0e - char BGR_Name[128]; -//Offset 0x8e - char MLFB[LEN_MLFB]; -// Offset 0xa2 - u8 uniqueNumber[26]; -// Offset 0xbc - u8 fill_1[12]; -//Offset 0xc8 - u8 hwRevision[2]; -// Offset 0xca - u8 fill_2[18]; -// Offset 0xdc - u8 panelFeatures[32]; -// Offset 0xfc - u8 fill_3[8]; -// Offset 0x104 - s32 nextInfoOffset; -// Offset 0x108 - u8 fill_4[25]; -} __attribute__ ((packed)); - -struct edidinfo { -// Offset 0x0 - char magicNumber[LEN_MAGIC_NUM]; -// Offset 0x08 - u8 versionID[4]; -// Offset 0x0c - u16 length; -// Offset 0x0e - u8 fill_1[2]; -// Offset 0x10 - u8 edid[LEN_EDID]; -// Offset 0x90 - u8 fill_2[32]; -// Offset 0xb0 - s32 nextInfoOffset; -// Offset 0xb4 - u8 fill_3; -} __attribute__ ((packed)); - -u8* get_first_linked_block(char *filename, u8 **starting_adr); -struct hwinfo* get_hwinfo(char *filename); -struct shortinfo* get_shortinfo(char *filename); -struct edidinfo* get_edidinfo(char *filename); -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); - -#endif /* _MODHWINFO_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index e371e53..21847bd 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -14,33 +14,52 @@ */ #include <console/console.h> +#include <hwilib.h> #include "soc/i2c.h" #include "ptn3460.h" /** \brief This functions sets up the DP2LVDS-converter to be used with the * appropriate lcd panel - * @param lcd_type Type of LCD we should set up the converter for - * @param *sib Pointer to short info block structure - * @param *eib Pointer to EDID info block structure - * @return 0 on success or error code + * @param *hwi_block Filename in CBFS of the block to use as HW-Info + * @return 0 on success or error code */ -int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib) +int ptn3460_init(char *hwi_block) { struct ptn_3460_config cfg; int status; + uint8_t disp_con = 0, color_depth = 0; + uint8_t edid_data[0x80]; + if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", + hwi_block); + return 1; + } status = i2c_init(PTN_I2C_CONTROLER); if (status) return (PTN_BUS_ERROR | status); - /* If we are here, we have all the desired information for setting up */ - /* DP2LVDS converter. In addition, the information matches the connected */ - /* LCD-panel and therefore, we do not have to distinguish between */ - /* different panels here for the timing. Inside the converter, table 6 */ - /* will be used for the timings. */ - status = ptn3460_write_edid(6, eib->edid); - if (status) + /* Get all needed information from hwinfo block */ + if (hwilib_get_field(Edid, edid_data, 0x80) != sizeof(edid_data)) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", + hwi_block); + return 1; + } + if ((hwilib_get_field(PF_DisplCon, &disp_con, 1) != 1)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + if (hwilib_get_field(PF_Color_Depth ,&color_depth, 1) != 1) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + /* Here, all the desired information for setting up DP2LVDS converter*/ + /* are present. Inside the converter, table 6 will be used for */ + /* the timings. */ + if ((status = ptn3460_write_edid(6, edid_data)) != 0) return status; /* Select this table to be emulated */ ptn_select_edid(6); @@ -50,12 +69,12 @@ int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib) if (status) return (PTN_BUS_ERROR | status); - /* Set up configuration data according to the information blocks we get */ + /* Set up configuration data according to the hwinfo blocks we get */ cfg.dp_interface_ctrl = 0; cfg.lvds_interface_ctrl1 = 0x00; - if (sib->panelFeatures[SIB_DISP_CON_IDX] == SIB_LVDS_DUAL_LANE) + if (disp_con == PF_DISPLCON_LVDS_DUAL) cfg.lvds_interface_ctrl1 |= 0x0b; /* Turn on dual LVDS lane and clock */ - if ((sib->panelFeatures[SIB_HWINIT_IDX] & 0x03) == SIB_COLOR_6BIT) + if (color_depth == PF_COLOR_DEPTH_6BIT) cfg.lvds_interface_ctrl1 |= 0x20; /* Use 18 bits per pixel */ cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h index 3e0c065..533607c 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.h +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h @@ -17,7 +17,6 @@ #define PTN3460_H_ #include <delay.h> -#include "modhwinfo.h" #include "lcd_panel.h" #define PTN_SLAVE_ADR 0x20 @@ -66,7 +65,7 @@ struct ptn_3460_flash{ }__attribute__((packed)); -int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib); +int ptn3460_init(char *hwi_block); int ptn3460_read_edid(u8 edid_num, u8 *data); int ptn3460_write_edid(u8 edid_num, u8 *data); int ptn_select_edid(u8 edid_num); diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 1fa78ca..c8cc66b 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -33,7 +33,7 @@ #include <soc/acpi.h> #include <soc/baytrail.h> #include <drivers/intel/fsp1_0/fsp_util.h> -#include "modhwinfo.h" +#include <hwilib.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -166,35 +166,44 @@ const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - struct hwinfo *hwi_main; + uint8_t spd[0x80]; UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - /* Initialize the Azalia Verb Tables to mainboard specific version */ + /* Initialize the Azalia Verb Tables to mainboard specific version. */ UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; - /* Get SPD data from hardware information block and setup memory down */ - /* parameters for FSP accordingly */ - hwi_main = get_hwinfo((char*)"hwinfo.hex"); - if (hwi_main) { - UpdData->PcdMemoryParameters.EnableMemoryDown = 1; - UpdData->PcdMemoryParameters.DRAMType = hwi_main->SPD[2]; - UpdData->PcdMemoryParameters.DIMM0Enable = hwi_main->SPD[3] & 0x01; - UpdData->PcdMemoryParameters.DIMM1Enable = (hwi_main->SPD[3] >> 1) & 0x01; - UpdData->PcdMemoryParameters.DIMMDensity = hwi_main->SPD[4]; - UpdData->PcdMemoryParameters.DIMMDWidth = hwi_main->SPD[5]; - UpdData->PcdMemoryParameters.DIMMSides = hwi_main->SPD[7]; - UpdData->PcdMemoryParameters.DIMMBusWidth = hwi_main->SPD[8]; - UpdData->PcdMemoryParameters.DRAMSpeed = hwi_main->SPD[12]; - UpdData->PcdMemoryParameters.DIMMtCL = hwi_main->SPD[14]; - UpdData->PcdMemoryParameters.DIMMtWR = hwi_main->SPD[17]; - UpdData->PcdMemoryParameters.DIMMtRPtRCD = hwi_main->SPD[18]; - UpdData->PcdMemoryParameters.DIMMtRRD = hwi_main->SPD[19]; - UpdData->PcdMemoryParameters.DIMMtWTR = hwi_main->SPD[26]; - UpdData->PcdMemoryParameters.DIMMtRTP = hwi_main->SPD[27]; - UpdData->PcdMemoryParameters.DIMMtFAW = hwi_main->SPD[28]; - /*If one need output from MRC to be used in Intel RMT, simply */ - /*enable the following line */ - //UpdData->PcdMrcDebugMsg = 1; - } else - printk(BIOS_ERR, "HWInfo not found, leave default timings for DDR3.\n"); + /* Get SPD data from hwinfo block and set up memory down */ + /* parameters for FSP accordingly. */ + if (hwilib_find_blocks("hwinfo.hex")) { + printk(BIOS_ERR, + "HWInfo not found, use default timings for DDR3.\n"); + return; + } + + if (hwilib_get_field(SPD, spd, sizeof(spd)) != sizeof(spd)) { + printk(BIOS_ERR, + "SPD not found in HWInfo, use defaults for DDR3.\n"); + return; + } + /*Set up DDR timings from HWInfo. */ + UpdData->PcdMemoryParameters.EnableMemoryDown = 1; + UpdData->PcdMemoryParameters.DRAMType = spd[2]; + UpdData->PcdMemoryParameters.DIMM0Enable = spd[3] & 0x01; + UpdData->PcdMemoryParameters.DIMM1Enable = (spd[3] >> 1) & 0x01; + UpdData->PcdMemoryParameters.DIMMDensity = spd[4]; + UpdData->PcdMemoryParameters.DIMMDWidth = spd[5]; + UpdData->PcdMemoryParameters.DIMMSides = spd[7]; + UpdData->PcdMemoryParameters.DIMMBusWidth = spd[8]; + UpdData->PcdMemoryParameters.DRAMSpeed = spd[12]; + UpdData->PcdMemoryParameters.DIMMtCL = spd[14]; + UpdData->PcdMemoryParameters.DIMMtWR = spd[17]; + UpdData->PcdMemoryParameters.DIMMtRPtRCD = spd[18]; + UpdData->PcdMemoryParameters.DIMMtRRD = spd[19]; + UpdData->PcdMemoryParameters.DIMMtWTR = spd[26]; + UpdData->PcdMemoryParameters.DIMMtRTP = spd[27]; + UpdData->PcdMemoryParameters.DIMMtFAW = spd[28]; + + /*If one need output from MRC to be used in Intel RMT, simply */ + /*enable the following line */ + //UpdData->PcdMrcDebugMsg = 1; }

1 0

Patch set updated for coreboot: vendorcode/siemens: Add hwilib for Siemens specific info struct
by Werner Zeh 26 Apr '16

26 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14505 -gerrit commit fe6bd3e889b84d3337c0b4c04b299df7057add19 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Apr 22 14:14:45 2016 +0200 vendorcode/siemens: Add hwilib for Siemens specific info struct Add a library which unifies access to Siemens specific hardware information data. This library is meant to be used with Siemens platforms and can be selected in Kconfig. The needed source of information has to be present in cbfs. This lib can be used in romstage and ramstage. Change-Id: I2c6e003b0c123b4cf6a84906c2b133b8c38c8b1a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/vendorcode/Makefile.inc | 1 + src/vendorcode/siemens/Kconfig | 20 ++ src/vendorcode/siemens/Makefile.inc | 16 ++ src/vendorcode/siemens/hwilib/Makefile.inc | 19 ++ src/vendorcode/siemens/hwilib/hwilib.c | 310 +++++++++++++++++++++++++++++ src/vendorcode/siemens/hwilib/hwilib.h | 72 +++++++ 6 files changed, 438 insertions(+) diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 741a04a..440972f 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += amd subdirs-y += google subdirs-y += intel +subdirs-y += siemens diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig new file mode 100644 index 0000000..8bbab62 --- /dev/null +++ b/src/vendorcode/siemens/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config USE_SIEMENS_HWILIB + bool + default n + +source "src/vendorcode/siemens/*/Kconfig" diff --git a/src/vendorcode/siemens/Makefile.inc b/src/vendorcode/siemens/Makefile.inc new file mode 100644 index 0000000..ece2b4d --- /dev/null +++ b/src/vendorcode/siemens/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-$(CONFIG_USE_SIEMENS_HWILIB) += hwilib diff --git a/src/vendorcode/siemens/hwilib/Makefile.inc b/src/vendorcode/siemens/hwilib/Makefile.inc new file mode 100644 index 0000000..1c6f6c9 --- /dev/null +++ b/src/vendorcode/siemens/hwilib/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CFLAGS_x86_32 += -Isrc/vendorcode/siemens/hwilib + +romstage-y += hwilib.c +ramstage-y += hwilib.c diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c new file mode 100644 index 0000000..a8736ea --- /dev/null +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -0,0 +1,310 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbfs.h> +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/early_variables.h> +#include "hwilib.h" + + +#define MAX_BLOCK_NUM 3 +#define LEN_HIB 0x1fd +#define LEN_SIB 0x121 +#define LEN_EIB 0x0b5 +#define NEXT_OFFSET_HIB 0x1dc +#define NEXT_OFFSET_SIB 0x104 +#define NEXT_OFFSET_EIB 0x0b0 +#define LEN_UNIQUEL_NUM 0x010 +#define LEN_HW_REV 0x002 +#define LEN_MAC_ADDRESS 0x006 +#define LEN_SPD 0x080 +#define LEN_EDID 0x080 +#define LEN_OFFSET 0x00c +#define EIB_FEATRUE_OFFSET 0x00e +#define LEN_MAGIC_NUM 0x007 +#define BLOCK_MAGIC "H1W2M3I" + +/* Define all supported block types. */ +enum { + EMPTY = 0, + BLK_HIB, + BLK_SIB, + BLK_EIB, +}; + +/* This structure holds a valid position for a given field */ +/* Every field can have multiple positions of which the first available */ +/* will be taken by the library. */ +struct param_pos { + uint8_t blk_type; /* Valid for a specific block type */ + uint32_t offset; /* Offset in given block */ + uint32_t len; /* Length for the field in this block */ +}; + +/* This structure holds all the needed information for a given field type */ +/* and a pointer to a function which is able to extracting the desired data. */ +struct param_info { + struct param_pos pos[MAX_BLOCK_NUM]; + uint64_t mask; + uint8_t mask_offset; + uint32_t (*get_field)(const struct param_info *param, uint8_t *dst, + uint32_t maxlen); +}; + +/* Storage for pointers to the different blocks. The contents will be filled */ +/* in hwilib_find_blocks(). */ +static uint8_t *all_blocks[MAX_BLOCK_NUM + 1] CAR_GLOBAL; + +static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, + uint32_t maxlen); + +/* Add all supported fields to this variable. It is important to use the */ +/* field type of a given field as the array index so that all the information */ +/* is on the appropriate place inside the array. In this way one do not need */ +/* to search for fields but can simply use an index into the array. */ +static const struct param_info params[] = { + [HIB_VerID] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, + [SIB_VerID] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, + [EIB_VerID] = { + .pos[0] = {.blk_type = BLK_EIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, + [HIB_HwRev] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xbe, .len = 2}, + .get_field = hwilib_read_bytes }, + [SIB_HwRev] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xc8, .len = 2}, + .get_field = hwilib_read_bytes }, + [UniqueNum] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xa2, .len = 10}, + .pos[1] = {.blk_type = BLK_SIB, .offset = 0xa2, .len = 10}, + .get_field = hwilib_read_bytes }, + [Mac1] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xc0, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac1Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xc6, .len = 1}, + .get_field = hwilib_read_bytes }, + [Mac2] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xc8, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac2Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xce, .len = 1}, + .get_field = hwilib_read_bytes }, + [Mac3] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xd0, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac3Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xd6, .len = 1}, + .get_field = hwilib_read_bytes }, + [Mac4] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xd8, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac4Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xde, .len = 1}, + .get_field = hwilib_read_bytes }, + [SPD] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xe0, .len = 0x80}, + .get_field = hwilib_read_bytes }, + [FF_FreezeDis] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1b8, .len = 4}, + .mask = 0x10, + .mask_offset = 4, + .get_field = hwilib_read_bytes }, + [FF_FanReq] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1b8, .len = 4}, + .mask = 0x400, + .mask_offset = 10, + .get_field = hwilib_read_bytes }, + [BiosFlags] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1c0, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping1] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1cc, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping2] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d0, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping3] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d4, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping4] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d8, .len = 4}, + .get_field = hwilib_read_bytes }, + [PF_Color_Depth] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xea, .len = 1}, + .mask = 0x03, + .mask_offset = 0, + .get_field = hwilib_read_bytes }, + [PF_DisplType] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xe3, .len = 1}, + .get_field = hwilib_read_bytes }, + [PF_DisplCon] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xf2, .len = 1}, + .get_field = hwilib_read_bytes }, + [Edid] = { + .pos[0] = {.blk_type = BLK_EIB, .offset = 0x10, .len = 0x80}, + .get_field = hwilib_read_bytes }, + [VddRef] = { + .pos[0] = {.blk_type = BLK_EIB, .offset = 0x90, .len = 2}, + .get_field = hwilib_read_bytes }, +}; + +/** \brief This functions reads the given field from the first valid hwinfo + * block + * @param *param Parameter to read from hwinfo + * @param *dst Pointer to memory where the data will be stored in + * @return number of copied bytes on success, 0 on error + */ +static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, + uint32_t maxlen) +{ + uint8_t i = 0, *blk = NULL; + uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); + + if (!param || !dst) + return 0; + /* Take the first valid block to get the parameter from */ + do { + if ((param->pos[i].blk_type != EMPTY) && + blk_ptr[param->pos[i].blk_type]) { + blk = blk_ptr[param->pos[i].blk_type]; + break; + } + i++; + } while (i < MAX_BLOCK_NUM + 1); + + /* Ensure there is a valid block available for this parameter and */ + /* the length of the parameter do not exceed maxlen. */ + if (!blk || param->pos[i].len > maxlen) + return 0; + /* We can now copy the wanted data. */ + memcpy(dst, (blk + param->pos[i].offset), param->pos[i].len); + /* If there is a mask given, apply it only for parameters with a */ + /* length of 1, 2, 4 or 8 bytes. */ + if (param->mask) { + switch (param->pos[i].len) { + case 1: + /* Apply a mask on a 8 bit value */ + *dst &= (param->mask & 0xff); + *dst >>= (param->mask_offset); + break; + case 2: + /* Apply mask on a 16 bit value */ + *((uint16_t *)(dst)) &= (param->mask & 0xffff); + *((uint16_t *)(dst)) >>= (param->mask_offset); + break; + case 4: + /* Apply mask on a 32 bit value */ + *((uint32_t *)(dst)) &= (param->mask & 0xffffffff); + *((uint32_t *)(dst)) >>= (param->mask_offset); + break; + case 8: + /* Apply mask on a 64 bit value */ + *((uint64_t *)(dst)) &= (param->mask); + *((uint64_t *)(dst)) >>= (param->mask_offset); + break; + default: + /* Warn if there is a mask for an invalid length. */ + printk(BIOS_WARNING, + "HWILIB: Invalid field length for given mask.\n"); + break; + } + } + return param->pos[i].len; +} + +/** \brief This function finds all available block types in a given cbfs file. + * @param *hwi_filename Name of the cbfs-file to use. + * @return CB_SUCCESS when no error, otherwise error code + */ +enum cb_err hwilib_find_blocks (const char *hwi_filename) +{ + uint8_t *ptr = NULL, *base = NULL; + uint32_t next_offset = 1; + uint8_t **blk_ptr = car_get_var_ptr(&all_blocks[0]); + + /* Check for a valid parameter */ + if (!hwi_filename) + return CB_ERR_ARG; + ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, NULL); + if (!ptr) { + printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", + hwi_filename); + return CB_ERR; + } + /* Ensure the block has the right magic */ + if (strncmp((char*)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) { + printk(BIOS_ERR, "HWILIB: Bad magic at start of block!\n"); + return CB_ERR; + } + /* Reset all static pointers to blocks as they might have been set */ + /* in prior calls to this function. */ + /* This way the caller do not need to "close" already opened blocks. */ + memset(blk_ptr, 0, MAX_BLOCK_NUM + 1); + /* Check which blocks are available by examining the length field. */ + base = ptr; + while(!(strncmp((char *)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) && + next_offset) { + uint16_t len = read16(ptr + LEN_OFFSET); + if (len == LEN_HIB) { + blk_ptr[BLK_HIB] = ptr; + next_offset = read32(ptr + NEXT_OFFSET_HIB); + if (next_offset) + ptr = base + next_offset; + } else if (len == LEN_SIB) { + blk_ptr[BLK_SIB] = ptr; + next_offset = read32(ptr + NEXT_OFFSET_SIB); + if (next_offset) + ptr = base + next_offset; + } else if (len == LEN_EIB) { + /* Skip preliminary blocks */ + if (!(read16(ptr + EIB_FEATRUE_OFFSET) & 0x01)) + blk_ptr[BLK_EIB] = ptr; + next_offset = read32(ptr + NEXT_OFFSET_EIB); + if (next_offset) + ptr = base + next_offset; + } else { + next_offset = 0; + } + } + /* We should have found at least one valid block */ + if (blk_ptr[BLK_HIB] || blk_ptr[BLK_SIB] || blk_ptr[BLK_EIB]) + return CB_SUCCESS; + else + return CB_ERR; +} + + +/* Use this function to ask the lib for fields from info blocks. */ +/** \brief This functions is used from caller to get a specific field from + * hwinfo block. + * @param field Field type to read from hwinfo + * @param *dst Pointer to memory where the data will be stored in + * @return number of copied bytes on success, 0 on error + */ +uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *dst, uint32_t maxlen) +{ + /* Check the boundaries of params-variable */ + if ((uint32_t)field < ((sizeof(params))/(sizeof(struct param_info)))) + return params[field].get_field(&params[field], dst, maxlen); + else + return 0; +} diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h new file mode 100644 index 0000000..72dabcc --- /dev/null +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SIEMENS_HWI_LIB_H_ +#define SIEMENS_HWI_LIB_H_ + +#include <types.h> + + +/* Declare all supported fields which can be get with hwilib. */ +typedef enum { + HIB_VerID = 0, + SIB_VerID, + EIB_VerID, + HIB_HwRev, + SIB_HwRev, + UniqueNum, + Mac1, + Mac1Aux, + Mac2, + Mac2Aux, + Mac3, + Mac3Aux, + Mac4, + Mac4Aux, + SPD, + FF_FreezeDis, + FF_FanReq, + BiosFlags, + MacMapping1, + MacMapping2, + MacMapping3, + MacMapping4, + PF_Color_Depth, + PF_DisplType, + PF_DisplCon, + Edid, + VddRef +}hwinfo_field_t; + +/* Define used values in supported fields */ +#define PF_COLOR_DEPTH_6BIT 0x00 +#define PF_COLOR_DEPTH_8BIT 0x01 +#define PF_COLOR_DEPTH_10BIT 0x02 +#define PF_DISPLCON_LVDS_SINGLE 0x00 +#define PF_DISPLCON_LVDS_DUAL 0x05 +#define FF_FREEZE_DISABLE 0x01 +#define FF_FAN_NEEDED 0x01 + +/* Use this function to find all supported blocks in cbfs. It must be called */ +/* once with a valid cbfs file name before hwilib_get_field() can be used. */ +enum cb_err hwilib_find_blocks (const char *hwi_filename); + +/* Use this function to get fields out of supported info blocks */ +/* This function returns the number of copied bytes or 0 on error. */ +uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *data, uint32_t maxlen); + +/* This functions needs to be implemented for every mainboard that uses i210. */ +enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +#endif /* SIEMENS_HWI_LIB_H_ */

1 0

Patch set updated for coreboot: soc/intel/apollolake: Fix northbridge _crs scope
by Lijian Zhao 26 Apr '16

26 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14477 -gerrit commit 542f85cde02c7dde52167d3bd03f4554430a5066 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:19:44 2016 -0700 soc/intel/apollolake: Fix northbridge _crs scope Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 167 +++++++++++++------------- 1 file changed, 84 insertions(+), 83 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 8415ffe..a73a8a9 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -36,97 +36,98 @@ Device (MCHC) Offset(0xBC), TLUD, 32, /* Top of Low Useable DRAM */ } - Name (MCRS, ResourceTemplate() - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,,) - - /* Data and GFX stolen memory */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, - 0x04200000,,, STOM) - - /* - * PCI MMIO Region (TOLUD - PCI extended base MMCONF) - * This assumes that MMCONF is placed after PCI config space, - * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. - */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - }) - - /* Current Resource Settings */ - Method (_CRS, 0, Serialized) - { +} +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + NonCacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, ^PM01._MIN, PMIN) - CreateDwordField (MCRS, ^PM01._MAX, PMAX) - CreateDwordField (MCRS, ^PM01._LEN, PLEN) + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) - /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^TLUD, 0xFFF00000, PMIN) - /* Read MMCONF base */ - And(^MCNF, 0xF0000000, PMAX) + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) - /* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) - /* Find GFX resource area in GCRS */ - CreateDwordField(MCRS, ^STOM._MIN, GMIN) - CreateDwordField(MCRS, ^STOM._MAX, GMAX) - CreateDwordField(MCRS, ^STOM._LEN, GLEN) + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN) - /* Read BGSM */ - And(^BGSM, 0xFFF00000, GMIN) + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) - /* Read TOLUD */ - And(^TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN) - Store (^TUUD, Local0) + Store (^MCHC.TUUD, Local0) - If (LLessEqual (Local0, 0x1000000000)) - { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) + If (LLessEqual (Local0, 0x1000000000)) + { + Store (0, MMIN) + Store (0, MLEN) } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) } +

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coreboot-gerrit April 2016