coreboot-gerrit April 2016

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Patch merged into coreboot/master: nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change
by gerrit＠coreboot.org 25 Apr '16

25 Apr '16

the following patch was just integrated into master: commit 4488d7371a2b05e8f1f6952cc969821dfcd4ce42 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Apr 22 22:16:45 2016 -0500 nb/amd/mct_ddr3: Scale lane delays for each DIMM after MEMCLK change When more than one DIMM is installed on a DCT, only the first DIMM delay values are scaled to the new memory clock frequency after a memory clock change during write leveling. Store the previous memory clock of each DIMM during write leveling to ensure that every DIMM has its delay values rescaled. Change-Id: I56e816d3d3256925598219d92783246f5f4ab567 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14479 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14479 for details. -gerrit

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Patch merged into coreboot/master: board_status/to-wiki: Indicate age of test results by background color
by gerrit＠coreboot.org 25 Apr '16

25 Apr '16

the following patch was just integrated into master: commit 7501b6c285cb8b4f75d3197f8571127a0ad9d504 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Apr 21 17:06:37 2016 -0500 board_status/to-wiki: Indicate age of test results by background color A major issue with the board-status Wiki page is that it shows all test results equally regardless of age. As a test result ages it becomes more likely that the board no longer works peroperly under coreboot due to code churn. Visually indicate board-test status "at a glance" by smoothly fading the background color of the test result from green to yellow as the test result ages. This patch sets the full yellow transition to 255 days after test for programming convenience, however the number of days required to fully "stale" a test result could be modified relatively easily. Change-Id: I5a076a6cc17d53fda8e4681e38074fc1f46c0e12 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/14457 Reviewed-by: Vladimir Serbinenko <phcoder(a)gmail.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14457 for details. -gerrit

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Patch merged into coreboot/master: payloads/Makefile.inc: Add phony targets
by gerrit＠coreboot.org 25 Apr '16

25 Apr '16

the following patch was just integrated into master: commit 3383a25f91fab26ce20f40f9981eeee5b2ba9eb0 Author: Martin Roth <martinroth(a)google.com> Date: Sat Apr 23 17:12:28 2016 -0600 payloads/Makefile.inc: Add phony targets Add 'nvramcui' target to make it easier to build and test. Put both nvramcui & coreinfo targets into .PHONY because they both exist as directories. Change-Id: I9cf76785e69f3c8e47fe92f1b1648fd0f7a63c3e Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/14481 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/14481 for details. -gerrit

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New patch to review for coreboot: mc_tcu3: Switch to hwilib instead of own hwinfo implementation
by Werner Zeh 25 Apr '16

25 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14506 -gerrit commit 4a0db09a83234ee0da34fc3bcb9f17f6956c91f2 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Mon Apr 25 12:24:17 2016 +0200 mc_tcu3: Switch to hwilib instead of own hwinfo implementation Use hwilib in vendorcode/siemens/hwilib to get fields from hwinfo instead of having mainboard specific hwinfo code. This patch do not change the functional behavior in any way. Change-Id: Idb226a82a08b1b753f654c5cde106236e72f33c3 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/Kconfig | 1 + src/mainboard/siemens/mc_tcu3/Makefile.inc | 3 - src/mainboard/siemens/mc_tcu3/lcd_panel.c | 26 ++--- src/mainboard/siemens/mc_tcu3/mainboard.c | 40 ++++++- src/mainboard/siemens/mc_tcu3/modhwinfo.c | 144 ------------------------- src/mainboard/siemens/mc_tcu3/modhwinfo.h | 166 ----------------------------- src/mainboard/siemens/mc_tcu3/ptn3460.c | 49 ++++++--- src/mainboard/siemens/mc_tcu3/ptn3460.h | 3 +- src/mainboard/siemens/mc_tcu3/romstage.c | 65 ++++++----- 9 files changed, 120 insertions(+), 377 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/Kconfig b/src/mainboard/siemens/mc_tcu3/Kconfig index d7ff867..5ff233d 100644 --- a/src/mainboard/siemens/mc_tcu3/Kconfig +++ b/src/mainboard/siemens/mc_tcu3/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select USE_BLOBS select CBFS_AUTOGEN_ATTRIBUTES select FSP_BAYTRAIL_GFX_INIT + select USE_SIEMENS_HWILIB config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc index 12be6a7..2922eef 100644 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -13,11 +13,8 @@ ## GNU General Public License for more details. ## -romstage-y += modhwinfo.c - ramstage-y += gpio.c ramstage-y += irqroute.c -ramstage-y += modhwinfo.c ramstage-y += lcd_panel.c ramstage-y += ptn3460.c diff --git a/src/mainboard/siemens/mc_tcu3/lcd_panel.c b/src/mainboard/siemens/mc_tcu3/lcd_panel.c index 91159f9..214773a 100644 --- a/src/mainboard/siemens/mc_tcu3/lcd_panel.c +++ b/src/mainboard/siemens/mc_tcu3/lcd_panel.c @@ -15,11 +15,11 @@ #include <cbfs.h> #include <console/console.h> #include <string.h> -#include "modhwinfo.h" #include "soc/gpio.h" #include "lcd_panel.h" #include "ptn3460.h" + /** \brief Reads GPIOs used for LCD panel encoding and returns the 4 bit value * @param no parameters * @return LCD panel type encoded in 4 bits @@ -42,10 +42,8 @@ u8 get_lcd_panel_type(void) */ int setup_lcd_panel(void) { - u8 lcd_type; + u8 lcd_type; int status; - struct edidinfo *eib = NULL; - struct shortinfo *sib = NULL; char blockname[33]; lcd_type = get_lcd_panel_type(); @@ -71,20 +69,12 @@ int setup_lcd_panel(void) status = 1; break; } - - /* Now that we have the panel type, get the matching block and setup */ - /* the DP2LVDS converter accordingly */ - eib = get_edidinfo(blockname); - sib = get_shortinfo(blockname); - - if ((!eib) || (!sib)) { - printk(BIOS_ERR, "LCD: Info block named \"%s\" not found!\n", blockname); - status = 1; - } else { - printk(BIOS_INFO, "LCD: Found SIB at 0x%x, EIB at 0x%x\n", - (int)sib, (int)eib); - status = ptn3460_init(lcd_type, eib, sib); + /* Now that we have the panel type, setup the DP2LVDS converter */ + status = ptn3460_init(blockname); + if (status) + printk(BIOS_ERR, "LCD: Setup PTN with status 0x%x\n", status); + else printk(BIOS_INFO, "LCD: Setup PTN with status 0x%x\n", status); - } + return status; } diff --git a/src/mainboard/siemens/mc_tcu3/mainboard.c b/src/mainboard/siemens/mc_tcu3/mainboard.c index 8a966dc..cdea2ec 100644 --- a/src/mainboard/siemens/mc_tcu3/mainboard.c +++ b/src/mainboard/siemens/mc_tcu3/mainboard.c @@ -29,9 +29,47 @@ #include <arch/io.h> #include <arch/interrupt.h> #include <boot/coreboot_tables.h> - +#include <hwilib.h> #include "lcd_panel.h" + +/** \brief This function will search for a MAC address which can be assigned + * to a MACPHY. + * @param pci_bdf Bus, device and function of the given PCI-device + * @param mac buffer where to store the MAC address + * @return cb_err CB_ERR or CB_SUCCESS + */ +enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) +{ + uint8_t mac_adr[6]; + u32 i; + + /* Open main hwinfo block */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return CB_ERR; + /* Get first MAC address from hwinfo. */ + if (hwilib_get_field(Mac1, mac_adr) != sizeof(mac_adr)) + return CB_ERR; + /* Ensure the first MAC-Address is not completely 0x00 or 0xff */ + for (i = 0; i < 6; i++) { + if (mac_adr[i] != 0xFF) + break; + } + if (i == 6){ + return CB_ERR; + } + for (i = 0; i < 6; i++) { + if (mac_adr[i] != 0x00) + break; + } + if (i == 6){ + return CB_ERR; + } else { + memcpy(mac, mac_adr, 6); + return CB_SUCCESS; + } +} + /* * mainboard_enable is executed as first thing after enumerate_buses(). * This is the earliest point to add customization. diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.c b/src/mainboard/siemens/mc_tcu3/modhwinfo.c deleted file mode 100644 index ac7404b..0000000 --- a/src/mainboard/siemens/mc_tcu3/modhwinfo.c +++ /dev/null @@ -1,144 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Siemens AG. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include "modhwinfo.h" -#include "lcd_panel.h" -#include <cbfs.h> -#include <string.h> - -/** \brief This function will find the first linked info block. - * @param *filename Filename in cbfs - * @param *file_offset Pointer to the offset of the cbfs file contents - * @return u8* Pointer to the found block - */ -u8* get_first_linked_block(char *filename, u8 **file_offset) -{ - u8* block_ptr = NULL; - - block_ptr = cbfs_boot_map_with_leak(filename, 0x50, NULL); - if (!block_ptr) - return NULL; - if (!strncmp((char*)block_ptr, "H1W2M3I4", LEN_MAGIC_NUM)) { - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET)) == LEN_MAIN_HWINFO) && - (*((s32*)(block_ptr + NEXT_OFFSET_HWINFO)) != 0x00)) { - *file_offset = block_ptr; - return *((s32*)(block_ptr + NEXT_OFFSET_HWINFO)) + block_ptr; - } else - return NULL; - } else if (!strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM)) { - *file_offset = block_ptr; - return block_ptr; - } else - return NULL; -} - -/** \brief This function will find the main info block - * @param *filename Filename in cbfs - * @return *hwinfo Pointer to the data of the main info block - */ -struct hwinfo* get_hwinfo(char *filename) -{ - struct hwinfo* main_hwinfo; - - main_hwinfo = cbfs_boot_map_with_leak(filename, 0x50, NULL); - if ((main_hwinfo) && - (!strncmp(main_hwinfo->magicNumber, "H1W2M3I4", LEN_MAGIC_NUM)) && - (main_hwinfo->length == LEN_MAIN_HWINFO)) - return main_hwinfo; - else - return NULL; -} - -/** \brief This function will find the short info block - * @param *filename Filename in cbfs - * @return *shortinfo Pointer to the data of the short info block - */ -struct shortinfo* get_shortinfo(char *filename) -{ - u8 *block_ptr = NULL; - u8 *file_offset = NULL; - - block_ptr = get_first_linked_block(filename, &file_offset); - if ((block_ptr == NULL) || - (strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM))) - return NULL; - - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_SHORT_INFO) - return (struct shortinfo *)block_ptr; - - block_ptr = (file_offset + *((s32*)(block_ptr + NEXT_OFFSET_EDID))); - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_SHORT_INFO) - return (struct shortinfo *)block_ptr; - else - return NULL; -} - -/** \brief This function will find the edid info block - * @param *filename Filename in cbfs - * @return *edidinfo Pointer to the data of the edid info block - */ -struct edidinfo* get_edidinfo(char *filename) -{ - u8 *block_ptr = NULL; - u8 *file_offset = NULL; - - block_ptr = get_first_linked_block(filename, &file_offset); - if ((block_ptr == NULL) || - (strncmp((char*)block_ptr, "H1W2M3I5", LEN_MAGIC_NUM))) - return NULL; - - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_EDID_INFO) - return (struct edidinfo *)block_ptr; - - block_ptr = (file_offset + *((s32*)(block_ptr + NEXT_OFFSET_SIB))); - if ((*((u16*)(block_ptr + HWI_LEN_OFFSET))) == LEN_EDID_INFO) - return (struct edidinfo *)block_ptr; - else - return NULL; -} - -/** \brief This function will search for a MAC address which can be assigned - * to a MACPHY. - * @param pci_bdf Bus, device and function of the given PCI-device - * @param mac buffer where to store the MAC address - * @return cb_err CB_ERR or CB_SUCCESS - */ -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]) -{ - struct hwinfo* main_hwinfo; - u32 i; - - main_hwinfo = get_hwinfo((char*)"hwinfo.hex"); - if (!main_hwinfo) - return CB_ERR; - /* Ensure the first MAC-Address is not completely 0x00 or 0xff */ - for (i = 0; i < 6; i++) { - if (main_hwinfo->macAddress1[i] != 0xFF) - break; - } - if (i == 6){ - return CB_ERR; - } - for (i = 0; i < 6; i++) { - if (main_hwinfo->macAddress1[i] != 0x00) - break; - } - if (i == 6){ - return CB_ERR; - } else { - memcpy(mac, main_hwinfo->macAddress1, 6); - return CB_SUCCESS; - } -} diff --git a/src/mainboard/siemens/mc_tcu3/modhwinfo.h b/src/mainboard/siemens/mc_tcu3/modhwinfo.h deleted file mode 100644 index 6bf891c..0000000 --- a/src/mainboard/siemens/mc_tcu3/modhwinfo.h +++ /dev/null @@ -1,166 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Siemens AG - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _MODHWINFO_H_ -#define _MODHWINFO_H_ - -#include <types.h> - -#define LEN_MAGIC_NUM 8 -#define LEN_MLFB 20 -#define LEN_SERIAL_NUM 16 -#define LEN_HW_REVISION 2 -#define LEN_MAC_ADDRESS 6 -#define LEN_SPD 128 -#define NUMBER_OF_MAC_ADDR 4 -#define LEN_EDID 128 -#define LEN_MAIN_HWINFO 509 -#define LEN_SHORT_INFO 289 -#define LEN_EDID_INFO 181 -#define NEXT_OFFSET_HWINFO 476 -#define NEXT_OFFSET_SIB 260 -#define NEXT_OFFSET_EDID 176 -#define HWI_LEN_OFFSET 12 - -/* Define some masks and values */ -#define SIB_HWINIT_IDX 0x0e -#define SIB_COLOR_6BIT 0x00 -#define SIB_COLOR_8BIT 0x01 -#define SIB_COLOR_10BIT 0x02 -#define SIB_DISP_CON_IDX 0x16 -#define SIB_LVDS_SINGLE_LANE 0x00 -#define SIB_LVDS_DUAL_LANE 0x05 - -struct PhysDevStruc { - u8 bustype; - u8 devfn; - u16 bus; -} __attribute__ ((packed)); - - -struct hwinfo { -// Offset 0x0 - char magicNumber[LEN_MAGIC_NUM]; -// Offset 0x08 - u8 versionID[4]; -// Offset 0x0c - u16 length; -// Offset 0x0e - char BGR_Name[128]; -//Offset 0x8e - char MLFB[LEN_MLFB]; -// Offset 0xa2 - u8 uniqueNumber[16]; -// Offset 0xb2 - u8 fill_1[12]; -// Offset 0xbe - u8 hwRevision[LEN_HW_REVISION]; -//Offset 0xc0 - u8 macAddress1[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr1; - u8 fill_2; -//Offset 0xc8 - u8 macAddress2[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr2; - u8 fill_3; -//Offset 0xd0 - u8 macAddress3[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr3; - u8 fill_4; -//Offset 0xd8 - u8 macAddress4[LEN_MAC_ADDRESS]; - u8 numOfAuxMacAddr4; - u8 fill_5; -// Offset 0xe0 - u8 SPD[LEN_SPD]; -// Offset 0x160 - u8 fill_6[88]; -// Offset 0x1b8 - u32 featureFlags; -// Offset 0x1bc - u8 fill_7[4]; -// Offset 0x1c0 - u32 biosFlags; -// Offset 0x1c4 - u8 fill_8[8]; -//Offset 0x1cc - struct PhysDevStruc etherDev[NUMBER_OF_MAC_ADDR]; -// Offset 0x1dc - s32 nextInfoOffset; -// Offset 0x1e0 - u8 fill_9[4]; -// Offset 0x1e4 - u32 portRTC; -// Offset 0x1e8 - u8 typeRTC; -// Offset 0x1e9 - u8 fill_10[20]; -} __attribute__ ((packed)); - -struct shortinfo { -// Offset 0x0 - char magicNumber[LEN_MAGIC_NUM]; -// Offset 0x08 - u8 versionID[4]; -// Offset 0x0c - u16 length; -// Offset 0x0e - char BGR_Name[128]; -//Offset 0x8e - char MLFB[LEN_MLFB]; -// Offset 0xa2 - u8 uniqueNumber[26]; -// Offset 0xbc - u8 fill_1[12]; -//Offset 0xc8 - u8 hwRevision[2]; -// Offset 0xca - u8 fill_2[18]; -// Offset 0xdc - u8 panelFeatures[32]; -// Offset 0xfc - u8 fill_3[8]; -// Offset 0x104 - s32 nextInfoOffset; -// Offset 0x108 - u8 fill_4[25]; -} __attribute__ ((packed)); - -struct edidinfo { -// Offset 0x0 - char magicNumber[LEN_MAGIC_NUM]; -// Offset 0x08 - u8 versionID[4]; -// Offset 0x0c - u16 length; -// Offset 0x0e - u8 fill_1[2]; -// Offset 0x10 - u8 edid[LEN_EDID]; -// Offset 0x90 - u8 fill_2[32]; -// Offset 0xb0 - s32 nextInfoOffset; -// Offset 0xb4 - u8 fill_3; -} __attribute__ ((packed)); - -u8* get_first_linked_block(char *filename, u8 **starting_adr); -struct hwinfo* get_hwinfo(char *filename); -struct shortinfo* get_shortinfo(char *filename); -struct edidinfo* get_edidinfo(char *filename); -enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); - -#endif /* _MODHWINFO_H_ */ diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index e371e53..0b5fc7f 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -14,33 +14,52 @@ */ #include <console/console.h> +#include <hwilib.h> #include "soc/i2c.h" #include "ptn3460.h" /** \brief This functions sets up the DP2LVDS-converter to be used with the * appropriate lcd panel - * @param lcd_type Type of LCD we should set up the converter for - * @param *sib Pointer to short info block structure - * @param *eib Pointer to EDID info block structure - * @return 0 on success or error code + * @param *hwi_block Filename in CBFS of the block to use as HW-Info + * @return 0 on success or error code */ -int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib) +int ptn3460_init(char *hwi_block) { struct ptn_3460_config cfg; int status; + uint8_t disp_con = 0, color_depth = 0; + uint8_t edid_data[0x80]; + if (!hwi_block || hwilib_find_blocks(hwi_block) != CB_SUCCESS) { + printk(BIOS_ERR, "LCD: Info block \"%s\" not found!\n", + hwi_block); + return 1; + } status = i2c_init(PTN_I2C_CONTROLER); if (status) return (PTN_BUS_ERROR | status); - /* If we are here, we have all the desired information for setting up */ - /* DP2LVDS converter. In addition, the information matches the connected */ - /* LCD-panel and therefore, we do not have to distinguish between */ - /* different panels here for the timing. Inside the converter, table 6 */ - /* will be used for the timings. */ - status = ptn3460_write_edid(6, eib->edid); - if (status) + /* Get all needed information from hwinfo block */ + if (hwilib_get_field(Edid, edid_data) != sizeof(edid_data)) { + printk(BIOS_ERR, "LCD: No EDID data available in %s\n", + hwi_block); + return 1; + } + if ((hwilib_get_field(PF_DisplCon, &disp_con) != 1)) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + if (hwilib_get_field(PF_Color_Depth ,&color_depth) != 1) { + printk(BIOS_ERR, "LCD: Missing panel features from %s\n", + hwi_block); + return 1; + } + /* Here, all the desired information for setting up DP2LVDS converter*/ + /* are present. Inside the converter, table 6 will be used for */ + /* the timings. */ + if ((status = ptn3460_write_edid(6, edid_data)) != 0) return status; /* Select this table to be emulated */ ptn_select_edid(6); @@ -50,12 +69,12 @@ int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib) if (status) return (PTN_BUS_ERROR | status); - /* Set up configuration data according to the information blocks we get */ + /* Set up configuration data according to the hwinfo blocks we get */ cfg.dp_interface_ctrl = 0; cfg.lvds_interface_ctrl1 = 0x00; - if (sib->panelFeatures[SIB_DISP_CON_IDX] == SIB_LVDS_DUAL_LANE) + if (disp_con == PF_DISPLCON_LVDS_DUAL) cfg.lvds_interface_ctrl1 |= 0x0b; /* Turn on dual LVDS lane and clock */ - if ((sib->panelFeatures[SIB_HWINIT_IDX] & 0x03) == SIB_COLOR_6BIT) + if (color_depth == PF_COLOR_DEPTH_6BIT) cfg.lvds_interface_ctrl1 |= 0x20; /* Use 18 bits per pixel */ cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.h b/src/mainboard/siemens/mc_tcu3/ptn3460.h index 3e0c065..533607c 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.h +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.h @@ -17,7 +17,6 @@ #define PTN3460_H_ #include <delay.h> -#include "modhwinfo.h" #include "lcd_panel.h" #define PTN_SLAVE_ADR 0x20 @@ -66,7 +65,7 @@ struct ptn_3460_flash{ }__attribute__((packed)); -int ptn3460_init(char lcd_type, struct edidinfo *eib, struct shortinfo *sib); +int ptn3460_init(char *hwi_block); int ptn3460_read_edid(u8 edid_num, u8 *data); int ptn3460_write_edid(u8 edid_num, u8 *data); int ptn_select_edid(u8 edid_num); diff --git a/src/mainboard/siemens/mc_tcu3/romstage.c b/src/mainboard/siemens/mc_tcu3/romstage.c index 1fa78ca..d076790 100644 --- a/src/mainboard/siemens/mc_tcu3/romstage.c +++ b/src/mainboard/siemens/mc_tcu3/romstage.c @@ -33,7 +33,7 @@ #include <soc/acpi.h> #include <soc/baytrail.h> #include <drivers/intel/fsp1_0/fsp_util.h> -#include "modhwinfo.h" +#include <hwilib.h> /** * /brief mainboard call for setup that needs to be done before fsp init @@ -166,35 +166,44 @@ const PCH_AZALIA_CONFIG mainboard_AzaliaConfig = { */ void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) { - struct hwinfo *hwi_main; + uint8_t spd[0x80]; UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr; - /* Initialize the Azalia Verb Tables to mainboard specific version */ + /* Initialize the Azalia Verb Tables to mainboard specific version. */ UpdData->AzaliaConfigPtr = (UINT32)&mainboard_AzaliaConfig; - /* Get SPD data from hardware information block and setup memory down */ - /* parameters for FSP accordingly */ - hwi_main = get_hwinfo((char*)"hwinfo.hex"); - if (hwi_main) { - UpdData->PcdMemoryParameters.EnableMemoryDown = 1; - UpdData->PcdMemoryParameters.DRAMType = hwi_main->SPD[2]; - UpdData->PcdMemoryParameters.DIMM0Enable = hwi_main->SPD[3] & 0x01; - UpdData->PcdMemoryParameters.DIMM1Enable = (hwi_main->SPD[3] >> 1) & 0x01; - UpdData->PcdMemoryParameters.DIMMDensity = hwi_main->SPD[4]; - UpdData->PcdMemoryParameters.DIMMDWidth = hwi_main->SPD[5]; - UpdData->PcdMemoryParameters.DIMMSides = hwi_main->SPD[7]; - UpdData->PcdMemoryParameters.DIMMBusWidth = hwi_main->SPD[8]; - UpdData->PcdMemoryParameters.DRAMSpeed = hwi_main->SPD[12]; - UpdData->PcdMemoryParameters.DIMMtCL = hwi_main->SPD[14]; - UpdData->PcdMemoryParameters.DIMMtWR = hwi_main->SPD[17]; - UpdData->PcdMemoryParameters.DIMMtRPtRCD = hwi_main->SPD[18]; - UpdData->PcdMemoryParameters.DIMMtRRD = hwi_main->SPD[19]; - UpdData->PcdMemoryParameters.DIMMtWTR = hwi_main->SPD[26]; - UpdData->PcdMemoryParameters.DIMMtRTP = hwi_main->SPD[27]; - UpdData->PcdMemoryParameters.DIMMtFAW = hwi_main->SPD[28]; - /*If one need output from MRC to be used in Intel RMT, simply */ - /*enable the following line */ - //UpdData->PcdMrcDebugMsg = 1; - } else - printk(BIOS_ERR, "HWInfo not found, leave default timings for DDR3.\n"); + /* Get SPD data from hwinfo block and set up memory down */ + /* parameters for FSP accordingly. */ + if (hwilib_find_blocks("hwinfo.hex")) { + printk(BIOS_ERR, + "HWInfo not found, use default timings for DDR3.\n"); + return; + } + + if (hwilib_get_field(SPD, spd) != sizeof(spd)) { + printk(BIOS_ERR, + "SPD not found in HWInfo, use defaults for DDR3.\n"); + return; + } + /*Set up DDR timings from HWInfo. */ + UpdData->PcdMemoryParameters.EnableMemoryDown = 1; + UpdData->PcdMemoryParameters.DRAMType = spd[2]; + UpdData->PcdMemoryParameters.DIMM0Enable = spd[3] & 0x01; + UpdData->PcdMemoryParameters.DIMM1Enable = (spd[3] >> 1) & 0x01; + UpdData->PcdMemoryParameters.DIMMDensity = spd[4]; + UpdData->PcdMemoryParameters.DIMMDWidth = spd[5]; + UpdData->PcdMemoryParameters.DIMMSides = spd[7]; + UpdData->PcdMemoryParameters.DIMMBusWidth = spd[8]; + UpdData->PcdMemoryParameters.DRAMSpeed = spd[12]; + UpdData->PcdMemoryParameters.DIMMtCL = spd[14]; + UpdData->PcdMemoryParameters.DIMMtWR = spd[17]; + UpdData->PcdMemoryParameters.DIMMtRPtRCD = spd[18]; + UpdData->PcdMemoryParameters.DIMMtRRD = spd[19]; + UpdData->PcdMemoryParameters.DIMMtWTR = spd[26]; + UpdData->PcdMemoryParameters.DIMMtRTP = spd[27]; + UpdData->PcdMemoryParameters.DIMMtFAW = spd[28]; + + /*If one need output from MRC to be used in Intel RMT, simply */ + /*enable the following line */ + //UpdData->PcdMrcDebugMsg = 1; }

1 0

New patch to review for coreboot: vendorcode/siemens: Add hwilib for Siemens specific info struct
by Werner Zeh 25 Apr '16

25 Apr '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14505 -gerrit commit c9047fb8720a1bf37ba701304a4618385f88c1fc Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Apr 22 14:14:45 2016 +0200 vendorcode/siemens: Add hwilib for Siemens specific info struct Add a library which unifies access to Siemens specific hardware information data. This library is meant to be used with Siemens platforms and can be selected in Kconfig. The needed source of information has to be present in cbfs. This lib can be used in romstage and ramstage. Change-Id: I2c6e003b0c123b4cf6a84906c2b133b8c38c8b1a Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/vendorcode/Makefile.inc | 1 + src/vendorcode/siemens/Kconfig | 20 ++ src/vendorcode/siemens/Makefile.inc | 16 ++ src/vendorcode/siemens/hwilib/Makefile.inc | 19 ++ src/vendorcode/siemens/hwilib/hwilib.c | 305 +++++++++++++++++++++++++++++ src/vendorcode/siemens/hwilib/hwilib.h | 70 +++++++ 6 files changed, 431 insertions(+) diff --git a/src/vendorcode/Makefile.inc b/src/vendorcode/Makefile.inc index 741a04a..440972f 100644 --- a/src/vendorcode/Makefile.inc +++ b/src/vendorcode/Makefile.inc @@ -1,3 +1,4 @@ subdirs-y += amd subdirs-y += google subdirs-y += intel +subdirs-y += siemens diff --git a/src/vendorcode/siemens/Kconfig b/src/vendorcode/siemens/Kconfig new file mode 100644 index 0000000..8bbab62 --- /dev/null +++ b/src/vendorcode/siemens/Kconfig @@ -0,0 +1,20 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config USE_SIEMENS_HWILIB + bool + default n + +source "src/vendorcode/siemens/*/Kconfig" diff --git a/src/vendorcode/siemens/Makefile.inc b/src/vendorcode/siemens/Makefile.inc new file mode 100644 index 0000000..ece2b4d --- /dev/null +++ b/src/vendorcode/siemens/Makefile.inc @@ -0,0 +1,16 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +subdirs-$(CONFIG_USE_SIEMENS_HWILIB) += hwilib diff --git a/src/vendorcode/siemens/hwilib/Makefile.inc b/src/vendorcode/siemens/hwilib/Makefile.inc new file mode 100644 index 0000000..1c6f6c9 --- /dev/null +++ b/src/vendorcode/siemens/hwilib/Makefile.inc @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Siemens AG +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +CFLAGS_x86_32 += -Isrc/vendorcode/siemens/hwilib + +romstage-y += hwilib.c +ramstage-y += hwilib.c diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c new file mode 100644 index 0000000..36da0a7 --- /dev/null +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -0,0 +1,305 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <cbfs.h> +#include <string.h> +#include <console/console.h> +#include <arch/io.h> +#include <arch/early_variables.h> +#include "hwilib.h" + + +#define MAX_BLOCK_NUM 3 +#define LEN_HIB 0x1fd +#define LEN_SIB 0x121 +#define LEN_EIB 0x0b5 +#define NEXT_OFFSET_HIB 0x1dc +#define NEXT_OFFSET_SIB 0x104 +#define NEXT_OFFSET_EIB 0x0b0 +#define LEN_UNIQUEL_NUM 0x010 +#define LEN_HW_REV 0x002 +#define LEN_MAC_ADDRESS 0x006 +#define LEN_SPD 0x080 +#define LEN_EDID 0x080 +#define LEN_OFFSET 0x00c +#define EIB_FEATRUE_OFFSET 0x00e +#define LEN_MAGIC_NUM 0x007 +#define BLOCK_MAGIC "H1W2M3I" + +/* Define all supported block types. */ +enum { + EMPTY = 0, + BLK_HIB, + BLK_SIB, + BLK_EIB, +}; + +/* Some forward-declarations which must be used inside structures. */ +struct param_info; +static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst); + +/* This structure holds a valid position for a given field */ +/* Every field can have multiple positions of which the first available */ +/* will be taken by the library. */ +struct param_pos { + uint8_t blk_type; /* Valid for a specific block type */ + uint32_t offset; /* Offset in given block */ + uint32_t len; /* Length for the field in this block */ +}; + +/* This structure holds all the needed information for a given field type */ +/* and a pointer to a function which is able to extracting the desired data. */ +struct param_info { + struct param_pos pos[MAX_BLOCK_NUM]; + uint64_t mask; + uint8_t mask_offset; + uint32_t (*get_field)(const struct param_info *param, uint8_t *dst); +}; + +/* Storage for pointers to the different blocks. The contents will be filled */ +/* in hwilib_find_blocks(). */ +static uint8_t *all_blocks[MAX_BLOCK_NUM + 1] CAR_GLOBAL; + +/* Add all supported fields to this variable. It is important to use the */ +/* field type of a given field as the array index so that all the information */ +/* is on the appropriate place inside the array. In this way one do not need */ +/* to search for fields but can simply use an index into the array. */ +const struct param_info params[] = { + [HIB_VerID] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, + [SIB_VerID] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, + [EIB_VerID] = { + .pos[0] = {.blk_type = BLK_EIB, .offset = 0x8, .len = 4}, + .get_field = hwilib_read_bytes }, + [HIB_HwRev] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xbe, .len = 2}, + .get_field = hwilib_read_bytes }, + [SIB_HwRev] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xc8, .len = 2}, + .get_field = hwilib_read_bytes }, + [UniqueNum] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xa2, .len = 10}, + .pos[1] = {.blk_type = BLK_SIB, .offset = 0xa2, .len = 10}, + .get_field = hwilib_read_bytes }, + [Mac1] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xc0, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac1Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xc6, .len = 1}, + .get_field = hwilib_read_bytes }, + [Mac2] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xc8, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac2Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xce, .len = 1}, + .get_field = hwilib_read_bytes }, + [Mac3] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xd0, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac3Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xd6, .len = 1}, + .get_field = hwilib_read_bytes }, + [Mac4] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xd8, .len = 6}, + .get_field = hwilib_read_bytes }, + [Mac4Aux] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xde, .len = 1}, + .get_field = hwilib_read_bytes }, + [SPD] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0xe0, .len = 0x80}, + .get_field = hwilib_read_bytes }, + [FF_FreezeDis] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1b8, .len = 4}, + .mask = 0x10, + .mask_offset = 4, + .get_field = hwilib_read_bytes }, + [FF_FanReq] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1b8, .len = 4}, + .mask = 0x400, + .mask_offset = 10, + .get_field = hwilib_read_bytes }, + [BiosFlags] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1c0, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping1] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1cc, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping2] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d0, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping3] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d4, .len = 4}, + .get_field = hwilib_read_bytes }, + [MacMapping4] = { + .pos[0] = {.blk_type = BLK_HIB, .offset = 0x1d8, .len = 4}, + .get_field = hwilib_read_bytes }, + [PF_Color_Depth] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xea, .len = 1}, + .mask = 0x03, + .mask_offset = 0, + .get_field = hwilib_read_bytes }, + [PF_DisplType] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xe3, .len = 1}, + .get_field = hwilib_read_bytes }, + [PF_DisplCon] = { + .pos[0] = {.blk_type = BLK_SIB, .offset = 0xf2, .len = 1}, + .get_field = hwilib_read_bytes }, + [Edid] = { + .pos[0] = {.blk_type = BLK_EIB, .offset = 0x10, .len = 0x80}, + .get_field = hwilib_read_bytes }, + [VddRef] = { + .pos[0] = {.blk_type = BLK_EIB, .offset = 0x90, .len = 2}, + .get_field = hwilib_read_bytes }, +}; + +/** \brief This functions reads the given field from the first valid hwinfo + * block + * @param *param Parameter to read from hwinfo + * @param *dst Pointer to memory where the data will be stored in + * @return number of copied bytes on success, 0 on error + */ +static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst) +{ + uint8_t i = 0, *blk = NULL; + + if (!param || !dst) + return 0; + /* Take the first valid block to get the parameter from */ + do { + if ((param->pos[i].blk_type != EMPTY) && + car_get_var(all_blocks[param->pos[i].blk_type])) { + blk = car_get_var(all_blocks[param->pos[i].blk_type]); + break; + } + i++; + } while (i < MAX_BLOCK_NUM + 1); + + /* Ensure there is a valid block available for this parameter. */ + if (!blk) + return 0; + /* We can now copy the wanted data. */ + memcpy(dst, (blk + param->pos[i].offset), param->pos[i].len); + /* If there is a mask given, apply it only for parameters with a */ + /* length of 1, 2, 4 or 8 bytes. */ + if (param->mask) { + switch (param->pos[i].len) { + case 1: + /* Apply a mask on a 8 bit value */ + *dst &= (param->mask & 0xff); + *dst >>= (param->mask_offset); + break; + case 2: + /* Apply mask on a 16 bit value */ + *((uint16_t *)(dst)) &= (param->mask & 0xffff); + *((uint16_t *)(dst)) >>= (param->mask_offset); + break; + case 4: + /* Apply mask on a 32 bit value */ + *((uint32_t *)(dst)) &= (param->mask & 0xffffffff); + *((uint32_t *)(dst)) >>= (param->mask_offset); + break; + case 8: + /* Apply mask on a 64 bit value */ + *((uint64_t *)(dst)) &= (param->mask); + *((uint64_t *)(dst)) >>= (param->mask_offset); + break; + default: + /* Warn if there is a mask for an invalid length. */ + printk(BIOS_WARNING, + "HWILIB: Invalid field length for given mask.\n"); + break; + } + } + return param->pos[i].len; +} + +/** \brief This function finds all available block types in a given cbfs file. + * @param *hwi_filename Name of the cbfs-file to use. + * @return CB_SUCCESS when no error, otherwise error code + */ +enum cb_err hwilib_find_blocks (const char *hwi_filename) +{ + uint8_t *ptr = NULL, *base = NULL, i = 0; + uint32_t next_offset = 1; + + /* Check for a valid parameter */ + if (!hwi_filename) + return CB_ERR_ARG; + ptr = cbfs_boot_map_with_leak(hwi_filename, CBFS_TYPE_RAW, NULL); + if (!ptr) { + printk(BIOS_ERR,"HWILIB: Missing file \"%s\" in cbfs.\n", + hwi_filename); + return CB_ERR; + } + /* Ensure the block has the right magic */ + if (strncmp((char*)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) { + printk(BIOS_ERR, "HWILIB: Bad magic at start of block!\n"); + return CB_ERR; + } + /* Reset all static pointers to blocks as they might have been set */ + /* in prior calls to this function. */ + /* This way the caller do not need to "close" already opened blocks. */ + for (i = 0; i < MAX_BLOCK_NUM + 1; i++) + car_set_var(all_blocks[i], NULL); + /* Check which blocks are available by examining the length field. */ + base = ptr; + while(!(strncmp((char *)ptr, BLOCK_MAGIC, LEN_MAGIC_NUM)) && + next_offset) { + uint16_t len = read16(ptr + LEN_OFFSET); + if (len == LEN_HIB) { + car_set_var(all_blocks[BLK_HIB], ptr); + next_offset = read32(ptr + NEXT_OFFSET_HIB); + if (next_offset) + ptr = base + next_offset; + } else if (len == LEN_SIB) { + car_set_var(all_blocks[BLK_SIB], ptr); + next_offset = read32(ptr + NEXT_OFFSET_SIB); + if (next_offset) + ptr = base + next_offset; + } else if (len == LEN_EIB) { + /* Skip preliminary blocks */ + if (!(read16(ptr + EIB_FEATRUE_OFFSET) & 0x01)) + car_set_var(all_blocks[BLK_EIB], ptr); + next_offset = read32(ptr + NEXT_OFFSET_EIB); + if (next_offset) + ptr = base + next_offset; + }else { + next_offset = 0; + } + } + /* We should have found at least one valid block */ + if (car_get_var(all_blocks[BLK_HIB]) || car_get_var(all_blocks[BLK_SIB]) + || car_get_var(all_blocks[BLK_EIB])) + return CB_SUCCESS; + else + return CB_ERR; +} + + +/* Use this function to ask the lib for fields from info blocks. */ +/** \brief This functions is used from caller to get a specific field from + * hwinfo block. + * @param field Field type to read from hwinfo + * @param *dst Pointer to memory where the data will be stored in + * @return number of copied bytes on success, 0 on error + */ +uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *dst) +{ + return params[field].get_field(&params[field], dst); +} diff --git a/src/vendorcode/siemens/hwilib/hwilib.h b/src/vendorcode/siemens/hwilib/hwilib.h new file mode 100644 index 0000000..3641670 --- /dev/null +++ b/src/vendorcode/siemens/hwilib/hwilib.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Siemens AG + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SIEMENS_HWI_LIB_H_ +#define SIEMENS_HWI_LIB_H_ + +#include <types.h> + + +/* Declare all supported fields which can be get with hwilib. */ +typedef enum { + HIB_VerID = 0, + SIB_VerID, + EIB_VerID, + HIB_HwRev, + SIB_HwRev, + UniqueNum, + Mac1, + Mac1Aux, + Mac2, + Mac2Aux, + Mac3, + Mac3Aux, + Mac4, + Mac4Aux, + SPD, + FF_FreezeDis, + FF_FanReq, + BiosFlags, + MacMapping1, + MacMapping2, + MacMapping3, + MacMapping4, + PF_Color_Depth, + PF_DisplType, + PF_DisplCon, + Edid, + VddRef +}hwinfo_field_t; + +/* Define used values in supported fields */ +#define PF_COLOR_DEPTH_6BIT 0x00 +#define PF_COLOR_DEPTH_8BIT 0x01 +#define PF_COLOR_DEPTH_10BIT 0x02 +#define PF_DISPLCON_LVDS_SINGLE 0x00 +#define PF_DISPLCON_LVDS_DUAL 0x05 +#define FF_FREEZE_DISABLE 0x01 +#define FF_FAN_NEEDED 0x01 + +/* Use this function to find all supported blocks in cbfs */ +enum cb_err hwilib_find_blocks (const char *hwi_filename); + +/* Use this function to get fields out of supported info blocks */ +uint32_t hwilib_get_field (hwinfo_field_t field, uint8_t *data); + +/* This functions needs to be implemented for every mainboard that uses i210. */ +enum cb_err mainboard_get_mac_address(u16 bus, u8 devfn, u8 mac[6]); +#endif /* SIEMENS_HWI_LIB_H_ */

1 0

Patch set updated for coreboot: console/serialice: Add SerialICE
by Patrick Rudolph 25 Apr '16

25 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 7340695a6f84a0b447292fc6ddeabedd80bed7b0 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520. Needs tests: * Ramstage * Serial cable * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/Kconfig | 27 +++ src/console/Makefile.inc | 2 + src/console/init.c | 13 + src/console/serialice.c | 446 +++++++++++++++++++++++++++++++++++ src/include/console/serialice.h | 27 +++ src/include/console/serialice_priv.h | 103 ++++++++ src/include/console/uart.h | 2 + src/include/console/usb.h | 2 + 8 files changed, 622 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index f9bd661..202267e 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,33 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + depends on ARCH_X86 && (CONSOLE_SERIAL || CONSOLE_USB) + default n + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..660d98e 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-$(ARCH_X86) += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-$(ARCH_X86) += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..3aee65a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,18 @@ void console_init(void) console_hw_init(); +#if !defined(__PRE_RAM__) + if (IS_ENABLED(CONFIG_DEBUG_SERIALICE) && + IS_ENABLED(CONFIG_DEBUG_SERIALICE_RAMSTAGE)) { + serialice_main(); + } +#else + if (IS_ENABLED(CONFIG_DEBUG_SERIALICE) && + IS_ENABLED(CONFIG_DEBUG_SERIALICE_ROMSTAGE)) { + serialice_main(); + } +#endif + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..0c9aa18 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,446 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/usb.h> +#include <console/uart.h> +#include <console/serialice.h> +#include <console/serialice_priv.h> +#include <arch/io.h> + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_flush(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_byte(byte); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + if (IS_ENABLED(CONFIG_CONSOLE_USB)) { + val = __usb_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + val = __uart_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +int serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } + + // Never get here: + return 0; +} diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..522b4aa --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,27 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +#ifdef ARCH_X86 +int serialice_main(void); +#else +static inline int serialice_main(void) { return 0; } +#endif + +#endif diff --git a/src/include/console/serialice_priv.h b/src/include/console/serialice_priv.h new file mode 100644 index 0000000..078ef04 --- /dev/null +++ b/src/include/console/serialice_priv.h @@ -0,0 +1,103 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..278e0e3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -59,10 +59,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} +static inline u8 __uart_rx_byte(void) { return 0; } #endif #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..2f7da49 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,10 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} +static inline u8 __usb_rx_byte(void) { return 0; } #endif /* */

1 0

Patch set updated for coreboot: console/serialice: Add SerialICE
by Patrick Rudolph 25 Apr '16

25 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 5e2a19ccdf7b8d8f32271b7ecfdb6beed2d1292e Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520. Needs tests: * Ramstage * Serial cable * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/Kconfig | 27 +++ src/console/Makefile.inc | 2 + src/console/init.c | 13 + src/console/serialice.c | 446 +++++++++++++++++++++++++++++++++++ src/include/console/serialice.h | 23 ++ src/include/console/serialice_priv.h | 103 ++++++++ src/include/console/uart.h | 2 + src/include/console/usb.h | 2 + 8 files changed, 618 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index f9bd661..62e5662 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,33 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + depends on CONSOLE_SERIAL || CONSOLE_USB + default n + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..ce0b01e 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-y += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-y += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..3aee65a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,18 @@ void console_init(void) console_hw_init(); +#if !defined(__PRE_RAM__) + if (IS_ENABLED(CONFIG_DEBUG_SERIALICE) && + IS_ENABLED(CONFIG_DEBUG_SERIALICE_RAMSTAGE)) { + serialice_main(); + } +#else + if (IS_ENABLED(CONFIG_DEBUG_SERIALICE) && + IS_ENABLED(CONFIG_DEBUG_SERIALICE_ROMSTAGE)) { + serialice_main(); + } +#endif + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..0c9aa18 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,446 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/usb.h> +#include <console/uart.h> +#include <console/serialice.h> +#include <console/serialice_priv.h> +#include <arch/io.h> + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_flush(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_byte(byte); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + if (IS_ENABLED(CONFIG_CONSOLE_USB)) { + val = __usb_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + val = __uart_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +int serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } + + // Never get here: + return 0; +} diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..522906c --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,23 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +int serialice_main(void); + +#endif diff --git a/src/include/console/serialice_priv.h b/src/include/console/serialice_priv.h new file mode 100644 index 0000000..078ef04 --- /dev/null +++ b/src/include/console/serialice_priv.h @@ -0,0 +1,103 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..278e0e3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -59,10 +59,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} +static inline u8 __uart_rx_byte(void) { return 0; } #endif #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..2f7da49 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,10 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} +static inline u8 __usb_rx_byte(void) { return 0; } #endif /* */

1 0

New patch to review for coreboot: console/serialice: Add SerialICE
by Patrick Rudolph 25 Apr '16

25 Apr '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14504 -gerrit commit 6915e2bbbb75f27e71784981d4d6c1ce19b9577d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Apr 25 11:00:17 2016 +0200 console/serialice: Add SerialICE Add Kconfig Option to build SerialICE shell into coreboot stages. You can select between romstage and ramstage. The SerialICE shell will be launched instead of coreboot console. As minimal system initialization is already done in coreboot, it should work on all boards. Tested with EHCI Debug on Lenovo T520. Needs tests: * Ramstage * Serial cable * On other boards Change-Id: I1fa6eb4f40e0f625c8c8302d1580bcd2664d670b Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/Kconfig | 27 +++ src/console/Makefile.inc | 2 + src/console/init.c | 13 + src/console/serialice.c | 446 +++++++++++++++++++++++++++++++++++ src/include/console/serialice.h | 23 ++ src/include/console/serialice_priv.h | 103 ++++++++ src/include/console/uart.h | 2 + src/include/console/usb.h | 2 + 8 files changed, 618 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index f9bd661..31886af 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1078,6 +1078,33 @@ config DEBUG_COVERAGE If enabled, the code coverage hooks in coreboot will output some information about the coverage data that is dumped. +config DEBUG_SERIALICE + bool "Enable SerialICE instead normal boot" + depends on CONSOLE_SERIAL || CONSOLE_USB + default n + help + If enabled, SerialICE will be run instead of normal boot. + You need to connect a serial cable or EHCI debug dongle to + communicate with SerialICE shell. + +choice + prompt "SerialICE bootstage" + default DEBUG_SERIALICE_ROMSTAGE + help + Choose the stage SerialICE to start. You can choose between + ROMSTAGE and RAMSTAGE. + +config DEBUG_SERIALICE_ROMSTAGE + bool "Start SerialICE instead of Romstage" + help + Start SerialICE in romstage, right after minimal system initialization. + +config DEBUG_SERIALICE_RAMSTAGE + bool "Start SerialICE instead of Ramstage" + help + Start SerialICE in ramstage. +endchoice + endmenu # These probably belong somewhere else, but they are needed somewhere. diff --git a/src/console/Makefile.inc b/src/console/Makefile.inc index 0fee12a..ce0b01e 100644 --- a/src/console/Makefile.inc +++ b/src/console/Makefile.inc @@ -2,6 +2,7 @@ ramstage-y += vtxprintf.c printk.c vsprintf.c ramstage-y += init.c console.c ramstage-y += post.c ramstage-y += die.c +ramstage-y += serialice.c smm-$(CONFIG_DEBUG_SMI) += init.c console.c vtxprintf.c printk.c smm-$(CONFIG_SMM_TSEG) += die.c @@ -17,6 +18,7 @@ romstage-y += vtxprintf.c printk.c romstage-y += init.c console.c romstage-y += post.c romstage-y += die.c +romstage-y += serialice.c postcar-y += vtxprintf.c printk.c postcar-y += init.c console.c diff --git a/src/console/init.c b/src/console/init.c index 8f40abb..3aee65a 100644 --- a/src/console/init.c +++ b/src/console/init.c @@ -16,6 +16,7 @@ #include <console/console.h> #include <console/uart.h> +#include <console/serialice.h> #include <console/streams.h> #include <device/pci.h> #include <option.h> @@ -43,6 +44,18 @@ void console_init(void) console_hw_init(); +#if !defined(__PRE_RAM__) + if (IS_ENABLED(CONFIG_DEBUG_SERIALICE) && + IS_ENABLED(CONFIG_DEBUG_SERIALICE_RAMSTAGE)) { + serialice_main(); + } +#else + if (IS_ENABLED(CONFIG_DEBUG_SERIALICE) && + IS_ENABLED(CONFIG_DEBUG_SERIALICE_ROMSTAGE)) { + serialice_main(); + } +#endif + printk(BIOS_INFO, "\n\ncoreboot-%s%s %s " ENV_STRING " starting...\n", coreboot_version, coreboot_extra_version, coreboot_build); } diff --git a/src/console/serialice.c b/src/console/serialice.c new file mode 100644 index 0000000..0c9aa18 --- /dev/null +++ b/src/console/serialice.c @@ -0,0 +1,446 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#include <console/console.h> +#include <console/usb.h> +#include <console/uart.h> +#include <console/serialice.h> +#include <console/serialice_priv.h> +#include <arch/io.h> + +#define VERSION "1.6" + +/* Uart wrapper functions */ + +static void sio_flush(void) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_flush(); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_flush(); +} + +static void sio_putc(u8 byte) +{ + if (IS_ENABLED(CONFIG_CONSOLE_USB)) + __usb_tx_byte(byte); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) + __uart_tx_byte(byte); +} + +static u8 sio_getc(void) +{ + u8 val = 0; + + if (IS_ENABLED(CONFIG_CONSOLE_USB)) { + val = __usb_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + val = __uart_rx_byte(); +#ifdef ECHO_MODE + sio_putc(val); +#endif + return val; + } + return 0; +} + +/* String functions */ + +static void sio_putstring(const char *string) +{ + /* Very simple, no %d, %x etc. */ + while (*string) { + if (*string == '\n') + sio_putc('\r'); + sio_putc(*string); + string++; + } + sio_flush(); +} + +static void sio_put8(u8 data) +{ + u8 c; + + c = (data >> 4) & 0xf; + sio_put_nibble(c); + + c = data & 0xf; + sio_put_nibble(c); + sio_flush(); +} + +static void sio_put16(u16 data) +{ + int i; + u8 c; + + for (i = 12; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static void sio_put32(u32 data) +{ + int i; + u8 c; + + for (i = 28; i >= 0; i -= 4) { + c = (data >> i) & 0xf; + sio_put_nibble(c); + } + sio_flush(); +} + +static u8 sio_get_nibble(void) +{ + u8 ret = 0; + u8 nibble = sio_getc(); + + if (nibble >= '0' && nibble <= '9') { + ret = (nibble - '0'); + } else if (nibble >= 'a' && nibble <= 'f') { + ret = (nibble - 'a') + 0xa; + } else if (nibble >= 'A' && nibble <= 'F') { + ret = (nibble - 'A') + 0xa; + } else { + sio_putstring("ERROR: parsing number\n"); + } + return ret; +} + +static u8 sio_get8(void) +{ + u8 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + return data; +} + +static u16 sio_get16(void) +{ + u16 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +static u32 sio_get32(void) +{ + u32 data; + + data = sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + data = data << 4; + data |= sio_get_nibble(); + + return data; +} + +/* SerialICE interface functions */ + +static void serialice_read_memory(void) +{ + u8 width; + u32 *addr; + + // Format: + // *rm00000000.w + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(read8(addr)); + break; + case 'w': + sio_put16(read16(addr)); + break; + case 'l': + sio_put32(read32(addr)); + break; + } +} + +static void serialice_write_memory(void) +{ + u8 width; + u32 *addr; + u32 data; + + // Format: + // *wm00000000.w=0000 + addr = (u32 *)sio_get32(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + write8(addr, (u8)data); + break; + case 'w': + data = sio_get16(); + write16(addr, (u16)data); + break; + case 'l': + data = sio_get32(); + write32(addr, (u32)data); + break; + } +} + +static void serialice_read_io(void) +{ + u8 width; + u16 port; + + // Format: + // *ri0000.w + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + + sio_putc('\r'); sio_putc('\n'); + + switch (width) { + case 'b': + sio_put8(inb(port)); + break; + case 'w': + sio_put16(inw(port)); + break; + case 'l': + sio_put32(inl(port)); + break; + } +} + +static void serialice_write_io(void) +{ + u8 width; + u16 port; + u32 data; + + // Format: + // *wi0000.w=0000 + port = sio_get16(); + sio_getc(); // skip . + width = sio_getc(); + sio_getc(); // skip = + + switch (width) { + case 'b': + data = sio_get8(); + outb((u8)data, port); + break; + case 'w': + data = sio_get16(); + outw((u16)data, port); + break; + case 'l': + data = sio_get32(); + outl((u32)data, port); + break; + } +} + +static void serialice_read_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *rc00000000.9c5a203a + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // key in %edi + + sio_putc('\r'); sio_putc('\n'); + + msr = rdmsr(addr, key); + sio_put32(msr.hi); + sio_putc('.'); + sio_put32(msr.lo); +} + +static void serialice_write_msr(void) +{ + u32 addr, key; + msr_t msr; + + // Format: + // *wc00000000.9c5a203a=00000000.00000000 + addr = sio_get32(); + sio_getc(); // skip . + key = sio_get32(); // read key in %edi + sio_getc(); // skip = + msr.hi = sio_get32(); + sio_getc(); // skip . + msr.lo = sio_get32(); + +#ifdef __ROMCC__ + /* Cheat to avoid register outage */ + wrmsr(addr, msr, 0x9c5a203a); +#else + wrmsr(addr, msr, key); +#endif +} + +static void serialice_cpuinfo(void) +{ + u32 eax, ecx; + u32 reg32; + + // Format: + // --EAX--- --ECX--- + // *ci00000000.00000000 + eax = sio_get32(); + sio_getc(); // skip . + ecx = sio_get32(); + + sio_putc('\r'); sio_putc('\n'); + + /* This code looks quite crappy but this way we don't + * have to worry about running out of registers if we + * occupy eax, ebx, ecx, edx at the same time + */ + reg32 = cpuid_eax(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ebx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_ecx(eax, ecx); + sio_put32(reg32); + sio_putc('.'); + + reg32 = cpuid_edx(eax, ecx); + sio_put32(reg32); +} + +static void serialice_mainboard(void) +{ + int i = 0; + const char mb_string[] = CONFIG_MAINBOARD_VENDOR" " + CONFIG_MAINBOARD_PART_NUMBER; + + sio_putc('\r'); sio_putc('\n'); + + while (i < 32 && mb_string[i] > 0) { + sio_putc(mb_string[i]); + i++; + } + while (i < 32) { + sio_putc(' '); + i++; + } + + sio_flush(); +} + +static void serialice_version(void) +{ + sio_putstring("\nSerialICE v" VERSION "\n"); +} + +int serialice_main(void) +{ + u16 c; + + serialice_version(); + + while (1) { + sio_putstring("\n> "); + + c = sio_getc(); + if (c != '*') + continue; + + c = sio_getc() << 8; + c |= sio_getc(); + + switch (c) { + case (('r' << 8)|'m'): // Read Memory *rm + serialice_read_memory(); + break; + case (('w' << 8)|'m'): // Write Memory *wm + serialice_write_memory(); + break; + case (('r' << 8)|'i'): // Read IO *ri + serialice_read_io(); + break; + case (('w' << 8)|'i'): // Write IO *wi + serialice_write_io(); + break; + case (('r' << 8)|'c'): // Read CPU MSR *rc + serialice_read_msr(); + break; + case (('w' << 8)|'c'): // Write CPU MSR *wc + serialice_write_msr(); + break; + case (('c' << 8)|'i'): // Read CPUID *ci + serialice_cpuinfo(); + break; + case (('m' << 8)|'b'): // Read mainboard type *mb + serialice_mainboard(); + break; + case (('v' << 8)|'i'): // Read version info *vi + serialice_version(); + break; + default: + sio_putstring("ERROR\n"); + break; + } + } + + // Never get here: + return 0; +} diff --git a/src/include/console/serialice.h b/src/include/console/serialice.h new file mode 100644 index 0000000..522906c --- /dev/null +++ b/src/include/console/serialice.h @@ -0,0 +1,23 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_H +#define CONSOLE_SERIALICE_H + +int serialice_main(void); + +#endif diff --git a/src/include/console/serialice_priv.h b/src/include/console/serialice_priv.h new file mode 100644 index 0000000..078ef04 --- /dev/null +++ b/src/include/console/serialice_priv.h @@ -0,0 +1,103 @@ +/* + * SerialICE + * + * Copyright (C) 2009 coresystems GmbH + * Copyright (C) 2016 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + */ + +#ifndef CONSOLE_SERIALICE_PRIV_H +#define CONSOLE_SERIALICE_PRIV_H + +/* String functions */ + +#define sio_put_nibble(nibble) \ + do { \ + if (nibble > 9) \ + nibble += ('a' - 10); \ + else \ + nibble += '0'; \ + sio_putc(nibble); \ + } while (0) + +/* MSR functions */ + +typedef struct { u32 lo, hi; } msr_t; + +static inline msr_t rdmsr(u32 index, u32 key) +{ + msr_t result; + + __asm__ __volatile__ ( + "rdmsr" + : "=a" (result.lo), "=d" (result.hi) + : "c" (index), "D" (key) + ); + return result; +} + +static inline void wrmsr(u32 index, msr_t msr, u32 key) +{ + __asm__ __volatile__ ( + "wrmsr" + : /* No outputs */ + : "c" (index), "a" (msr.lo), "d" (msr.hi), "D" (key) + ); +} + +/* CPUID functions */ + +static inline u32 cpuid_eax(u32 op, u32 op2) +{ + u32 eax; + + __asm__("cpuid" + : "=a" (eax) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return eax; +} + +static inline u32 cpuid_ebx(u32 op, u32 op2) +{ + u32 ebx; + + __asm__("cpuid" + : "=b" (ebx) + : "a" (op), "c" (op2) + : "edx"); + return ebx; +} + +static inline u32 cpuid_ecx(u32 op, u32 op2) +{ + u32 ecx; + + __asm__("cpuid" + : "=c" (ecx) + : "a" (op), "c" (op2) + : "ebx", "edx"); + return ecx; +} + +static inline u32 cpuid_edx(u32 op, u32 op2) +{ + u32 edx; + + __asm__("cpuid" + : "=d" (edx) + : "a" (op), "c" (op2) + : "ebx"); + return edx; +} + +#endif diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..278e0e3 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -59,10 +59,12 @@ void oxford_remap(unsigned int new_base); static inline void __uart_init(void) { uart_init(CONFIG_UART_FOR_CONSOLE); } static inline void __uart_tx_byte(u8 data) { uart_tx_byte(CONFIG_UART_FOR_CONSOLE, data); } static inline void __uart_tx_flush(void) { uart_tx_flush(CONFIG_UART_FOR_CONSOLE); } +static inline u8 __uart_rx_byte(void) { return uart_rx_byte(CONFIG_UART_FOR_CONSOLE); } #else static inline void __uart_init(void) {} static inline void __uart_tx_byte(u8 data) {} static inline void __uart_tx_flush(void) {} +static inline u8 __uart_rx_byte(void) { return 0; } #endif #if CONFIG_GDB_STUB && (ENV_ROMSTAGE || ENV_RAMSTAGE) diff --git a/src/include/console/usb.h b/src/include/console/usb.h index b758c03..2f7da49 100644 --- a/src/include/console/usb.h +++ b/src/include/console/usb.h @@ -37,10 +37,12 @@ int usb_can_rx_byte(int idx); static inline void __usbdebug_init(void) { usbdebug_init(); } static inline void __usb_tx_byte(u8 data) { usb_tx_byte(USB_PIPE_FOR_CONSOLE, data); } static inline void __usb_tx_flush(void) { usb_tx_flush(USB_PIPE_FOR_CONSOLE); } +static inline u8 __usb_rx_byte(void) { return usb_rx_byte(USB_PIPE_FOR_CONSOLE); } #else static inline void __usbdebug_init(void) {} static inline void __usb_tx_byte(u8 data) {} static inline void __usb_tx_flush(void) {} +static inline u8 __usb_rx_byte(void) { return 0; } #endif /* */

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Patch set updated for coreboot: soc/intel/apollolake: Fix northbridge _crs scope
by Lijian Zhao 25 Apr '16

25 Apr '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14477 -gerrit commit 2880a178cfe559588eefccd70bc6d6a36aa5f631 Author: Zhao, Lijian <lijian.zhao(a)intel.com> Date: Fri Apr 22 11:19:44 2016 -0700 soc/intel/apollolake: Fix northbridge _crs scope Move _CRS scope from MCHC device only to whole pci root bus. Otherwise ACPI will not able to assign resource to devices other than MCHC. Change-Id: Iaa294c63e03a4fc6644f1be5d69ab3de077e6cc3 Signed-off-by: Zhao, Lijian <lijian.zhao(a)intel.com> --- src/soc/intel/apollolake/acpi/northbridge.asl | 167 +++++++++++++------------- 1 file changed, 84 insertions(+), 83 deletions(-) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index 8415ffe..1c8067f 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -36,97 +36,98 @@ Device (MCHC) Offset(0xBC), TLUD, 32, /* Top of Low Useable DRAM */ } - Name (MCRS, ResourceTemplate() - { - /* Bus Numbers */ - WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, - 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) - - /* IO Region 0 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) - - /* PCI Config Space */ - Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) - - /* IO Region 1 */ - DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, - 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) - - /* VGA memory (0xa0000-0xbffff) */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, - 0x00020000,,,) - - /* Data and GFX stolen memory */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - Cacheable, ReadWrite, - 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, - 0x04200000,,, STOM) - - /* - * PCI MMIO Region (TOLUD - PCI extended base MMCONF) - * This assumes that MMCONF is placed after PCI config space, - * and that no resources are allocated after the MMCONF region. - * This works, sicne MMCONF is hardcoded to 0xe00000000. - */ - DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x00000000, 0x00000000, 0x00000000, - 0x00000000,,, PM01) - - /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ - QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, - NonCacheable, ReadWrite, - 0x00000000, 0x10000, 0x1ffff, 0x00000000, - 0x10000,,, PM02) - }) - - /* Current Resource Settings */ - Method (_CRS, 0, Serialized) - { +} +Name (MCRS, ResourceTemplate() +{ + /* Bus Numbers */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100,,,) + + /* IO Region 0 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8,,,) + + /* PCI Config Space */ + Io (Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x01000, 0xffff, 0x0000, 0xf000,,,) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000,,,) + + /* Data and GFX stolen memory */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x3be00000, 0x3fffffff, 0x00000000, + 0x04200000,,, STOM) + + /* + * PCI MMIO Region (TOLUD - PCI extended base MMCONF) + * This assumes that MMCONF is placed after PCI config space, + * and that no resources are allocated after the MMCONF region. + * This works, sicne MMCONF is hardcoded to 0xe00000000. + */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000,,, PM01) + + /* PCI Memory Region (TOUUD - (TOUUD + ABOVE_4G_MMIO_SIZE)) */ + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x10000, 0x1ffff, 0x00000000, + 0x10000,,, PM02) +}) + +/* Current Resource Settings */ +Method (_CRS, 0, Serialized) +{ - /* Find PCI resource area in MCRS */ - CreateDwordField (MCRS, ^PM01._MIN, PMIN) - CreateDwordField (MCRS, ^PM01._MAX, PMAX) - CreateDwordField (MCRS, ^PM01._LEN, PLEN) + /* Find PCI resource area in MCRS */ + CreateDwordField (MCRS, ^PM01._MIN, PMIN) + CreateDwordField (MCRS, ^PM01._MAX, PMAX) + CreateDwordField (MCRS, ^PM01._LEN, PLEN) - /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ - And(^TLUD, 0xFFF00000, PMIN) - /* Read MMCONF base */ - And(^MCNF, 0xF0000000, PMAX) + /* Read C-Unit PCI CFG Reg. 0xBC for TOLUD (shadow from B-Unit) */ + And(^MCHC.TLUD, 0xFFF00000, PMIN) + /* Read MMCONF base */ + And(^MCHC.MCNF, 0xF0000000, PMAX) - /* Calculate PCI MMIO Length */ - Add(Subtract(PMAX, PMIN), 1, PLEN) + /* Calculate PCI MMIO Length */ + Add(Subtract(PMAX, PMIN), 1, PLEN) - /* Find GFX resource area in GCRS */ - CreateDwordField(MCRS, ^STOM._MIN, GMIN) - CreateDwordField(MCRS, ^STOM._MAX, GMAX) - CreateDwordField(MCRS, ^STOM._LEN, GLEN) + /* Find GFX resource area in GCRS */ + CreateDwordField(MCRS, ^STOM._MIN, GMIN) + CreateDwordField(MCRS, ^STOM._MAX, GMAX) + CreateDwordField(MCRS, ^STOM._LEN, GLEN) - /* Read BGSM */ - And(^BGSM, 0xFFF00000, GMIN) + /* Read BGSM */ + And(^MCHC.BGSM, 0xFFF00000, GMIN) - /* Read TOLUD */ - And(^TLUD, 0xFFF00000, GMAX) - Decrement(GMAX) - Add(Subtract(GMAX, GMIN), 1, GLEN) + /* Read TOLUD */ + And(^MCHC.TLUD, 0xFFF00000, GMAX) + Decrement(GMAX) + Add(Subtract(GMAX, GMIN), 1, GLEN) - /* Patch PM02 range based on Memory Size */ - CreateQwordField (MCRS, ^PM02._MIN, MMIN) - CreateQwordField (MCRS, ^PM02._MAX, MMAX) - CreateQwordField (MCRS, ^PM02._LEN, MLEN) + /* Patch PM02 range based on Memory Size */ + CreateQwordField (MCRS, ^PM02._MIN, MMIN) + CreateQwordField (MCRS, ^PM02._MAX, MMAX) + CreateQwordField (MCRS, ^PM02._LEN, MLEN) - Store (^TUUD, Local0) + Store (^MCHC.TUUD, Local0) - If (LLessEqual (Local0, 0x1000000000)) - { - Store (0, MMIN) - Store (0, MLEN) - } - Subtract (Add (MMIN, MLEN), 1, MMAX) - - Return (MCRS) + If (LLessEqual (Local0, 0x1000000000)) + { + Store (0, MMIN) + Store (0, MLEN) } + Subtract (Add (MMIN, MLEN), 1, MMAX) + + Return (MCRS) } +

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New patch to review for coreboot: nb/amd/mct_ddr3: Only initialize ECC bits once
by Timothy Pearson 25 Apr '16

25 Apr '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14503 -gerrit commit 22a49883583f57dfd9f0f801c0a983ba36a4994c Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Sun Apr 24 20:56:31 2016 -0500 nb/amd/mct_ddr3: Only initialize ECC bits once The ECC check bits of all ECC DIMMS were inadvertently initialized twice in the same routine, significantly delaying startup. Part of this was related to an obsolete MCA workaround that has been fixed through multiple commits, therefore the workaround is no longer needed. Only initialize the ECC check bits once. Change-Id: I90ac1147d9b006794d29b866a9cb5b7ead8f01e7 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index abf40a1..c0ae440 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2010 Advanced Micro Devices, Inc. - * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2015 - 2016 Raptor Engineering, LLC * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -137,10 +137,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Clear the RAM before enabling ECC to prevent MCE-related lockups */ - DCTMemClr_Init_D(pMCTstat, pDCTstat); - DCTMemClr_Sync_D(pMCTstat, pDCTstat); } }

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coreboot-gerrit April 2016